Transistor and semiconductor device

Abstract

The utility model relates to a transistor and a semiconductor device. The transistor comprises a substrate in which an active region with a first doping type is arranged; a gate structure disposed on the active region; the source electrode region and the drain electrode region are arranged in the active region, are located on the opposite sides of the gate structure and are of the second doping type, and the source electrode region and the drain electrode region deviate relative to each other in the first direction parallel to the thickness direction of the substrate; the inclined surface is arranged between the source electrode region and the drain electrode region and extends in a direction which is not parallel to the first direction and is not parallel to a second direction which is vertical to the thickness direction of the substrate; and a channel region disposed in the active region between the source region and the drain region, the channel region being at least partially defined by the slope, where, when the transistor is turned on, a conductive channel connecting the source region and the drain region is formed in the channel region, the conductive channel comprising a first portion extending along the slope.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a transistor and a semiconductor device including the transistor. Background Art

[0002] Various transistors such as Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) are widely used in integrated circuits. With the advancement of semiconductor technology, integrated circuits are constantly developing towards high integration and miniaturization. To this end, the size of transistors is designed to be smaller and smaller, so that the channel length in the transistor is also reduced. When the channel length in the transistor is too small, the "short channel effect" is likely to occur, which may have an adverse effect on the performance of the transistor. Utility Model Content

[0003] A brief overview of the disclosure is given below in order to provide a basic understanding of some aspects of the disclosure. However, it should be understood that this overview is not an exhaustive overview of the disclosure. It is not intended to identify the key or important parts of the disclosure, nor is it intended to limit the scope of the disclosure. Its purpose is simply to give some concepts of the disclosure in a simplified form as a prelude to a more detailed description given later.

[0004] According to a first aspect of the present disclosure, a transistor is provided. The transistor comprises: a substrate, an active region having a first doping type is arranged in the substrate; a gate structure arranged on the active region; a source region and a drain region having a second doping type arranged in the active region and located on opposite sides of the gate structure, wherein the source region and the drain region are offset relative to each other in a first direction parallel to the thickness direction of the substrate; an inclined plane arranged between the source region and the drain region, the inclined plane extending not parallel to the first direction and not parallel to a second direction perpendicular to the thickness direction of the substrate; and a channel region arranged in the active region and located between the source region and the drain region, the channel region being at least partially defined by the inclined plane, wherein when the transistor is turned on, a conductive channel connecting the source region and the drain region is formed in the channel region, the conductive channel comprising a first portion extending along the inclined plane.

[0005] In some embodiments, the angle between the inclined surface and the second direction is between 45° and 75°.

[0006] In some embodiments, the conductive channel also includes at least one of: a second portion located between the source region and the first portion, the second portion and the source region are aligned with each other in the first direction; a third portion located between the drain region and the first portion, the third portion and the drain region are aligned with each other in the first direction.

[0007] In some embodiments, the transistor further includes a recess disposed between the source region and the drain region, the channel region being at least partially defined by the recess, wherein the conductive channel includes a fourth portion extending along a surface of the recess.

[0008] In some embodiments, the groove includes the slope, and the fourth portion of the conductive channel includes the first portion.

[0009] In some embodiments, the groove is connected to the inclined surface, and the fourth portion of the conductive channel is connected to the first portion.

[0010] According to a second aspect of the present disclosure, a transistor is provided. The transistor comprises: a substrate, an active region having a first doping type is arranged in the substrate; a gate structure arranged on the active region; a source region and a drain region having a second doping type arranged in the active region and located on opposite sides of the gate structure, wherein the source region and the drain region are offset relative to each other in a first direction parallel to the thickness direction of the substrate; a groove arranged between the source region and the drain region; and a channel region arranged in the active region and located between the source region and the drain region, the channel region being at least partially defined by the groove, wherein when the transistor is turned on, a conductive channel connecting the source region and the drain region is formed in the channel region, the conductive channel comprising a first portion extending along the surface of the groove.

[0011] In some embodiments, the sidewalls of the groove extend along the first direction.

[0012] In some embodiments, a sidewall and / or a bottom surface of the groove extends non-parallel to the first direction and non-parallel to a second direction perpendicular to the thickness direction of the substrate.

[0013] In some embodiments, the conductive channel also includes at least one of: a second portion located between the source region and the first portion, the second portion and the source region are aligned with each other in the first direction; a third portion located between the drain region and the first portion, the third portion and the drain region are aligned with each other in the first direction.

[0014] In some embodiments, the transistor further includes a plurality of grooves disposed between the source region and the drain region, the channel region being at least partially defined by the plurality of grooves, wherein the conductive channel includes portions extending along surfaces of the plurality of grooves.

[0015] According to a third aspect of the present disclosure, a semiconductor device is provided, comprising the transistor according to any one of the embodiments of the first aspect or the second aspect of the present disclosure.

[0016] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The foregoing and other features and advantages of the present disclosure will become apparent from the following description of the embodiments of the present disclosure in conjunction with the accompanying drawings. The accompanying drawings are incorporated herein and form a part of the specification, and are further used to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. Among them:

[0018] Figure 1 shows a schematic cross-sectional view of a conventional transistor;

[0019] Figure 2 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0020] Figure 3 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0021] Figure 4 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0022] Figure 5 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0023] Figure 6 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0024] Figure 7 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0025] Figure 8 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0026] Fig. 9 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0027] Fig.10 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0028] Fig.11 shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0029] Fig.12shows a schematic cross-sectional view of a transistor according to some embodiments of the present disclosure;

[0030] Fig.13 A schematic cross-sectional view of a transistor according to some embodiments of the present disclosure is shown.

[0031] Note that in the embodiments described below, sometimes the same reference numerals are used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In some cases, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0032] For ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, etc. Therefore, the present disclosure is not limited to the position, size, range, etc. disclosed in the drawings and the like. DETAILED DESCRIPTION

[0033] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0034] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0035] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0036] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0037] Figure 1 A conventional transistor 10 is schematically shown. Figure 1As shown, the transistor 10 includes a substrate 12, and an active region 14 formed by, for example, ion implantation with a first doping type (e.g., one of a P-type and an N-type) in the substrate 12. The transistor 10 also includes a source region 16 formed by, for example, ion implantation with a second doping type (e.g., the other of a P-type and an N-type) in the active region 14. 1 and drain region 16 2 , and a source region 16 disposed on the active region 14 1 and drain region 16 2 The gate structure 18 is generally provided between the active region 14 and the gate dielectric layer 18. 2 and disposed on the gate dielectric layer 18 2 The gate electrode layer 18 1 The source region 16 in the active region 14 is located below the gate structure 18. 1 and drain region 16 2 The region between the two channels may be referred to as the channel region 18. 0 When the gate electrode layer 18 1 When a suitable voltage is applied, in the channel region 18 0 A connection source region 16 is formed in 1 and drain region 16 2 , thereby turning on transistor 10.

[0038] In the source region 16 1 Between the active region 14 and the drain region 16 2 A PN junction is formed between the active region 14. Due to the diffusion movement of carriers caused by the concentration gradient and the drift movement caused by the built-in electric field, depletion regions 16 are formed in these PN junctions. 10 and 16 20 .from Figure 1 As can be seen in FIG. 1 , the gate structure 18 extends beyond the source region 16. 1 and drain region 16 2 The planar structure between the channel region 18 0 The maximum length of the conductive channel that can be formed in the source region 16 is limited by 1 and drain region 16 2 As the size of transistor 10 decreases, L also decreases accordingly, and depletion region 16 10 and 16 20 The expansion in the channel region will become non-negligible, resulting in a 18 0The length of the conductive channel that can be formed even further deteriorates from L to L', and the amount of charge in the depletion region controlled by the gate structure 18 per unit area is reduced, so that the control ability of the gate structure 18 over the transistor is weakened, and the performance of the transistor 10 is reduced due to the short channel effect. Therefore, the short channel effect hinders the further reduction of the size of the transistor, and further limits the development of integrated circuits towards high integration and miniaturization.

[0039] In order to improve the short channel effect caused by the reduction of transistor size, the commonly used methods include reducing the gate dielectric layer 18 2 However, this will increase the possibility of transistor breakdown, so it cannot completely and effectively solve the problems caused by the short channel effect.

[0040] To this end, the present disclosure provides a transistor with an improved structure, which can realize a conductive channel with a length exceeding the source-drain spacing limit, thereby Figure 1 The conventional transistor shown can have a longer conductive channel under the condition of the same transistor size, thereby effectively alleviating the adverse effects of the short channel effect, helping to reduce the size of the transistor, improve the integration density of the transistor and ensure the flexibility of the transistor design, thereby promoting the development of integrated circuits towards high integration and miniaturization.

[0041] The transistors according to various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It will be understood that the actual transistor may have other components, and in order to avoid blurring the main points of the present disclosure, these other components are not shown in the drawings and are not discussed herein. In the drawings, the boundaries of the active area are indicated by dotted lines, and the boundaries of the conductive channel are indicated by dashed lines. It will be understood that this is merely illustrative and not restrictive.

[0042] In the present disclosure, a first direction parallel to the thickness direction of the transistor is indicated by z, a second direction perpendicular to the thickness direction of the transistor is indicated by y, and a third direction perpendicular to the first direction z and the second direction y is indicated by x. In addition, in this document, for ease of explanation, "high", "low", "up", "down", "deep", "shallow", etc. may be used to describe the relative relationship of the transistors in the first direction z, "left", "right", etc. may be used to describe the relative relationship of the transistors in the second direction y, and "front", "back", etc. may be used to describe the relative relationship of the transistors in the third direction x.

[0043] Reference now Figure 2 , which shows a schematic cross-sectional view of a transistor 100 according to some embodiments of the present disclosure. Figure 2As shown, transistor 100 includes a substrate 102. In some embodiments, substrate 102 includes but is not limited to a semiconductor substrate, which may include a unitary semiconductor material (such as silicon or germanium, etc.) or a compound semiconductor material (such as silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide) or a combination thereof. In the embodiments according to the present disclosure, there is no particular limitation on the substrate, as long as it is suitable for forming components therein for realizing corresponding functions. Part or all of substrate 102 may also be doped with a certain concentration of impurity elements, for example, it may be doped with N-type or P-type impurities. As Figure 2 As shown, an active region 104 having a first doping type is provided in the substrate 102. In this document, "first doping type" and "second doping type" are used to distinguish different doping types. In some embodiments, the first doping type is N-type and the second doping type is P-type. In other embodiments, the first doping type is P-type and the second doping type is N-type.

[0044] The transistor 100 also includes a gate structure 110 disposed on the active region 104. It is understood that the gate structure 110 may actually specifically include, for example, a gate electrode layer and a gate dielectric layer as described above, but in order to make the description concise, the specific composition of the gate structure may not be described in detail here, and only the gate structure as a whole is illustrated in a schematic manner. By the way, as a non-limiting example, the material of the gate electrode layer may include one or more of the following: polysilicon, doped polysilicon (such as polysilicon doped with phosphorus ions, polysilicon doped with arsenic ions, polysilicon doped with antimony ions), metal (such as copper), etc., and the material of the gate dielectric layer may include one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, etc.

[0045] The transistor 100 further includes a source region 1061 and a drain region 1062 having a second doping type disposed in the active region 104 on opposite sides of the gate structure 110. Figure 2 As shown, the source region 1061, the gate structure 110, and the drain region 1062 are arranged in sequence in the second direction y, wherein the source region 1061 is located on the left side of the gate structure 110, and the drain region 1062 is located on the right side of the gate structure 110. Of course, this is merely exemplary and not restrictive, and the positions of the source region and the drain region may be swapped according to actual needs, that is, the source region 1061 may also be located on the right side of the gate structure 110, and the drain region 1062 may be located on the left side of the gate structure 110. In this article, the source region is located on the left side of the gate structure and the drain region is located on the right side of the gate structure as an example for explanation, but it can be understood that the present disclosure is also applicable to the case where the source region is located on the right side of the gate structure and the drain region is located on the left side of the gate structure.

[0046] The transistor 100 further includes a channel region disposed in the active region 104 between the source region 1061 and the drain region 1062. The channel region may be a portion of the active region 104, and its doping concentration may be the same as or different from the doping concentration of other portions of the active region 104. In some embodiments, the threshold voltage of the transistor 100 may be adjusted by adjusting the doping concentration of the channel region. When the transistor 100 is turned on, a conductive channel 108 connecting the source region 1061 and the drain region 1062 is formed in the channel region.

[0047] In particular, if Figure 2 As shown, the source region 1061 and the drain region 1062 of the transistor 100 are offset relative to each other in a first direction z parallel to the thickness direction of the substrate 102 (i.e., the thickness direction of the transistor 100), and the transistor 100 also includes an inclined surface 114 disposed between the source region 1061 and the drain region 1062. The inclined surface 114 extends non-parallel to the first direction z and non-parallel to the second direction y perpendicular to the thickness direction of the substrate 102. In this case, when the transistor 100 is turned on, the conductive channel 108 formed in the channel region includes a portion 1081 extending along the inclined surface 114. That is, since the source region 1061 and the drain region 1062 are arranged at different depth levels, at least a portion (e.g., portion 1081) of the conductive channel 108 extends obliquely, thereby connecting the source region 1061 and the drain region 1062 arranged in a longitudinally staggered manner. Therefore, the length of the conductive channel 108 is no longer limited to the lateral spacing L1 between the source region 1061 and the drain region 1062 (for example, in the second direction y), but is increased to the oblique distance L2 between the source region 1061 and the drain region 1062, thereby improving the short channel effect that may be caused when the lateral spacing L1 is very small.

[0048] Understandable, although Figure 2 The source region 1061 and the drain region 1062 in the embodiment are depicted as being completely offset relative to each other in the first direction z (i.e., the corresponding projections of the source region 1061 and the drain region 1062 on the xz plane do not overlap), but in other embodiments, the source region 1061 and the drain region 1062 may also be partially offset in the first direction z (i.e., the corresponding projections of the source region 1061 and the drain region 1062 on the xz plane partially overlap), and those skilled in the art may adjust the offset of the source region 1061 and the drain region 1062 in the first direction z according to actual needs, and the offset will determine the length of the conductive channel 108 to a certain extent. In addition, it can also be understood that although Figure 2The source region 1061 and the drain region 1062 in the transistor 100 are depicted as the source region 1061 being higher than the drain region 1062, but in other embodiments, the transistor 100 may also be formed such that the source region 1061 is lower than the drain region 1062. In this document, the source region being higher than the drain region will be used as an example for explanation, but it can be understood that the present disclosure is also applicable to the case where the source region is lower than the drain region.

[0049] On the one hand, the offset of the source region 1061 and the drain region 1062 of the transistor 100 relative to each other in the first direction z may generate stress (especially at the junction of the primary active region 1041 and the tertiary active region 1043 and the junction of the secondary active region 1042 and the tertiary active region 1043, which is easy to generate stress, as described later) and cause the transistor 100 to deform. In this regard, the setting of the inclined surface 114 can relieve stress and suppress the deformation of the transistor 100. On the other hand, the inclined surface 114 is conducive to forming a gate structure 110 thereon, especially when the gate structure 110 is deposited by a multi-layer thin film process. In some embodiments, the angle α between the inclined surface 114 and the second direction y can be between 45° and 75°, or between 50° and 70°, or between 55° and 65°, for example, 60°. These angles can be very beneficial for relieving stress and promoting the formation of the gate structure. Those skilled in the art can adjust the angle of the inclined surface 114 according to actual needs, and the angle will determine the length of the conductive channel 108 to a certain extent. It is also understandable that although Figure 2 The inclined surface 114 is shown as being flat, but it may be curved or bent, that is, the angle between the inclined surface 114 and the xy plane may be different at various locations.

[0050] For non-limiting purposes, the transistor 100 can be prepared, for example, by the following process. A substrate 102 is provided in which an active region 104 having a first doping type is disposed, and a portion of the active region 104 is obliquely etched downward to a certain depth by a photolithography process, thereby obtaining a primary active region 1041, a secondary active region 1042, and a tertiary active region 1043, wherein the surface of the primary active region 1041 is not etched, the surfaces of the secondary active region 1042 and the tertiary active region 1043 are etched, and the surface of the tertiary active region 1043 is inclined to provide an inclined surface 114. The primary active region 1041 is mainly used to set one of the source region and the drain region (for example, the source region 1061), the secondary active region 1042 is mainly used to set the other of the source region and the drain region (for example, the drain region 1062), and the tertiary active region 1043 is mainly used to set the channel region. The length of the conductive channel 108 formed in the communication area when the transistor 100 is turned on in the future can be adjusted by adjusting the depth and angle of the oblique downward etching. Then, a gate structure 110 is formed on the tertiary active area 1043. The gate structure 110 can not only extend across the surface of the tertiary active area 1043, but also extend to above the surface of the primary active area 1041 and / or extend to above the surface of the secondary active area 1042. The specific design can be flexibly made by those skilled in the art according to actual needs. In the case where the gate structure 110 extends above the surface of the primary active area 1041 and / or extends to above the surface of the secondary active area 1042, the channel region will also extend to below the surface of the primary active area 1041 and / or extend to below the surface of the secondary active area 1042 accordingly. Next, by, for example, an ion implantation process of the second doping type, for example, a source region 1061 is formed in the primary active area 1041 and a drain region 1062 is formed in the secondary active area 1042, thereby obtaining a gate structure having the following characteristics: Figure 2 Transistor 100 of the structure shown.

[0051] exist Figure 2 In the illustrated embodiment, the conductive channel 108 is illustrated as portion 1081, but it is understood that this is merely illustrative and not restrictive, and a person skilled in the art will appreciate that the conductive channel 108 may also have any other suitable structure. Other example structures of the conductive channel 108 will be further described below.

[0052] Figure 3 Schematically shows a variation 100A of the transistor 100 according to some embodiments of the present disclosure. Figure 3As shown, the right boundary of the source region 1061 is located at a certain distance from the boundary between the primary active region 1041 and the tertiary active region 1043, the left boundary of the drain region 1062 is located at the boundary between the secondary active region 1042 and the tertiary active region 1043, and the gate structure 110 extends between the left boundary of the drain region 1062 and the right boundary of the source region 1061. When the transistor 100A is turned on, the conductive channel 108 formed in the channel region includes a portion 1081 and a portion 1082 located between the source region 1061 and the portion 1081, and the portion 1082 and the source region 1061 are aligned with each other in the first direction z.

[0053] Figure 4 Schematically shows a variation 100B of the transistor 100 according to some other embodiments of the present disclosure. Figure 4 As shown, the right boundary of the source region 1061 is located at the junction of the primary active region 1041 and the tertiary active region 1043, the left boundary of the drain region 1062 is located at a certain distance from the junction of the secondary active region 1042 and the tertiary active region 1043, and the gate structure 110 extends between the left boundary of the drain region 1062 and the right boundary of the source region 1061. When the transistor 100B is turned on, the conductive channel 108 formed in the channel region includes a portion 1081 and a portion 1083 located between the drain region 1062 and the portion 1081, and the portion 1083 and the drain region 1062 are aligned with each other in the first direction z.

[0054] Figure 5 FIG. 1 schematically shows a variation 100C of the transistor 100 according to some other embodiments of the present disclosure. Figure 5 As shown, the right boundary of the source region 1061 is located at a certain distance from the boundary between the primary active region 1041 and the tertiary active region 1043, the left boundary of the drain region 1062 is located at a certain distance from the boundary between the secondary active region 1042 and the tertiary active region 1043, and the gate structure 110 extends between the left boundary of the drain region 1062 and the right boundary of the source region 1061. When the transistor 100C is turned on, the conductive channel 108 formed in the channel region includes a portion 1081, a portion 1082 located between the source region 1061 and the portion 1081, and a portion 1083 located between the drain region 1062 and the portion 1081, the portion 1082 and the source region 1061 are aligned with each other in the first direction z, and the portion 1083 and the drain region 1062 are aligned with each other in the first direction z.

[0055] Figures 3 to 5The case where the channel region "invades" the primary active region 1041 and / or the secondary active region 1042 from the tertiary active region 1043 is shown. In other cases, the source region 1061 can also "invade" the tertiary active region 1043 from the primary active region 1041 and / or the drain region 1062 can "invade" the tertiary active region 1043 from the secondary active region 1042, which can still achieve a longer channel compared to a conventional transistor structure when the lateral spacing between the source region 1061 and the drain region 1062 is constant, thereby alleviating the short channel effect. The range of "invasion" can be achieved by controlling the region with ion implantation of the second doping type. For example, the source region 1061 can be made to "invade" the tertiary active region 1043 by performing ion implantation with the second doping type on a portion of the primary active region 1041 adjacent to the tertiary active region 1043, and the drain region 1062 can be made to "invade" the tertiary active region 1043 by performing ion implantation with the second doping type on a portion of the secondary active region 1042 adjacent to the tertiary active region 1043.

[0056] The depth of each location along the conductive channel 108 may vary monotonically from the depth of the source region 1061 to the depth of the drain region 1062. In other cases, the depth of each location along the conductive channel 108 may also vary non-monotonically from the depth of the source region 1061 to the depth of the drain region 1062.

[0057] For example, in some embodiments, the transistor 100 further includes a groove disposed between the source region 1061 and the drain region 1062, and the channel region may be at least partially defined by the groove, and when the transistor 100 is turned on, the conductive channel 108 formed in the channel region includes a portion extending along the surface of the groove.

[0058] Figure 6 Schematically shows a variation 100D of the transistor 100 according to some embodiments of the present disclosure. Figure 6As shown, the groove 112 is disposed between the source region 1061 and the drain region 1062. When the transistor 100D is turned on, the conductive channel 108 formed in the channel region includes a portion 1084 extending along the surface of the groove 112. At least one sidewall and / or bottom surface of the groove 112 may be non-parallel to the first direction z and non-parallel to the second direction y, and accordingly, the portion 1084 of the conductive channel 108 may include at least one portion extending non-parallel to the first direction z and non-parallel to the second direction y. In this case, the inclined surface 114 may constitute a portion of the groove 112, for example, a sidewall or bottom surface of the groove 112 or a portion thereof, in other words, the groove 112 may include the inclined surface 114. Therefore, the length of the conductive channel 108 is no longer limited to the lateral spacing L1 between the source region 1061 and the drain region 1062, nor is it limited to the oblique distance L2 between the source region 1061 and the drain region 1062, but is increased to the tortuous path length L3 as shown in the figure, thereby improving the short channel effect that may be caused when the lateral spacing L1 is very small or even the oblique distance L2 is also very small.

[0059] Figure 7 Schematically shows a variation 100E of the transistor 100 according to some other embodiments of the present disclosure. Figure 7 As shown, the transistor 100E includes a groove 112 disposed between the source region 1061 and the drain region 1062, and an inclined surface 114 disposed between the source region 1061 and the groove 112, which is not parallel to the first direction z and is not parallel to the second direction y. The inclined surface 114 may be connected to the groove 112. When the transistor 100E is turned on, the conductive channel 108 formed in the channel region includes a portion 1084 extending along the surface of the groove 112 and a portion 1081 extending along the inclined surface 114, wherein the portion 1081 is connected to the portion 1084. Additionally or alternatively, although not shown, the transistor 100E may also include another inclined surface disposed between the drain region 1062 and the groove 112, which is not parallel to the first direction z and is not parallel to the second direction y, so that when the transistor 100E is turned on, the conductive channel 108 formed in the channel region further includes another portion extending along the other inclined surface, wherein the other portion is connected to the portion 1084.

[0060] Understandable, although Figure 6 and Figure 7 The bevel and / or groove surface is shown as flat, but it can be curved or bent, that is, the angle between the bevel and / or groove surface and the xy plane can be different at various locations. Figure 8 A variation 100F of the transistor 100 according to still other embodiments of the present disclosure is schematically shown, wherein the conductive channel 108 includes a portion 1084 extending along the curved surface of the groove 112 and a portion 1081 extending along the bent slope.

[0061] In addition, although Figures 6 to 8 Only one groove is shown in the figure, but those skilled in the art can set two or more grooves between the source region 1061 and the drain region 1062 according to actual needs, optionally use an inclined surface or plane for connecting any two adjacent grooves, optionally use an inclined surface or plane for connecting the source region 1061 and the leftmost groove, and optionally use an inclined surface or plane for connecting the drain region 1062 and the rightmost groove to obtain a tortuous conductive channel with a desired length. When multiple grooves are set, the shapes of these grooves and their sizes in various dimensions can be the same or different.

[0062] In addition, in the case of providing a groove, the channel region can also be made to "invade" the primary active region 1041 and / or the secondary active region 1042 from the tertiary active region 1043, so that the conductive channel 108 also includes a portion aligned with the source region 1061 in the first direction z and / or a portion aligned with the drain region 1062 in the first direction z, similar to Figures 3 to 5 Similarly, in other cases, the source region 1061 can "invade" the tertiary active region 1043 from the primary active region 1041 and / or the drain region 1062 can "invade" the tertiary active region 1043 from the secondary active region 1042, which can still achieve a longer channel compared to a conventional transistor structure when the lateral spacing between the source region 1061 and the drain region 1062 is constant, thereby alleviating the short channel effect.

[0063] Reference now Fig. 9 , which shows a schematic cross-sectional view of a transistor 200 according to some embodiments of the present disclosure. Fig. 9 As shown, the transistor 200 includes a substrate 202, an active region 204 having a first doping type disposed in the substrate 202, a gate structure 210 disposed on the active region 204, a source region 2061 and a drain region 2062 having a second doping type disposed in the active region 204 and located on opposite sides of the gate structure 210, and a channel region disposed in the active region 204 and located between the source region 2061 and the drain region 2062. The description of the substrate 202, the active region 204, the gate structure 210, the source region 2061, the drain region 2062 and the channel region can refer to the description of the transistor 100 above, so it is not repeated here.

[0064] In particular, the source region 2061 and the drain region 2062 are also offset relative to each other in the first direction z, and the transistor 200 further includes a groove 212 disposed between the source region 2061 and the drain region 2062, so that the channel region is at least partially defined by the groove 212. When the transistor 200 is turned on, a conductive channel 208 connecting the source region 2061 and the drain region 2062 is formed in the channel region, and the conductive channel 208 includes a portion 2081 extending along the surface of the groove 212. Therefore, the length of the conductive channel 208 is no longer limited to the lateral spacing between the source region 2061 and the drain region 2062 (for example, in the second direction y), nor is it limited to the oblique distance between the source region 2061 and the drain region 2062. Instead, it is increased to the length of the tortuous path extending along the surface of the groove 212 as shown in the figure, thereby improving the short channel effect that may be caused when the lateral spacing between the source region 2061 and the drain region 2062 is very small or even the oblique distance is also very small.

[0065] In some embodiments, for example, Fig. 9 As shown, the sidewall of the groove 212 extends along the first direction z. In some embodiments, at least one sidewall and / or bottom surface of the groove 212 may also extend non-parallel to the first direction z and non-parallel to the second direction y, for example, Fig.12 As shown. Fig. 9 The middle groove 212 is shown as a square, but this is only exemplary and not restrictive, and those skilled in the art will understand that the groove 212 of the transistor 200 may also be any other suitable shape, such as a trapezoid, an arc, etc. For example, although the surfaces of the groove are shown as flat, they may be curved or bent, that is, the angle between each position of the groove surface and the xy plane may be different.

[0066] For the purpose of non-limiting description, the transistor 200 can be prepared, for example, by the following process. A substrate 202 is provided in which an active region 204 having a first doping type is disposed, and a portion of the active region 204 is etched downward to a certain depth by a photolithography process, thereby obtaining a primary active region 2041 and a secondary active region 2042. Then, a portion of the secondary active region 2042 close to the primary active region 2041 is etched downward to a certain depth by a photolithography process again, thereby obtaining a tertiary active region 2043, wherein the surface of the primary active region 2041 is not etched, the surfaces of the secondary active region 2042 and the tertiary active region 2043 are etched, and the tertiary active region 2043 is recessed downward compared to the primary active region 2041 and the secondary active region 2042, thereby forming a groove 212 between the primary active region 2041 and the secondary active region 2042. The surface of the tertiary active region 2043 can provide the bottom surface of the groove 212. The primary active region 2041 is mainly used to set one of the source region and the drain region (for example, the source region 2061), the secondary active region 2042 is mainly used to set the other of the source region and the drain region (for example, the drain region 2062), and the tertiary active region 2043 is mainly used to set the channel region. The length of the conductive channel 208 formed in the communication region when the transistor 200 is turned on in the future can be adjusted by adjusting the depth (and in some cases, the angle) of the two downward etchings. Then, a gate structure 210 is formed on the tertiary active region 2043. The gate structure 210 can not only extend across the surface of the tertiary active region 2043, but also extend to the surface above the primary active region 2041 and / or extend to the surface above the secondary active region 2042, and can be flexibly designed by those skilled in the art according to actual needs. In the case where the gate structure 210 extends above the surface of the primary active region 2041 and / or extends above the surface of the secondary active region 2042, the channel region will also extend below the surface of the primary active region 2041 and / or extend below the surface of the secondary active region 2042 accordingly. Next, by, for example, an ion implantation process of the second doping type, for example, a source region 2061 is formed in the primary active region 2041 and a drain region 2062 is formed in the secondary active region 2042, thereby obtaining a structure having the following characteristics: Fig. 9 Transistor 200 of the structure shown.

[0067] exist Fig. 9 In the illustrated embodiment, the conductive channel 208 is illustrated as part 2081, but it is understood that this is merely illustrative and not restrictive, and those skilled in the art will appreciate that the conductive channel 208 may also have any other suitable structure. Other example structures of the conductive channel 208 will be further described below.

[0068] Fig.10 Schematically shows a variation 200A of the transistor 200 according to some embodiments of the present disclosure. Fig.10 As shown, the right boundary of the source region 2061 is located at a certain distance from the boundary between the primary active region 2041 and the tertiary active region 2043, the left boundary of the drain region 2062 is located at the boundary between the secondary active region 2042 and the tertiary active region 2043, and the gate structure 210 extends between the left boundary of the drain region 2062 and the right boundary of the source region 2061. When the transistor 200A is turned on, the conductive channel 208 formed in the channel region includes a portion 2081 and a portion 2082 located between the source region 2061 and the portion 2081, and the portion 2082 and the source region 2061 are aligned with each other in the first direction z.

[0069] Fig.11 Schematically shows a variation 200B of the transistor 200 according to some other embodiments of the present disclosure. Fig.11 As shown, the right boundary of the source region 2061 is located at the junction of the primary active region 2041 and the tertiary active region 2043, the left boundary of the drain region 2062 is located at a certain distance from the junction of the secondary active region 2042 and the tertiary active region 2043, and the gate structure 210 extends between the left boundary of the drain region 2062 and the right boundary of the source region 2061. When the transistor 200B is turned on, the conductive channel 208 formed in the channel region includes a portion 2081 and a portion 2083 located between the drain region 2062 and the portion 2081, and the portion 2083 and the drain region 2062 are aligned with each other in the first direction z.

[0070] Fig.12 Schematically shows a variation 200C of the transistor 100 according to some other embodiments of the present disclosure. Fig.12 As shown, the right boundary of the source region 2061 is located at a certain distance from the boundary between the primary active region 2041 and the tertiary active region 2043, the left boundary of the drain region 2062 is located at a certain distance from the boundary between the secondary active region 2042 and the tertiary active region 2043, and the gate structure 210 extends between the left boundary of the drain region 2062 and the right boundary of the source region 2061. When the transistor 200C is turned on, the conductive channel 208 formed in the channel region includes a portion 2081, a portion 2082 located between the source region 2061 and the portion 2081, and a portion 2083 located between the drain region 2062 and the portion 2081, the portion 2082 and the source region 2061 are aligned with each other in the first direction z, and the portion 2083 and the drain region 2062 are aligned with each other in the first direction z.

[0071] Figures 10 to 12The case where the channel region "invades" the primary active region 2041 and / or the secondary active region 2042 from the tertiary active region 2043 is shown. In other cases, the source region 2061 can "invade" the tertiary active region 2043 from the primary active region 2041 and / or the drain region 2062 can "invade" the tertiary active region 2043 from the secondary active region 2042, which can still achieve a longer channel compared to a conventional transistor structure when the lateral spacing between the source region 2061 and the drain region 2062 is constant, thereby alleviating the short channel effect.

[0072] In some embodiments, the transistor 200 further includes a plurality of grooves 212 disposed between the source region 2061 and the drain region 2062, and the channel region may be at least partially defined by the plurality of grooves 212, so that the conductive channel 208 may include portions extending along the surfaces of the plurality of grooves 212. For example, Fig.13 As shown, the variant 200D of the transistor 200 includes two grooves 2121 and 2122 disposed between the source region 2061 and the drain region 2062. When the transistor 200D is turned on, the conductive channel 208 formed in the channel region includes portions extending along the surfaces of the grooves 2121 and 2122. It can be understood that although Fig.13 The groove 2121 and the groove 2122 shown have the same shape, but this is only exemplary and not restrictive. The groove 2121 and the groove 2122 may also have different shapes, and may also have the same or different sizes in various dimensions. Those skilled in the art may set any number of grooves between the source region 2061 and the drain region 2062 according to actual needs, optionally a slope or plane for connecting any two adjacent grooves, optionally a slope or plane for connecting the source region 2061 and the leftmost groove, and optionally a slope or plane for connecting the drain region 2062 and the rightmost groove, so as to obtain a tortuous conductive channel with a desired length.

[0073] It is understood that any embodiments of transistor 100 and transistor 200 and variations thereof may be referenced to each other, and any aspects of these embodiments may be combined with each other to provide further additional embodiments.

[0074] The present disclosure also provides a semiconductor device, which includes the transistor according to any embodiment of the present disclosure. Such a semiconductor device may be, for example, but not limited to, a semiconductor device or integrated circuit that uses one or more of the transistors as a switch or a switch circuit.

[0075] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words so used are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or at other orientations), and the relative spatial relationships will be interpreted accordingly.

[0076] In the specification and claims, when an element is referred to as being "on", "attached", "connected", "coupled", or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being "directly" "on", "directly attached", "directly connected", "directly coupled", or "directly contacting" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is located above or below an adjacent feature.

[0077] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the technical field, background technology, utility model content, or detailed description.

[0078] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0079] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0080] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0081] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0082] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0083] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are equally possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0084] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A transistor, characterized in that: The transistor comprises: a substrate in which an active region having a first doping type is disposed; A gate structure disposed on the active area; a source region and a drain region of a second doping type disposed in the active region on opposite sides of the gate structure, wherein the source region and the drain region are offset relative to each other in a first direction parallel to a thickness direction of the substrate; an inclined surface disposed between the source region and the drain region, the inclined surface extending non-parallel to the first direction and non-parallel to a second direction perpendicular to the thickness direction of the substrate; and A channel region is arranged in the active region and is located between the source region and the drain region, and the channel region is at least partially defined by the inclined surface, wherein when the transistor is turned on, a conductive channel connecting the source region and the drain region is formed in the channel region, and the conductive channel includes a first portion extending along the inclined surface.

2. The transistor according to claim 1, characterized in that An included angle between the inclined surface and the second direction is between 45° and 75°.

3. The transistor according to claim 1, characterized in that The conductive channel further includes at least one of the following: a second portion located between the source region and the first portion, the second portion and the source region being aligned with each other in the first direction; A third portion is located between the drain region and the first portion, and the third portion and the drain region are aligned with each other in the first direction.

4. The transistor according to claim 1, characterized in that The transistor further includes a recess disposed between the source region and the drain region, the channel region being at least partially defined by the recess, wherein the conductive channel includes a fourth portion extending along a surface of the recess.

5. The transistor according to claim 4, characterized in that The groove includes the inclined surface, and the fourth portion of the conductive channel includes the first portion.

6. The transistor according to claim 4, characterized in that The groove is connected to the inclined surface, and the fourth portion of the conductive channel is connected to the first portion.

7. A transistor, characterized in that: The transistor comprises: a substrate in which an active region having a first doping type is disposed; A gate structure disposed on the active area; a source region and a drain region of a second doping type disposed in the active region on opposite sides of the gate structure, wherein the source region and the drain region are offset relative to each other in a first direction parallel to a thickness direction of the substrate; A groove disposed between the source region and the drain region; and A channel region is arranged in the active region and is located between the source region and the drain region, and the channel region is at least partially defined by the groove, wherein when the transistor is turned on, a conductive channel connecting the source region and the drain region is formed in the channel region, and the conductive channel includes a first portion extending along the surface of the groove.

8. The transistor according to claim 7, characterized in that The sidewall of the groove extends along the first direction; or The sidewall and / or bottom surface of the groove extends non-parallel to the first direction and non-parallel to a second direction perpendicular to the thickness direction of the substrate.

9. The transistor according to claim 7, characterized in that The conductive channel further includes at least one of the following: a second portion located between the source region and the first portion, the second portion and the source region being aligned with each other in the first direction; A third portion is located between the drain region and the first portion, and the third portion and the drain region are aligned with each other in the first direction.

10. The transistor according to claim 7, characterized in that The transistor further includes a plurality of recesses disposed between the source region and the drain region, the channel region being at least partially defined by the plurality of recesses, wherein the conductive channel includes portions extending along surfaces of the plurality of recesses.

11. A semiconductor device, characterized in that: The semiconductor device includes the transistor according to any one of claims 1 to 10.

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