Anti-reverse-connection anti-surge protection circuit

Abstract

The utility model discloses an anti-reverse-connection anti-surge protection circuit, and belongs to the technical field of electronics. The utility model relates to an anti-reverse-connection anti-surge protection circuit. Comprising a reverse connection protection unit, a delay unit, a bypass resistor unit, a first resistor series branch, a second resistor series branch, a third resistor series branch, a diode series branch, a bidirectional breakdown diode, an eleventh resistor, a twelfth resistor, a fourth voltage-regulator tube, a fifth voltage-regulator tube, a sixth voltage-regulator tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. The anti-reverse connection and anti-surge protection circuit provided by the utility model not only has an anti-surge function, but also can prevent reverse connection.

Description

Technical Field

[0001] The utility model belongs to the field of electronic technology, and particularly relates to an anti-reverse connection and anti-surge protection circuit. Background Art

[0002] Surge refers to the instantaneous voltage or current that exceeds the normal operating range. Surge protection design is usually required in the design of electronic devices to ensure that the electronic devices are not affected by surges. The existing surge protection circuit has a single function and usually only has a surge protection function. Utility Model Content

[0003] The utility model aims to overcome the deficiencies of the prior art and provide an anti-reverse connection and anti-surge protection circuit.

[0004] The purpose of the utility model is achieved through the following technical solutions: an anti-reverse connection and anti-surge protection circuit, including a reverse connection protection unit, a delay unit, a bypass resistor unit, a first resistor series branch, a second resistor series branch, a third resistor series branch, a diode series branch, a bidirectional breakdown diode, an eleventh resistor, a twelfth resistor, a fourth voltage regulator tube, a fifth voltage regulator tube, a sixth voltage regulator tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;

[0005] Two ends of the bidirectional breakdown diode are respectively configured as a first current input end and a second current input end of the protection circuit, and a first end of the reverse connection protection unit is connected to the first current input end;

[0006] An eleventh resistor is connected in series between the source and the gate of the second NMOS tube, a fifth voltage regulator tube is connected in series between the source and the gate of the second NMOS tube, and a sixth voltage regulator tube is connected in series between the source and the drain of the second NMOS tube;

[0007] The source of the second NMOS tube is connected to the second end of the reverse connection protection unit, the gate of the second NMOS tube is connected to the first end of the first resistor series branch, and the second end of the first resistor series branch is connected to the second current input end via the diode series branch;

[0008] The gate of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the first NMOS tube is connected to the second current input terminal via the second resistor series branch, the source of the first NMOS tube is connected to the second end of the reverse connection protection unit, and the drain of the first NMOS tube is connected to the first end of the delay unit via the twelfth resistor;

[0009] The fourth voltage regulator is connected in series between the first end and the second end of the delay unit, the second end of the delay unit is connected to the second end of the reverse connection protection unit, the first end of the delay unit is connected to the first end of the third resistor series branch, the second end of the third resistor series branch is configured as the second current output end of the protection circuit, and the second current output end is connected to the second current input end;

[0010] The source of the third NMOS tube is connected to the second end of the reverse connection protection unit, the gate of the third NMOS tube is connected to the first end of the delay unit, and the drain of the third NMOS tube is configured as the first current output end of the protection circuit;

[0011] The gate of the fourth NMOS tube is connected to the first end of the delay unit, the source of the fourth NMOS tube is connected to the second end of the reverse connection protection unit, and the drain of the fourth NMOS tube is connected to the first current output end;

[0012] The first end of the bypass resistor unit is connected to the second end of the reverse connection protection unit, and the second end of the bypass resistor unit is connected to the first current output end.

[0013] Furthermore, the reverse connection protection unit includes a seventh diode and an eighth diode, the cathode of the seventh diode is connected to the cathode of the eighth diode, the anode of the seventh diode is connected to the anode of the eighth diode, the cathode of the seventh diode is configured as the first end of the reverse connection protection unit, and the anode of the seventh diode is configured as the second end of the reverse connection protection unit.

[0014] Further, the first resistor series branch includes a seventh resistor and a tenth resistor, one end of the tenth resistor is configured as the first end of the first resistor series branch, the other end of the tenth resistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is configured as the second end of the first resistor series branch.

[0015] Furthermore, the diode series branch includes a first Zener diode and a second Zener diode, the cathode of the first Zener diode is connected to the second current input end, the anode of the first Zener diode is connected to the cathode of the second Zener diode, and the cathode of the second Zener diode is connected to the second end of the first resistor series branch.

[0016] Further, the second resistor series branch includes an eighth resistor, a fifth resistor, a third resistor and a first resistor connected in series in sequence, one end of the eighth resistor is configured as the first end of the second resistor series branch, and one end of the first resistor is configured as the second end of the second resistor series branch.

[0017] Further, the third resistor series branch includes a ninth resistor, a sixth resistor, a fourth resistor and a second resistor connected in series in sequence, one end of the ninth resistor is configured as a first end of the third resistor series branch, and one end of the second resistor is configured as a second end of the third resistor series branch.

[0018] Further, the delay unit includes a first capacitor, a second capacitor and a thirteenth resistor, the first end of the first capacitor is configured as the first end of the delay unit, the second end of the first capacitor is configured as the second end of the delay unit, the second capacitor is connected in parallel with the first capacitor, the first end of the thirteenth resistor is connected to the first end of the first capacitor, and the second end of the thirteenth resistor is connected to the second end of the first capacitor.

[0019] Further, the bypass resistor unit includes a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor, the first end of the fourteenth resistor is configured as the first end of the bypass resistor unit, the second end of the fourteenth resistor is configured as the second end of the bypass resistor unit, and the fifteenth resistor, the sixteenth resistor and the seventeenth resistor are all connected in parallel with the fourteenth resistor.

[0020] The beneficial effect of the utility model is that the anti-reverse connection and anti-surge protection circuit in the utility model not only has the function of surge protection, but also can prevent reverse connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The utility model is a circuit principle diagram of the anti-reverse connection and anti-surge protection circuit. DETAILED DESCRIPTION

[0022] The following will be combined with the embodiments to clearly and completely describe the technical solution of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0023] See also Figure 1 The utility model provides an anti-reverse connection and anti-surge protection circuit:

[0024] like Figure 1As shown, a reverse connection and anti-surge protection circuit includes a reverse connection protection unit, a delay unit, a bypass resistor unit, a first resistor R1 series branch, a second resistor R2 series branch, a third resistor R3 series branch, a diode series branch, a bidirectional breakdown diode D3, an eleventh resistor R11, a twelfth resistor R12, a fourth voltage regulator D4, a fifth voltage regulator D5, a sixth voltage regulator D6, a first NMOS tube Q1, a second NMOS tube Q2, a third NMOS tube Q3 and a fourth NMOS tube Q4. The reverse connection protection unit includes a seventh diode D7 and an eighth diode D8, the delay unit includes a first capacitor C1, a second capacitor C2 and a thirteenth resistor R13, the bypass resistor unit includes a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a seventeenth resistor R17, the diode series branch includes a first voltage regulator tube D1 and a second voltage regulator tube D2, the first resistor R1 series branch includes a seventh resistor R7 and a tenth resistor R10, the second resistor R2 series branch includes an eighth resistor R8, a fifth resistor R5, a third resistor R3 and a first resistor R1 connected in series in sequence, and the third resistor R3 series branch includes a ninth resistor R9, a sixth resistor R6, a fourth resistor R4 and a second resistor R2 connected in series in sequence.

[0025] Two ends of the bidirectional breakdown diode D3 are respectively configured as a first current input terminal and a second current input terminal of the protection circuit.

[0026] A cathode of the seventh diode D7 is connected to the first current input terminal, a cathode of the seventh diode D7 is connected to a cathode of the eighth diode D8, and an anode of the seventh diode D7 is connected to an anode of the eighth diode D8.

[0027] The first end of the eleventh resistor R11 is connected to the source of the second NMOS transistor Q2, and the second end of the eleventh resistor R11 is connected to the gate of the second NMOS transistor Q2. The anode of the fifth voltage regulator tube D5 is connected to the source of the second NMOS tube Q2, and the cathode of the fifth voltage regulator tube D5 is connected to the gate of the second NMOS tube Q2. The anode of the sixth voltage regulator tube D6 is connected to the source of the second NMOS tube Q2, and the cathode of the sixth voltage regulator tube D6 is connected to the drain of the second NMOS tube Q2.

[0028] The source of the second NMOS tube Q2 is connected to the anode of the seventh diode D7, the gate of the second NMOS tube Q2 is connected to the first end of the tenth resistor R10, the second end of the tenth resistor R10 is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the anode of the second voltage regulator tube D2, the cathode of the second voltage regulator tube D2 is connected to the anode of the first voltage regulator tube D1, and the cathode of the first voltage regulator tube D1 is connected to the second current input end.

[0029] The gate of the first NMOS tube Q1 is connected to the drain of the second NMOS tube Q2, the source of the first NMOS tube Q1 is connected to the anode of the seventh diode D7, the gate of the first NMOS tube Q1 is connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the second current input end.

[0030] The drain of the first NMOS transistor Q1 is connected to the first end of the twelfth resistor R12 , the second end of the twelfth resistor R12 is connected to the cathode of the fourth voltage regulator tube D4 , and the anode of the fourth voltage regulator tube D4 is connected to the anode of the seventh diode D7 .

[0031] The first end of the ninth resistor R9 is connected to the cathode of the fourth voltage-stabilizing tube D4, the second end of the ninth resistor R9 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is configured as the second current output end of the protection circuit, and the second current output end is connected to the second current input end.

[0032] The first end of the first capacitor C1 is connected to the cathode of the fourth voltage-stabilizing tube D4, the second end of the first capacitor C1 is connected to the anode of the seventh diode D7, the second capacitor C2 is connected to the first capacitor C1 in parallel, the first end of the thirteenth resistor R13 is connected to the first end of the first capacitor C1, and the second end of the thirteenth resistor R13 is connected to the second end of the first capacitor C1.

[0033] The source of the third NMOS tube Q3 is connected to the anode of the seventh diode D7, the gate of the third NMOS tube Q3 is connected to the cathode of the fourth voltage regulator tube D4, and the drain of the third NMOS tube Q3 is configured as the first current output end of the protection circuit.

[0034] The gate of the fourth NMOS tube Q4 is connected to the cathode of the fourth voltage regulator tube D4, the source of the fourth NMOS tube Q4 is connected to the anode of the seventh diode D7, and the drain of the fourth NMOS tube Q4 is connected to the first current output end.

[0035] A first end of the fourteenth resistor R14 is connected to the anode of the seventh diode D7, a second end of the fourteenth resistor R14 is connected to the first current output end, and the fifteenth resistor R15, the sixteenth resistor R16 and the seventeenth resistor R17 are all connected in parallel with the fourteenth resistor R14.

[0036] This embodiment is used to prevent surge and reverse connection of the 270VDC power supply line. After the 270V power supply is connected, the cut-off time of the third NMOS tube Q3 and the fourth NMOS tube Q4 is 4ms. During the cut-off time, the load capacitor (160UF) is charged to 220V through the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16 and the seventeenth resistor R17, and the charging current is less than 60A; after 4ms, after 10ms, the third NMOS tube Q3 and the fourth NMOS tube Q4 enter the fully turned-on state from the cut-off state, and the high-power load at the output end can work after the conduction. The delay of 4ms is achieved by the thirteenth resistor R13, the first capacitor C1 and the second capacitor C2.

[0037] The working process of the input voltage rising from 0V to 220V is as follows: when the input voltage is lower than the 195V voltage of the first voltage regulator tube D1 and the second voltage regulator tube D2, the second NMOS tube Q2 stops, the voltage of the sixth voltage regulator tube D6 is high level, the first NMOS tube Q1 is turned on, the voltage of the fourth voltage regulator tube D4 is kept at a low level, then the third NMOS tube Q3 and the fourth NMOS tube Q4 are not turned on, and the output terminal voltage flows through the bypass resistor (the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16 and the seventeenth resistor R17). Due to the charging delay effect of the first capacitor C1 and the second capacitor C2, the first NMOS tube Q1 is turned on with the third NMOS tube Q3 and the fourth NMOS tube Q4 in advance, so the third NMOS tube Q3 and the fourth NMOS tube Q4 are always in the off state.

[0038] When the input voltage is higher than 220V, the voltage of the fifth voltage regulator tube D5 is 15V, the second NMOS tube Q2 is turned on to make the voltage of the sixth voltage regulator tube D6 low level, the first NMOS tube Q1 is turned off, and the 15V voltage of the fourth voltage regulator tube D4 turns on the third NMOS tube Q3 and the fourth NMOS tube Q4.

[0039] Delay trigger voltage jump: When the input voltage drops from high to below 220V, the voltage of the first capacitor C1 and the second capacitor C2 in the delay circuit drops to 0V within 6us, and the third NMOS tube Q3 and the fourth NMOS tube Q4 quickly enter the cut-off state. In this 6us, the input voltage is not easy to instantly return to 270V. Since the third NMOS tube Q3 and the fourth NMOS tube Q4 are in the on-state and linear region with small internal resistance, the capacitor voltage of the load rises from 220V to 270V instantly, and the 50V voltage difference may cause the impact current to exceed the standard. The seventh diode D7 and the eighth diode D8 are used at the front end as reverse connection protection, which can also block the current loop when the trigger voltage jumps.

[0040] The above is only a preferred embodiment of the utility model. It should be understood that the utility model is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the utility model, and should be within the scope of protection of the claims attached to the utility model.

Claims

1. A reverse connection and surge protection circuit, characterized in that: It includes a reverse connection protection unit, a delay unit, a bypass resistor unit, a first resistor series branch, a second resistor series branch, a third resistor series branch, a diode series branch, a bidirectional breakdown diode, an eleventh resistor, a twelfth resistor, a fourth voltage regulator tube, a fifth voltage regulator tube, a sixth voltage regulator tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; Two ends of the bidirectional breakdown diode are respectively configured as a first current input end and a second current input end of the protection circuit, and a first end of the reverse connection protection unit is connected to the first current input end; An eleventh resistor is connected in series between the source and the gate of the second NMOS tube, a fifth voltage regulator tube is connected in series between the source and the gate of the second NMOS tube, and a sixth voltage regulator tube is connected in series between the source and the drain of the second NMOS tube; The source of the second NMOS tube is connected to the second end of the reverse connection protection unit, the gate of the second NMOS tube is connected to the first end of the first resistor series branch, and the second end of the first resistor series branch is connected to the second current input end via the diode series branch; The gate of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the first NMOS tube is connected to the second current input terminal via the second resistor series branch, the source of the first NMOS tube is connected to the second end of the reverse connection protection unit, and the drain of the first NMOS tube is connected to the first end of the delay unit via the twelfth resistor; The fourth voltage regulator is connected in series between the first end and the second end of the delay unit, the second end of the delay unit is connected to the second end of the reverse connection protection unit, the first end of the delay unit is connected to the first end of the third resistor series branch, the second end of the third resistor series branch is configured as the second current output end of the protection circuit, and the second current output end is connected to the second current input end; The source of the third NMOS tube is connected to the second end of the reverse connection protection unit, the gate of the third NMOS tube is connected to the first end of the delay unit, and the drain of the third NMOS tube is configured as the first current output end of the protection circuit; The gate of the fourth NMOS tube is connected to the first end of the delay unit, the source of the fourth NMOS tube is connected to the second end of the reverse connection protection unit, and the drain of the fourth NMOS tube is connected to the first current output end; The first end of the bypass resistor unit is connected to the second end of the reverse connection protection unit, and the second end of the bypass resistor unit is connected to the first current output end.

2. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The reverse connection protection unit includes a seventh diode and an eighth diode, the cathode of the seventh diode is connected to the cathode of the eighth diode, the anode of the seventh diode is connected to the anode of the eighth diode, the cathode of the seventh diode is configured as the first end of the reverse connection protection unit, and the anode of the seventh diode is configured as the second end of the reverse connection protection unit.

3. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The first resistor series branch includes a seventh resistor and a tenth resistor, one end of the tenth resistor is configured as the first end of the first resistor series branch, the other end of the tenth resistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is configured as the second end of the first resistor series branch.

4. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The diode series branch includes a first voltage regulator tube and a second voltage regulator tube, the cathode of the first voltage regulator tube is connected to the second current input end, the anode of the first voltage regulator tube is connected to the cathode of the second voltage regulator tube, and the cathode of the second voltage regulator tube is connected to the second end of the first resistor series branch.

5. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The second resistor series branch includes an eighth resistor, a fifth resistor, a third resistor and a first resistor connected in series in sequence, one end of the eighth resistor is configured as the first end of the second resistor series branch, and one end of the first resistor is configured as the second end of the second resistor series branch.

6. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The third resistor series branch includes a ninth resistor, a sixth resistor, a fourth resistor and a second resistor connected in series in sequence, one end of the ninth resistor is configured as a first end of the third resistor series branch, and one end of the second resistor is configured as a second end of the third resistor series branch.

7. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The delay unit includes a first capacitor, a second capacitor and a thirteenth resistor, the first end of the first capacitor is configured as the first end of the delay unit, the second end of the first capacitor is configured as the second end of the delay unit, the second capacitor is connected in parallel with the first capacitor, the first end of the thirteenth resistor is connected to the first end of the first capacitor, and the second end of the thirteenth resistor is connected to the second end of the first capacitor.

8. The anti-reverse connection and anti-surge protection circuit according to claim 1, characterized in that: The bypass resistor unit includes a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor, the first end of the fourteenth resistor is configured as the first end of the bypass resistor unit, the second end of the fourteenth resistor is configured as the second end of the bypass resistor unit, and the fifteenth resistor, the sixteenth resistor and the seventeenth resistor are all connected in parallel with the fourteenth resistor.

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