Integrated circuit

Abstract

An integrated circuit includes a complementary transistor, a first source / drain contact, a second source / drain contact, and an interconnect structure. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is over the first transistor in the vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The interconnect structure is electrically coupled to the first source / drain contact and the second source / drain contact, the interconnect structure including an inclined portion extending from the first source / drain contact to the second source / drain contact at an offset angle from a vertical direction. Some embodiments of the present disclosure are used for simplifying the process flow and reducing the cost.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a complementary field effect transistor, and more particularly to a complementary field effect transistor having an inclined conduction through a substrate layer. Background Art

[0002] There is an ongoing demand for computing power in electronic devices, including smartphones, tablet computers, desktop computers, notebook computers, and many other types of electronic devices. Integrated circuits provide computing power for these electronic devices. One way to increase the computing power of an integrated circuit is to increase the number of transistors and other integrated circuit features that can be included in a given area of ​​a semiconductor substrate.

[0003] Complementary field effect transistors (CFETs) can be used to increase the density of transistors in integrated circuits. Complementary field effect transistors (CFETs) can include vertically stacked N-type transistors and P-type transistors. The gate electrodes of the N-type transistor and the P-type transistor can be electrically short-circuited to each other. Utility Model Content

[0004] The purpose of the embodiments disclosed herein is to provide an integrated circuit, including a complementary transistor, a first source / drain contact, a second source / drain contact and an interconnection structure. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is located above the first transistor in a vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The interconnection structure is electrically coupled to the first source / drain contact and the second source / drain contact, and the interconnection structure includes an inclined portion, which extends from the first source / drain contact to the second source / drain contact at an offset angle from the vertical direction.

[0005] The purpose of the embodiments disclosed herein is to propose another integrated circuit, including a complementary transistor, a first source / drain contact, a second source / drain contact and a conductive through-substrate layer. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is located above the first transistor in a vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The conductive through-substrate layer is electrically coupled to the first source / drain contact and the second source / drain contact, and the conductive through-substrate layer includes a vertical portion extending through the first source / drain contact in the vertical direction and an inclined portion extending from the first source / drain contact to the second source / drain contact in the vertical direction at an offset angle.

[0006] The purpose of the embodiments disclosed herein is to propose another integrated circuit, including a complementary transistor, a first source / drain contact, a second source / drain contact and an interconnection structure. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is located above the first transistor in a vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The interconnection structure is electrically coupled to the first source / drain contact and the second source / drain contact, and the interconnection structure includes a seed layer located in an opening of the first source / drain contact and an inclined portion located on the seed layer, and the inclined portion extends from the first source / drain contact to the second source / drain contact at an offset angle from the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figures 1A to 1F is a schematic diagram of an integrated circuit including a complementary field effect transistor (CFET) according to some embodiments;

[0009] Figures 2A to 2M is a schematic cross-sectional view of an integrated circuit at various processing stages according to some embodiments;

[0010] FIG. 3A to FIG. 3D is a schematic perspective view of an integrated circuit at various processing stages according to some embodiments;

[0011] FIG. 4A to FIG. 4Dis a schematic perspective view of an integrated circuit at various processing stages according to some embodiments;

[0012] Figure 5 and Figure 6 is a flow chart of a process for forming an integrated circuit according to some embodiments.

[0013]

Explanation of symbols

[0014] 100,100A:Integrated Circuit

[0015] 100B: Side

[0016] 101:Substrate

[0017] 102: Complementary Field Effect Transistor (CFET) / Transistor

[0018] 104, 105A: first transistor / transistor

[0019] 105,104A: Second transistor / transistor

[0020] 106,107:Semiconductor Nanostructures

[0021] 108:interface gate dielectric layer

[0022] 110: High K gate dielectric layer

[0023] 112,113: Gate Metal

[0024] 114: Internal spacer

[0025] 116,117: Source / drain region

[0026] 118,119: Source / drain contacts

[0027] 120,121: Silicide

[0028] 122,123,124,125: Conductive layer

[0029] 126: Isolation Structure

[0030] 127,150: Semiconductor layer

[0031] 128: Interlayer dielectric layer

[0032] 129,130,134,136,138,158,172,176,180: Dielectric layer

[0033] 131: Sidewall spacer

[0034] 132: Gate cap metal

[0035] 133: Semiconductor layer / semiconductor substrate

[0036] 135: Top

[0037] 137: Bottom surface

[0038] 139: Interface

[0039] 144: Gate contact

[0040] 146: Conductive via

[0041] 149:Semiconductor fins

[0042] 152,154: Sacrificial semiconductor layer

[0043] 156: Virtual gate structure

[0044] 160: Polysilicon

[0045] 164: Source / drain trench

[0046] 165: Sacrificial semiconductor nanostructures

[0047] 166: Depression

[0048] 170: Gap

[0049] 174,182: Polymer materials

[0050] 220,220A,220B: Source / drain contacts

[0051] 250,450: Conductive through-substrate layer (TSL)

[0052] 300:Mask

[0053] 310,310M: Open

[0054] 330,410X,450O: inclined part

[0055] 330A: Vertical opening

[0056] 410: Seed layer

[0057] 450A: Vertical section

[0058] 1000,2000:Method

[0059] 1100,1200,1300,1400,1500,2100,2200,2300,2400,2500,2600: Action

[0060] AA,BB,CC,DD,EE:Hatch line

[0061] X,Y,Z: Direction / Axis DETAILED DESCRIPTION

[0062] In the following description, many thicknesses and many materials are described for various layers and various structures within the integrated circuit die. Specific dimensions and materials are given by way of example of various embodiments. Based on the content of some embodiments of the present disclosure, those skilled in the art will recognize that other dimensions and other materials can be used in many cases without departing from the scope of some embodiments of the present disclosure.

[0063] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the description, a first feature is formed above or on a second feature, which may include an embodiment in which the first feature and the second feature are formed in direct contact, which may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or text in various examples. This repetition is for the purpose of simplicity and clarity, but is not itself used to specify the relationship between the various embodiments and / or architectures discussed.

[0064] Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to facilitate description of the relationship of one element or feature to another element or features as depicted in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be oriented in different ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0065] In the following description, certain specific details are set forth to provide a thorough understanding of the various embodiments of the present disclosure. However, those skilled in the art will appreciate that some embodiments of the present disclosure may be implemented without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0066] Unless the context requires otherwise, throughout the specification and the claims that follow, the word "comprise" and variations such as "comprises" and "comprising" are to be interpreted in an open, inclusive sense, i.e., "including, but not limited to."

[0067] The use of ordinal numbers such as first, second, and third does not necessarily imply a sequential sense of order but may simply distinguish between multiple instances of a behavior or a structure.

[0068] References throughout this specification to "an embodiment" or "one embodiment" mean that a particular feature, particular structure, or particular characteristic described in conjunction with that embodiment is included in at least some embodiments. Thus, the phrases "in an embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily all refer to the same embodiment. Furthermore, particular features, particular structures, or particular characteristics may be combined in any suitable manner in one or more embodiments.

[0069] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used in its sense, including "and / or," unless the content clearly dictates otherwise.

[0070] As used in this specification and the appended claims, the terms "fill", "fills", "filling" and "filled" include both partially filled and completely filled. For example, a conductive layer may be said to "fill" an opening, which may include the conductive layer contacting adjacent walls of the opening, or the conductive layer being present in the opening with one or more layers of different material between the conductive layer and the adjacent walls.

[0071] As used in this specification and the appended claims, the terms "surround," "surrounds," "surrounding," and "surrounded" include both completely surrounded and partially surrounded. For example, a hexagonal volume (e.g., a rectangular prism) being "surrounded" includes the meaning of being completely surrounded by material on all six sides, or may be partially surrounded such that one or more of the six sides are not completely covered by the material and at least a portion is exposed.

[0072] Embodiments of the present disclosure provide an integrated circuit of a complementary field effect transistor (CFET) with improved electrical characteristics. The complementary field effect transistor (CFET) includes a first transistor vertically stacked on a second transistor. The first transistor and the second transistor each have a plurality of semiconductor nanostructures, which serve as channel regions of the first transistor and the second transistor. A first gate metal surrounds the semiconductor nanostructure of the first transistor. A second gate metal surrounds the semiconductor nanostructure of the second transistor.

[0073] Three-dimensional (3D) stacking to form complementary field effect transistors (CFETs) has been proposed as a potential transistor architecture to further extend Moore's law. Due to the nature of three-dimensional stacked N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs), vertical local interconnects (vertical local interconnects, VLIs or conductive through-substrate layers (TSLs)) are advantageous for interconnecting the top device and the bottom device. However, the large area of ​​the vertical local interconnect (VLI) may result in a considerable gate-to-source / drain capacitance (Cgs / Cgd), which can significantly degrade the performance and / or power of complementary metal-oxide-semiconductor (CMOS) circuits. Due to potential shorting of the vertical local interconnect (VLI) through source / drain contacts and source / drain vias, the first metal layer on the top of the vertical local interconnect (VLI) may be separated from the vertical local interconnect (VLI) by a long distance, which wastes the limited routing resources of the first metal layer.

[0074] The L-shaped conductive through-substrate layer (TSL) can establish a connection while reducing the cross-sectional profile of the conductive through-substrate layer (TSL). However, the formation of the L-shaped profile generally includes at least two etching operations. When performing L-shaped patterning of the conductive through-substrate layer (TSL), time mode etching (e.g., without an etching stop layer) is also included.

[0075] Some embodiments of the present disclosure include a conductive through-substrate layer (TSL) formed to have a tilted orientation by wafer tilting during etching or by directional metal growth. In fin field effect transistor (FinFET) and nanosheet structures, the P-type source / drain and the N-type source / drain can be directly connected through the same source / drain contact without additional Z-direction losses. In a Z-direction stacked complementary field effect transistor (CFET) structure with N-type / P-type source / drain, the N-type / P-type source / drain interconnection may migrate to a three-dimensional (e.g., X, Y, and Z-direction) interconnection. The conductive through-substrate layer (TSL) of some embodiments may extend from an upper source / drain contact to a lower source / drain contact. The conductive through-substrate layer (TSL) may form a shorter path between the upper source / drain contact and the lower source / drain contact, which is beneficial in reducing the resistance of the conductive through-substrate layer (TSL). The conductive through-substrate layer (TSL) can have a reduced cross-sectional profile, which is beneficial to reduce parasitic capacitance between the conductive through-substrate layer (TSL) and adjacent structures (e.g., source / drain regions, metal gates, etc.). In some embodiments, 3D patterning can be achieved directly through a single patterning and etching operation. Directed atomic layer deposition (ALD) can also be used for tilted column deposition. Some embodiments reduce the number of patterning and etching operations, which can reduce costs and simplify the process flow.

[0076] Figure 1A and Figure 1B 1 is a diagrammatic top view of an integrated circuit 100, 100A according to various embodiments. The integrated circuit 100 includes an L-shaped conductive through-substrate layer (TSL) 250 that is wider at a lower portion than an upper portion. The integrated circuit 100A includes an inclined conductive through-substrate layer (TSL) 450 that extends diagonally from a first source / drain contact 220A to a second source / drain contact 220B at a different level. For clarity of illustration, some features may be omitted from the view in the figure. Figure 1C is a cross-sectional view of an integrated circuit 100A (or integrated circuit 100 ) according to some embodiments. Figure 1C The view can correspond to Figure 1A and Figure 1B Referring to the integrated circuit 100A, Figure 1C The same description applies to integrated circuit 100. Figures 1A to 1E and Figures 2A to 2M For understanding the following reference FIG. 3A to FIG. 3D , FIG. 4A to FIG. 4D , Figure 5 and Figure 6 The process described further provides context.

[0077] The integrated circuit 100A includes a complementary field effect transistor (CFET or cFET) 102. The complementary field effect transistor (CFET) 102 includes a first transistor 104 of a first conductivity type and a second transistor 105 of a second conductivity type. The first transistor 104 is vertically stacked on the second transistor 105. The complementary field effect transistor (CFET) 102 uses an isolation structure 126 to separate the stacked channel region of the first transistor 104 from the stacked channel region of the second transistor 105 to improve the electrical characteristics of the complementary field effect transistor (CFET) 102. In other words, a hybrid nanostructure (e.g., a hybrid sheet) including the stacked channel region of the first transistor 104, the isolation structure 126, and the stacked channel region of the second transistor 105 is formed.

[0078] The complementary field effect transistor (CFET) 102 may correspond to a gate all around transistor. The gate all around transistor structure may be patterned by any suitable method. For example, one or more optical lithography processes (including double patterning processes or multiple patterning processes) may be used to pattern the structure. Typically, the double patterning process or multiple patterning process combines an optical lithography process with a self-alignment process, thereby allowing the created pattern to have, for example, a smaller spacing than that obtainable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and an optical lithography process is used to pattern the sacrificial layer. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the gate all around structure. In addition, the gate all around complementary field effect transistor (CFET) 102 may include a plurality of semiconductor nanostructures corresponding to the channel region of the complementary field effect transistor (CFET) 102. The semiconductor nanostructure may include a nanosheet, a nanowire, or other types of nanostructures. The gate all around transistor may also be referred to as a nanostructure transistor.

[0079] Figure 1C The view is an X-view of the integrated circuit 100A, where the X-axis is the horizontal axis, the Z-axis is the vertical axis, and the Y-axis extends into and out of the drawing. As used herein, the term "X-view" corresponds to a cross-sectional view (where the X-axis is the horizontal dimension and the Z-axis is the vertical dimension). As used herein, the term "Y-view" corresponds to a cross-sectional view (where the Y-axis is the horizontal dimension and the Z-axis is the vertical dimension).

[0080] Integrated circuit 100A includes substrate 101. Substrate 101 may include a semiconductor layer, a dielectric layer, or a combination thereof. In addition, conductive structures may be formed in substrate 101 as backside conductive vias and interconnects, which will be described in more detail below. In some embodiments, substrate 101 includes a single crystalline semiconductor layer at least on a surface portion. Substrate 101 may include a single crystalline semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

[0081] In some embodiments, the substrate 101 may include a dielectric layer, the dielectric layer including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric material. In some embodiments, the substrate 101 may include shallow trench isolation regions formed in the semiconductor layer. Various configurations of the substrate 101 may be used without departing from the scope of some embodiments of the present disclosure. In some embodiments, for example, when the substrate 101 is removed before forming the backside interconnect structure, the substrate 101 is not present.

[0082] Transistor 105 is formed over substrate 101. Transistor 104 is formed over transistor 105. In some embodiments, transistor 104 is an N-type transistor and transistor 105 is a P-type transistor. However, in some embodiments, transistor 104 may be a P-type transistor and transistor 105 may be an N-type transistor.

[0083] The transistor 104 includes a plurality of semiconductor nanostructures 106. The semiconductor nanostructures 106 are stacked in a vertical direction or in a Z direction. Figure 1C In the example of FIG. 1 , there are three stacked semiconductor nanostructures 106. However, in practice, there may be only two stacked semiconductor nanostructures 106 or there may be more than three stacked semiconductor nanostructures 106 without departing from the scope of some embodiments of the present disclosure. In addition, in some embodiments, there may be only a single semiconductor nanostructure 106 and a single semiconductor nanostructure 107. The semiconductor nanostructure 106 corresponds to the channel region of the transistor 102. The semiconductor nanostructure 106 may be a nanosheet, a nanowire, or another type of nanostructure.

[0084] The transistor 105 includes a plurality of semiconductor nanostructures 107. The semiconductor nanostructures 107 are stacked in a vertical direction or in a Z direction. Figure 1CIn the example of FIG. 1 , there are three stacked semiconductor nanostructures 107. However, in practice, there may be only two stacked semiconductor nanostructures 107 or there may be more than three stacked semiconductor nanostructures 107 without departing from the scope of some embodiments of the present disclosure. The semiconductor nanostructure 107 corresponds to the channel region of the transistor 102. The semiconductor nanostructure 107 may be a nanosheet, a nanowire, or another type of nanostructure. The number of semiconductor nanostructures 107 may be the same as or different from the number of semiconductor nanostructures 106.

[0085] Semiconductor nanostructures 106 and 107 may include Si, SiGe or other semiconductor materials. In the non-limiting examples described herein, semiconductor nanostructure 106 is silicon. The vertical thickness of semiconductor nanostructure 106 may be between 2nm and 5nm. Semiconductor nanostructures 106 may be separated from each other by 4nm to 10nm in the vertical direction. Other thicknesses and materials may be used for semiconductor nanostructure 106 without departing from the scope of some embodiments of the present disclosure. Semiconductor nanostructure 107 may have the same material and size as semiconductor nanostructure 106 or may have a different semiconductor material than semiconductor nanostructure 106.

[0086] Transistors 104 and 105 include gate dielectrics. The gate dielectrics include an interfacial gate dielectric layer 108 and a high-K gate dielectric layer 110. The interfacial gate dielectric layer 108 is a low-K gate dielectric layer. The interfacial gate dielectric layer 108 is in contact with semiconductor nanostructures 106 and 107. The high-K gate dielectric layer 110 is in contact with the low-K gate dielectric layer. The interfacial gate dielectric layer 108 is located between the semiconductor nanostructure 106 and the high-K gate dielectric layer 110 and between the semiconductor nanostructure 107 and the high-K gate dielectric layer 110.

[0087] The interface gate dielectric layer 108 may include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. The interface gate dielectric layer 108 may include a relatively low-K dielectric relative to a high-K dielectric, such as hafnium oxide or other high-K dielectric materials that may be used for the gate dielectric layer of a transistor. The interface gate dielectric layer 108 may include a native oxide layer grown on the surface of the semiconductor nanostructures 106 and 107. The interface gate dielectric layer 108 may have a thickness between 0.4 nm and 2 nm. Other materials, configurations, and thicknesses may be used for the interface gate dielectric layer 108 without departing from the scope of some embodiments of the present disclosure.

[0088] The high-K gate dielectric layer includes one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The thickness of the high-K dielectric is in the range of about 1 nm to about 3 nm. Other thicknesses, deposition processes, and materials may be used for the high-K gate dielectric layer without departing from the scope of some embodiments of the present disclosure. The high-K gate dielectric layer may include a first layer and a second layer, the first layer including HfO2 having a dipole doping including La and Mg, and the second layer including a high-K ZrO layer having a crystallization.

[0089] The transistor 104 includes a gate metal 112. The gate metal 112 surrounds the semiconductor nanostructure 106. The gate metal 112 contacts the high-K gate dielectric layer 110. The gate metal 112 corresponds to the gate electrode of the transistor 104. In an example where the transistor 104 is an N-type transistor, the gate metal 112 may include a material that results in a desired work function with the semiconductor nanostructure 106. In one example, the gate metal 112 includes titanium aluminum, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive materials. In some embodiments, the gate metal 112 surrounds the semiconductor nanostructure 106 on four sides (e.g., top, bottom, left, and right). In some embodiments, such as in a forksheet transistor, the gate metal 112 may surround the semiconductor nanostructure 106 on three sides, while the gate metal 112 is substantially absent on the fourth side. For example, the gate metal 112 may be present on the outer edge of the fourth side and may occupy less than about 5% of the area of ​​the fourth side.

[0090] Figure 1C A single gate metal 112 is illustrated. However, in practice, the gate electrode of the transistor 104 may include multiple metal layers. For example, the gate metal 112 may include one or more liner layers or adhesive layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. The gate metal 112 may include a gate fill material that fills the remaining volume between the semiconductor nanostructures 106 after the one or more liner layers have been deposited. Various materials, combinations of materials, and configurations may be used for the gate metal 112 without departing from the scope of some embodiments of the present disclosure.

[0091] The transistor 105 includes a gate metal 113. The gate metal 113 surrounds the semiconductor nanostructure 107. The gate metal 113 contacts the high-K gate dielectric layer 110. The gate metal 113 corresponds to a gate electrode of the transistor 105. In an example where the transistor 105 is a P-type transistor, the gate metal 113 may include a material that results in a desired work function with the semiconductor nanostructure 107. In one example, the gate metal 113 includes titanium nitride, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive materials.

[0092] Figure 1C A single gate metal 113 is illustrated. However, in reality, the gate from transistor 105 may include multiple metal layers surrounding semiconductor nanostructures 107. For example, gate metal 112 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. Gate metal 113 may include a gate fill material that fills the remaining volume between semiconductor nanostructures 107 after one or more liner layers have been deposited. Various materials, combinations of materials, and configurations may be used for gate metal 113 without departing from the scope of some embodiments of the present disclosure.

[0093] The transistor 104 includes a source / drain region 116. The source / drain region 116 contacts each semiconductor nanostructure 106. Each semiconductor nanostructure 106 extends along the X direction between the source / drain regions 116. The source / drain region 116 includes a semiconductor material. The transistor 105 includes a source / drain region 117. The source / drain region 117 contacts each semiconductor nanostructure 107. Each semiconductor nanostructure 107 extends along the X direction between the source / drain regions 117. The source / drain region 117 includes a semiconductor material.

[0094] In an example where transistor 104 is an N-type transistor and transistor 105 is a P-type transistor, source / drain region 116 may be doped with an N-type doping species. The N-type doping species may include phosphorus (P), arsenic (As), or other N-type doping species. In the case of a P-type transistor, source / drain region 117 may be doped with a P-type doping species. The P-type doping species may include boron (B) or other P-type doping species. Doping may be performed in-situ during the epitaxial growth of source / drain region 117. Without departing from the scope of some embodiments of the present disclosure, source / drain regions 116 and 117 may include other materials and structures.

[0095] As used herein, the term "source / drain region" may refer to a source region or a drain region, either individually or collectively, depending on the context. Thus, one of the source / drain regions 116 may be a source region while the other source / drain region 116 is a drain region, or vice versa. Furthermore, in some cases, one or both of the source / drain regions 116 may be shared with one or more laterally adjacent transistors.

[0096] Transistors 104 and 105 each include an internal spacer 114. Without departing from the scope of some embodiments of the present disclosure, the internal spacer 114 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. In one example, the internal spacer 114 includes silicon carbon oxynitride.

[0097] The internal spacer 114 of transistor 104 physically separates the gate metal 112 from the source / drain region 116. This prevents a short circuit between the gate metal 112 and the source / drain region 116. The internal spacer 114 of transistor 105 physically separates the gate metal 113 from the source / drain region 117. This prevents a short circuit between the gate metal 113 and the source / drain region 117.

[0098] The transistor 104 may include source / drain contacts 118. Each source / drain contact 118 is located above and electrically connected to a corresponding source / drain region 116. An electrical signal may be applied to the source / drain region 116 via the source / drain contact 118. The source / drain contact 118 may include a silicide 120. The silicide 120 is formed on top of the source / drain region 116. The silicide 120 may include titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicides.

[0099] The source / drain contact 118 may also include a conductive layer 122 on the silicide 120. The conductive layer 122 may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The source / drain contact 118 may also include a conductive layer 124 on the conductive layer 122. The conductive layer 124 may include a conductive material, such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for the source / drain contact 118 without departing from the scope of some embodiments of the present disclosure.

[0100] The transistor 105 may include source / drain contacts 119. Each source / drain contact 119 is located under a corresponding source / drain region 117 and is electrically connected to the corresponding source / drain region 117. An electrical signal may be applied to the source / drain region 117 via the source / drain contact 119. The source / drain contact 119 may include silicide 121. The silicide 121 is formed at the bottom of the source / drain region 117. The silicide 121 may include titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicides.

[0101] The source / drain contact 119 may also include a conductive layer 123 on the silicide 121. The conductive layer 123 may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The source / drain contact 119 may also include a conductive layer 125 on the conductive layer 123. The conductive layer 125 may include a conductive material, such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for the source / drain contact 119 without departing from the scope of some embodiments of the present disclosure.

[0102] The transistor 102 includes sidewall spacers 131. The sidewall spacers 131 are located near the uppermost portion of the gate metal 112 and electrically isolate the gate metal 112 from the source / drain contacts 118. The sidewall spacers 131 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric material. Other thicknesses and materials may be used for the sidewall spacers 131 without departing from the scope of some embodiments of the present disclosure.

[0103] The transistor 102 may include a gate cap metal 132 located on the uppermost portion of the gate metal 112. In some embodiments, the gate cap metal 132 includes tungsten, fluorine free tungsten, or other suitable conductive materials. The gate cap metal 132 may have a height between 1 nm and 10 nm. Other configurations, materials, and thicknesses may be used for the gate cap metal 132 without departing from the scope of some embodiments of the present disclosure.

[0104] Substrate 101 may include dielectric layer 136 and dielectric layer 138. Dielectric layer 138 may be positioned to contact the sidewalls of source / drain contacts 119 and the lowest portion of the interface gate dielectric layer 108 of transistor 105. Dielectric layer 138 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorinated silicate glass (FSG), low-K dielectric material, or other dielectric material. Dielectric layer 136 is positioned to contact dielectric layer 138. Dielectric layer 136 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorinated silicate glass (FSG), low-K dielectric material, or other dielectric material.

[0105] The complementary field effect transistor (CFET) 102 can be operated by applying voltage to the source / drain regions 116 / 117 and the gate metal 112 / 113. The voltage can be applied to the source / drain regions 116 / 117 via the source / drain contacts 118 / 119. Figure 1C A gate contact (not shown) is used to apply voltage to the gate metal 112 / 113. Figure 1C As is not apparent from the view of FIG. 1 , gate metal 112 and gate metal 113 are shorted together. Thus, gate metal 112 and gate metal 113 together correspond to the gate electrode of complementary field effect transistor (CFET) 102. A voltage applied to gate metals 112 / 113 may turn on transistor 104 and turn off transistor 105 or may turn on transistor 105 and turn off transistor 104. Although gate metals 112 / 113 are shorted together, source / drain region 116 is not shorted together with source / drain region 117. Depending on the particular circuit configuration, current flow may be selectively enabled or disabled through source / drain regions 116 and 117, respectively.

[0106] As previously described, it may be beneficial to obtain the desired work function of transistors 104 and 105 by using different materials for gate metals 112 and 113. One possible way to form gate metals 112 / 113 is to first deposit gate metal 113 around all semiconductor nanostructures 106 and 107, and then perform a timed etch to remove gate metal 113 from around semiconductor nanostructure 106. Gate metal 112 is then deposited around semiconductor nanostructure 106 after the timed etch of gate metal 113. However, one disadvantage of this process is that, in some cases, gate metal 113 may not be completely removed directly below the lowest semiconductor nanostructure 106. This can interfere with the work function of transistor 104, thereby affecting the threshold voltage of transistor 104 in an undesirable manner.

[0107] The complementary field effect transistor (CFET) 102 avoids or reduces the possibility of work function interference by utilizing an isolation structure 126 between the semiconductor nanostructure 106 and the semiconductor nanostructure 107. More specifically, the isolation structure 126 is positioned directly between the lowest semiconductor nanostructure 106 and the highest semiconductor nanostructure 107. The isolation structure 126 may include upper and lower semiconductor layers 127 and a dielectric layer 129 located between the upper and lower semiconductor layers 127. Various structures and compositions may be used for the isolation structure 126 without departing from the scope of some embodiments of the present disclosure. In some embodiments, the isolation structure 126 is not included.

[0108] The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. The length of the dielectric layer 129 in the X direction may be between 15 nm and 30 nm. The length within this range may be sufficient to match or exceed the length of the semiconductor nanostructures 106 and 107 in the X direction. However, depending on the length of the semiconductor nanostructures 106 and 107, a longer or shorter length of the dielectric layer 129 may be selected. The dielectric layer 129 may have a height in the Z direction between 5 nm and 25 nm. These dimensions may be sufficient to ensure that there is no possibility of work function interference from the gate metal 113 and the semiconductor nanostructure 106. In addition, these dimensions may provide a reduced gate-to-drain capacitance. Other materials, dimensions, and configurations may be used for the dielectric layer 129 without departing from the scope of some embodiments of the present disclosure. The dielectric layer 129 may be referred to as a dielectric nanostructure. The dielectric nanostructures may include dielectric nanosheets, dielectric nanowires, or other types of dielectric nanostructures.

[0109] The dielectric layer 129 has a top surface 135 and a bottom surface 137. The gate metals 112 and 113 meet at an interface 139. In some embodiments, the interface 139 between the gate metals 112 and 113 is below the top surface 135 of the dielectric layer 129. In some embodiments, the interface 139 is below the top surface 135 of the dielectric layer 129 and above the bottom surface 137 of the dielectric layer 129. This helps ensure that the gate metal 113 does not interfere with the work function of the transistor 102.

[0110] Each semiconductor layer 127 may have a vertical thickness between 1 nm and 5 nm. The semiconductor layer 127 may include silicon or other suitable semiconductor materials. Other materials and dimensions may be used for the semiconductor layer 127 without departing from the scope of some embodiments of the present disclosure.

[0111] although Figure 1CA single dielectric layer 129 is illustrated, but in practice, the dielectric layer 129 may include multiple layers of different dielectric materials positioned between the semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be positioned in contact with each semiconductor layer 127. A second dielectric layer of silicon nitride may be positioned between the upper and lower portions of the first dielectric layer. Various configurations of dielectric barriers between the top semiconductor nanostructure 107 and the bottom semiconductor nanostructure 106 may be used without departing from the scope of some embodiments of the present disclosure.

[0112] In some embodiments of the present disclosure, a first transistor 105A and a second transistor 104A are electrically connected by an interconnect structure including an inclined portion. The first transistor 105A has a first source / drain region 117. The second transistor 104A is located above the first transistor 105A in a vertical direction (e.g., a Z-axis direction) and has a second source / drain region 116. The second transistor 104A is offset from the first transistor 105A in a first direction perpendicular to the vertical direction (e.g., an X-axis direction). The first source / drain contact 119 is electrically coupled to the first source / drain region 117. The second source / drain contact 118 is electrically coupled to the second source / drain region 116. Reference FIG. 3A to FIG. 3D and FIG. 4A to FIG. 4D The depicted interconnect structure is electrically coupled to first source / drain contact 119 and second source / drain contact 118 and includes an inclined portion extending from first source / drain contact 119 to second source / drain contact 118 at an offset angle from a vertical direction. In some embodiments, the "first transistor" is transistor 104A and the "second transistor" is transistor 105A, the "first source / drain region" is source / drain region 116 and the "second source / drain region" is source / drain region 117, the "first source / drain contact" is source / drain contact 118 and the "second source / drain contact" is source / drain contact 119.

[0113] Figure 1D is along Figure 1C Cut line 1B is taken Figure 1C Y-view of the integrated circuit 100A. Figure 1D In a view, the Y axis is the horizontal axis, while the X axis extends into and out of the drawing. Figure 1D The view is a wide cut through the gate metals 112 and 113 of transistors 104 and 105. Figure 1D It is illustrated how the gate metal 112 surrounds each semiconductor nanostructure 106 of the transistor 104. Correspondingly, the gate metal 113 surrounds each semiconductor nanostructure 107 of the transistor 105.

[0114] Figure 1DA gate contact 144 is shown extending into the dielectric layer 134. The gate contact 144 contacts the gate cap metal 132. Thus, the gate contact 144 is electrically connected to the gate metals 112 and 113 of the transistors 104 and 105. The gate contact 144 may include tungsten, titanium, tantalum, aluminum, copper, tantalum nitride, titanium nitride, or other suitable conductive materials. Various configurations and materials may be used for the gate contact 144 without departing from the scope of some embodiments of the present disclosure.

[0115] Figure 1D Also illustrated is an isolation structure 126 located between the lowest semiconductor nanostructure 106 and the highest semiconductor nanostructure 107. The isolation structure 126 includes a dielectric layer 129 and semiconductor layers 127 above and below the dielectric layer 129. Figure 1D Also illustrated is the presence of an interfacial gate dielectric layer 108 on the outer surface of the semiconductor layer 127. The high-K gate dielectric layer 110 surrounds the isolation structure 126 in the YZ plane.

[0116] In some embodiments, the width of the isolation structure 126 in the Y direction is substantially equal to or slightly greater than the width of the semiconductor nanostructure 106 / 107 in the Y direction. The isolation structure 126 is thicker in the Z direction than the semiconductor nanostructure 106 / 107. In addition, the isolation structure 126 is thicker in the Z direction than the portion of the gate metal 113 between the top semiconductor nanostructure 107 and the isolation structure 126. This is because the sacrificial semiconductor layer 154 (see Figure 2A ) is thicker than the sacrificial semiconductor layer 152. A gate metal 112 / 113 is formed to replace the sacrificial semiconductor layer 152.

[0117] In some embodiments, the junction or interface of the gate metal 112 / 113 occurs at a vertical height corresponding to a vertically intermediate level of the isolation structure 126. The junction or interface of the gate metal 112 / 113 may occur at any vertical level between the semiconductor layers 127. Other configurations of the gate metal 112 / 113 and the isolation structure 126 may be used without departing from the scope of some embodiments of the present disclosure.

[0118] Figure 1E yes Figure 1C The integrated circuit 100A along Figure 1C The cross-sectional view is taken along the cutting line 1C. Figure 1E In a view, the Y axis is the horizontal axis, while the X axis extends into and out of the drawing. Figure 1D The view of FIG. 1 is a wide cut through source / drain regions 116 and 117 from one side of complementary field effect transistor (CFET) 102 .

[0119] Figure 1EThe dielectric layer 130 is illustrated surrounding the source / drain regions 116 and 117 in the YZ plane, except for the source / drain contacts 118 / 119 connected to the source / drain regions 116 / 117 . Figure 1E An interlayer dielectric layer 128 is also illustrated surrounding the outer surface of the dielectric layer 130 and filling the space between the source / drain region 116 and the source / drain region 117 . Figure 1E Also shown are conductive vias 146 electrically connected to source / drain contacts 118 of transistor 104. Conductive vias 146 may include tungsten, titanium, aluminum, copper, titanium nitride, tantalum nitride, or other suitable conductive layers. Figure 1E Not shown, but the conductive vias may also extend through the substrate 101 to contact the bottom of the source / drain contacts 119 to provide an electrical connection to the source / drain regions 117 .

[0120] Figure 1F According to some embodiments Figure 1C 100A is a perspective view of an integrated circuit 100A. Figure 1F Interlayer dielectric layer 128 or dielectric layer 130 are not shown so that the locations of source / drain regions 116 and 117 are apparent. Figure 1F Shown are semiconductor nanostructures 106 and 107, an interfacial gate dielectric layer 108 and a high-K gate dielectric layer 110 surrounding semiconductor nanostructures 106 and 107, a gate metal 112 surrounding semiconductor nanostructure 106, and a gate metal 113 surrounding semiconductor nanostructure 107. An isolation structure 126 exists between the lowest semiconductor nanostructure 106 and the highest semiconductor nanostructure 107. A gate cap metal 132 is visible on top of the gate metal 112. Source / drain contacts 118 are coupled to the source / drain regions 116. Figure 1F It is also illustrated that the high-K gate dielectric layer 110 is also present on the sidewalls of the gate metals 112 and 113 and at the bottom of the gate metal 113. The substrate 101 may also include a semiconductor layer 133, although at this point in the processing, the semiconductor layer 133 may also be completely removed after forming the backside conductive structure. Various other configurations of the integrated circuit 100A may be used without departing from the scope of some embodiments of the present disclosure.

[0121] Figures 2A to 2M is a cross-sectional view of an integrated circuit 100A at various processing stages in accordance with some embodiments. Figures 2A to 2M A process for forming a complementary field effect transistor (CFET) 102 is illustrated in accordance with some embodiments.

[0122] Figure 2A is a cross-sectional X-view of the integrated circuit 100A according to some embodiments. Figure 2AIn the embodiment, the semiconductor fin 149 includes a plurality of semiconductor layers 150, a plurality of sacrificial semiconductor layers 152 stacked on the substrate 101, the semiconductor layer 127, and a special sacrificial semiconductor layer 154. The sacrificial semiconductor layer 152 is located between the semiconductor layers 150. As will be described in more detail below, the semiconductor layers 150 will eventually be patterned to form semiconductor nanostructures 106 / 107 corresponding to the channel regions of the complementary transistors 104 / 105 that together constitute the complementary field effect transistor (CFET) 102. Therefore, the semiconductor layer 150 may have a Figure 1A and Figure 1B The semiconductor nanostructures 106 / 107 are of the described materials and vertical thicknesses. The semiconductor fins 149 may be referred to as hybrid nanostructures or may be patterned to form hybrid nanostructures, as will be described in more detail below.

[0123] The sacrificial semiconductor layer 152 includes a semiconductor material that is different from the semiconductor material of the semiconductor layer 150. Specifically, the sacrificial semiconductor layer 152 includes a material that is selectively etchable relative to the material of the semiconductor layer 150. As will be described in further detail below, the sacrificial semiconductor layer 152 will eventually be patterned to form sacrificial semiconductor nanostructures. The sacrificial semiconductor nanostructures will eventually be replaced by gate metals located between the semiconductor nanostructures 106. In one example, the sacrificial semiconductor layer 152 may include a single crystalline semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In the example process described herein, the sacrificial semiconductor layer 152 includes SiGe and the semiconductor layer 150 includes Si. Other materials and configurations may be used for the sacrificial semiconductor layer 152 and the semiconductor layer 150 without departing from the scope of some embodiments of the present disclosure.

[0124] In some embodiments, each semiconductor layer 150 includes intrinsic silicon and each sacrificial semiconductor layer 152 includes silicon germanium. The sacrificial semiconductor layer 152 may have a relatively low germanium concentration between 10% and 35%. Concentrations within this range may provide sacrificial semiconductor layers 152 that are selectively etchable relative to the semiconductor layer 150. In some embodiments, the semiconductor layer 150 has a thickness between 2nm and 5nm. In some embodiments, the sacrificial semiconductor layer 152 has a thickness between 4nm and 10nm. Other materials, concentrations, and thicknesses may be used for the semiconductor layer 150 and the sacrificial semiconductor layer 152 without departing from the scope of some embodiments of the present disclosure.

[0125] In some embodiments, the semiconductor fin 149 is formed by performing a series of epitaxial growth processes. The first epitaxial growth process grows the lowest sacrificial semiconductor layer 152 on the semiconductor substrate 133. The second epitaxial growth process grows the lowest semiconductor layer 150 on the lowest sacrificial semiconductor layer 152. Alternating epitaxial growth processes are performed to form four lowest sacrificial semiconductor layers 152 and three lowest semiconductor layers 150. More or fewer sacrificial semiconductor layers 152 and semiconductor layers 150 may be formed depending on the number of semiconductor nanostructures required for the lower transistor 105 of the complementary field effect transistor (CFET) 102.

[0126] After forming the semiconductor layer 150 and the sacrificial semiconductor layer 152 associated with the lower transistor 105, the layer associated with the isolation structure 126 will be formed. Specifically, an epitaxial growth process is performed to form the lower semiconductor layer 127. In one example, the lower semiconductor layer 127 is intrinsic silicon with a thickness between 1nm and 3nm. After forming the lower semiconductor layer 127, other epitaxial growth processes are performed to form a special sacrificial semiconductor layer 154. The sacrificial semiconductor layer 154 has a composition that can be selectively etched relative to the semiconductor layer 150 and the sacrificial semiconductor layer 152. In the example where the sacrificial semiconductor layer 152 is silicon germanium with a relatively low germanium concentration, the sacrificial semiconductor layer 154 may include silicon germanium with a relatively high germanium concentration. In some embodiments, the germanium concentration in the sacrificial semiconductor layer 154 is greater than 50%.

[0127] In some embodiments, the germanium concentration in sacrificial semiconductor layer 154 is at least 25% higher than the germanium concentration in sacrificial semiconductor layer 152. For example, if the germanium concentration of sacrificial semiconductor layer 152 is 35%, then sacrificial semiconductor layer 154 will have a germanium concentration greater than or equal to 60%. In some embodiments, the germanium concentration in sacrificial semiconductor layer 154 is 2-5 times greater than the germanium concentration in sacrificial semiconductor layer 152. In some embodiments, the germanium concentration in sacrificial semiconductor layer 154 is less than or equal to 80%. Sacrificial semiconductor layer 154 can have a thickness between 5nm and 25nm and a length between 15nm and 30nm. The thickness of sacrificial semiconductor layer 154 is greater than the thickness of sacrificial semiconductor layer 152. The thickness of sacrificial semiconductor layer 152 is greater than the thickness of semiconductor layer 150. Other compositions, materials, and thicknesses may be used for sacrificial semiconductor layer 154 without departing from the scope of some embodiments of the present disclosure.

[0128] After forming the sacrificial semiconductor layer 154, an epitaxial growth process is performed to form an upper semiconductor layer 127 on the sacrificial semiconductor layer 154. The upper semiconductor layer 127 may have a composition thickness substantially the same as that of the lower semiconductor layer 127.

[0129] After forming sacrificial semiconductor layer 154 and upper semiconductor layer 127, upper sacrificial semiconductor layer 152 and semiconductor layer 150 associated with upper transistor 104 are formed. Upper sacrificial semiconductor layer 152 and semiconductor layer 150 may be formed using the alternating epitaxial growth process described with respect to lower semiconductor layer 150 and sacrificial semiconductor layer 152.

[0130] A dummy gate structure 156 has been formed on top of the uppermost semiconductor layer 150. The dummy gate structure 156 may correspond to a fin extending in the Y direction. Because the gate electrode of the transistor 102 will be formed, partially replacing the dummy gate structure 156, the dummy gate structure 156 is referred to as a dummy gate structure or a "sacrificial gate structure".

[0131] The dummy gate structure 156 includes a dielectric layer 158. The dielectric layer 158 may include a thin layer of silicon oxide grown on the top semiconductor layer 150 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The dielectric layer 158 may have a thickness between 0.2 nm and 2 nm. Other thicknesses of materials and deposition processes may be used for the dielectric layer 158 without departing from the scope of some embodiments of the present disclosure.

[0132] The dummy gate structure 156 includes a layer of polysilicon 160. The layer of polysilicon 160 may have a thickness that may be between 20 nm and 100 nm. The layer of polysilicon 160 may be deposited by epitaxial growth, a CVD process, a physical vapor deposition (PVD) process, or an ALD process. Other thicknesses and deposition processes may be used to deposit the layer of polysilicon 160 without departing from the scope of some embodiments of the present disclosure.

[0133] The dummy gate structure 156 may also include one or more additional dielectric layers above the layer of polysilicon 160. Various configurations and materials may be used for the dummy gate structure 156 without departing from the scope of some embodiments of the present disclosure.

[0134] Figure 2B is an X-view of the integrated circuit 100A according to some embodiments. Figure 2B, a sidewall spacer 131 is formed on the sidewall of the dummy gate structure 156. The sidewall spacer 131 may include a plurality of dielectric layers. Each dielectric layer of the sidewall spacer 131 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. The dielectric layer of the sidewall spacer 131 may be deposited by CVD, PVD, ALD, or other suitable processes.

[0135] Figure 2C is an X-view of the integrated circuit 100A according to some embodiments. Figure 2C , source / drain trenches 164 have been formed through semiconductor fins 149. Source / drain trenches 164 correspond to locations where source / drain regions 116 and 117 will be formed. The etching process that forms source / drain trenches 164 etches semiconductor layer 150, sacrificial semiconductor layer 152, semiconductor layer 127, and sacrificial semiconductor layer 154 to form semiconductor nanostructures 106 and 107 from semiconductor layer 150. More specifically, the etching process forms a stack of semiconductor nanostructures 106 and 107. Semiconductor nanostructure 106 corresponds to a channel region of transistor 104. Semiconductor nanostructure 107 corresponds to a channel region of transistor 105. The etching process also forms sacrificial semiconductor nanostructure 165 from sacrificial semiconductor layer 152. Sacrificial semiconductor nanostructure 165 is located between semiconductor nanostructures 106 and between semiconductor nanostructures 107. Source / drain trenches 164 extend into semiconductor substrate 133.

[0136] The etching process may include one or more anisotropic etching processes that selectively etches the materials of the semiconductor layer 150 and the sacrificial semiconductor layer 152 in the vertical direction. The etching process may include a single step or multiple steps. The etching process may include one or more timed etchings. Other types of etching processes may be used without departing from the scope of some embodiments of the present disclosure.

[0137] exist Figure 2C106, a recess step has been performed to recess the sacrificial semiconductor nanostructure 165. The recessing process removes the exterior of the sacrificial semiconductor nanostructure 165 without completely removing the sacrificial semiconductor nanostructure 165. The recessing process may be performed using an isotropic etch, which selectively etches the material of the sacrificial semiconductor nanostructure 165 relative to the material of the semiconductor nanostructure 106 / 107, the sacrificial semiconductor layer 154, and the substrate 101. The isotropic etch process may include a timed etch process. The duration of the etch process is selected to remove only a portion of the sacrificial semiconductor nanostructure 165 without completely removing the sacrificial semiconductor nanostructure 165. The result of the etch process is the formation of a recess 166 in the sacrificial semiconductor nanostructure 165.

[0138] The etching process may include dry etching using a gas that is a mixture of SF6, H2, and CF4. The etching process may etch the sacrificial semiconductor nanostructure 165 at a rate greater than 10 times the rate of etching the sacrificial semiconductor layer 154. Other etchants and etching processes may be used without departing from the scope of some embodiments of the present disclosure.

[0139] Figure 2D is an X-view of the integrated circuit 100A according to some embodiments. Figure 2D , the inner spacer 114 has been formed in the recess 166. The inner spacer 114 can be formed by depositing a dielectric layer on the exposed sidewalls of the semiconductor nanostructures 106 / 107, on the bottom of the source / drain trench 164, and in the recess 166 formed in the sacrificial semiconductor nanostructure 165. Without departing from the scope of some embodiments of the present disclosure, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, carbon oxynitride silicon, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric material. The dielectric layer can be formed by CVD, PVD, ALD, or by other processes. The lateral thickness of the dielectric layer can be between 2nm and 10nm. Without departing from the scope of some embodiments of the present disclosure, other thicknesses, materials, and deposition processes can be used for the dielectric layer.

[0140] An etching process is then performed to remove excess portions of the dielectric layer. The etching process may include an isotropic etching process that etches in all directions. The isotropic etching process is timed so as to remove the dielectric layer at all locations except for locations where the lateral thickness increase is caused by the recesses 166 in the sacrificial semiconductor nanostructures 165. The result is that the internal spacers 114 remain at the recesses 166 in the sacrificial semiconductor nanostructures 165. Other processes may be used to form the internal spacers 114 without departing from the scope of some embodiments of the present disclosure.

[0141] Figure 2E is an X-view of the integrated circuit 100A according to some embodiments. Figure 2E , an etching process has been performed to remove the sacrificial semiconductor layer 154 from between the semiconductor layers 127. The etching process may include isotropic etching that selectively etches the sacrificial semiconductor layer 154 relative to the semiconductor nanostructures 106 / 107, the semiconductor substrate 133, and the sacrificial semiconductor nanostructures 165. Because the sacrificial semiconductor layer 154 has a significantly different germanium concentration relative to the sacrificial semiconductor nanostructures 165, the sacrificial semiconductor layer 154 may be selectively etched relative to the sacrificial semiconductor nanostructures 165 and the semiconductor nanostructures 106 / 107. In some embodiments, the etching process may include a dry etching process using an etchant of CF4 or HBr gas, which etches the sacrificial semiconductor layer 154 at a rate that is 10 times higher than the etching rate of the semiconductor nanostructures 106 / 107 and the semiconductor layer 127. Other etching processes may be used without departing from the scope of some embodiments of the present disclosure.

[0142] Figure 2E As a result of the etching process in , voids 170 are formed between semiconductor layers 127. As will be described in more detail below, a dielectric layer 129 will be formed in place of voids 170.

[0143] Figure 2F is an X-view of the integrated circuit 100A according to some embodiments. Figure 2F , a dielectric layer 172 is deposited. The dielectric layer 172 is deposited in the gaps 170 between the semiconductor layers 127, in the source / drain trenches 164, and on the dummy gate structure 156. Without departing from the scope of some embodiments of the present disclosure, the dielectric layer 172 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric material. The dielectric layer 172 may be deposited using CVD, ALD, or PVD. Other materials and deposition processes may be used for the dielectric layer 172 without departing from the scope of some embodiments of the present disclosure.

[0144] Figure 2G is an X-view of the integrated circuit 100A according to some embodiments. Figure 2G, a dielectric layer 129 has been formed between the semiconductor layers 127. The dielectric layer 129 is formed by performing an etching process on the dielectric layer 172. The etching process may include anisotropic etching that selectively etches in a downward direction. The etching process removes the dielectric layer 172 from all locations except between the semiconductor layers 127. Therefore, the dielectric layer 129 is a remnant of the dielectric layer 172. The dielectric layer 129 and the semiconductor layer 127 may collectively correspond to a hybrid nanosheet that will help provide improved gate metal characteristics, as will be described in more detail below.

[0145] Although Figure 2G The dielectric layer 129 is illustrated as having substantially vertical sidewalls, but in reality, the dielectric layer 129 may include concave sidewalls. This may be a result of an anisotropic etching process. This may occur because an isotropic etching process may not be completely anisotropic. For example, an anisotropic etching process may etch at a rate between 10 and 100 times greater in a downward direction than in a lateral direction. Although relatively small, some etching occurs in the lateral direction, thereby creating a depression in the dielectric layer 129. The dielectric layer 129 may have various other configurations without departing from the scope of some embodiments of the present disclosure.

[0146] Figure 2H is an X-view of the integrated circuit 100A according to some embodiments. Figure 2H In the embodiment of the present invention, a layer of polymer material 174 has been deposited in the source / drain trench 164. Alternatively, the polymer material 174 can be replaced by a non-polymer dielectric material. After the deposition of the polymer material 174, an etch-back process is performed to reduce the height of the polymer material 174 to a level below the lower semiconductor layer 127.

[0147] exist Figure 2H 1 , a dielectric layer 176 has been deposited on the polymer material 174, as well as on the sidewalls of the dielectric layer 129, the inner spacers 114, the semiconductor nanostructures 106, and the sidewall spacers 131. In some embodiments, the dielectric layer 176 includes aluminum oxide (Al2O3). The dielectric layer 176 can be deposited by CVD, PVD, or ALD. Other materials and processes can be used for the dielectric layer 176 without departing from the scope of some embodiments of the present disclosure. After the dielectric layer 176 is deposited, an anisotropic etching process is performed to remove the dielectric layer 176 from the horizontal surfaces of the polymer material 174 and the dummy gate structure 156.

[0148] Fig.2I is an X-view of the integrated circuit 100A according to some embodiments. Fig.2I In FIG. 1 , polymer material 174 has been removed. The removal of polymer material 174 exposes the sidewalls of semiconductor nanostructure 107 and semiconductor substrate 133. Fig.2I , the source / drain region 117 has been formed at a position in the source / drain trench 164 that is not covered by the dielectric layer 176. The source / drain region 117 can be formed by epitaxial growth of the semiconductor nanostructure 107 and the semiconductor substrate 133. The source / drain region 117 includes a semiconductor material. The semiconductor material may include the same semiconductor material as the semiconductor nanostructure 107. Alternatively, the semiconductor material of the source / drain region 117 may be different from the semiconductor material of the semiconductor nanostructure 107. The source / drain region 117 may be in-situ doped with dopant atoms during the epitaxial growth process. In the example where the lower transistor 105 is a P-type transistor, the source / drain region 117 may be in-situ doped with P-type dopant atoms. The P-type dopant atoms may include boron or other P-type dopant atoms.

[0149] Figure 2J is an X-view of the integrated circuit 100A according to some embodiments. Figure 2J , dielectric layer 176 has been removed. Dielectric layer 180 has been deposited. Polymer material 182 has also been deposited. Dielectric layer 180 may include the same material as dielectric layer 176. Polymer material 182 may have the same material as polymer material 174. An etch-back process is also performed to reduce the height of dielectric layer 180 and polymer material 182 to expose the sidewalls of semiconductor nanostructure 106.

[0150] Figure 2K is an X-view of the integrated circuit 100A according to some embodiments. Figure 2K , the source / drain region 116 has been formed in the source / drain above the dielectric layer 180 and the polymer material 182. The source / drain region 116 can be formed by epitaxial growth of the semiconductor nanostructure 106. The source / drain region 116 includes a semiconductor material. The semiconductor material may include the same semiconductor material as the semiconductor nanostructure 106. Alternatively, the semiconductor material of the source / drain region 116 may be different from the semiconductor material of the semiconductor nanostructure 106. The source / drain region 116 may be in-situ doped with dopant atoms during the epitaxial growth process. In the example where the upper transistor 104 is an N-type transistor, the source / drain region 116 may be in-situ doped with N-type dopant atoms. The N-type dopant atoms may include phosphorus or other N-type dopant atoms.

[0151] Figure 2L is an X-view of the integrated circuit 100A according to some embodiments. Figure 2L, the polymer material 182 and the dielectric layer 180 have been removed. The dielectric layer 130 has been deposited using a conformal deposition process. The dielectric layer 130 is deposited on the exposed sidewalls of the inner spacer 114, on the semiconductor layer 127, and on the dielectric layer 129 between the source / drain region 116 and the source / drain region 117. The dielectric layer 130 is also deposited on the top surface of the source / drain region 117, the bottom surface, the side surface and the top surface of the source / drain region 116, and the sidewall spacer 131 of the dummy gate structure 156. The dielectric layer 130 may be deposited by CVD, ALD, or other suitable process. The dielectric layer 130 may include a contact-etching stop-layer (CESL). The dielectric layer 130 may include one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material or other dielectric materials.

[0152] An interlayer dielectric layer 128 has been deposited to cover the dielectric layer 130. The interlayer dielectric layer 128 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric material. The interlayer dielectric layer may be deposited by CVD, PVD, or ALD. Other materials and dimensions may be used for the interlayer dielectric layer 128 and the dielectric layer 130 without departing from the scope of some embodiments of the present disclosure.

[0153] Figure 2M is an X-view of the integrated circuit 100A according to some embodiments. Figure 2M The X view is relative to Figure 2L Laterally expanded to show portions of laterally adjacent transistors. The dummy gate structure 156 has been removed. After the dummy gate structure 156 is removed, the sacrificial semiconductor nanostructure 165 is removed by an etching process that selectively removes the sacrificial semiconductor nanostructure 165 relative to the semiconductor nanostructures 106 / 107.

[0154] After removing the sacrificial semiconductor nanostructure 165, a gap remains at the location of the sacrificial semiconductor nanostructure 165. The semiconductor nanostructure 106 / 107 is exposed. An interfacial gate dielectric layer 108 and a high-K gate dielectric layer 110 are then deposited around the semiconductor nanostructure 106 / 107. The interfacial gate dielectric layer 108 may include silicon oxide having a thickness between 2 angstroms and 10 angstroms. The high-K gate dielectric layer 110 is deposited on the interfacial gate dielectric layer 108 and may include hafnium oxide. The thickness of the high-K dielectric layer may be between 5 angstroms and 20 angstroms. The materials of the interfacial gate dielectric layer 108 and the high-K gate dielectric layer 110 may be deposited by ALD, CVD, or PVD. Other structures, materials, thicknesses, and deposition processes may be used for the gate dielectric layer without departing from the scope of some embodiments of the present disclosure.

[0155] After depositing the interfacial gate dielectric layer 108 and the high-K gate dielectric layer 110 around the semiconductor nanostructure 106 / 107, the gate metal 113 is deposited. The gate metal 113 may be deposited by PVD, CVD, ALD, or other suitable processes. One or more materials of the gate metal 113 are selected to provide a desired work function of the semiconductor nanostructure 107 with respect to the P-type transistor 105. In one example, the gate metal 113 includes titanium aluminum. However, other conductive materials may be used for the gate metal 113 without departing from the scope of some embodiments of the present disclosure.

[0156] When gate metal 113 is initially deposited, gate metal 113 surrounds semiconductor nanostructure 106 and semiconductor nanostructure 107. However, gate metal 113 has a material that provides a desired work function for lower transistor 105, and gate metal 113 may not provide a desired work function for upper transistor 104. Therefore, an etch-back process is performed. The etch-back process removes gate metal 113 to a level far below the lowest semiconductor nanostructure 106. In some embodiments, the etch-back process removes gate metal 113 to a level approximately in the vertical middle of dielectric layer 129.

[0157] Because of the presence of dielectric layer 129, the etch-back process can have a duration that reliably removes all of gate metal 113 directly from between dielectric layer 129 and the lowest semiconductor nanostructure 106 without removing gate metal 113 from between the highest semiconductor nanostructure 107 and dielectric layer 129. The result is that gate metal 113 cannot interfere with the work function of the upper transistor 104.

[0158] After the etch-back process of the gate metal 113, the gate metal 112 is deposited. The gate metal 112 may be deposited using ALD, PVD, CVD, or other suitable deposition processes. In one example, the gate metal 112 includes titanium nitride. Alternatively, the gate metal 112 may include any other suitable conductive material. The gate metal 112 surrounds the semiconductor nanostructure 106. Specifically, the gate metal 112 contacts the high-K gate dielectric 110 surrounding the semiconductor nanostructure 106. The material of the gate metal 112 is selected to provide a desired work function for the transistor 104.

[0159] After the gate metal 112 is deposited, an etch-back process is performed to reduce the height of the gate metal 112 above the top semiconductor nanostructure 106. After the etch-back process of the gate metal 112, a gate cap metal 132 is deposited on the gate metal 112. The gate cap metal 132 may include tungsten, fluorine-free tungsten, or other suitable conductive materials. The gate cap metal 132 may be deposited by PVD, CVD, ALD, or other suitable deposition processes. The gate cap metal 132 may have a vertical thickness between 1 nm and 10 nm. Other dimensions may be used without departing from the scope of some embodiments of the present disclosure.

[0160] After the gate cap metal 132 is deposited, a dielectric layer 134 is deposited. The dielectric layer 134 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. The dielectric layer 134 may be deposited by PVD, CVD, ALD, or other suitable deposition processes.

[0161] FIG. 3A to FIG. 3D is a diagrammatic perspective view of an integrated circuit 100A at an intermediate stage in forming a conductive through-substrate layer (TSL) 450 according to various embodiments. FIG. 4A to FIG. 4D is a diagrammatic perspective view of an integrated circuit 100A at an intermediate stage in forming a conductive through-substrate layer (TSL) 450 according to various other embodiments. For clarity of illustration, most of the components of the integrated circuit 100A are shown in FIG. FIG. 3A to FIG. 3D and FIG. 4A to FIG. 4D is omitted.

[0162] Figure 5 and Figure 6 A flow chart of a method of forming an integrated circuit according to various embodiments is illustrated. Figure 5 The method 1000 shown may be used to form FIG. 3A to FIG. 3D The integrated circuit 100A shown in FIG. Figure 6 The method 1000 shown may be used to form FIG. 4A to FIG. 4DThe integrated circuit 100A shown. In some embodiments, the method 1000, 2000 for forming a semiconductor structure includes a plurality of operations. The method 1000, 2000 for forming a semiconductor structure will be further described according to one or more embodiments. It should be noted that the operations of the method 1000, 2000 may be rearranged or otherwise modified within the scope of various aspects. It should also be noted that additional processes may be provided before, between, and after the method 1000, 2000, and some other processes may only be briefly described herein.

[0163] Figure 3A is a diagrammatic perspective view of an integrated circuit 100A according to various embodiments. For clarity, most elements have been removed from the diagram. Figure 3A The integrated circuit 100A includes source / drain contacts 220 that contact the source / drain regions 116, 117. The first source / drain contact is labeled 220A and the second source / drain contact is labeled 220B. The source / drain contacts 220, 220A, 220B are Figure 1C , Figure 1E 100A. The source / drain contact 220A may be a front source / drain contact and the source / drain contact 220B may be a back source / drain contact. The source / drain contact 220A may be a back source / drain contact and the source / drain contact 220B may be a front source / drain contact. It should be understood that “frontside” and “backside” refer to two different sides of the integrated circuit 100A. Reference Figure 2M , "back side" refers to the side 100B where the substrate (eg, substrate 101) is or was located. "Front side" refers to the side above the device (eg, transistors 104, 105) opposite to the back side.

[0164] exist Figure 3A , forming a first source / drain contact 220A, corresponding to actions 1100 and 2100 of methods 1000 and 2000, respectively. As shown, the first source / drain contact 220A can be a front source / drain contact formed on the source / drain region 116. In some embodiments, the first source / drain contact 220A is formed on the source / drain region 117. That is, the first source / drain contact can be a back source / drain contact. The first source / drain contact 220A can be similar or identical to the source / drain contacts 118 and 119. The first source / drain contact 220A can be formed by etching an opening, and then depositing the material of the first source / drain contact 220A in the opening by a suitable deposition operation such as PVD, CVD, ALD, etc.

[0165] exist Figure 3AIn the method 1000, a second source / drain contact 220B is formed, corresponding to actions 1200 and 2200 of methods 1000 and 2000, respectively. As shown, the second source / drain contact 220B can be a back source / drain contact formed on the source / drain region 117. In some embodiments, the second source / drain contact 220B is formed on the source / drain region 116. That is, the first source / drain contact can be a front source / drain contact. The second source / drain contact 220B can be similar or identical to the source / drain contacts 118 and 119. The second source / drain contact 220B can be formed by etching an opening, and then depositing the material of the second source / drain contact 220B in the opening by a suitable deposition operation such as PVD, CVD, ALD, etc.

[0166] The first and second source / drain contacts 220A, 220B are on different levels of the integrated circuit 100A. That is, the first source / drain contact 220A can be coupled to or contact the upper source / drain region of the upper transistor, and the second source / drain contact 220B can be coupled to or contact the lower source / drain region of the lower transistor. The upper source / drain region and the lower source / drain region can be different types from each other. For example, the upper source / drain region can be N-type and the lower source / drain region can be P-type. For example, the upper source / drain region can be P-type and the lower source / drain region can be N-type.

[0167] exist Figure 3A In the embodiment of the present invention, a mask 300 is formed on the first source / drain contact 220A. The mask 300 can be any suitable mask and can be or include one or more layers of the following: a photoresist, an anti-reflective coating (ARC) layer, a hard mask (e.g., SiN), etc. After forming the mask 300, an opening 310M is formed in the mask 300. The opening 310M can be formed by patterning the mask 300 (e.g., by exposing the photoresist of the mask 300 to light of a selected wavelength, such as extreme ultraviolet (EUV) light). The opening 310M can be formed by one or more etching operations. The opening 310M exposes the first source / drain contact 220A, such as the upper surface of the first source / drain contact 220A.

[0168] exist Figure 3AIn the method 1000, corresponding to actions 1300, 2300 of 2000, a vertical opening 330A is formed by extending the opening 310 into or through (e.g., completely through) the first source / drain contact 220A. The vertical opening 330A can expose the structural material below the first source / drain contact 220A. The exposed material can be the material of the interlayer dielectric (ILD) between the first source / drain contact 220A and the second source / drain contact 220B.

[0169] exist Figure 3B In the method 1000, corresponding to act 1400, after forming the vertical opening 330A through the first source / drain contact 220A, the opening 310 is further extended as shown. Figure 3B The inclined portion 330 may expose the second source / drain contact 220B.

[0170] The inclined portion 330 can be formed by an etching operation, such as a plasma etching operation, etc. The etching operation is performed while the wafer on which the integrated circuit 100A is placed is tilted or rotated. The tilt angle or offset angle can be controlled by a wafer stage on which the wafer is mounted. The tilt angle of the wafer stage can correspond to a selected tilt angle associated with, for example, the shortest distance between the first source / drain contact 220A and the second source / drain contact 220B. For example, an imaginary line can be drawn from the center of the opening in the first source / drain contact 220A to the center of the second source / drain contact 220B along the X-axis direction. The imaginary line can have an angular offset (or tilt) relative to a vertical direction (e.g., perpendicular to the main surface of the substrate 101). The tilt angle can be in the range of about 10 degrees to 70 degrees, for example, in the range of about 10 degrees to about 40 degrees, in the range of about 20 degrees to about 30 degrees, or in another suitable range. In some embodiments, for example, when the first source / drain contact 220A and the second source / drain contact 220B are offset from each other by a large distance along the X-axis direction, the tilt angle may exceed 40 degrees. FIG. 3A to FIG. 3D The first source / drain contact 220A and the second source / drain contact 220B are adjacent along the X-axis direction, but this is not required. In some embodiments, one or more source / drain contacts 220 are between the first source / drain contact 220A and the second source / drain contact 220B along the X-axis direction. For example, the inclined portion 330 may extend from the first source / drain contact 220A to the FIG. 3A to FIG. 3D Another source / drain contact not shown in FIG. In this case, the tilt angle may exceed 40 degrees, for example in the range of about 40 degrees to about 70 degrees, or higher.

[0171] The inclined portion 330 may extend parallel to the first direction, which may be Figure 3B The first direction may be perpendicular to the second direction (eg, the Y-axis direction) in which the first source / drain contact 220A extends. It is not necessary to extend completely parallel to the first direction, and deviation from being parallel to the first direction is also an embodiment of the present invention.

[0172] The cross-sectional profile of the inclined portion 330 in the XY plane may be substantially the same as the cross-sectional profile of the vertical opening 330A. The inclined portion 330 may be cylindrical. In some embodiments, the inclined portion 330 has tapered sidewalls and is tapered, narrowing toward the second source / drain contact 220B.

[0173] Figure 3C The resulting structure is shown after forming the inclined portion 330 of the opening 310 and removing the mask 300. The opening 310 includes a vertical opening 330A extending through the first source / drain contact 220A, and an inclined portion 330 extending from the first source / drain contact 220A to the second source / drain contact 220B. In some embodiments, after removing the mask 300, an ashing operation is performed to remove byproducts of the etching that forms the opening 310.

[0174] exist Figure 3D In the embodiment of the present invention, corresponding to act 1500 of method 1000, a conductive through-substrate layer (TSL) 450 is formed in the opening 310. The conductive through-substrate layer (TSL) 450 may be formed by a suitable deposition operation such as PVD, CVD, ALD, etc. In some embodiments, the conductive through-substrate layer (TSL) 450 is or includes one or more metals such as ruthenium, tungsten, cobalt, nickel, aluminum, copper, gold, alloys thereof, multilayers thereof, etc. In some embodiments, the conductive through-substrate layer (TSL) 450 is ruthenium. The conductive through-substrate layer (TSL) 450 may inherit the shape of the opening 310. For example, the conductive through-substrate layer (TSL) 450 may extend from the upper surface of the first source / drain contact 220A, vertically pass through the first source / drain contact 220A, at a certain angle toward the second source / drain contact 220B, and may fall on the second source / drain contact 220B. The conductive through-substrate layer (TSL) 450 may include a vertical portion 450A extending through the first source / drain contact 220A in a vertical direction and an inclined portion 450O extending from the first source / drain contact 220A to the second source / drain contact 220B at an offset angle from the vertical direction.

[0175] The method 1000 for forming a conductive through substrate layer (TSL) 450 is beneficial because only a single mask is used to form the opening 310 in which the conductive through substrate layer (TSL) 450 is formed. In this way, the process flow can be simplified and costs can be reduced. The method 1000 can be performed without using a time mode or "timed" etching, which would otherwise be difficult to perform due to the lack of elemental byproduct information in the etching operation. This also simplifies the formation of the opening 310.

[0176] Although the case where the second source / drain contact 220B is formed before forming the conductive through substrate layer (TSL) 450 is described FIG. 3A to FIG. 3D , but it should be understood that this is not required. For example, in many integrated circuits, a front interconnect structure including many metal interconnect layers is formed above the first source / drain contact 220A before forming a back interconnect structure that may include the second source / drain contact 220B. In this way, the conductive through-substrate layer (TSL) 450 can be formed before forming the front interconnect structure and before forming the second source / drain contact 220B. For example, after forming the first source / drain contact 220A, the conductive through-substrate layer (TSL) 450 can be formed at a certain angle and a certain depth to fall at the location where the second source / drain contact 220B is to be formed. Then, after forming the front interconnect structure above the first source / drain contact 220A, the wafer can be flipped and the substrate 101 can be removed to expose the lower side of the conductive through-substrate layer (TSL) 450. After exposing the conductive through-substrate layer (TSL) 450, the second source / drain contact 220B can be formed on the conductive through-substrate layer (TSL) 450.

[0177] In another example, the first source / drain contact 220A may be a back source / drain contact, and the second source / drain contact 220B may be a front source / drain contact. In this case, a front interconnect structure may be formed on the second source / drain contact 220B in an operation prior to forming the first source / drain contact 220A. Thus, the front interconnect structure may be formed in the manner described in reference to FIG. FIG. 3A to FIG. 3D The formation of the second source / drain contact 220B is described by forming a conductive through-substrate layer (TSL) 450, i.e., the second source / drain contact 220B is in place. Then, after forming the conductive through-substrate layer (TSL) 450, the remaining metal layer of the backside interconnect structure can be formed over the first source / drain contact 220A.

[0178] FIG. 4A to FIG. 4D is a diagrammatic perspective view of forming a conductive through substrate layer (TSL) 450 according to various embodiments. FIG. 4A to FIG. 4D In FIG. 4 , a conductive through-substrate layer (TSL) 450 is grown from a seed layer using directional ALD.

[0179] exist Figure 4A In the method 2000, corresponding to actions 2100 and 2200, a first source / drain contact 220A and a second source / drain contact 220B are formed, similar to the reference Figure 3A After forming the first source / drain contact 220A, a mask 300 is formed, which is similar to Figure 3A Description. An opening is formed in the mask 300 exposing the first source / drain contact 220A, and then the opening extends vertically through the first source / drain contact 220A, corresponding to action 2300 of method 2000. After the opening extends vertically through the first source / drain contact 220A, a seed layer 410 is formed in the opening, corresponding to action 2400 of method 2000. The seed layer 410 may extend through the mask 300 and the opening in the first source / drain contact 220A. In some embodiments, the seed layer 410 includes ruthenium, tungsten, cobalt, nickel, aluminum, copper, gold, etc. In some embodiments, the seed layer 410 is ruthenium. In some embodiments, the material of the seed layer 410 is different from the material of the first source / drain contact 220A and the second source / drain contact 220B to facilitate an inclined portion 410X on the seed layer 410 (see Figure 4B ) rather than selective growth on the first source / drain contact 220A or the second source / drain contact 220B or the source / drain contact 220.

[0180] exist Figure 4B In the embodiment, the inclined portion 410X is grown on the seed layer 410 at an offset angle, corresponding to action 2500 of method 2000. The details of the offset angle may be similar to those described above with reference to FIG. 3A to FIG. 3D The details of the tilt angle described above. The tilt portion 410X can be grown by a directional ALD operation with an offset angle and can be grown with a non-orthogonal (e.g., non-vertical) profile. In some embodiments, there is no Figure 4B The mask 300 shown in FIG. 1 , ie, the mask 300 may be removed before performing the directional ALD operation. The offset angle may be selected by tilting a wafer stage on which the wafer having the integrated circuit 100A mounted thereon.

[0181] exist Figure 4C In the embodiment, the growth of the inclined portion 410X continues until the inclined portion 410X lands on (eg, contacts) the second source / drain contact 220B. Figure 4B and Figure 4C As shown, during the growth of the inclined portion 410X, the inclined portion 410X may have a conical shape that becomes narrower as the proximity to the second source / drain contact 220B increases. Figure 3DThe conductive through substrate layer (TSL) 450, the inclined portion 410X may extend parallel to the X-axis direction.

[0182] exist Figure 4D In the embodiment of the present invention, after the inclined portion 410X contacts the second source / drain contact 220B, an annealing operation may be performed to improve the profile of the inclined portion 410X and improve the connection between the inclined portion 410X and the second source / drain contact 220B, corresponding to action 2600 of method 2000. The annealing operation may reduce the contact resistance between the inclined portion 410X and the second source / drain contact 220B. Annealing may reduce the contact resistance between the inclined portion 410X and the metal of the second source / drain contact 220B by improving the quality of the metal-to-metal interface. When two metal surfaces are in contact, tiny irregularities and impurities may appear, which prevent the formation of a good electrical connection. Surface defects increase contact resistance, which in turn can cause heating and other problems. The annealing operation may include heating the metal to a high temperature and then allowing the metal to cool slowly. The annealing process may help smooth surface irregularities and redistribute any impurities, thereby forming a more uniform and cleaner metal-to-metal interface. The improved metal-to-metal interface can reduce the contact resistance between the two metals. Annealing can also improve the mechanical properties of both metals, such as their hardness and ductility, which can increase the metal's resistance to deformation and wear, and may also help reduce contact resistance over time.

[0183] It should be understood that similar to FIG. 3A to FIG. 3D Description, FIG. 4A to FIG. 4D It is described in the case where the second source / drain contact 220B is formed before forming the conductive through substrate layer (TSL) 450, but this is not required. For example, in many integrated circuits, a front-side interconnect structure including many metal interconnect layers above the first source / drain contact 220A is formed before forming a back-side interconnect structure that may include the second source / drain contact 220B. In this way, the conductive through substrate layer (TSL) 450 can be formed before forming the front-side interconnect structure and before forming the second source / drain contact 220B. For example, after forming the first source / drain contact 220A, the conductive through substrate layer (TSL) 450 can be formed at a certain angle and a certain depth to fall at the location where the second source / drain contact 220B is to be formed. Then, after forming the front-side interconnect structure above the first source / drain contact 220A, the wafer can be flipped and the substrate 101 can be removed to expose the underside of the conductive through substrate layer (TSL) 450. After exposing the conductive through substrate layer (TSL) 450 , the second source / drain contacts 220B may be formed on the conductive through substrate layer (TSL) 450 .

[0184] In another example, the first source / drain contact 220A may be a back source / drain contact, and the second source / drain contact 220B may be a front source / drain contact. In this case, a front interconnect structure may be formed on the second source / drain contact 220B in an operation prior to forming the first source / drain contact 220A. Thus, the front interconnect structure may be formed in the manner described in reference to FIG. FIG. 3A to FIG. 3D The formation of the second source / drain contact 220B is described by forming a conductive through-substrate layer (TSL) 450, i.e., the second source / drain contact 220B is in place. Then, after forming the conductive through-substrate layer (TSL) 450, the remaining metal layer of the backside interconnect structure can be formed over the first source / drain contact 220A.

[0185] In some embodiments, the inclined portion 410X is grown through air or open space in a vacuum environment. Therefore, one or more etching operations can be performed before the inclined portion 410X is formed to remove the material between the first source / drain contact 220A and the second source / drain contact 220B. After the inclined portion 410X is formed, a dielectric material can be deposited in the space to surround the inclined portion 410X. The dielectric material can electrically isolate the inclined portion 410X from adjacent structures and can provide physical support that is conducive to preventing the inclined portion 410X from being damaged.

[0186] Some embodiments of the present disclosure provide an integrated circuit of a complementary field effect transistor (CFET) with improved electrical characteristics. The complementary field effect transistor (CFET) includes a first transistor vertically stacked on a second transistor. The first transistor and the second transistor each have a plurality of semiconductor nanostructures that serve as channel regions of the first transistor and the second transistor. A first gate metal surrounds the semiconductor nanostructure of the first transistor. A second gate metal surrounds the semiconductor nanostructure of the second transistor. The complementary field effect transistor (CFET) includes an isolation structure located between the lowest semiconductor nanostructure of the first transistor and the highest semiconductor nanostructure of the second transistor. The complementary field effect transistor (CFET) includes a conductive through substrate layer (TSL) having a sloped portion that can reduce parasitic capacitance. This helps ensure that the conductive through substrate layer (TSL) does not excessively increase the parasitic capacitance of nearby gate metal and / or source / drain regions. The conductive through substrate layer (TSL) having the sloped portion is formed using a single patterning and etch loop, which simplifies the formation of the conductive through substrate layer (TSL) and reduces costs.

[0187] In some embodiments, an integrated circuit includes a complementary transistor, a first source / drain contact, a second source / drain contact, and an interconnection structure. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is located above the first transistor in a vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The interconnection structure is electrically coupled to the first source / drain contact and the second source / drain contact, and the interconnection structure includes an inclined portion, which extends from the first source / drain contact to the second source / drain contact at an offset angle from the vertical direction. In some embodiments, the interconnection structure also includes a vertical portion, which extends through the first source / drain contact. In some embodiments, the material of the inclined portion is different from the material of the first source / drain contact. In some embodiments, the material of the inclined portion is ruthenium. In some embodiments, the integrated circuit further comprises a metal-to-metal interface between the second source / drain contact and the inclined portion. In some embodiments, the offset angle is in the range of about 10 degrees to about 40 degrees. In some embodiments, the offset angle is in the range of about 40 degrees to about 70 degrees. In some embodiments, the offset angle is in the range of about 20 degrees to about 30 degrees. In some embodiments, one of the first source / drain region and the second source / drain region is N-type, and the other of the first source / drain region and the second source / drain region is P-type. In some embodiments, the first source / drain contact is a back source / drain contact, and the second source / drain contact is a front source / drain contact. In some embodiments, the first source / drain contact is a front source / drain contact, and the second source / drain contact is a back source / drain contact. In some embodiments, the inclined portion is cylindrical.

[0188] In some embodiments, an integrated circuit includes a complementary transistor, a first source / drain contact, a second source / drain contact, and a conductive through-substrate layer. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is located above the first transistor in a vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The conductive through-substrate layer is electrically coupled to the first source / drain contact and the second source / drain contact, and the conductive through-substrate layer includes a vertical portion extending through the first source / drain contact in a vertical direction and an inclined portion extending from the vertical portion to the second source / drain contact at an offset angle in the vertical direction. In some embodiments, the material of the inclined portion is different from the material of the first source / drain contact. In some embodiments, the material of the inclined portion is ruthenium. In some embodiments, the above-mentioned integrated circuit also includes a metal-to-metal interface between the second source / drain contact and the inclined portion. In some embodiments, wherein the offset angle is in the range of about 10 degrees to about 40 degrees. In some embodiments, wherein the offset angle is in the range of about 40 degrees to about 70 degrees. In some embodiments, wherein the offset angle is in the range of about 20 degrees to about 30 degrees. In some embodiments, wherein one of the first source / drain region and the second source / drain region is N-type, wherein the other of the first source / drain region and the second source / drain region is P-type. In some embodiments, wherein the first source / drain contact is a back source / drain contact, wherein the second source / drain contact is a front source / drain contact. In some embodiments, wherein the first source / drain contact is a front source / drain contact, wherein the second source / drain contact is a back source / drain contact. In some embodiments, wherein the inclined portion is cylindrical.

[0189] In some embodiments, an integrated circuit includes a complementary transistor, a first source / drain contact, a second source / drain contact, and an interconnection structure. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is located above the first transistor in a vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The interconnection structure is electrically coupled to the first source / drain contact and the second source / drain contact, and the interconnection structure includes a seed layer and an inclined portion located in the first source / drain contact, and the inclined portion extends from the seed layer to the second source / drain contact at an offset angle from the vertical direction. In some embodiments, the interconnection structure also includes a vertical portion that extends through the first source / drain contact. In some embodiments, the material of the inclined portion is different from the material of the first source / drain contact. In some embodiments, the material of the inclined portion is ruthenium. In some embodiments, the integrated circuit further comprises a metal-to-metal interface between the second source / drain contact and the inclined portion. In some embodiments, the offset angle is in the range of about 10 degrees to about 40 degrees. In some embodiments, the offset angle is in the range of about 40 degrees to about 70 degrees. In some embodiments, the offset angle is in the range of about 20 degrees to about 30 degrees. In some embodiments, one of the first source / drain region and the second source / drain region is N-type, and the other of the first source / drain region and the second source / drain region is P-type. In some embodiments, the first source / drain contact is a back source / drain contact, and the second source / drain contact is a front source / drain contact. In some embodiments, the first source / drain contact is a front source / drain contact, and the second source / drain contact is a back source / drain contact. In some embodiments, the inclined portion is cylindrical.

[0190] In some embodiments, a method for forming an integrated circuit includes: forming a first transistor and a second transistor on a substrate, wherein the second transistor is stacked on the first transistor in a vertical direction, wherein the second transistor is offset from the first transistor along a first direction perpendicular to the vertical direction; forming a first source / drain contact, wherein the first source / drain contact contacts the first source / drain region of the first transistor and the second transistor; forming a second source / drain contact, wherein the second source / drain contact contacts the second source / drain region of the first transistor and the second transistor, wherein the second source / drain region is offset from the first source / drain region along the vertical direction and the first direction; and forming an interconnect structure. Wherein, forming the interconnect structure includes: forming a vertical portion of an opening in the first source / drain contact; forming an inclined portion of the opening by extending the opening from the first portion along an offset angle to a depth associated with the second source / drain contact; and forming an inclined conductive portion and a vertical conductive portion in the opening. In some embodiments, wherein forming the inclined conductive portion and the vertical conductive portion in the opening includes depositing a first conductive material in the opening, wherein the first conductive material is different from a second conductive material of the first source / drain contact. In some embodiments, wherein the first conductive material is ruthenium. In some embodiments, wherein forming the inclined portion of the opening comprises forming the inclined portion of the opening by extending the opening from the first portion along the offset angle, wherein the offset angle is in the range of about 10 degrees to about 70 degrees. In some embodiments, wherein forming the first source / drain contact is forming a back source / drain contact. In some embodiments, wherein forming the second source / drain contact is forming a front source / drain contact before forming the first source / drain contact. In some embodiments, wherein forming the first source / drain contact is forming a front source / drain contact, the above-mentioned method of forming an integrated circuit also includes exposing the inclined conductive portion by removing the substrate; and forming the second source / drain contact is forming a back source / drain contact on an exposed portion of the inclined conductive portion.

[0191] In some embodiments, a method for forming an integrated circuit includes: forming a first transistor and a second transistor on a substrate, wherein the second transistor is stacked on the first transistor in a vertical direction, wherein the second transistor is offset from the first transistor along a first direction perpendicular to the vertical direction; forming a first source / drain contact, wherein the first source / drain contact contacts the first source / drain region of the first transistor and the second transistor; forming a second source / drain contact, wherein the second source / drain contact contacts the second source / drain region of the first transistor and the second transistor, wherein the second source / drain region is offset from the first source / drain region along the vertical direction and the first direction; and forming an interconnect structure. Wherein, forming the interconnect structure includes: forming an opening in the first source / drain contact; forming a seed layer in the opening; and forming an inclined portion on the seed layer, wherein the inclined portion is grown by a directional deposition operation at an offset angle from the vertical direction toward a position associated with the second source / drain contact. In some embodiments, the above-mentioned method for forming an integrated circuit also includes changing the profile of the inclined portion by performing an annealing operation. In some embodiments, forming the seed layer includes forming a metal layer, wherein a material of the metal layer is different from a material of the first source / drain contact.

[0192] The above summarizes the features of several embodiments, so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same goals and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, characterized in that: include: A complementary transistor comprising: a first transistor having a first source / drain region; and a second transistor located above the first transistor in a vertical direction, wherein the second transistor has a second source / drain region, wherein the second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction; a first source / drain contact electrically coupled to the first source / drain region; a second source / drain contact electrically coupled to the second source / drain region; and An interconnect structure is electrically coupled to the first source / drain contact and the second source / drain contact, wherein the interconnect structure includes an inclined portion extending from the first source / drain contact to the second source / drain contact at an offset angle from the vertical direction.

2. An integrated circuit, characterized in that: include: A complementary transistor comprising: a first transistor having a first source / drain region; and a second transistor located above the first transistor in a vertical direction, wherein the second transistor has a second source / drain region, wherein the second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction; a first source / drain contact electrically coupled to the first source / drain region; a second source / drain contact electrically coupled to the second source / drain region; and A conductive through-substrate layer is electrically coupled to the first source / drain contact and the second source / drain contact, wherein the conductive through-substrate layer includes a vertical portion extending through the first source / drain contact in the vertical direction and an inclined portion extending from the vertical portion to the second source / drain contact at an offset angle from the vertical direction.

3. An integrated circuit, characterized in that: include: A complementary transistor comprising: a first transistor having a first source / drain region; and a second transistor located above the first transistor in a vertical direction, wherein the second transistor has a second source / drain region, wherein the second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction; a first source / drain contact electrically coupled to the first source / drain region; a second source / drain contact electrically coupled to the second source / drain region; and An interconnect structure electrically coupled to the first source / drain contact and the second source / drain contact, wherein the interconnect structure includes a seed layer located in the first source / drain contact and an inclined portion, wherein the inclined portion extends from the seed layer to the second source / drain contact at an offset angle from the vertical direction.

4. The integrated circuit according to claim 1, wherein: The interconnect structure further includes a vertical portion extending through the first source / drain contact.

5. An integrated circuit as claimed in claim 1, 2 or 3, characterized in that The offset angle is in the range of 10 degrees to 40 degrees.

6. An integrated circuit as claimed in claim 1, 2 or 3, characterized in that The offset angle is in the range of 40 degrees to 70 degrees.

7. An integrated circuit as claimed in claim 1, 2 or 3, characterized in that The offset angle is in the range of 20 degrees to 30 degrees.

8. An integrated circuit as claimed in claim 1, 2 or 3, characterized in that The first source / drain contact is a back source / drain contact, and the second source / drain contact is a front source / drain contact.

9. An integrated circuit as claimed in claim 1, 2 or 3, characterized in that The first source / drain contact is a front source / drain contact, and the second source / drain contact is a back source / drain contact.

10. An integrated circuit as claimed in claim 1, 2 or 3, characterized in that The inclined portion is cylindrical.

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