Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a display area and a binding area arranged on one side of the display area, the display area comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprises a pixel driving circuit, and the binding area at least comprises a plurality of data outgoing lines; the display area further comprises a plurality of data signal lines and a plurality of data connecting lines, the data signal lines are configured to provide data signals for the pixel driving circuits, and the data signal lines are connected with the data outgoing lines through the data connecting lines; the at least one data connecting line comprises at least two transverse sub-lines extending in the first direction and at least two vertical sub-lines extending in the second direction, the two transverse sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns. According to the invention, the twill watermarks can be reduced or even eliminated.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, existing OLED display devices have problems such as mura. Utility Model Content

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a display device to solve the problems such as diagonal watermarks existing in the existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including a display area and a binding area arranged on one side of the display area, the display area including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, and the binding area including at least a plurality of data lead lines; the display area also includes a plurality of data signal lines and a plurality of data connection lines, the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns, and the first direction intersects with the second direction.

[0007] In an exemplary embodiment, at least two transverse sub-lines are arranged in at least one unit row, and the two transverse sub-lines connect different vertical sub-lines.

[0008] In an exemplary embodiment, at least two vertical sub-lines are disposed in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.

[0009] In an exemplary embodiment, an orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps an orthographic projection of at least one vertical sub-line on the display substrate.

[0010] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display area includes multiple conductive layers, the two horizontal sub-lines are arranged in the same conductive layer, the two vertical sub-lines are arranged in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines are arranged in different conductive layers.

[0011] In an exemplary embodiment, the multiple conductive layers include at least a first source-drain metal layer disposed on a substrate and a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line is disposed in the first source-drain metal layer, and the vertical sub-line is disposed in the second source-drain metal layer.

[0012] In an exemplary embodiment, the at least two horizontal sub-lines include at least a first horizontal sub-line and a second horizontal sub-line, and the at least two vertical sub-lines include at least a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: the first end of the first vertical sub-line is connected to the data lead-out line, the second end of the first vertical sub-line is connected to the first end of the first horizontal sub-line after extending in a direction away from the binding area, the second end of the first horizontal sub-line is connected to the first end of the second vertical sub-line after extending in a direction close to the second vertical sub-line, the second end of the second vertical sub-line is connected to the first end of the second horizontal sub-line after extending in a direction away from the binding area, and the second end of the second horizontal sub-line is connected to the data signal line after extending in a direction close to the data signal line.

[0013] In an exemplary embodiment, the display area further includes a plurality of first data connection blocks; in at least one circuit unit, the first data connection block is connected to the first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected to the first data connection block through a via; in at least another circuit unit, the first data connection block is connected to the first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected to the first data connection block through a via.

[0014] In an exemplary embodiment, the display area further includes a plurality of data transfer bars, and in at least one circuit unit, the first end of the first horizontal sub-line is connected to the first data connection block through the data transfer bar; in at least another circuit unit, the first end of the second horizontal sub-line is connected to the first data connection block through the data transfer bar.

[0015] In an exemplary embodiment, in at least one circuit unit, the first horizontal sub-line, the first data connection block and the data transfer bar are an interconnected integrated structure; in at least another circuit unit, the second horizontal sub-line, the first data connection block and the data transfer bar are an interconnected integrated structure.

[0016] In an exemplary embodiment, the display area further includes a plurality of first dummy electrodes, and a position and a connection structure of at least one of the first dummy electrodes in one circuit unit are the same as a position and a connection structure of at least one of the first data connection blocks in another circuit unit.

[0017] In an exemplary embodiment, in at least one circuit unit, the first vertical sub-line is connected to at least one first dummy electrode through a via hole; in at least another circuit unit, the second vertical sub-line is connected to at least one first dummy electrode through a via hole.

[0018] In an exemplary embodiment, the display area further includes a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected to the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected to the second data connection block through a via.

[0019] In an exemplary embodiment, in at least one circuit unit, the first transverse sub-line and the second data connection block are an integrated structure connected to each other.

[0020] In an exemplary embodiment, the display area further includes a plurality of second dummy electrodes, and a position and a connection structure of at least one of the second dummy electrodes in one circuit unit are the same as a position and a connection structure of at least one of the second data connection blocks in another circuit unit.

[0021] In an exemplary embodiment, in at least one circuit unit, the first vertical sub-line is connected to at least one second dummy electrode through a via hole; in at least another circuit unit, the second vertical sub-line is connected to at least one second dummy electrode through a via hole.

[0022] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0023] The present disclosure provides a display substrate and a display device, which effectively reduces the difference in the number of data connection line coupling unit columns in different unit rows by configuring at least one data connection line into at least two horizontal sub-lines and at least two vertical sub-lines, and configuring the two horizontal sub-lines in different unit rows and the two vertical sub-lines in different unit columns, and can effectively reduce or even eliminate the appearance of diagonal watermarks at the two corners of the display area close to the binding area.

[0024] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0026] Figure 1 is a structural schematic diagram of a display device;

[0027] Figure 2 It is a structural schematic diagram of a display substrate;

[0028] Figure 3 A schematic diagram of a planar structure of a display area in a display area;

[0029] Figure 4 A schematic diagram of a cross-sectional structure of a display area in a display area;

[0030] Figure 5 is an equivalent circuit diagram of a pixel driving circuit;

[0031] Figure 6 It is a schematic diagram of the structure of a data connection line in a display substrate;

[0032] Figure 7 It is a structural schematic diagram of a data connection line of an exemplary embodiment of the present disclosure;

[0033] Figure 8 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Fig. 9 It is a schematic diagram after forming a first semiconductor layer pattern according to an embodiment of the present disclosure;

[0035] Fig. 10A and Fig. 10B It is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0036] Fig.11A and Fig. 11B It is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0037] Fig. 12A and Fig. 12B It is a schematic diagram after forming a second semiconductor layer pattern according to an embodiment of the present disclosure;

[0038] Fig.13A and Fig. 13B It is a schematic diagram after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0039] Fig.14 It is a schematic diagram after forming a sixth insulating layer pattern according to an embodiment of the present disclosure;

[0040] Fig.15A and Fig. 15B It is a schematic diagram after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0041] Fig.16 It is a schematic diagram after forming a first planar layer pattern according to an embodiment of the present disclosure;

[0042] Fig.17A and Fig. 17B It is a schematic diagram after forming a fifth conductive layer pattern according to an embodiment of the present disclosure;

[0043] Fig. 17C It is a schematic diagram of connecting the horizontal sub-line and the vertical sub-line of an exemplary embodiment of the present disclosure;

[0044] Fig.18 It is a schematic diagram after forming a second planar layer pattern according to an embodiment of the present disclosure;

[0045] Fig.19A and Fig.19B It is a schematic diagram after forming an anode conductive layer pattern according to an embodiment of the present disclosure.

[0046] Description of reference numerals:

[0047] 11—first active layer; 12—second active layer; 13—third active layer;

[0048] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0049] 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line;

[0050] 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line;

[0051] 25—luminous signal line; 31—first electrode plate; 32—second electrode plate;

[0052] 33—opening; 34—plate connecting strip; 35—shielding line;

[0053] 41—first initial signal line; 42—second initial signal line; 43—third initial signal line;

[0054] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0055] 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode;

[0056] 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode;

[0057] 61—first initial connection line; 62—second initial connection line; 71—first power line;

[0058] 72—data signal line; 73—anode connection electrode; 74—power shielding block;

[0059] 80—data lead line; 81—first data connection line; 82—second data connection line;

[0060] 83—data transfer bar; 84—first data connection block; 85—second data connection block;

[0061] 86—first dummy electrode; 87—second dummy electrode; 91—first power supply wiring;

[0062] 92—second power supply wiring; 100—display area; 101—substrate;

[0063] 102—driving structure layer; 103—light emitting structure layer; 104—packaging structure layer;

[0064] 110—first area; 120—second area; 200—binding area;

[0065] 300—Border area. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0067] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0069] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0070] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0071] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0072] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0073] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0074] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0076] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, chamfers, curved edges and deformations, etc. "About" in this disclosure means that the limits are not strictly defined, and the values ​​within the range of process and measurement errors are allowed.

[0077] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0078] Figure 2 FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including a plurality of sub-pixels constituting a pixel array, the plurality of sub-pixels being configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (Active Area, referred to as AA). In an exemplary embodiment, the display substrate may be a flexible substrate, so that the display substrate may be deformable, such as curling, bending, folding or rolling up.

[0079] In an exemplary embodiment, the binding area 200 may include a lead area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area, and the lead area is connected to the display area 100 and includes at least a data lead. The bending area is connected to the lead area and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (BondingPad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0080] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks arranged on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove arranged on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.

[0081] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 may be provided with an isolation dam, which may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100, and the edge of the display area is the edge of one side of the display area binding area or the border area.

[0082] Figure 3FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3 As shown, the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the light-emitting signal line, and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0083] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

[0084] In other exemplary embodiments, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally or vertically, etc., which is not limited in the present disclosure.

[0085] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0086] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, and the light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0087] Figure 5 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 5 As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 10 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, fourth scanning signal line S4, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power line VDD).

[0088] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0089] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0090] In an exemplary embodiment, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the third node N3 .

[0091] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the fourth scan signal line S4 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0092] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0093] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0094] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0095] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0096] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second reset transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0097] In an exemplary embodiment, the eighth transistor T8 may be referred to as a third reset transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0098] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).

[0099] In an exemplary embodiment, the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, the second power line VSS is configured to provide a constant second voltage signal to the light emitting device, and the first voltage signal is a high level signal, and the second voltage signal is a low level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal may be constant voltage signals, which are not limited in the present disclosure.

[0100] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include a P-type transistor and an N-type transistor.

[0101] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide). The low-temperature polysilicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantages of low leakage current. The low-temperature polysilicon transistor and the metal oxide transistor are integrated on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0102] In an exemplary embodiment, the second transistor T2 may be a metal oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low temperature polysilicon transistors.

[0103] With the development of display technology, consumers have higher and higher requirements for the display effect and display quality of display products. Products such as full screen and narrow frame have gradually become the development trend of display products with their large screen-to-body ratio and ultra-narrow frame. Therefore, the narrowing of the frame or even the frameless design has been paid more and more attention in the design of OLED display products. In a display substrate, a fan-out line is located in the panel (Fanout in Panel, referred to as FIP) structure is adopted, and multiple data connection lines are arranged in the display area. One end of the multiple data connection lines is connected to the multiple data signal lines in the display area, and the other end of the multiple data connection lines extends to the binding area and is connected to the integrated circuit through the multiple data lead lines in the lead line area. Since the lead line area does not need to be provided with a fan-shaped oblique line, the width of the lead line area is reduced, thereby reducing the width of the lower frame.

[0104] Figure 6 FIG. 1 is a schematic diagram of the structure of a data connection line in a display substrate. Figure 6 As shown, the display area 100 may include a plurality of data signal lines 72, a plurality of first data connection lines 81, and a plurality of second data connection lines 82, and the binding area 200 may include a plurality of data lead lines 80. The plurality of first data connection lines 81 may be in the shape of a straight line or a folded line extending along the first direction X, and the plurality of data signal lines 72, the plurality of second data connection lines 82, and the plurality of data lead lines 80 may be in the shape of a straight line or a folded line extending along the second direction Y.

[0105] In an exemplary embodiment, at least one data signal line 72 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 72 is configured to provide a data signal to the connected pixel driving circuit. A plurality of first data connection lines 81 are sequentially arranged at set intervals in the second direction Y, and a plurality of second data connection lines 82 are sequentially arranged at set intervals in the first direction X, forming a structure arranged outward layer by layer. The first end of the second data connection line 82 is connected to the data lead-out line 80 in the binding area 200, the second end of the second data connection line 82 is connected to the first end of the first data connection line 81, and the second end of the first data connection line 81 is connected to the data signal line 72, so that the data signal line 72 in the display area is connected to the data lead-out line 80 in the binding area through the first data connection line 81 and the second data connection line 82, forming a FIP structure (also called a FIAA structure). In an exemplary embodiment, the first data connection line 81 and the second data connection line 82 are collectively referred to as data connection lines.

[0106] In an exemplary embodiment, since the data connection line is provided in a partial area of ​​the display area, the display area can be divided into a first area 110 and a second area 120 according to the presence or absence of the data connection line. The first area 110 can be an area where the first data connection line 81 and the second data connection line 82 are provided ( Figure 6 The second area 120 may be an area where the first data connection line 81 and the second data connection line 82 are not provided ( Figure 6 In an exemplary embodiment, the first area 110 may be referred to as a FIP area, and the second area 120 may be referred to as a non-FIP area.

[0107] At present, OLED display devices using FIP structures have problems such as mura. The inventors of this application have found that the mura problem is caused by the large difference in the number of coupling unit columns of the first data connection lines. Figure 6 As shown, the first data connection line farther from the binding area has a longer extension length, and is coupled with more unit columns, while the first data connection line closer to the binding area has a shorter extension length, and is coupled with fewer unit columns. Due to the large difference in the number of unit columns coupled by the first data connection lines in different unit rows, diagonal watermarks appear at the two corners of the display area close to the binding area.

[0108] In order to eliminate the diagonal watermark, the exemplary embodiment of the present disclosure provides a display substrate. In an exemplary embodiment, the display substrate includes a display area and a binding area arranged on one side of the display area, the display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and the binding area includes at least a plurality of data lead-out lines; the display area also includes a plurality of data signal lines, a plurality of first data connection lines, and a plurality of second data connection lines, the data signal lines are configured to provide data signals to the pixel driving circuit, and the data lead-out lines are connected to the data signal lines through the first data connection lines and the second data connection lines; at least one first data connection line includes at least two horizontal sub-lines extending along a first direction, the two horizontal sub-lines are arranged in different unit rows, and at least one second data connection line includes at least two vertical sub-lines extending along a second direction, the two vertical sub-lines are arranged in different unit columns, and the first direction and the second direction intersect.

[0109] In an exemplary embodiment, at least two transverse sub-lines are arranged in at least one unit row, and the two transverse sub-lines connect different vertical sub-lines.

[0110] In an exemplary embodiment, at least two vertical sub-lines are disposed in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.

[0111] In an exemplary embodiment, an orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps an orthographic projection of at least one vertical sub-line on the display substrate.

[0112] In an exemplary embodiment, the two horizontal sub-lines are a first horizontal sub-line and a second horizontal sub-line, and the two vertical sub-lines are a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: the first end of the first vertical sub-line is connected to the data lead-out line, the second end of the first vertical sub-line is connected to the first end of the first horizontal sub-line after extending in a direction away from the binding area, the second end of the first horizontal sub-line is connected to the first end of the second vertical sub-line after extending in a direction close to the second vertical sub-line, the second end of the second vertical sub-line is connected to the first end of the second horizontal sub-line after extending in a direction away from the binding area, and the second end of the second horizontal sub-line is connected to the data signal line after extending in a direction close to the data signal line.

[0113] The exemplary embodiments of the present disclosure provide a display substrate, which adopts a fan-out in panel (Fanout in Panel, referred to as FIP) structure. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer of the display area 100 may include a plurality of circuit units, and the light-emitting structure layer of the display area 100 may include a plurality of light-emitting units.

[0114] In an exemplary embodiment, a plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, a plurality of circuit units in each unit row are sequentially arranged along a first direction X, a plurality of circuit units in each unit column are sequentially arranged along a second direction Y, forming a circuit unit array arranged in an array, and the first direction X intersects with the second direction Y. A plurality of light-emitting units may form a plurality of light-emitting rows and a plurality of light-emitting columns, a plurality of light-emitting units in each light-emitting row are sequentially arranged along a first direction X, a plurality of light-emitting units in each light-emitting column are sequentially arranged along a second direction Y, forming a light-emitting unit array arranged in an array. In an exemplary embodiment, at least one circuit unit may include at least a pixel driving circuit, and at least one circuit unit may include a light-emitting device, the light-emitting device is connected to a pixel driving circuit of a corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to a current output by the connected pixel driving circuit.

[0115] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0116] Figure 7 FIG. 1 is a schematic diagram of a data connection line according to an exemplary embodiment of the present disclosure. Figure 7 As shown, the display area 100 may include a plurality of data signal lines 72 and a plurality of data connection lines, and the binding area 200 may include a plurality of data lead lines 80. The plurality of data signal lines 72 and the plurality of data lead lines 80 may be in the shape of a straight line or a folded line extending along the second direction Y, and the plurality of data connection lines may be in the shape of a folded line, including both a straight line extending along the first direction X and a straight line extending along the second direction Y. The data signal line 72 is configured to provide a data signal to the connected pixel driving circuit, and the data signal line 72 is connected to the data lead line 80 through the data connection line. Specifically, the first ends of the plurality of data connection lines are connected to the plurality of data lead lines 80 in the binding area 200, and the second ends of the plurality of data connection lines are connected to the plurality of data signal lines 72 after extending in a direction away from the binding area 200, so that the data signal lines 72 in the display area are connected to the data lead lines 80 in the binding area through the data connection lines, forming a FIP structure (also called a FIAA structure). Since the data connection line is set in the display area, the lead-out line area does not need to be set with a fan-shaped oblique line, thereby reducing the length of the second direction Y of the binding area, reducing the width of the lower frame, and increasing the screen-to-body ratio, which is conducive to achieving full-screen display.

[0117] In an exemplary embodiment, the display area 100 may have a center line O, and the plurality of data signal lines 72, the plurality of data connection lines, and the plurality of data lead lines 80 may be mirror-symmetric relative to the center line O, and the center line O may be a straight line that bisects the plurality of unit columns in the plurality of display areas and extends along the second direction Y.

[0118] In an exemplary embodiment, at least one data connection line may include at least two horizontal sub-lines and at least two vertical sub-lines, the shape of the horizontal sub-line may be a straight line or a folded line extending along the first direction X, the shape of the vertical sub-line may be a straight line or a folded line extending along the second direction Y, the two horizontal sub-lines may be arranged in different unit rows, the two vertical sub-lines may be arranged in different unit columns, and the horizontal sub-lines and the vertical sub-lines are interconnected to form a folded line-shaped data connection line including the horizontal sub-lines and the vertical sub-lines.

[0119] In an exemplary embodiment, at least two horizontal sub-lines may be disposed in at least one unit row, and the two horizontal sub-lines may connect different vertical sub-lines.

[0120] In an exemplary embodiment, at least two vertical sub-lines may be disposed in at least one unit column, and the two vertical sub-lines may connect different horizontal sub-lines.

[0121] In an exemplary embodiment, an orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps an orthographic projection of at least one vertical sub-line on the display substrate.

[0122] In an exemplary embodiment, the two horizontal sub-lines may be a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2 extending along a first direction X, and the two vertical sub-lines may be a first vertical sub-line 82-1 and a second vertical sub-line 82-2 extending along a second direction Y. The first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 are respectively arranged in different unit rows, the first horizontal sub-line 81-1 may be arranged in a unit row close to the binding area, and the second horizontal sub-line 81-2 may be arranged in a unit row on a side of the first horizontal sub-line 81-1 away from the binding area. The first vertical sub-line 82-1 and the second vertical sub-line 82-2 are respectively arranged in different unit columns, the first vertical sub-line 82-1 may be arranged in a unit column close to the center line O, and the second vertical sub-line 82-2 may be arranged in a unit column on a side of the first vertical sub-line 82-1 away from the center line O.

[0123] In an exemplary embodiment, in the first direction X, the first transverse subline 81-1 may be disposed on a side of the first vertical subline 82-1 away from the center line O, the second vertical subline 82-2 may be disposed on a side of the first transverse subline 81-1 away from the center line O, and the second transverse subline 81-2 may be disposed on a side of the second vertical subline 82-2 away from the center line O. In the second direction Y, the first transverse subline 81-1 may be disposed on a side of the first vertical subline 82-1 away from the binding area, the second vertical subline 82-2 may be disposed on a side of the first transverse subline 81-1 away from the binding area, and the second transverse subline 81-2 may be disposed on a side of the second vertical subline 82-2 away from the binding area.

[0124] In an exemplary embodiment, the data signal line 72 is connected to the data lead-out line 80 via the data connection line and may include: a first end of a first vertical sub-line 82-1 is connected to the data lead-out line 80, a second end of the first vertical sub-line 82-1 is connected to a first end of a first horizontal sub-line 81-1 after extending in a direction away from the binding area, a second end of the first horizontal sub-line 81-1 is connected to a first end of a second vertical sub-line 82-2 after extending in a direction away from the center line O (in a direction close to the second vertical sub-line 82-2), a second end of the second vertical sub-line 82-2 is connected to a first end of the second horizontal sub-line 81-2 after extending in a direction away from the binding area, and a second end of the second horizontal sub-line 81-2 is connected to the data signal line 72 after extending in a direction away from the center line O (in a direction close to the data signal line 72).

[0125] In an exemplary embodiment, at least one horizontal sub-line may be connected to two vertical sub-lines. For example, a first end of the first horizontal sub-line 81-1 is connected to the first vertical sub-line 82-1, and a second end of the first horizontal sub-line 81-1 is connected to the second vertical sub-line 82-2.

[0126] In an exemplary embodiment, at least one vertical subline may be connected to two horizontal sublines. For example, a first end of the second vertical subline 82-2 is connected to the first horizontal subline 81-1, and a second end of the second vertical subline 82-2 is connected to the second horizontal subline 81-2.

[0127] In an exemplary embodiment, the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 can be referred to as a first data connection line 81, and the first vertical sub-line 82-1 and the second vertical sub-line 82-2 can be referred to as a second data connection line 82, that is, the data connection line may include a first data connection line 81 and a second data connection line 82, the first data connection line 81 may include a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2, and the second data connection line 82 may include a first vertical sub-line 82-1 and a second vertical sub-line 82-2.

[0128] In an exemplary embodiment, the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead line through a data connection line. Alternatively, the number of data connection lines in the display area may be less than the number of data signal lines, and a portion of the data signal lines in the display area are connected to the corresponding data lead lines through the data connection lines, and another portion of the data signal lines are directly connected to the data lead lines, which is not limited in the present disclosure.

[0129] In an exemplary embodiment, the data lead-out line 80 may be directly connected to the data signal line 72 and the data connection line, or may be connected through a via hole, which is not limited in the present disclosure.

[0130] In an exemplary embodiment, the display area may be divided into a first area 110 and a second area 120, and the first area 110 may be an area where horizontal sub-lines and vertical sub-lines are provided ( Figure 7 The second area 120 may be an area where no horizontal sub-lines and vertical sub-lines are set ( Figure 7 areas outside the medium-dark areas).

[0131] Figure 8 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, Figure 7 In an exemplary embodiment, the display area may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel driving circuit, which is connected to the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the fourth scanning signal line 24, the light emitting signal line 25, the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, the first power line 71, and the data signal line 72, respectively.

[0132] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24 and the light emitting signal line 25 are configured to respectively provide the first scan signal, the second scan signal, the third scan signal, the fourth scan signal and the light emitting control signal to the pixel driving circuit, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 are configured to respectively provide the first initial signal, the second initial signal and the third initial signal to the pixel driving circuit, the first power line 71 is configured to provide the first power signal to the pixel driving circuit, and the data signal line 72 is configured to provide the data signal to the pixel driving circuit. Among them, the plurality of signal lines connected to the pixel driving circuit may be located in the corresponding circuit unit.

[0133] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be straight lines or folded lines with the main parts extending along the first direction X, and the shapes of the first power line 71 and the data signal line 72 can be straight lines or folded lines with the main parts extending along the second direction Y.

[0134] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" means "the main part of A extends along direction B".

[0135] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The storage capacitor may include a first electrode plate and a second electrode plate stacked together, and the plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, a seventh transistor T7 as a second reset transistor, and an eighth transistor T8 as a third reset transistor. Among them, the second transistor T2 may be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 may be low temperature polysilicon transistors.

[0136] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first electrode of the second transistor T2 is connected to the first electrode plate of the storage capacitor (also the gate electrode of the third transistor T3). The first electrode of the third transistor T3 is respectively connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line 72. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line 25, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line 25, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the second scanning signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0137] In an exemplary embodiment, in at least one circuit unit, the fourth scan signal line 24 may be disposed on the side of the storage capacitor (third transistor T3) in the opposite direction of the second direction Y, the first scan signal line 21 may be disposed on the side of the fourth scan signal line 24 away from the storage capacitor, the third scan signal line 23 and the second initial signal line 42 may be disposed on the side of the first scan signal line 21 away from the storage capacitor, and the first initial signal line 41 may be disposed on the side of the third scan signal line 23 away from the storage capacitor. The light-emitting signal line 25 may be disposed on the side of the storage capacitor in the second direction Y, and the second scan signal line 22 and the third initial signal line 43 may be disposed on the side of the light-emitting signal line 25 away from the storage capacitor.

[0138] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third scan signal line 23 on the substrate, and the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 on the substrate.

[0139] In an exemplary embodiment, at least one circuit unit may further include a first initial connection line 61. The first initial connection line 61 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y, and is connected to the first initial signal line 41, and the first initial signal line 41 and the first initial connection line 61 form a meshed connection structure for transmitting the first initial signal.

[0140] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 62. The second initial connection line 62 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y, and is connected to the second initial signal line 42, and the second initial signal line 42 and the second initial connection line 62 form a meshed connection structure for transmitting the second initial signal.

[0141] In an exemplary embodiment, the display area may further include a plurality of data connection lines, and at least one data connection line may include a first horizontal sub-line 81-1, a second horizontal sub-line 81-2, a first vertical sub-line 82-1, and a second vertical sub-line 82-2. The first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 may be in the shape of a straight line or a folded line extending along the first direction X, the first horizontal sub-line 81-1 may be arranged in the M+5th unit row, and the second horizontal sub-line 81-2 may be arranged in the Mth unit row. The first vertical sub-line 82-1 and the second vertical sub-line 82-2 may be in the shape of a straight line or a folded line extending along the second direction Y, the first vertical sub-line 82-1 may be arranged between the N+10th unit column and the N+11th unit column, and the second vertical sub-line 82-2 may be arranged between the Nth unit column and the N+1th unit column.

[0142] In an exemplary embodiment, the first end of the first vertical sub-line 82-1 is connected to the data lead-out line of the binding area, the second end of the first vertical sub-line 82-1 is extended in the opposite direction of the second direction Y (towards the direction close to the first horizontal sub-line 81-1), and is connected to the first end of the first horizontal sub-line 81-1, the second end of the first horizontal sub-line 81-1 is extended in the opposite direction of the first direction X (towards the direction close to the second vertical sub-line 82-2), and is connected to the first end of the second vertical sub-line 82-2, the second end of the second vertical sub-line 82-2 is extended in the opposite direction of the second direction Y (towards the direction close to the second horizontal sub-line 81-2), and is connected to the first end of the second horizontal sub-line 81-2, and the second end of the second horizontal sub-line 81-2 is extended in the opposite direction of the first direction X (towards the direction close to the data signal line 72), and is connected to the data signal line 72.

[0143] In an exemplary embodiment, at least one circuit unit may further include a data transfer bar 83 and a first data connection block 84. The data transfer bar 83 may be in a bar shape extending along the second direction Y, and the first data connection block 84 may be in a block shape (such as a rectangle). The first end of the data transfer bar 83 is connected to the first horizontal sub-line 81-1 or the second horizontal sub-line 81-2, and the second end of the data transfer bar 83 is connected to the first data connection block 84. The first data connection block 84 is configured to be connected to the first vertical sub-line 82-1 or the second vertical sub-line 82-2. For example, in the Mth unit row, the first data connection block 84 is connected to the second horizontal sub-line 81-2 through the data transfer bar 83, and the second end of the second vertical sub-line 82-2 is connected to the first data connection block 84, thereby realizing the connection between the second end of the second vertical sub-line 82-2 and the first end of the second horizontal sub-line 81-2. For another example, in the M+5th unit row, the first data connection block 84 is connected to the first horizontal sub-line 81-1 through the data transfer bar 83, and the second end of the first vertical sub-line 82-1 is connected to the first data connection block 84, thereby realizing the connection between the second end of the first vertical sub-line 82-1 and the first end of the first horizontal sub-line 81-1.

[0144] In an exemplary embodiment, at least one circuit unit may further include a second data connection block 85. The second data connection block 85 may be in a block shape (e.g., rectangular) and connected to the second end of the first horizontal sub-line 81-1. The second data connection block 85 is configured to be connected to the first end of the second vertical sub-line 82-2. For example, in the M+5th unit row, the second data connection block 85 is connected to the second end of the first horizontal sub-line 81-1, and the first end of the second vertical sub-line 82-2 is connected to the second data connection block 85, thereby realizing the connection between the second end of the first horizontal sub-line 81-1 and the first end of the second vertical sub-line 82-2.

[0145] In an exemplary embodiment, at least one circuit unit may further include a first dummy electrode 86, which may be block-shaped (e.g., rectangular) and configured to be connected to the vertical sub-line. The position and connection structure of the first dummy electrode 86 in one circuit unit may be substantially the same as the position and connection structure of the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated.

[0146] In an exemplary embodiment, at least one circuit unit may further include a second dummy electrode 87. The second dummy electrode 87 may be block-shaped (e.g., rectangular) and configured to be connected to the vertical sub-line. The position and connection structure of the second dummy electrode 87 in one circuit unit may be substantially the same as the position and connection structure of the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated.

[0147] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving structure layer of the display area may include multiple conductive layers, the horizontal sub-lines may be set in the same conductive layer, the vertical sub-lines may be set in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines may be set in different conductive layers.

[0148] In an exemplary embodiment, the multiple conductive layers may include at least a first source-drain metal layer (SD1) disposed on a substrate and a second source-drain metal layer (SD2) disposed on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line may be disposed in the first source-drain metal layer, and the vertical sub-line may be disposed in the second source-drain metal layer.

[0149] In an exemplary embodiment, the first data connection block 84 , the second data connection block 85 , the first dummy electrode 86 , and the second dummy electrode 87 may be disposed in the first source-drain metal layer.

[0150] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0151] In an exemplary embodiment, taking 72 circuit units (6 unit rows and 12 unit columns) as an example, the preparation process of the display substrate may include the following operations.

[0152] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process, forming a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, such as Fig. 9 shown.

[0153] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integral structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0154] In an exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 may be located on one side of the third active layer 13 in the present circuit unit, and the fourth active layer 14 and the fifth active layer 15 may be located on the other side of the third active layer 13 in the present circuit unit. In the second direction Y, the first active layer 11 and the fourth active layer 14 may be located on one side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y.

[0155] In an exemplary embodiment, the third active layer 13 may have an “Ω” shape, the fourth active layer 14 and the sixth active layer 16 may have an “L” shape, and the first active layer 11, the fifth active layer 15, the seventh active layer 17, and the eighth active layer 18 may have an “I” shape.

[0156] In an exemplary embodiment, the first active layer 11, the third active layer 13 to the eighth active layer 18 may each include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be separately provided.

[0157] In an exemplary embodiment, in one unit row, the first regions 15-1 of the fifth active layers in two adjacent circuit units may be connected to each other, and the fifth active layers in the two circuit units may be connected to each other as an integrated structure. For example, the fifth active layer of the Nth unit column and the fifth active layer of the N+1th unit column may be connected to each other as an integrated structure, the fifth active layer of the N+2th unit column and the fifth active layer of the N+3th unit column may be connected to each other as an integrated structure, the fifth active layer of the N+4th unit column and the fifth active layer of the N+5th unit column may be connected to each other as an integrated structure, the fifth active layer of the N+6th unit column and the fifth active layer of the N+7th unit column may be connected to each other as an integrated structure, the fifth active layer of the N+8th unit column and the fifth active layer of the N+9th unit column may be connected to each other as an integrated structure, and the fifth active layer of the N+10th unit column and the fifth active layer of the N+11th unit column may be connected to each other as an integrated structure. Since the first area of ​​the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the fifth active layers of adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0158] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the first semiconductor layer of the Nth cell column and the first semiconductor layer of the N+1th cell column may be mirror-symmetric with respect to a column boundary, and the first semiconductor layer of the N+1th cell column and the first semiconductor layer of the N+2th cell column may be mirror-symmetric with respect to a column boundary. In an exemplary embodiment, the shapes of the first semiconductor layers in a plurality of cell rows may be substantially the same.

[0159] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the first transistor, the third transistor to the seventh transistor are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.

[0160] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on a substrate having the aforementioned pattern, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig. 10A and Fig. 10B As shown, Fig. 10B for Fig. 10A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0161] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 25 , and a first electrode plate 31 of a storage capacitor.

[0162] In an exemplary embodiment, the shape of the first electrode plate 31 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 31 may simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0163] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line with the main part extending along the first direction X. The first scan signal line 21 can be located on the side of the first electrode 31 in the opposite direction of the second direction Y. The area where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0164] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line with the main part extending along the first direction X. The second scan signal line 22 can be located on one side of the first electrode plate 31 in the second direction Y. The area where the second scan signal line 22 overlaps with the seventh active layer can be used as the gate electrode of the seventh transistor T7, and the area where the second scan signal line 22 overlaps with the eighth active layer can be used as the gate electrode of the eighth transistor T8.

[0165] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main part extending along the first direction X. The third scan signal line 23 can be located on the side of the first scan signal line 21 away from the first electrode plate 31, and the area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0166] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 25 can be located between the second scanning signal line 22 and the first electrode plate 31. The area where the light-emitting signal line 25 overlaps with the fifth active layer can be used as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 25 overlaps with the sixth active layer can be used as the gate electrode of the sixth transistor T6.

[0167] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 25 can be designed with unequal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0168] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 25 may include an overlapping area with the first semiconductor layer and a non-overlapping area with the first semiconductor layer, and the width of the signal line in the overlapping area with the first semiconductor layer may be greater than the width of the signal line in the non-overlapping area with the first semiconductor layer.

[0169] In an exemplary embodiment, the first conductive layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the first conductive layer of the Nth cell column and the first conductive layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, and the first conductive layer of the N+1th cell column and the first conductive layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the first conductive layers in the plurality of cell rows may be substantially the same.

[0170] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 and the third transistor T3 to the eighth transistor T8 are both conductorized.

[0171] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Fig.11A and Fig. 11B As shown, Fig. 11B for Fig.11A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0172] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second electrode 32 of the storage capacitor, a shielding line 35 and a first initial signal line 41 .

[0173] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0174] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. The opening 33 may be rectangular and may be located in the middle of the second electrode plate 32, so that the second electrode plate 32 forms a ring structure. The opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a thirteenth via hole formed subsequently. The thirteenth via hole is located in the opening 33 and exposes the first electrode plate 31, so that the first connection electrode formed subsequently is connected to the first electrode plate 31.

[0175] In an exemplary embodiment, a plate connecting bar 34 is disposed on the second electrode plate 32. The plate connecting bar 34 may be in the shape of a bar extending along the first direction X, and may be disposed on one side of the second electrode plate 32 in the first direction X or on one side in the opposite direction of the first direction X. A first end of the plate connecting bar 34 is connected to the second electrode plate 32 in the current circuit unit, and a second end of the plate connecting bar 34 is connected to the second electrode plate 32 in an adjacent circuit unit in the first direction X or in the opposite direction of the first direction X.

[0176] In an exemplary embodiment, in a unit row, the second plates 32 and the plate connecting strips 34 in two adjacent circuit units are interconnected as an integrated structure. Since the second plates 32 in each circuit unit are connected to the first power line formed later, by forming the second plates 32 of adjacent circuit units into an integrated structure that is interconnected, the second plates of the integrated structure can be reused as power signal lines, which can ensure that the second plates of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0177] In an exemplary embodiment, the shape of the shielding line 35 can be a straight line or a broken line with the main part extending along the first direction X, and can be located between the first scanning signal line 21 and the second electrode plate 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and is configured as a bottom gate electrode of the second transistor T2.

[0178] In an exemplary embodiment, the shielding lines 35 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0179] In an exemplary embodiment, the shape of the first initial signal line 41 may be a straight line or a folded line with a main portion extending along the first direction X, and the first initial signal line 41 may be located on a side of the third scan signal line 23 away from the second electrode plate 32. A first initial connection block 41-1 may be provided on the first initial signal line 41 of each circuit unit, and the first initial connection block 41-1 may be in a block shape (such as a rectangle) and connected to the first initial signal line 41, and the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a seventh connection electrode formed subsequently.

[0180] In an exemplary embodiment, the first initial connection blocks 41-1 of some of the circuit units adjacent in the first direction X may be connected to each other to form an interconnected integrated structure, so that some of the adjacent circuit units share the same first initial connection block 41-1. For example, the first initial connection block 41-1 of the N+1th unit column and the first initial connection block 41-1 of the N+2th unit column are interconnected integrated structures. For another example, the first initial connection block 41-1 of the N+3th unit column and the first initial connection block 41-1 of the N+4th unit column are interconnected integrated structures.

[0181] In an exemplary embodiment, the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the second conductive layer of the Nth cell column and the second conductive layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, and the second conductive layer of the N+1th cell column and the second conductive layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the second conductive layers in the plurality of cell rows may be substantially the same.

[0182] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, such as Fig. 12A and Fig. 12B As shown, Fig. 12B for Fig. 12A Schematic plan view of the second semiconductor layer in FIG.

[0183] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .

[0184] In an exemplary embodiment, the second active layer 12 may be in an “L” shape, and an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the shielding line 35 on the substrate.

[0185] In an exemplary embodiment, the first region 12 - 1 of the second active layer may be located on a side of the shielding line 35 away from the second electrode plate 32 , and the second region 12 - 2 of the second active layer may be located on a side of the shielding line 35 close to the second electrode plate 32 .

[0186] In an exemplary embodiment, the second semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the second semiconductor layer of the Nth cell column and the second semiconductor layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, and the second semiconductor layer of the N+1th cell column and the second semiconductor layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the second semiconductor layers in the plurality of cell rows may be substantially the same.

[0187] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the second transistor T2 is an oxide transistor. In an exemplary embodiment, the second semiconductor film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0188] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, such as Fig.13A and Fig. 13B As shown, Fig. 13B for Fig.13A In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0189] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a fourth scan signal line 24 , a second preliminary signal line 42 , and a third preliminary signal line 43 .

[0190] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main part extending along the first direction X. The fourth scan signal line 24 can be located between the first scan signal line 21 and the second electrode plate 32. The area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0191] In an exemplary embodiment, the orthographic projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the orthographic projection of the shielding line 35 on the substrate, and the fourth scan signal line 24 and the shielding line 35 can be connected to the same signal source, so that the shielding line 35 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0192] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 42 can be located on the side of the first scanning signal line 21 away from the second electrode plate 32. A second initial connection block 42-1 can be provided on the second initial signal line 42 of each circuit unit. The shape of the second initial connection block 42-1 can be block-shaped (such as a rectangle) and connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through the subsequently formed eighth connection electrode.

[0193] In an exemplary embodiment, the positive projection of the second initial signal line 42 on the substrate at least partially overlaps with the positive projection of the third scanning signal line 23 on the substrate. The second initial signal line 42 transmitting a constant voltage can shield the influence of the third scanning signal line 23 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0194] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main part extending along the first direction X. The third initial signal line 43 can be located between the second electrode plate 32 and the first initial signal line 41. A third initial connection block 43-1 can be provided on the third initial signal line 43 of each circuit unit. The shape of the third initial connection block 43-1 can be block-shaped (such as a rectangle) and connected to the third initial signal line 43. The third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through a ninth connection electrode formed subsequently.

[0195] In an exemplary embodiment, the third initial connection blocks 43-1 of some of the circuit units adjacent in the first direction X may be connected to each other to form an interconnected integrated structure, so that some of the adjacent circuit units share the same third initial connection block 43-1. For example, the third initial connection block 43-1 of the Nth unit column and the third initial connection block 43-1 of the N+1th unit column are interconnected integrated structures. For another example, the third initial connection block 43-1 of the N+2th unit column and the third initial connection block 43-1 of the N+3th unit column are interconnected integrated structures.

[0196] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate. The third initial signal line 43 transmitting a constant voltage can shield the influence of the second scanning signal line 22 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0197] In an exemplary embodiment, the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the third conductive layer of the Nth cell column and the third conductive layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, and the third conductive layer of the N+1th cell column and the third conductive layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the third conductive layers in a plurality of cell rows may be substantially the same.

[0198] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, and providing a plurality of vias on the sixth insulating layer, such as Fig.14 shown.

[0199] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0200] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed seventh connecting electrode to the first region of the first active layer through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer), and the fifth via hole V5 is configured to connect a subsequently formed fifth connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the sixth via hole V6 is configured to connect a subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fourth active layer, and the seventh via hole V7 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the fifth active layer, and the eighth via hole V8 is configured to connect a fourth connection electrode formed subsequently to the first region of the fifth active layer through the via hole. In an exemplary embodiment, since the first regions of the fifth active layers of some adjacent circuit units in a unit row are connected to each other, some adjacent circuit units can share one eighth via hole V8.

[0208] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the ninth via hole V9 is configured to connect a subsequently formed sixth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect a subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer, and the twelfth via hole V12 is configured to connect a subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0212] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first electrode plate 31, and the thirteenth via hole V13 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 31 through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the plate connecting bar 34 of the second plate 32 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourteenth via hole V14 are etched away, exposing the surface of the plate connecting bar 34, and the fourteenth via hole V14 is configured to connect the subsequently formed fourth connecting electrode to the plate connecting bar 34 through the via hole. In an exemplary embodiment, since the second plates 32 of adjacent circuit units in a unit row are connected to each other through the plate connecting bar 34, adjacent circuit units in a unit row can share one fourteenth via hole V14.

[0214] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first initial connection block 41-1, and the fifteenth via hole V15 is configured to connect the subsequently formed seventh connection electrode to the first initial connection block 41-1 through the via hole.

[0215] In an exemplary embodiment, since the first initial connection blocks 41 - 1 of some adjacent circuit units in a unit row are interconnected as an integrated structure, the adjacent circuit units share the same first initial connection block 41 - 1 , and thus some adjacent circuit units may share a fifteenth via V15 .

[0216] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the sixth insulating layer in the sixteenth via hole V16 is etched away to expose the surface of the second initial connection block 42-1, and the sixteenth via hole V16 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 42-1 through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the sixth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the third initial connection block 43-1, and the seventeenth via hole V17 is configured to connect the subsequently formed ninth connection electrode to the third initial connection block 43-1 through the via hole.

[0218] In an exemplary embodiment, since the third initial connection blocks 43-1 of some adjacent circuit units in a unit row are interconnected as an integrated structure, the adjacent circuit units share the same third initial connection block 43-1, and thus some adjacent circuit units may share a seventeenth via V17.

[0219] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, such as Fig.15A and Fig. 15B As shown, Fig. 15B for Fig.15A In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0220] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0221] In an exemplary embodiment, the shape of the first connection electrode 51 may be a strip shape with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the first region of the second active layer through the third via hole V3. The second end of the first connection electrode 51 is connected to the first electrode plate 31 through the thirteenth via hole V13 after extending along the second direction Y. In an exemplary embodiment, since the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 enables the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first electrode plate 31 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0222] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip whose main part extends along the second direction Y. The first end of the second connection electrode 52 is connected to the second region of the first active layer through the second via hole V2. After the second end of the second connection electrode 52 extends along the second direction Y, it is connected to the second region of the third active layer (also the first region of the sixth active layer) through the sixth via hole V6. The portion between the first end and the second end of the second connection electrode 52 is connected to the second region of the second active layer through the fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 enables the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0223] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (eg, rectangular), connected to the first region of the fourth active layer through the seventh via hole V7, and configured to be connected to a subsequently formed data signal line.

[0224] In an exemplary embodiment, the fourth connection electrode 54 may be in the shape of a strip extending along the second direction Y, the first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the eighth via hole V8, and the second end of the fourth connection electrode 54 is connected to the plate connection bar 34 through the fourteenth via hole V14 after extending in the opposite direction of the second direction Y. Since the plate connection bar 34 is connected to the second plate 32, the first electrode of the fifth transistor T5 in the circuit unit and the second plate 32 of the storage capacitor have the same potential.

[0225] In an exemplary embodiment, since some adjacent two circuit cells in one cell row share one eighth via hole V8 and one fourteenth via hole V14 , some adjacent circuit cells may share one fourth connection electrode 54 .

[0226] In an exemplary embodiment, at least one circuit unit may further include a power connection block 54-1. The power connection block 54-1 may be in the shape of a strip extending along the first direction X, a first end of the power connection block 54-1 is connected to a second end of the fourth connection electrode 54, a second end of the power connection block 54-1 extends in a direction away from the fourth connection electrode 54, and the power connection block 54-1 is configured to be connected to a first power line formed subsequently.

[0227] In an exemplary embodiment, in at least one circuit unit, the fourth connection electrode 54 and the power connection block 54-1 may be an integrated structure connected to each other. Since some adjacent circuit units may share one fourth connection electrode 54, the fourth connection electrode 54 and the power connection block 54-1 in some two adjacent circuit units may be an integrated structure connected to each other, which can ensure that the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor of some adjacent circuit units have the same potential, which is beneficial to improve the uniformity of the panel, avoid poor display of the display substrate, and ensure the display effect of the display substrate.

[0228] In an exemplary embodiment, the fifth connection electrode 55 may be in a strip shape with a main portion extending along the second direction Y, a first end of the fifth connection electrode 55 is connected to the first region of the third active layer through a fifth via hole V5, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer through a twelfth via hole V12. In an exemplary embodiment, since the first region of the third active layer serves as the second region of the fourth active layer and the second region of the fifth active layer at the same time, the fifth connection electrode 55 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0229] In an exemplary embodiment, the shape of the sixth connection electrode 56 may be a block shape (such as a rectangle), and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to the anode connection electrode formed subsequently.

[0230] In an exemplary embodiment, the seventh connection electrode 57 may be in a strip shape extending along the first direction X, a first end of the seventh connection electrode 57 is connected to the first region of the first active layer through a first via hole V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 through a fifteenth via hole V15. In an exemplary embodiment, since the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 enables the first initial signal transmitted by the first initial signal line 41 to be written into the first electrode of the first transistor T1.

[0231] In an exemplary embodiment, since some adjacent circuit units share the same first initial connection block 41-1, the seventh connection electrodes 57 of some adjacent circuit units can be interconnected as an integrated structure, which can ensure that the first electrodes of the first transistors T1 of some adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate. For example, the seventh connection electrode 57 of the N+1th unit column and the seventh connection electrode 57 of the N+2th unit column are interconnected as an integrated structure. For another example, the seventh connection electrode 57 of the N+3th unit column and the seventh connection electrode 57 of the N+4th unit column are interconnected as an integrated structure.

[0232] In an exemplary embodiment, the shape of the eighth connection electrode 58 may be a strip shape extending along the first direction X, a first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 through a sixteenth via hole V16. In an exemplary embodiment, since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 implements writing of the second initial signal transmitted by the second initial signal line 42 into the first electrode of the seventh transistor T7.

[0233] In an exemplary embodiment, the ninth connection electrode 59 may be in a strip shape extending along the first direction X, a first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer through an eleventh via hole V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 through a seventeenth via hole V17. In an exemplary embodiment, since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 implements writing of the third initial signal transmitted by the third initial signal line 43 into the first electrode of the eighth transistor T8.

[0234] In an exemplary embodiment, since some adjacent circuit units share the same third initial connection block 43-1, the ninth connection electrodes 59 of some adjacent circuit units can be interconnected as an integrated structure, which can ensure that the first electrodes of the eighth transistors T8 of some adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate. For example, the ninth connection electrode 59 of the Nth unit column and the ninth connection electrode 59 of the N+1th unit column are interconnected as an integrated structure. For another example, the ninth connection electrode 59 of the N+2th unit column and the ninth connection electrode 59 of the N+3th unit column are interconnected as an integrated structure.

[0235] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a seventh connection block 57-1. The seventh connection block 57-1 may be in the shape of a bar extending along the second direction Y and connected to the seventh connection electrode 57, and the seventh connection block 57-1 is configured to be connected to the first initial connection line formed subsequently.

[0236] In an exemplary embodiment, the seventh connection block 57-1 may be disposed between some adjacent circuit units, and the adjacent circuit units share the same seventh connection block 57-1, and the seventh connection electrodes 57 in the two circuit units and the shared seventh connection block 57-1 are interconnected as an integrated structure.

[0237] In an exemplary embodiment, the seventh connection block 57-1 may be disposed between the N-1th cell column and the Nth cell column. For another example, the seventh connection block 57-1 may be disposed between the N+3th cell column and the N+4th cell column. For another example, the seventh connection block 57-1 may be disposed between the N+7th cell column and the N+8th cell column.

[0238] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include an eighth connection block 58-1. The eighth connection block 58-1 may be in the shape of a zigzag line extending along the second direction Y and connected to the eighth connection electrode 58. The eighth connection block 58-1 is configured to be connected to a second initial connection line formed subsequently.

[0239] In an exemplary embodiment, the eighth connection blocks 58-1 of some adjacent circuit units may be connected to each other, and the eighth connection electrodes 58 and the eighth connection blocks 58-1 in two circuit units are an integrated structure connected to each other. For example, the eighth connection block 58-1 may be arranged in the N+1th unit column and the N+2th unit column. For another example, the eighth connection block 58-1 may be arranged in the N+5th unit column and the N+6th unit column. For another example, the eighth connection block 58-1 may be arranged in the N+9th unit column and the N+10th unit column.

[0240] In an exemplary embodiment, the fifth conductive layer may further include a plurality of first wirings, which may be in the shape of a straight line or a folded line extending along the first direction X, and may be located between the first scan signal line and the first initial signal line 41 .

[0241] In an exemplary embodiment, at least one first routing line may include a transverse sub-line and a first power routing line 91, and a first break K1 is provided between the transverse sub-line and the first power routing line 91, and the first break K1 may cut off the transverse sub-line from the first power routing line 91, so that the transverse sub-lines and the first power routing line 91 on both sides of the first break K1 are insulated from each other. For example, the first routing line in the Mth unit row may include a second transverse sub-line 81-2 and a first power routing line 91 sequentially arranged along the first direction X. For another example, the first routing line in the M+1th unit row may include a fourth transverse sub-line 81-4 and a first power routing line 91 sequentially arranged along the first direction X. For another example, the first routing line in the M+2th unit row may include a sixth transverse sub-line 81-6 and a first power routing line 91 sequentially arranged along the first direction X.

[0242] In an exemplary embodiment, at least one first routing line may include a transverse sub-line and two first power routing lines 91, and a first break K1 is provided between the two first power routing lines 91 and the transverse sub-line, and the first break K1 may cut off the transverse sub-line from the first power routing line 91. For example, the first routing line in the M+5th unit row may include the first power routing line 91, the first transverse sub-line 81-1, and the first power routing line 91 sequentially arranged along the first direction X.

[0243] In an exemplary embodiment, at least one first routing line may include two transverse sub-lines and a first power routing line 91, and a first break K1 may be provided between the two transverse sub-lines, and the first break K1 may cut off the two transverse sub-lines, so that the two transverse sub-lines on both sides of the first break K1 are insulated from each other. A first break K1 is provided between the transverse sub-line and the first power routing line 91, and the first break K1 may cut off the transverse sub-line from the first power routing line 91. For example, the first routing line in the M+3th unit row may include the seventh transverse sub-line 81-7, the fifth transverse sub-line 81-5, and the first power routing line 91 arranged in sequence along the first direction X. For another example, the first routing line in the M+4th unit row may include the eighth transverse sub-line 81-8, the third transverse sub-line 81-3, and the first power routing line 91 arranged in sequence along the first direction X.

[0244] In an exemplary embodiment, the first horizontal sub-line 81-1 in the M+5th unit row and the second horizontal sub-line 81-2 in the Mth unit row can be referred to as the first first data connection line 81, one end of the two horizontal sub-lines can be connected together through a second vertical sub-line formed subsequently, the other end of the first horizontal sub-line 81-1 is configured to be connected to the first vertical sub-line formed subsequently, and the other end of the second horizontal sub-line 81-2 is configured to be connected to a data signal line formed subsequently.

[0245] In an exemplary embodiment, the third horizontal sub-line 81-3 in the M+4th unit row and the fourth horizontal sub-line 81-4 in the M+1th unit row can be referred to as the second first data connection line 81, one end of the two horizontal sub-lines can be connected together through a subsequently formed fourth vertical sub-line, the other end of the third horizontal sub-line 81-3 is configured to be connected to the subsequently formed third vertical sub-line, and the other end of the fourth horizontal sub-line 81-4 is configured to be connected to a subsequently formed data signal line.

[0246] In an exemplary embodiment, the fifth horizontal sub-line 81-5 in the M+3th unit row and the sixth horizontal sub-line 81-6 in the M+2th unit row can be referred to as the third first data connection line 81, one end of the two horizontal sub-lines can be connected together through a subsequently formed sixth vertical sub-line, the other end of the fifth horizontal sub-line 81-5 is configured to be connected to the subsequently formed fifth vertical sub-line, and the other end of the sixth horizontal sub-line 81-6 is configured to be connected to a subsequently formed data signal line.

[0247] In an exemplary embodiment, the seventh horizontal sub-line 81-7 in the M+3th unit row can be referred to as the fourth first data connection line 81, the first end of the seventh horizontal sub-line 81-7 is configured to be connected to the subsequently formed seventh vertical sub-line, and the second end of the seventh horizontal sub-line 81-7 is configured to be connected to the subsequently formed data signal line.

[0248] In an exemplary embodiment, the eighth horizontal sub-line 81-8 in the M+4th unit row can be referred to as the fifth first data connection line 81, the first end of the eighth horizontal sub-line 81-8 is configured to be connected to the subsequently formed eighth vertical sub-line, and the second end of the eighth horizontal sub-line 81-8 is configured to be connected to the subsequently formed data signal line.

[0249] In an exemplary embodiment, at least one circuit unit may further include a data transfer bar 83 and a first data connection block 84. The data transfer bar 83 may be in a bar shape extending along the second direction Y, and the first data connection block 84 may be in a block shape (such as a rectangle). The data transfer bar 83 and the first data connection block 84 may be arranged on a side of the horizontal sub-line close to the second electrode plate 32. The first end of the data transfer bar 83 is connected to a side of the horizontal sub-line close to the second electrode plate 32, and the second end of the data transfer bar 83 is connected to the horizontal sub-line after extending in the direction of the second electrode plate 32, and the first data connection block 84 is configured to be connected to a vertical sub-line formed subsequently.

[0250] In an exemplary embodiment, the data transfer bar 83 and the first data connection block 84 may be arranged between circuit units adjacent to each other in a portion of the first direction X. For example, in the Mth unit row, the data transfer bar 83 and the first data connection block 84 may be arranged between the Nth unit column and the N+1th unit column, and the first data connection block 84 is connected to the second horizontal sub-line 81-2 through the data transfer bar 83. For another example, in the M+1th unit row, the data transfer bar 83 and the first data connection block 84 may be arranged between the N+2th unit column and the N+3th unit column, and the first data connection block 84 is connected to the fourth horizontal sub-line 81-4 through the data transfer bar 83. For another example, in the M+2th unit row, the data transfer bar 83 and the first data connection block 84 may be arranged between the N+4th unit column and the N+5th unit column, and the first data connection block 84 is connected to the sixth horizontal sub-line 81-6 through the data transfer bar 83. For another example, in the M+3th unit row, the data transfer bar 83 and the first data connection block 84 can be arranged between the N+4th unit column and the N+5th unit column, and the first data connection block 84 is connected to the seventh horizontal sub-line 81-7 through the data transfer bar 83. Also, the data transfer bar 83 and the first data connection block 84 can be arranged between the N+6th unit column and the N+7th unit column, and the first data connection block 84 is connected to the fifth horizontal sub-line 81-5 through the data transfer bar 83. For another example, in the M+4th unit row, the data transfer bar 83 and the first data connection block 84 can be arranged between the N+2th unit column and the N+3th unit column, and the first data connection block 84 is connected to the eighth horizontal sub-line 81-8 through the data transfer bar 83. Also, the data transfer bar 83 and the first data connection block 84 can be arranged between the N+8th unit column and the N+9th unit column, and the first data connection block 84 is connected to the third horizontal sub-line 81-3 through the data transfer bar 83. For another example, in the M+5th unit row, the data transfer bar 83 and the first data connection block 84 can be arranged between the N+10th unit column and the N+11th unit column, and the first data connection block 84 is connected to the first horizontal sub-line 81 - 1 through the data transfer bar 83 .

[0251] In an exemplary embodiment, in at least one circuit unit, the horizontal sub-line, the data transfer bar 83 and the first data connection block 84 may be an integrated structure connected to each other.

[0252] In an exemplary embodiment, at least one circuit unit may further include a second data connection block 85. The second data connection block 85 may be block-shaped (eg, rectangular) and connected to the horizontal sub-line, and the second data connection block 85 is configured to be connected to a subsequently formed vertical sub-line.

[0253] In an exemplary embodiment, the second data connection block 85 may be disposed between circuit units adjacent to some of the first direction X. For example, the second data connection block 85 is not disposed in the Mth unit row to the M+2th unit row. For another example, in the M+3th unit row, the second data connection block 85 may be disposed between the N+4th unit column and the N+5th unit column, and connected to the fifth horizontal sub-line 81-5. For another example, in the M+4th unit row, the second data connection block 85 may be disposed between the N+2th unit column and the N+3th unit column, and connected to the third horizontal sub-line 81-3. For another example, in the M+5th unit row, the second data connection block 85 may be disposed between the Nth unit column and the N+1th unit column, and connected to the first horizontal sub-line 81-1.

[0254] In an exemplary embodiment, in at least one circuit unit, the transverse sub-line and the second data connection block 85 may be an integral structure connected to each other.

[0255] In an exemplary embodiment, at least one unit row may be provided with only the first data connection block 84. For example, one horizontal sub-line (the second horizontal sub-line 81-2, the fourth horizontal sub-line 81-4, or the sixth horizontal sub-line 81-6) may be provided in the Mth unit row to the M+2th unit row, and one end of the horizontal sub-line is connected to the first data connection block 84.

[0256] In an exemplary embodiment, at least one unit row may be provided with a first data connection block 84 and a second data connection block 85 at the same time, and the first data connection block 84 and the second data connection block 85 are respectively provided at both ends of the horizontal sub-line in the first direction X. For example, two horizontal sub-lines (the fifth horizontal sub-line 81-5 and the seventh horizontal sub-line 81-7) are provided in the M+3 unit row, and two horizontal sub-lines (the third horizontal sub-line 81-3 and the eighth horizontal sub-line 81-8) are provided in the M+4 unit row. In each unit row, one end of one horizontal sub-line is connected to the first data connection block 84, and the two ends of the other horizontal sub-line are respectively connected to the first data connection block 84 and the second data connection block 85.

[0257] In an exemplary embodiment, with respect to one transverse sub-line, the first data connection block 84 and the second data connection block 85 may be located at both sides of the transverse sub-line in the second direction Y, respectively.

[0258] In an exemplary embodiment, the positive projection of at least one horizontal sub-line on the substrate at least partially overlaps with the positive projection of the second initial signal line 42 on the substrate, so that the second initial signal line 42 with a constant potential can effectively shield the influence of voltage jumps in the horizontal sub-line on the pixel driving circuit.

[0259] In an exemplary embodiment, in at least one cell row, the first traces may include only the first power trace 91 .

[0260] In an exemplary embodiment, at least one circuit unit may further include a first dummy electrode 86, which may be block-shaped (e.g., rectangular) and configured to be connected to a subsequently formed vertical sub-line. In the first direction X, the first dummy electrode 86 may be disposed between circuit units adjacent to each other in part of the first direction X. In the second direction Y, the first dummy electrode 86 may be disposed on one side of the lateral sub-line close to the second electrode plate 32.

[0261] In an exemplary embodiment, the position and connection structure of the first dummy electrode 86 in one circuit unit can be substantially the same as the position and connection structure of the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated and is neither connected to the horizontal sub-line nor to other electrodes. In an exemplary embodiment, the morphology and connection structure presented by the first dummy electrode 86 are substantially the same as those of the first data connection block 84. The present disclosure not only improves the uniformity of the subsequent etching process through the same design of the transfer area, but also enables different positions to achieve the same display effect under transmitted and reflected light, realizes shadow elimination, effectively avoids the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), and improves the display quality.

[0262] In an exemplary embodiment, at least one circuit unit may further include a second dummy electrode 87, which may be block-shaped (e.g., rectangular) and configured to be connected to a subsequently formed vertical sub-line. In the first direction X, the second dummy electrode 87 may be disposed between some of the circuit units adjacent in the first direction X. In the second direction Y, the second dummy electrode 87 may be disposed on a side of the lateral sub-line away from the second electrode plate 32.

[0263] In an exemplary embodiment, the position and connection structure of the second dummy electrode 87 in one circuit unit can be substantially the same as the position and connection structure of the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated and is neither connected to the horizontal sub-line nor to other electrodes. In an exemplary embodiment, the morphology and connection structure presented by the second dummy electrode 87 are substantially the same as those of the second data connection block 85. The present disclosure not only improves the uniformity of the subsequent etching process through the same design of the transfer area, but also enables different positions to achieve the same display effect under transmitted and reflected light, realizes shadow elimination, effectively avoids the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), and improves the display quality and display quality.

[0264] In an exemplary embodiment, with respect to one transverse sub-line, the first dummy electrode 86 and the second dummy electrode 87 may be respectively located at both sides of the transverse sub-line in the second direction Y.

[0265] (8) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of via holes are disposed on the first planar layer, such as Fig.16 shown.

[0266] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0267] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connecting electrode 53, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0268] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the power connection block 54-1, and the twenty-second via hole V22 is configured to connect a subsequently formed first power line to the power connection block 54-1 through the via hole.

[0269] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.

[0270] In an exemplary embodiment, at least one circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the seventh connection block 57-1 on the substrate, the first flat layer in the twenty-fourth via hole V24 is etched away, exposing the surface of the seventh connection block 57-1, and the twenty-fourth via hole V24 is configured to connect the first initial connection line formed subsequently to the seventh connection block 57-1 through the via hole.

[0271] In an exemplary embodiment, the twenty-fourth via hole V24 may be disposed between some adjacent circuit units. For example, the twenty-fourth via hole V24 may be disposed between the N+3th unit column and the N+4th unit column. For another example, the twenty-fourth via hole V24 may be disposed between the N+7th unit column and the N+8th unit column.

[0272] In an exemplary embodiment, at least one circuit unit may further include a twenty-fifth via hole V25. The orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the eighth connection block 58-1 on the substrate, the first flat layer in the twenty-fifth via hole V25 is etched away, exposing the surface of the eighth connection block 58-1, and the twenty-fifth via hole V25 is configured to connect the second initial connection line formed subsequently to the eighth connection block 58-1 through the via hole.

[0273] In an exemplary embodiment, the twenty-fifth via hole V25 may be disposed between some adjacent circuit units. For example, the twenty-fifth via hole V25 may be disposed between the N+1th unit column and the N+2th unit column. For another example, the twenty-fifth via hole V25 may be disposed between the N+5th unit column and the N+6th unit column. For another example, the twenty-fifth via hole V25 may be disposed between the N+9th unit column and the N+10th unit column.

[0274] In an exemplary embodiment, at least one circuit unit may further include a twenty-sixth via hole V26. The orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the first data connection block 84 on the substrate, the first flat layer in the twenty-sixth via hole V26 is etched away, exposing the surface of the first data connection block 84, and the twenty-sixth via hole V26 is configured to connect a subsequently formed vertical sub-line to the first data connection block 84 through the via hole.

[0275] In an exemplary embodiment, at least one circuit unit may further include a twenty-seventh via hole V27. The orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the second data connection block 85 on the substrate, the first flat layer in the twenty-seventh via hole V27 is etched away, exposing the surface of the second data connection block 85, and the twenty-seventh via hole V27 is configured to connect a subsequently formed vertical sub-line to the second data connection block 85 through the via hole.

[0276] In an exemplary embodiment, at least one circuit unit may further include a twenty-eighth via hole V28. The orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the first dummy electrode 86 on the substrate, the first flat layer in the twenty-eighth via hole V28 is etched away, exposing the surface of the first dummy electrode 86, and the twenty-eighth via hole V28 is configured to connect a subsequently formed vertical sub-line to the first dummy electrode 86 through the via hole.

[0277] In an exemplary embodiment, at least one circuit unit may further include a twenty-ninth via hole V29. The orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the second dummy electrode 87 on the substrate, the first flat layer in the twenty-ninth via hole V29 is etched away, exposing the surface of the second dummy electrode 87, and the twenty-ninth via hole V29 is configured to connect a subsequently formed vertical sub-line to the second dummy electrode 87 through the via hole.

[0278] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Fig.17A and Fig. 17B As shown, Fig. 17B for Fig.17A In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0279] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .

[0280] In an exemplary embodiment, the shape of the first power line 71 can be a straight line or a folded line with the main part extending along the second direction Y, and the first power line 71 is connected to the power connection block 54-1 through the 22nd via hole V32. Since the power connection block 54-1 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first area of ​​the fifth active layer and the second electrode plate 32 of the storage capacitor, the first power line 71 writes the first power signal to the fifth transistor T5 and the second electrode plate 32 of the storage capacitor.

[0281] In an exemplary embodiment, the first power line 71 may be a zigzag line of unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0282] In an exemplary embodiment, a power shielding block 74 may be provided on the first power line 71. The power shielding block 74 may be in a block shape (e.g., rectangular) and may be provided on a side of the first power line 71 close to the second transistor T2 and connected to the first power line 71. The orthographic projection of the power shielding block 74 on the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate. In an exemplary embodiment, the power shielding block 74 may shield the second active layer, block the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the second transistor T2 of the oxide, prevent the oxide transistor from drifting in characteristics due to light, and improve the electrical characteristics of the oxide transistor.

[0283] In an exemplary embodiment, the positive projections of the first power line 71 and the power shielding block 74 on the substrate at least partially overlap with the positive projection of the first connecting electrode 51 on the substrate, so that the first power line 71 and the power shielding block 74 with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node N1, and improve the driving performance of the pixel driving circuit.

[0284] In an exemplary embodiment, in at least one circuit unit, the first power line 71 and the power shielding block 74 may be an integral structure connected to each other.

[0285] In an exemplary embodiment, the shape of the data signal line 72 may be a straight line or a folded line with a main portion extending along the second direction Y, and the data signal line 72 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 is connected to the first electrode of the fourth transistor T4, and the data signal line 72 can write the data signal to the first electrode of the fourth transistor T4.

[0286] In an exemplary embodiment, the anode connection electrode 73 may be in the shape of a strip extending along the second direction Y, and the anode connection electrode 73 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the anode connection electrode 73 is configured to be connected to the subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0287] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a first initial connection line 61. The shape of the first initial connection line 61 may be a straight line or a folded line with the main part extending along the second direction Y, and the first initial connection line 61 is connected to the seventh connection block 57-1 through the twenty-fourth via hole V24. Since the seventh connection block 57-1 is connected to the seventh connection electrode 57, and the seventh connection electrode 57 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first initial connection line 61 extending along the second direction Y are connected to each other, and the first initial signal line 41 and the first initial connection line 61 form a meshed meshed connection structure for transmitting the first initial signal, which can not only effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0288] In an exemplary embodiment, the first initial connection line 61 may be disposed between two first power lines 71 of some adjacent unit columns, and four first power lines 71 may be disposed between two first initial connection lines 61 adjacent in the first direction X. For example, the first initial connection line 61 may be disposed between the first power line 71 of the N+3th unit column and the first power line 71 of the N+4th unit column. For another example, the first initial connection line 61 may be disposed between the first power line 71 of the N+7th unit column and the first power line 71 of the N+8th unit column.

[0289] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second initial connection line 62. The shape of the second initial connection line 62 may be a straight line or a folded line with the main part extending along the second direction Y, and the second initial connection line 62 is connected to the eighth connection block 58-1 through the twenty-fifth via hole V25. Since the eighth connection block 58-1 is connected to the eighth connection electrode 58, and the eighth connection electrode 58 is connected to the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second initial connection line 62 extending along the second direction Y are connected to each other, and the second initial signal line 42 and the second initial connection line 62 form a meshed meshed connection structure for transmitting the second initial signal, which can not only effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0290] In an exemplary embodiment, the second initial connection line 62 may be disposed between two first power lines 71 of some adjacent unit columns, and four first power lines 71 may be disposed between two second initial connection lines 62 adjacent in the first direction X. For example, the second initial connection line 62 may be disposed between the first power line 71 of the N+1th unit column and the first power line 71 of the N+2th unit column. For another example, the second initial connection line 62 may be disposed between the first power line 71 of the N+5th unit column and the first power line 71 of the N+6th unit column. For another example, the second initial connection line 62 may be disposed between the first power line 71 of the N+9th unit column and the first power line 71 of the N+10th unit column.

[0291] In an exemplary embodiment, in the first direction X, the first initial connection lines 61 and the second initial connection lines 62 may be alternately arranged, one second initial connection line 62 may be arranged between adjacent first initial connection lines 61 in the first direction X, and one first initial connection line 61 may be arranged between adjacent second initial connection lines 62 in the first direction X.

[0292] In some possible embodiments, the fifth conductive layer of at least one circuit unit may also include a third initial connection line whose main body extends along the second direction Y. The third initial connection line may be connected to the third initial signal line through a via to form a mesh-like interconnected structure for transmitting the third initial signal. The present disclosure is not limited here.

[0293] In an exemplary embodiment, the fifth conductive layer may further include a plurality of second routing lines, the second routing lines may be in the shape of a straight line or a zigzag line with a main portion extending along the second direction Y, and may be located between two data signal lines 72 of some adjacent unit columns, and two first power lines 71 and two data signal lines 72 may be provided between two second routing lines adjacent in the first direction X. For example, the second routing line may be located between the data signal line 72 of the Nth unit column and the data signal line 72 of the N+1th unit column. For another example, the second routing line may be located between the data signal line 72 of the N+2th unit column and the data signal line 72 of the N+3th unit column. For another example, the second routing line may be located between the data signal line 72 of the N+4th unit column and the data signal line 72 of the N+5th unit column.

[0294] In an exemplary embodiment, at least one second routing line may include a vertical sub-line and a second power routing line 92, and a second break K2 may be provided between the vertical sub-line and the second power routing line 92, and the second break K2 may cut off the vertical sub-line from the second power routing line 92, so that the vertical sub-line and the second power routing line 92 on both sides of the second break K2 are insulated from each other. For example, the second routing line located between the N+6th unit column and the N+7th unit column may include the second power routing line 92 and the fifth vertical sub-line 82-5 sequentially arranged along the second direction Y. For another example, the second routing line located between the N+8th unit column and the N+9th unit column may include the second power routing line 92 and the third vertical sub-line 82-3 sequentially arranged along the second direction Y. For another example, the second routing line located between the N+10th unit column and the N+11th unit column may include the second power routing line 92 and the first vertical sub-line 82-1 sequentially arranged along the second direction Y.

[0295] In an exemplary embodiment, at least one second trace may include a vertical sub-line and two second power traces 92, and a second break K2 is provided between the two second power traces 92 and the vertical sub-line, and the second break K2 may cut off the vertical sub-line from the second power trace 92. For example, the second trace located between the Nth unit column and the N+1th unit column may include the second power trace 92, the second vertical sub-line 82-2, and the second power trace 92 sequentially arranged along the second direction Y.

[0296] In an exemplary embodiment, at least one second routing line may include two vertical sub-lines and a second power routing line 92, and a second break K2 may be provided between the two vertical sub-lines, and the second break K2 may cut off the two vertical sub-lines, so that the two vertical sub-lines on both sides of the second break K2 are insulated from each other. A second break K2 is provided between the vertical sub-line and the second power routing line 92, and the second break K2 may cut off the vertical sub-line from the second power routing line 92. For example, the second routing line located between the N+2 unit column and the N+3 unit column may include the second power routing line 92, the fourth vertical sub-line 82-4, and the eighth vertical sub-line 82-8 sequentially arranged along the second direction Y. For another example, the second routing line located between the N+4 unit column and the N+5 unit column may include the second power routing line 92, the sixth vertical sub-line 82-6, and the seventh vertical sub-line 82-7 sequentially arranged along the second direction Y.

[0297] In an exemplary embodiment, at least one vertical sub-line is configured to extend to the binding area at one end and connect to the data lead-out line, and the other end is connected to the first data connection block 84 through the twenty-sixth via V26, thereby realizing the interconnection between a vertical sub-line and a horizontal sub-line.

[0298] In an exemplary embodiment, at least one vertical sub-line is connected to the second data connection block 85 through the twenty-seventh via V27 at one end and to the first data connection block 84 through the twenty-sixth via V26 at the other end, thereby realizing the interconnection between one vertical sub-line and two horizontal sub-lines.

[0299] In an exemplary embodiment, at least one vertical sub-line is further connected to the first dummy electrode 86 through the twenty-eighth via hole V28 , so that each position of the display substrate presents the same morphology and connection structure.

[0300] In an exemplary embodiment, at least one vertical sub-line is further connected to the second dummy electrode 87 through a twenty-ninth via hole V29 , so that each position of the display substrate presents the same morphology and connection structure.

[0301] In an exemplary embodiment, the first vertical sub-line 82-1 between the N+10th unit column and the N+11th unit column and the second vertical sub-line 82-2 between the Nth unit column and the N+1th unit column can be referred to as the first second data connection line 82, the first vertical sub-line 82-1 is connected to the first horizontal sub-line 81-1, and the second vertical sub-line 82-2 is connected to the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, respectively.

[0302] In an exemplary embodiment, the third vertical sub-line 82-3 between the N+8th unit column and the N+9th unit column and the fourth vertical sub-line 82-4 between the N+2th unit column and the N+3th unit column can be referred to as the second second data connection line 82, the third vertical sub-line 82-3 is connected to the third horizontal sub-line 81-3, and the fourth vertical sub-line 82-4 is connected to the third horizontal sub-line 81-3 and the fourth horizontal sub-line 81-4, respectively.

[0303] In an exemplary embodiment, the fifth vertical sub-line 82-5 between the N+6th unit column and the N+7th unit column and the sixth vertical sub-line 82-6 between the N+4th unit column and the N+5th unit column can be referred to as the third second data connection line 82, the fifth vertical sub-line 82-5 is connected to the fifth horizontal sub-line 81-5, and the sixth vertical sub-line 82-6 is connected to the fifth horizontal sub-line 81-5 and the sixth horizontal sub-line 81-6, respectively.

[0304] In an exemplary embodiment, the seventh vertical sub-line 82 - 7 between the N+4th unit column and the N+5th unit column may be referred to as a fourth second data connection line 82 , and the seventh vertical sub-line 82 - 7 is connected to the seventh horizontal sub-line 81 - 7 .

[0305] In an exemplary embodiment, the eighth vertical sub-line 82 - 8 between the N+2 th unit column and the N+3 th unit column may be referred to as a fifth second data connection line 82 , and the eighth vertical sub-line 82 - 8 is connected to the eighth horizontal sub-line 81 - 8 .

[0306] Fig. 17C FIG. 1 is a schematic diagram of connecting the horizontal sub-lines and the vertical sub-lines of an exemplary embodiment of the present disclosure. Fig.17A , Fig. 17B and Fig. 17C As shown, the plurality of data link lines may include at least a first data link line 80A, a second data link line 80B, a third data link line 80C, a fourth data link line 80D, and a fifth data link line 80E.

[0307] In an exemplary embodiment, the first data connection line 80A may include at least a first first data connection line and a first second data connection line, the first first data connection line may include at least a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2, and the first second data connection line may include at least a first vertical sub-line 82-1 and a second vertical sub-line 82-2. The first horizontal sub-line 81-1 may be disposed in the M+5th unit row, the second horizontal sub-line 81-2 may be disposed in the Mth unit row, the first vertical sub-line 82-1 may be disposed between the N+10th unit column and the N+11th unit column, and the second vertical sub-line 82-2 may be disposed between the Nth unit column and the N+1th unit column.

[0308] In an exemplary embodiment, a first end of the first vertical sub-line 82-1 is connected to a data lead-out line in the binding area, and a second end of the first vertical sub-line 82-1 is connected to a first end of the first horizontal sub-line 81-1 through a first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the first horizontal sub-line 81-1 is connected to a first end of the second vertical sub-line 82-2 through a second data connection block 85 after extending in the first direction X or in the opposite direction of the first direction X. A second end of the second vertical sub-line 82-2 is connected to a first end of the second horizontal sub-line 81-2 through a first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the second horizontal sub-line 81-2 is connected to a data signal line after extending in the first direction X or in the opposite direction of the first direction X.

[0309] In an exemplary embodiment, the second data connection line 80B may include at least a second first data connection line and a second second data connection line, the second first data connection line may include at least a third horizontal sub-line 81-3 and a fourth horizontal sub-line 81-4, and the second second data connection line may include at least a third vertical sub-line 82-3 and a fourth vertical sub-line 82-4. The first horizontal sub-line 81-1 may be disposed in the M+4th unit row, the fourth horizontal sub-line 81-4 may be disposed in the M+1th unit row, the third vertical sub-line 82-3 may be disposed between the N+8th unit column and the N+9th unit column, and the fourth vertical sub-line 82-4 may be disposed between the N+2th unit column and the N+3th unit column.

[0310] In an exemplary embodiment, a first end of the third vertical sub-line 82-3 is connected to another data lead-out line in the binding area, and a second end of the third vertical sub-line 82-3 is connected to a first end of the third horizontal sub-line 81-3 through a first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the third horizontal sub-line 81-3 is connected to a first end of a fourth vertical sub-line 82-4 through a second data connection block 85 after extending in the first direction X or in the opposite direction of the first direction X. A second end of the fourth vertical sub-line 82-4 is connected to a first end of a fourth horizontal sub-line 81-4 through a first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the fourth horizontal sub-line 81-4 is connected to another data signal line after extending in the first direction X or in the opposite direction of the first direction X.

[0311] In an exemplary embodiment, the third data connection line 80C may include at least a third first data connection line and a third second data connection line, the third first data connection line may include at least a fifth horizontal sub-line 81-5 and a sixth horizontal sub-line 81-6, and the third second data connection line may include at least a fifth vertical sub-line 82-5 and a sixth vertical sub-line 82-6. The fifth horizontal sub-line 81-5 may be disposed in the M+3th unit row, the sixth horizontal sub-line 81-6 may be disposed in the M+2th unit row, the fifth vertical sub-line 82-5 may be disposed between the N+6th unit column and the N+7th unit column, and the sixth vertical sub-line 82-6 may be disposed between the N+4th unit column and the N+5th unit column.

[0312] In an exemplary embodiment, a first end of the fifth vertical sub-line 82-5 is connected to another data lead-out line in the binding area, and a second end of the fifth vertical sub-line 82-5 is connected to a first end of a fifth horizontal sub-line 81-5 through a first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the fifth horizontal sub-line 81-5 is connected to a first end of a sixth vertical sub-line 82-6 through a second data connection block 85 after extending in the first direction X or in the opposite direction of the first direction X. A second end of the sixth vertical sub-line 82-6 is connected to a first end of a sixth horizontal sub-line 81-6 through a first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the sixth horizontal sub-line 81-6 is connected to another data signal line after extending in the first direction X or in the opposite direction of the first direction X.

[0313] In an exemplary embodiment, the fourth data connection line 80D may include at least a fourth first data connection line and a fourth second data connection line, the fourth first data connection line may include at least a seventh horizontal sub-line 81-7, and the fourth second data connection line may include at least a seventh vertical sub-line 82-7. The seventh horizontal sub-line 81-7 may be disposed in the M+3th unit row, and the seventh vertical sub-line 82-7 may be disposed between the N+4th unit column and the N+5th unit column.

[0314] In an exemplary embodiment, a first end of the seventh vertical sub-line 82-7 is connected to another data lead-out line in the binding area, and a second end of the seventh vertical sub-line 82-7 is connected to the seventh horizontal sub-line 81-7 through the first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the seventh horizontal sub-line 81-7 is connected to another data signal line after extending in the first direction X or in the opposite direction of the first direction X.

[0315] In an exemplary embodiment, the fifth data connection line 80E may include at least a fifth first data connection line and a fifth second data connection line, the fifth first data connection line may include at least an eighth horizontal sub-line 81-8, and the fifth second data connection line may include at least an eighth vertical sub-line 82-8. The eighth horizontal sub-line 81-8 may be disposed in the M+4th unit row, and the eighth vertical sub-line 82-8 may be disposed between the N+2th unit column and the N+3th unit column.

[0316] In an exemplary embodiment, a first end of the eighth vertical sub-line 82-8 is connected to another data lead-out line in the binding area, and a second end of the eighth vertical sub-line 82-8 is connected to the eighth horizontal sub-line 81-8 through the first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the eighth horizontal sub-line 81-8 is connected to another data signal line after extending in the first direction X or in the opposite direction of the first direction X.

[0317] In an exemplary embodiment, the first power supply line 91 and the second power supply line 92 may be interconnected to form a mesh connection structure, which is not limited in the present disclosure.

[0318] In an exemplary embodiment, the first power line 91 and the second power line 92 can be connected to the power lead transmitting the second power signal through the border area or the binding area, so that the second power line is located in the panel (VSS in Panel, referred to as SIP) structure, which can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, achieve low power consumption, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the border power lead, greatly reduce the border width, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0319] In an exemplary embodiment, the first power lines 71 of adjacent cell columns may be mirror-symmetrical with respect to the column boundary, and the data signal lines 72 of adjacent cell columns may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the first power lines 71 and the data signal lines 72 in multiple cell rows may be substantially the same.

[0320] In an exemplary embodiment, an orthographic projection of the at least one second trace on the substrate at least partially overlaps an orthographic projection of the column dividing line on the substrate.

[0321] In an exemplary embodiment, in the first direction X, one second routing line and two data signal lines 72 may be disposed between two first power lines 71 of adjacent cell columns, the two first power lines 71 may be mirror-symmetrical with respect to the second routing line, and the two data signal lines 72 may be mirror-symmetrical with respect to the second routing line.

[0322] In an exemplary embodiment, in the first direction X, two first power lines 71 and two data signal lines 72 may be disposed between adjacent second routing lines, and the two second routing lines may be mirror-symmetric with respect to a column boundary line.

[0323] (10) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, and providing a plurality of anode vias V30 on the second planar layer, such as Fig.18 shown.

[0324] In an exemplary embodiment, the orthographic projection of the anode via V30 of each circuit unit on the substrate is located within the range of the orthographic projection of the anode connecting electrode 73 on the substrate, the second flat layer in the anode via V30 is removed to expose the surface of the anode connecting electrode 73, and the anode via V30 is configured to connect a subsequently formed anode to the anode connecting electrode 73 through the via.

[0325] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power line, and a data signal line connected to the pixel driving circuit.

[0326] In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, and a second flat layer sequentially arranged on the substrate. The first semiconductor layer may include at least the active layers of the first transistor, the third transistor to the eighth transistor, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the third scanning signal line, the light emitting signal line, and the first plate of the storage capacitor, the second conductive layer may include at least the first initial signal line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the second transistor, the third conductive layer may include at least the second initial signal line, the third initial signal line, and the fourth scanning signal line, the fourth conductive layer may include at least the first data connection line and a plurality of connection electrodes, and the fifth conductive layer may include at least the first power line, the data signal line, the first initial signal line, the second initial signal line, and the second data connection line.

[0327] In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0328] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first planar layer and the second planar layer may be made of organic materials, such as resin, etc.

[0329] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to a column boundary, where the column boundary is a straight line located between two adjacent circuit units and extending along the second direction Y. For example, the pixel driving circuit of the Nth unit column and the pixel driving circuit of the N+1th unit column may be mirror-symmetrical with respect to the column boundary. For another example, the pixel driving circuit of the N+1th unit column and the pixel driving circuit of the N+2th unit column may be mirror-symmetrical with respect to the column boundary.

[0330] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units may be substantially mirror-symmetrical with respect to a column boundary line and may include any one or more of the following: the first semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to a column boundary line, the first conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to a column boundary line, the second conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to a column boundary line, the second semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to a column boundary line, the third conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to a column boundary line, the fourth conductive layer in two adjacent circuit units in a unit row (except the first routing line and the data transfer bar) may be mirror-symmetrical with respect to a column boundary line, and the fifth conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to a column boundary line (except the second routing line and the anode connecting electrode).

[0331] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer, and the preparation process of the light emitting structure layer may include the following operations.

[0332] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, such as Fig.19A and Fig.19B As shown, Fig.19B for Fig.19A Schematic diagram of the plan view of the anode conductive layer.

[0333] In an exemplary embodiment, the plurality of anode patterns may include a first anode 90A located at a red light emitting unit emitting red light, a second anode 90B located at a blue light emitting unit emitting blue light, a third anode 90C located at a first green light emitting unit emitting green light, and a fourth anode 90D located at a second green light emitting unit emitting green light. The first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be respectively connected to the anode connecting electrode 73 of the circuit unit through the anode via V30.

[0334] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting part that are connected to each other. The shape of the anode main body may be a rhombus shape, and the corners of the rectangular shape may be provided with arc-shaped chamfers. The shape of the anode connecting part may be a strip shape. The first end of the anode connecting part is connected to the anode main body, and the second end of the anode connecting part extends in a direction away from the anode main body and is connected to the anode connecting electrode 73 through the anode via V30.

[0335] In an exemplary embodiment, the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D on the substrate do not overlap with the orthographic projection of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) on the substrate.

[0336] In an exemplary embodiment, the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D on the substrate do not overlap with the orthographic projection of the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) on the substrate.

[0337] In an exemplary embodiment, the orthographic projections of the first anode 90A, the third anode 90C and the fourth anode 90D on the substrate do not overlap with the orthographic projections of the first data connection block 84 (or the first dummy electrode 86 ) and the second data connection block 85 (or the second dummy electrode 87 ) on the substrate.

[0338] In an exemplary embodiment, an orthographic projection of the second anode 90B on the substrate at least partially overlaps with an orthographic projection of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) on the substrate.

[0339] In an exemplary embodiment, an orthographic projection of the second anode 90B on the substrate at least partially overlaps with an orthographic projection of the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) on the substrate.

[0340] In an exemplary embodiment, the orthographic projection of the second anode 90B on the substrate at least partially overlaps with the orthographic projections of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) on the substrate.

[0341] In an exemplary embodiment, the second anode 90B may have an anode center line, and the anode center line may be a zigzag shape passing through the geometric center of the anode body of the second anode and extending along the first direction X. The twenty-sixth via hole V26 (or the twenty-eighth via hole V28) may be located on one side of the anode center line in the second direction Y, and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) may be located on one side in the opposite direction of the anode center line in the second direction Y, that is, the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) may be arranged up and down relative to the anode center line.

[0342] In an exemplary embodiment, in the second direction Y, there is a first distance between the geometric center of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the anode center line, and there is a second distance between the geometric center of the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) and the anode center line. The anode center line may be a zigzag line passing through the geometric center of the anode body of the second anode and extending along the first direction X.

[0343] In an exemplary embodiment, a ratio of the first distance to the second distance may be approximately 0.9 to 1.1, ie, the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) may correspond to upper and lower positions relative to the anode centerline.

[0344] In an exemplary embodiment, the ratio of the first distance to the second distance may be approximately 1.0.

[0345] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0346] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer, the pixel definition layer is provided with a plurality of pixel openings, the plurality of pixel openings respectively exposing a first anode, a second anode, a third anode and a fourth anode. Then, an organic light-emitting layer is formed by evaporation or inkjet printing, and then a cathode is formed on the organic light-emitting layer, and then an encapsulation structure layer is formed, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer.

[0347] An exemplary embodiment of the present disclosure provides a display substrate, which effectively reduces the difference in the number of data connection line coupling unit columns in different unit rows by splitting a first data connection line with a longer extension length into two horizontal sub-lines, and the two horizontal sub-lines are arranged in different unit rows, so as to effectively reduce or even eliminate the appearance of diagonal watermarks at the two corners of the display area close to the binding area.

[0348] In an exemplary embodiment, Figure 6 Taking a first data connection line 81 which is far from the binding area as an example, the present disclosure splits the first data connection line into a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2. Figure 6 The number of cell columns coupled to the first data connection line 81 is substantially the same as the sum of the number of cell columns coupled to the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 of the present disclosure, but since the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 of the present disclosure are arranged in different cell rows, the number of cell columns coupled in the cell row where the first horizontal sub-line 81-1 is located is relatively small, the number of cell columns coupled in the cell row where the second horizontal sub-line 81-2 is located is relatively small, and the number of cell columns coupled to the first horizontal sub-line 81-1 and the number of cell columns coupled to the second horizontal sub-line 81-2 are similar, thereby effectively reducing the difference in the number of cell columns coupled to the data connection lines in different cell rows.

[0349] In an exemplary embodiment, Figure 6 For example, a first data connection line 81 which is closer to the binding area Figure 6 The extension length of the first data connection line is shorter, and it is coupled with fewer unit columns. However, since the present disclosure splits other first data connection lines into two horizontal sub-lines, horizontal sub-lines of other data connection lines are arranged in the unit row where the first data connection line is located, the number of unit columns coupled with the data connection lines in the unit row is increased and is close to the number of unit columns coupled with the data connection lines in other unit rows, thereby effectively reducing the difference in the number of unit columns coupled with the data connection lines in different unit rows.

[0350] Compare Figure 6 It can be seen from the first area 110 of the present invention that the present invention effectively reduces the area of ​​the first area (FIP area) by splitting the first data connection line with a longer extension length into two horizontal sub-lines and splitting the second data connection line with a longer extension length into two vertical sub-lines, which is beneficial to increasing the number of power lines and reducing the power signal voltage drop, and can effectively improve display uniformity, display quality and display quality.

[0351] The disclosed embodiment realizes a FIP structure by setting data connection lines in the display area, and connecting the data lead lines in the binding area to the data signal lines through the data connection lines. This makes it unnecessary to set fan-shaped oblique lines in the lead line area, effectively reduces the length of the lead line area, greatly reduces the width of the lower frame, and improves the screen-to-body ratio, which is conducive to achieving full-screen display.

[0352] The disclosed embodiment realizes a SIP structure by arranging a first power line and a second power line in the display area, which can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, achieve low power consumption, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can greatly reduce the width of the frame power lead, greatly reduce the frame width, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0353] The embodiment of the present disclosure sets a first initial connection line and a second initial connection line in the display area. The first initial connection line and the first initial signal line form a mesh connection structure, and the second initial connection line and the second initial signal line form a mesh connection structure. This can not only effectively reduce the resistance of the initial signal line, reduce the voltage drop of the initial signal, and effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0354] In the disclosed embodiment, a first dummy electrode and a second dummy electrode are provided, and the morphology and connection structure presented by the first dummy electrode are substantially the same as those of the first data connection block, and the morphology and connection structure presented by the second dummy electrode are substantially the same as those of the second data connection block, so that the display area has substantially the same transfer area structure, the uniformity of the etching process is improved, different areas can achieve the same display effect under transmitted and reflected light, and shadow elimination is realized, which effectively avoids the poor appearance of the display substrate and the occurrence of off-screen watermarks, and improves the display quality.

[0355] In the disclosed embodiment, the second anode is arranged to cover the transfer via hole on the first flat layer, and the two transfer via holes are arranged correspondingly at upper and lower positions relative to the center line of the anode, so that the anode has good flatness and can effectively improve color deviation.

[0356] The preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0357] The structure and preparation process shown above in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0358] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0359] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a display area and a binding area arranged on one side of the display area, the display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit includes a pixel driving circuit; the preparation method may include:

[0360] A plurality of data signal lines and a plurality of data connection lines are formed in the display area, and a plurality of data lead-out lines are formed in the binding area, wherein the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, wherein the two horizontal sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns, and the first direction intersects with the second direction.

[0361] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The invention comprises a display area and a binding area arranged on one side of the display area, wherein the display area comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprises a pixel driving circuit, and the binding area comprises at least a plurality of data lead-out lines; the display area further comprises a plurality of data signal lines and a plurality of data connection lines, wherein the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines; at least one data connection line comprises at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, wherein the at least two horizontal sub-lines are arranged in different unit rows, and the at least two vertical sub-lines are arranged in different unit columns, and the first direction intersects with the second direction.

2. The display substrate according to claim 1, characterized in that: At least two transverse sub-lines are arranged in at least one unit row, and the at least two transverse sub-lines are connected to different vertical sub-lines.

3. The display substrate according to claim 1, characterized in that: At least two vertical sub-lines are arranged in at least one unit column, and the at least two vertical sub-lines are connected to different horizontal sub-lines.

4. The display substrate according to claim 1, characterized in that: An orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps with an orthographic projection of at least one vertical sub-line on the display substrate.

5. The display substrate according to claim 1, characterized in that: In a direction perpendicular to the display substrate, the display area includes multiple conductive layers, the at least two horizontal sub-lines are arranged in the same conductive layer, the at least two vertical sub-lines are arranged in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines are arranged in different conductive layers.

6. The display substrate according to claim 5, characterized in that: The multiple conductive layers include at least a first source-drain metal layer arranged on a substrate and a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line is arranged in the first source-drain metal layer, and the vertical sub-line is arranged in the second source-drain metal layer.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The at least two horizontal sub-lines include at least a first horizontal sub-line and a second horizontal sub-line, and the at least two vertical sub-lines include at least a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: the first end of the first vertical sub-line is connected to the data lead-out line, the second end of the first vertical sub-line is connected to the first end of the first horizontal sub-line after extending in a direction away from the binding area, the second end of the first horizontal sub-line is connected to the first end of the second vertical sub-line after extending in a direction close to the second vertical sub-line, the second end of the second vertical sub-line is connected to the first end of the second horizontal sub-line after extending in a direction away from the binding area, and the second end of the second horizontal sub-line is connected to the data signal line after extending in a direction close to the data signal line.

8. The display substrate according to claim 7, characterized in that: The display area also includes multiple first data connection blocks; in at least one circuit unit, the first data connection block is connected to the first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected to the first data connection block through a via; in at least another circuit unit, the first data connection block is connected to the first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected to the first data connection block through a via.

9. The display substrate according to claim 8, characterized in that: The display area also includes multiple data transfer strips. In at least one circuit unit, the first end of the first horizontal sub-line is connected to the first data connection block through the data transfer strip; in at least another circuit unit, the first end of the second horizontal sub-line is connected to the first data connection block through the data transfer strip.

10. The display substrate according to claim 9, characterized in that: In at least one circuit unit, the first horizontal sub-line, the first data connection block and the data transfer bar are interconnected as an integrated structure; in at least another circuit unit, the second horizontal sub-line, the first data connection block and the data transfer bar are interconnected as an integrated structure.

11. The display substrate according to claim 8, characterized in that: The display area further includes a plurality of first dummy electrodes, and a position and a connection structure of at least one of the first dummy electrodes in one circuit unit are the same as a position and a connection structure of at least one of the first data connection blocks in another circuit unit.

12. The display substrate according to claim 11, characterized in that: In at least one circuit unit, the first vertical sub-line is connected to at least one first dummy electrode through a via hole; in at least another circuit unit, the second vertical sub-line is connected to at least one first dummy electrode through a via hole.

13. The display substrate according to claim 7, characterized in that: The display area further includes a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected to the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected to the second data connection block through a via.

14. The display substrate according to claim 13, characterized in that: In at least one circuit unit, the first transverse sub-line and the second data connection block are interconnected as an integral structure.

15. The display substrate according to claim 13, characterized in that: The display area further includes a plurality of second dummy electrodes, and a position and a connection structure of at least one of the second dummy electrodes in one circuit unit are the same as a position and a connection structure of at least one of the second data connection blocks in another circuit unit.

16. The display substrate according to claim 15, characterized in that: In at least one circuit unit, the first vertical sub-line is connected to at least one second dummy electrode through a via hole; in at least another circuit unit, the second vertical sub-line is connected to at least one second dummy electrode through a via hole.

17. A display device, characterized in that: Comprising the display substrate according to any one of claims 1 to 16.

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