Multiplexer module

Abstract

The utility model provides a multiplexer module which comprises a middle plastic package structure which comprises a plurality of filter chips, plastic package layers wrapping the back faces and the side walls of the filter chips, and retaining walls located on the two sides of the front faces of the filter chips. The isolation layer covers the retaining wall and forms a cavity with the retaining wall and the front surface of the filter chip; the at least one rewiring layer is located on the middle plastic package structure, the rewiring layer comprises a plurality of metal circuit layers and a dielectric layer for isolating the metal circuit layers, and the metal circuit layers are electrically connected with the front face of the filter chip; and the bonding pad is positioned on the rewiring layer and is electrically connected with the metal circuit layer. According to the utility model, at least one re-wiring layer is adopted to provide higher cavity strength, and cavity collapse in the subsequent secondary plastic packaging process can be resisted; according to the multiplexer module provided by the utility model, a smaller three-dimensional size can be realized, and a wider application field can be obtained.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a multiplexer module. Background Art

[0002] With the development of communication technology, filters and multiplexers are becoming more and more important in the communication field.

[0003] The multiplexer module is composed of multiple acoustic filters of different frequency bands. During the design process, it is difficult to make the thickness of the IDT (Interdigital Transducer) of the frequency band filters uniform, making it impossible to implement the multiplexer on the same wafer. At the same time, in order to ensure the normal operation of the filters in each frequency band, it is necessary to build a cavity on the surface of the IDT structure of the filter. Therefore, traditional multiplexers usually use multiple WLP (Wafer Level Packaging) with built cavities. ， Wafer-level packaging (WLP) filters are realized by welding and secondary packaging on a substrate, or the bare filter chip with bumps is first bonded or welded on a substrate, and then a layer of adhesive film is pasted on the entire module to form a cavity, and finally the packaging is completed by plastic packaging.

[0004] The main disadvantages of the multiplexer module formed by the above two methods are: 1. The package size is relatively thick, which does not meet the requirements of miniaturization of RF modules, especially the secondary packaging is extremely difficult in the PAMiD module with higher integration; 2. The filter wafer is relatively thin and is very easy to break during bump production or WLP packaging, resulting in yield loss; 3. It is extremely sensitive to molding pressure during the plastic encapsulation process, and is prone to cavity collapse or plastic encapsulation material infiltration, resulting in device failure. Utility Model Content

[0005] The utility model aims to provide a multiplexer module, which adopts at least one redistribution layer to provide higher cavity strength and can resist cavity collapse in the subsequent secondary plastic packaging process.

[0006] In order to solve the above technical problems, the utility model provides a multiplexer module, comprising:

[0007] An intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips;

[0008] at least one redistribution layer located on the intermediate plastic packaging structure, the redistribution layer comprising a plurality of metal wiring layers and a dielectric layer isolating the plurality of metal wiring layers, the metal wiring layer being electrically connected to the front side of the filter chip; and

[0009] A pad is located on the redistribution layer, and is electrically connected to the metal circuit layer.

[0010] Optionally, an IDT and electrodes located on both sides of the IDT are formed on the front side of the filter chip; the IDT is located in the cavity, the retaining wall and the isolation layer both have openings to expose at least part of the electrode, and the redistribution layer is electrically connected to the electrode.

[0011] Optionally, the thickness of the retaining wall is greater than the sum of the thickness of the interdigital transducer and the thickness of the electrode.

[0012] Optionally, a cross-sectional area of ​​the opening of the retaining wall at a side close to the filter chip is smaller than or equal to a cross-sectional area at a side away from the filter chip.

[0013] Optionally, a cross-sectional area of ​​the opening of the isolation layer at a side close to the filter chip is smaller than or equal to a cross-sectional area at a side away from the filter chip.

[0014] Optionally, a cross-sectional area of ​​the opening of the isolation layer at a side close to the filter chip is greater than or equal to a cross-sectional area of ​​an opening of the retaining wall at a corresponding position at a side away from the filter chip.

[0015] Optionally, the multiplexer module further includes a shielding layer, and the shielding layer at least covers the back side and side walls of the filter chip.

[0016] In summary, the multiplexer module provided by the utility model includes an intermediate plastic packaging structure, the intermediate plastic packaging structure includes multiple filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chip, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chip; at least one redistribution layer located on the intermediate plastic packaging structure, the redistribution layer includes multiple metal circuit layers and a dielectric layer isolating the multiple metal circuit layers, and the metal circuit layer is electrically connected to the front of the filter chip; a pad located on the redistribution layer, and the pad is electrically connected to the metal circuit layer. The utility model adopts at least one redistribution layer to provide higher cavity strength, which can resist cavity collapse in the subsequent secondary plastic packaging process; the utility model can combine WLP filter production and fan-out packaging to realize a multiplexer module, which can effectively reduce the complexity of multiplexer module production and reduce the filter wafer breakage rate. At the same time, the multiplexer module provided by the utility model can achieve a smaller three-dimensional size and can obtain a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1It is a flow chart of a method for manufacturing a multiplexer module provided by an embodiment of the utility model.

[0018] Figures 2 to 11 It is a structural schematic diagram of each step of the method for manufacturing a multiplexer module provided in the first embodiment of the utility model.

[0019] Figures 12 to 20 It is a structural schematic diagram of each step of the method for manufacturing a multiplexer module provided in the second embodiment of the present utility model.

[0020] Figure 21 to Figure 25 It is a structural schematic diagram of each step of the method for manufacturing a multiplexer module provided in the third embodiment of the present invention.

[0021] Figure 26 to Figure 32 It is a structural schematic diagram of each step of the method for manufacturing a multiplexer module provided in the fourth embodiment of the present utility model.

[0022] Figure 33 to Figure 36 It is a structural schematic diagram of each step of the method for manufacturing a multiplexer module provided in Embodiment 5 of the present utility model.

[0023] Figure 37 to Figure 39 It is a structural schematic diagram of each step of the method for manufacturing a multiplexer module provided in Example 6 of the present utility model.

[0024] Fig.40 It is a cross-sectional schematic diagram of a retaining wall opening provided in one embodiment of the utility model.

[0025] Fig.41 It is a cross-sectional schematic diagram of an isolation layer opening provided in one embodiment of the utility model.

[0026] Description of reference numerals:

[0027] 1-temporary bonding structure; 11-carrier; 12-bonding layer; 2-filter chip; 21-filter substrate; 22-interdigital transducer; 23-electrode; 24-side wall; 25-cavity; 3-shielding layer; 4-plastic sealing layer; 5-isolation layer; 6-rewiring layer; 61-metal circuit layer; 62-dielectric layer; 7-pad; 8-bump; 9-solder mask; 10-filter wafer. DETAILED DESCRIPTION

[0028] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0029] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0030] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a multiplexer module provided by an embodiment of the present invention. Figure 1 As shown, the method for manufacturing the multiplexer module includes the following steps:

[0031] S1: providing an intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips;

[0032] S2: forming at least one redistribution layer on the intermediate plastic packaging structure, wherein the redistribution layer is electrically connected to the front surface of the filter chip; and

[0033] S3: forming a pad on the redistribution layer, wherein the pad is electrically connected to the redistribution layer.

[0034] The utility model combines WLP filter production and fan-out packaging to realize a multiplexer module, which can effectively reduce the complexity of multiplexer module production and reduce the filter wafer breakage rate. At least one layer of redistribution layer provides a higher cavity strength to resist cavity collapse during the secondary plastic packaging process. At the same time, the smaller three-dimensional size produced thereby can obtain a wider range of applications.

[0035] The following is a detailed description of the method for manufacturing the multiplexer module of the present invention through specific embodiments.

[0036] [Example 1]

[0037] Figures 2 to 111 is a schematic diagram of the steps of the method for manufacturing a multiplexer module provided in the first embodiment of the present invention. Figure 1 and Figures 2 to 11 The manufacturing method of the multiplexer module provided by the embodiment of the utility model is described in detail.

[0038] In step S1, refer to Figure 8 As shown, an intermediate plastic packaging structure is provided, which includes multiple filter chips 2, a plastic packaging layer 4 covering the back and side walls of the filter chip 2, retaining walls 24 located on both sides of the front of the filter chip 2, and an isolation layer 5 covering the retaining wall 24 and forming a cavity 25 with the retaining wall 24 and the front of the filter chip 2.

[0039] Exemplarily, the intermediate plastic packaging structure may be formed through the following sub-steps S11 to S16.

[0040] Execute sub-step S11, please refer to Figure 2 and Figure 3 As shown, a filter wafer 10 is manufactured and divided into individual filter chips 2. Figure 2 is a top view of the entire filter wafer 10, Figure 3 It is a cross-sectional view of a single filter chip 2.

[0041] In this embodiment, filter chips are manufactured on a wafer to form a filter wafer 10, such as Figure 2 As shown, multiple filter chips are regularly arranged on the wafer. Then the filter wafer 10 is divided into multiple single filter chips 2. Please refer to Figure 3 As shown, the filter chip 2 includes a filter substrate 21, an IDT 22 formed on the front side of the filter substrate 21, and electrodes 23 located on both sides of the IDT 22. The side where the IDT 22 and the electrodes 23 are formed serves as the front side of the filter chip 2, and the other side opposite to the front side serves as the back side of the filter chip 2. The front side of the filter chip 2 and the front side of the filter substrate 21 are the same side.

[0042] Exemplarily, the material of the filter substrate 21 includes but is not limited to lithium niobate, lithium tantalate, silicon or a multilayer material with a piezoelectric material layer. The interdigital transducer 22 is composed of a single-layer film or a multilayer film of a metal material such as titanium (Ti), aluminum (Al), aluminum copper (AlCu), etc., and the surface of the interdigital transducer 22 can be covered with a silicon oxide or silicon nitride passivation layer to protect the interdigital transducer 22. The electrode 23 is composed of a single-layer film or a multilayer film of a metal material such as Ti, Al, AlCu, etc., and the surface of the electrode 23 can also be covered with a silicon oxide or silicon nitride passivation layer, and the passivation layer has an opening to expose a portion of the electrode 23.

[0043] Execute sub-step S12, please refer to Figure 4 As shown, a carrier board 11 is provided, and a plurality of filter chips 2 are mounted on the carrier board 11 with their front sides facing downward.

[0044] The carrier 11 can be a hard carrier, such as a silicon wafer, a glass plate or a metal panel. When the carrier 11 is a hard carrier, the supporting effect is better. The surface of the carrier 11 can be provided with a bonding layer 12, and the bonding layer 12 can be a debondable adhesive layer, which can be attached to the carrier 11 and can adhere to the chip or device placed on it. After the plastic sealing is completed, the carrier 11 can also be easily peeled off and removed. Of course, the bonding layer 12 can also be other material layers known in the art. The carrier 11 and the bonding layer 12 together constitute a temporary bonding structure 1.

[0045] A plurality of filter chips 2 are mounted on the temporary bonding structure 1 with their front faces facing downward. The IDT 22 and the electrode 23 on the front face of the filter chip 2 can be embedded in the bonding layer 12 , and the front face of the filter chip 2 can be attached to the surface of the bonding layer 12 .

[0046] Execute sub-step S13, please refer to Figure 5 As shown, a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the back side, the side wall and a part of the carrier board 11 of the filter chip 2 .

[0047] Exemplarily, the plastic encapsulation layer 4 can be formed by transfer film making, compression film making or lamination, etc. The plastic encapsulation layer 4 is a thermosetting resin material with inorganic fillers.

[0048] Execute sub-step S14, please refer to Figure 5 and Figure 6 As shown, the carrier board 11 is removed to expose the front side of the filter chip 2 .

[0049] Execute sub-step S15, please refer to Figure 7 As shown, retaining walls 24 are formed on both sides of the front side of the filter chip 2 .

[0050] Exemplarily, a barrier wall material layer is first formed on the front side of the filter chip 2, the barrier wall material layer covers the interdigital transducer 22, the electrode 23 and the filter substrate 21; then the barrier wall material layer is patterned to retain the barrier wall material layers on both sides of the filter chip 2 to form barrier walls 24. The material of the barrier wall 24 may be a dry film material or photoresist having exposure characteristics, but is not limited thereto.

[0051] The retaining wall 24 is located on both sides of the front side of the filter chip 2, exposing the IDT 22 on the front side of the filter chip 2, and the retaining wall 24 has an opening to expose at least a portion of the electrode 23. Fig.40 As shown, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 (only the filter substrate 21 and the electrode 23 are shown in the figure) is smaller than the cross-sectional area on the side away from the filter chip 2, that is, in the direction perpendicular to the filter substrate 21, the opening is wide at the top and narrow at the bottom, so as to facilitate the formation of the subsequent redistribution layer. In another embodiment of the utility model, please refer to Figure 7 As shown, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 is equal to the cross-sectional area on the side away from the filter chip 2 .

[0052] In an embodiment of the present invention, the thickness of the retaining wall 24 is greater than the sum of the thickness of the IDT 22 and the thickness of the electrode 23 to ensure the height of the cavity formed subsequently.

[0053] Execute sub-step S16, please refer to Figure 8 As shown, an isolation layer 5 is formed on the retaining wall 24 , and the isolation layer 5 , the retaining wall 24 and the front surface of the filter chip 2 form a cavity 25 .

[0054] The isolation layer 5 , the retaining wall 24 and the filter substrate 21 form a cavity 25 , and the IDT 22 is located in the cavity 25 .

[0055] In this embodiment, the material of the isolation layer 5 can be a dry film material or photoresist with exposure characteristics, or a thinned glass or silicon material with specific area openings. The thickness of the isolation layer 5 is not less than 3 μm.

[0056] The isolation layer 5 has an opening corresponding to the opening of the retaining wall 24 to expose a portion of the electrode 23. Fig.41 As shown, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 (only the filter substrate 21 and the electrode 23 are shown in the figure) is smaller than the cross-sectional area on the side away from the filter chip 2, that is, the opening of the isolation layer 5 is a structure that is wide at the top and narrow at the bottom, so as to facilitate the formation of the subsequent redistribution layer. In another embodiment of the utility model, please refer to Figure 8 As shown, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is equal to the cross-sectional area on the side away from the filter chip 2 .

[0057] In one embodiment of the utility model, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is greater than or equal to the cross-sectional area of ​​the opening of the retaining wall 24 at the corresponding position on the side away from the filter chip 2, so as to completely expose the electrode 23 exposed by the retaining wall 24.

[0058] In step S2, please refer to Fig. 9 As shown, at least one redistribution layer 6 is formed on the intermediate plastic packaging structure, and the redistribution layer 6 is electrically connected to the front side of the filter chip 2 .

[0059] The rewiring layer 6 may include a plurality of metal wiring layers 61 and a dielectric layer 62 isolating the plurality of metal wiring layers 61. The metal wiring layer 61 covers the opening of the isolation layer 5 and the electrode 23 exposed by the opening of the retaining wall 24, thereby being electrically connected to the electrode 23. The material of the metal wiring layer 61 may be a metal such as copper or aluminum, and a titanium / copper (Ti / Cu) or titanium tungsten / copper (TiW / Cu) seed layer may be provided at the bottom of the metal such as copper or aluminum, and the metal wiring layer 61 may be formed by electroplating and etching. In addition to connecting the electrodes 23 of each filter chip 2 for signal extraction and grounding, the metal wiring layer 61 also includes a matching circuit pattern to ensure the electrical performance of the module. The dielectric layer 62 may be a dry film material or photoresist with exposure characteristics, but is not limited thereto.

[0060] In this embodiment, a multi-layer redistribution layer 6 can be formed, and the metal circuit layers 61 in the multi-layer redistribution layer 6 are electrically connected. Fig. 9 Only two layers of the redistribution layer 6 are shown, but the invention is not limited thereto. The thickness of each metal wiring layer 61 in the multi-layer redistribution layer 6 may be the same or different, and the thickness of each dielectric layer 62 in the multi-layer redistribution layer 6 may be the same or different.

[0061] In step S3, please refer to Fig.10 As shown, a pad 7 is formed on the redistribution layer 6 , and the pad 7 is electrically connected to the redistribution layer 6 .

[0062] The material of the pad 7 includes but is not limited to copper, and the surface of the pad 7 can be treated to prevent oxidation. The pad 7 can be formed by electroplating and etching, and the pad 7 contacts the metal circuit layer 61 in the redistribution layer 6 to achieve electrical connection.

[0063] In an embodiment of the present invention, a bump 8 may be formed on the pad 7. The bump 8 may be a copper column or a solder ball.

[0064] In one embodiment of the present utility model, please refer to Fig.11As shown, in order to prevent short circuit during welding, a solder resist layer 9 can also be formed on the redistribution layer 6. The solder resist layer 9 is a material that is not wettable with tin or copper. The solder resist layer 9 has an opening at the pad 7 or the bump 8 to expose the pad 7 or the bump 8.

[0065] It can then be cut into individual modules and packaged.

[0066] The manufacturing method of the multiplexer module provided in this embodiment combines WLP filter manufacturing and fan-out packaging to realize the multiplexer module, which can effectively reduce the manufacturing complexity of the multiplexer module and reduce the filter wafer breakage rate. At least one layer of redistribution layer provides higher cavity strength to resist cavity collapse during the secondary plastic packaging process. At the same time, the smaller three-dimensional size produced thereby can obtain a wider range of applications.

[0067] [Example 2]

[0068] Compared with implementation one, the difference of this embodiment is that: after mounting the plurality of filter chips 2 with their front sides facing down on the carrier 11 and before forming the plastic encapsulation layer 4, it also includes: forming a shielding layer 3, wherein the shielding layer 3 covers the back and side walls of the filter chip 2 to increase electromagnetic shielding.

[0069] Figures 12 to 20 This is a schematic diagram of the various steps of the method for making a multiplexer module provided in the second embodiment of the present invention. Fig.12 As shown, after a plurality of the filter chips 2 are mounted on the carrier 11 with their front sides facing downward, a shielding layer 3 is formed, and the shielding layer 3 covers the back side, side walls and the carrier 11 between adjacent filter chips 2 (specifically the bonding layer 12 in this embodiment).

[0070] The shielding layer 3 is made of metal material, such as a single metal layer or a multi-layer metal composite layer such as copper or nickel. The shielding layer 3 can be formed by electroplating or sputtering. The thickness of the shielding layer 3 can be greater than or equal to 1 μm, but is not limited thereto.

[0071] Then, please refer to Fig.13 As shown, a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the shielding layer 3 .

[0072] Next, the carrier board 11 is removed to expose the front side of the filter chip 2 . Fig.14 This is a schematic diagram of the structure after the carrier board 11 is removed. Fig.15 for Fig.14 For the cross-sectional view at AB, please refer to Fig.14 and Fig.15As shown, the shielding layer 3 surrounds the back surface and side walls of the filter chip 2 and covers the plastic packaging layer 4 between adjacent filter chips 2 .

[0073] In an embodiment of the present invention, after removing the carrier board 11 , a portion of the shielding layer 3 may also be removed to expose a portion of the plastic packaging layer 4 . Fig.16 is a schematic diagram of the structure after removing part of the shielding layer, Fig.17 yes Fig.16 For the cross-sectional view at AB, please refer to Fig.16 and Fig.17 As shown, part of the shielding layer 3 is removed to expose the plastic packaging layer 4, which is beneficial to improving the bonding strength between the subsequently formed redistribution layer and the intermediate plastic packaging structure, thereby increasing the reliability of the module.

[0074] Next, please refer to Fig.18 and Fig.19 As shown, retaining walls 24 are formed on both sides of the front surface of the filter chip 2, and an isolation layer 5 is formed on the retaining walls 24. The isolation layer 5, the retaining walls 24 and the front surface of the filter chip 2 constitute a cavity 25, thereby forming an intermediate plastic packaging structure.

[0075] Then, please refer to Fig. 20 As shown, at least one redistribution layer 6 is formed on the intermediate plastic package structure, the metal wiring layer 61 in the redistribution layer 6 is electrically connected to the electrode 23, and the dielectric layer 62 is used to isolate the metal wiring layer 61. Afterwards, a pad 7 is formed on the redistribution layer 6, and the pad 7 is electrically connected to the redistribution layer 6. Afterwards, a bump 8 can also be formed on the pad 7, and a solder resist layer 9 is formed on the redistribution layer 6 to expose the pad 7 and the bump 8.

[0076] [Example 3]

[0077] Compared with the first embodiment, the present embodiment is different in that the method of forming the intermediate plastic packaging structure is different.

[0078] Figure 21 to Figure 25 The following is a schematic diagram of the steps of the method for manufacturing a multiplexer module provided in the third embodiment of the present invention. First, a filter wafer is manufactured, a retaining wall is formed on the filter wafer, and the filter wafer is divided into single filter chips 2 to form a filter wafer. Fig.21 The filter chip 2 includes a filter substrate 21, an IDT 22 formed on the front of the filter substrate 21, and electrodes 23 located on both sides of the IDT 22. Retaining walls 24 are formed on both sides of the front of the filter substrate 21, and the retaining walls 24 cover part of the electrodes 23, and the retaining walls 24 have openings to expose part of the electrodes 23.

[0079] Please refer to Fig. 22 As shown, a carrier board 11 is provided, and a plurality of filter chips 2 are mounted on the carrier board 11 with their front faces facing downward. A bonding layer 12 is also formed on the carrier board 11, and the carrier board 11 and the bonding layer 12 form a temporary bonding structure 1. The filter chips 2 are mounted on the temporary bonding structure 1 with their front faces facing downward, and the retaining wall 24 is in contact with the bonding layer 12 or embedded in the bonding layer 12.

[0080] Next, please refer to Fig.23 As shown, a plastic encapsulation layer 4 is formed on the carrier 11, and the plastic encapsulation layer 4 covers the back and side walls of the filter chip 2 and the carrier 11 (specifically the bonding layer 12). In this embodiment, the plastic encapsulation layer 4 also covers the side wall of the retaining wall 24 away from the IDT 22.

[0081] Please refer to Fig.24 As shown, the carrier board 11 is removed to expose the front side of the filter chip 2 .

[0082] Please refer to Fig.25 As shown, an isolation layer 5 is formed on the retaining wall 24 on the front side of the filter chip 2 , and the isolation layer 5 , the retaining wall 24 and the front side of the filter chip 2 form a cavity 25 .

[0083] In this embodiment, the retaining wall 24 is first formed on the filter wafer, and then the filter wafer is divided into individual filter chips 2. In this embodiment, the sidewalls 24 can be formed on the filter wafer at the same time, which saves process steps and reduces process costs compared with the first embodiment in which individual filter chips 2 are first cut and then sidewalls 24 are formed on each filter chip 2.

[0084] [Example 4]

[0085] Compared with the third embodiment, the difference of this embodiment lies in that: after mounting the plurality of filter chips 2 with their front sides facing down on the carrier 11 and before forming the plastic encapsulation layer 4, it also includes: forming a shielding layer 3, wherein the shielding layer 3 at least covers the back side and side walls of the filter chip 2 to increase electromagnetic shielding.

[0086] Figure 26 to Figure 32 This is a schematic diagram of the various steps of the method for making a multiplexer module provided in the fourth embodiment of the present invention. Fig.26 As shown, after a plurality of the filter chips 2 are mounted face down on the carrier 11, a shielding layer 3 is formed, and the shielding layer 3 covers the back side and side walls of the filter chip 2, the side wall of the retaining wall 24 away from the side of the interdigital transducer 22, and the carrier 11 between adjacent filter chips 2 (specifically the bonding layer 12 in this embodiment).

[0087] The shielding layer 3 is made of metal material, such as a single metal layer or a multi-layer metal composite layer such as copper or nickel. The shielding layer 3 can be formed by electroplating or sputtering. The thickness of the shielding layer 3 is greater than or equal to 1 μm, but is not limited thereto.

[0088] Then, please refer to Fig. 27 As shown, a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the shielding layer 3 .

[0089] Next, the carrier board 11 is removed to expose the front side of the filter chip 2 . Fig.28 This is a schematic diagram of the structure after the carrier board 11 is removed. Fig.29 for Fig.28 For the cross-sectional view at AB, please refer to Fig.28 and Fig.29 As shown, after the carrier board 11 is removed, the shielding layer 3 surrounds the back surface and side walls of the filter chip 2 and covers the plastic packaging layer 4 between adjacent filter chips 2 .

[0090] In an embodiment of the present invention, after removing the carrier board 11 , a portion of the shielding layer 3 may also be removed to expose a portion of the plastic packaging layer 4 . Fig.30 is a schematic diagram of the structure after removing part of the shielding layer, Fig.31 yes Fig.30 For the cross-sectional view at AB, please refer to Fig.30 and Fig.31 As shown, part of the shielding layer 3 is removed to expose the plastic packaging layer 4, which is beneficial to improving the bonding strength between the subsequently formed redistribution layer and the intermediate plastic packaging structure, thereby increasing the reliability of the module.

[0091] Next, please refer to Fig.32 As shown, an isolation layer 5 is formed on the retaining wall 24 , and the isolation layer 5 , the retaining wall 24 and the front surface of the filter chip 2 form a cavity 25 , thereby forming an intermediate plastic packaging structure.

[0092] [Example 5]

[0093] Compared with the first embodiment, the present embodiment is different in that the method of forming the intermediate plastic packaging structure is different.

[0094] Figure 33 to Figure 36 1 is a schematic diagram of the structure of each step of the method for manufacturing a multiplexer module provided in the fifth embodiment of the present invention. Similar to the third embodiment, a filter wafer is first manufactured, a retaining wall is formed on the filter wafer, and the filter wafer is divided into single filter chips 2 to form a filter wafer. Fig.21The filter chip 2 includes a filter substrate 21, an IDT 22 formed on the front of the filter substrate 21, and electrodes 23 located on both sides of the IDT 22. Retaining walls 24 are formed on both sides of the front of the filter substrate 21, and the retaining walls 24 cover part of the electrodes 23, and the retaining walls 24 have openings to expose part of the electrodes 23.

[0095] Please refer to Fig.33 As shown, a carrier 11 is provided, and an isolation layer 5 corresponding to the retaining wall 24 is formed on the carrier 11. This step can be performed simultaneously with the previous step. A bonding layer 12 is also formed on the carrier 11. The carrier 11 and the bonding layer 12 constitute a temporary bonding structure 1, and the isolation layer 5 is formed on the bonding layer 12.

[0096] Please refer to Fig.34 As shown, a plurality of the filter chips 2 are mounted on the carrier board 11 with their front sides facing downwards, and the isolation layer 5 , the retaining wall 24 and the filter substrate 21 form a cavity 25 .

[0097] Next, please refer to Fig.35 As shown, a plastic encapsulation layer 4 is formed on the carrier 11, and the plastic encapsulation layer 4 covers the back and side walls of the filter chip 2 and the carrier 11 (specifically, the bonding layer 12). In this embodiment, the plastic encapsulation layer 4 also covers the side wall of the retaining wall 24 away from the IDT 22 and the side wall of the isolation layer 5 away from the IDT 22.

[0098] Please refer to Fig.36 As shown, the carrier board 11 is removed to expose the front side of the filter chip 2 , and finally an intermediate plastic packaging structure is formed.

[0099] In this embodiment, a retaining wall 24 is first formed on the filter wafer, and then the filter wafer is divided into individual filter chips 2, and an isolation layer 5 is formed on the carrier 11. Compared with the third embodiment, the retaining wall 24 and the isolation layer 5 can be manufactured at the same time, thereby saving process time.

[0100] [Example 6]

[0101] Compared with the fifth embodiment, the difference of this embodiment is that after mounting the plurality of filter chips 2 with their front sides facing down on the carrier 11 and before forming the plastic encapsulation layer 4, it also includes: forming a shielding layer 3, wherein the shielding layer 3 at least covers the back side and side walls of the filter chip 2 to increase electromagnetic shielding.

[0102] Figure 37 to Figure 39 This is a schematic diagram of the various steps of the method for making a multiplexer module provided in the sixth embodiment of the present invention. Fig.37 As shown, after a plurality of the filter chips 2 are mounted face down on the carrier 11, a shielding layer 3 is formed, and the shielding layer 3 covers the back side and side walls of the filter chip 2, the side wall of the retaining wall 24 away from the side of the interdigital transducer 22, the side wall of the isolation layer 5 away from the side of the interdigital transducer 22, and the carrier 11 between adjacent filter chips 2 (specifically the bonding layer 12 in this embodiment).

[0103] Then, please refer to Fig.38 As shown, a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the shielding layer 3 .

[0104] Next, the carrier board 11 is removed to expose the front side of the filter chip 2, forming a Fig.39 The intermediate plastic package structure shown.

[0105] It should be noted that the embodiments in this specification are described in a progressive manner, and the production methods described later focus on the differences from the methods described previously, and the similarities and similarities between the embodiments can be referred to each other.

[0106] Correspondingly, the utility model also provides a multiplexer module, which can be manufactured by using the manufacturing method of the multiplexer module described in any one of the above embodiments.

[0107] Please refer to Fig.11 As shown, the multiplexer module manufactured by the manufacturing method of the multiplexer module described in the first embodiment is used as an example for description, and the multiplexer module includes:

[0108] An intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips 2, a plastic packaging layer 4 covering the back and side walls of the filter chips 2, retaining walls 24 located on both sides of the front of the filter chips 2, and an isolation layer 5 covering the retaining walls 24 and forming a cavity 25 with the retaining walls 24 and the front of the filter chips 2;

[0109] At least one redistribution layer 6 located on the intermediate plastic packaging structure, the redistribution layer 6 comprising a plurality of metal wiring layers 61 and a dielectric layer 62 isolating the plurality of metal wiring layers 61, the metal wiring layer 61 being electrically connected to the front side of the filter chip 2; and

[0110] The pad 7 is located on the redistribution layer 6 , and the pad 7 is electrically connected to the metal circuit layer 61 .

[0111] In this embodiment, an IDT 22 and electrodes 23 located on both sides of the IDT 22 are formed on the front side of the filter chip 2; the IDT 22 is located in the cavity 25, and the retaining wall 24 and the isolation layer 5 both have openings to expose at least part of the electrode 23, and the redistribution layer 6 is electrically connected to the electrode 23.

[0112] In an embodiment of the present invention, the thickness of the retaining wall 24 is greater than the sum of the thickness of the IDT 22 and the thickness of the electrode 23 , so as to ensure the height of the cavity 25 .

[0113] In one embodiment of the present utility model, please refer to Fig.40 As shown, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 (only the filter substrate 21 and the electrode 23 are shown in the figure) is smaller than the cross-sectional area on the side away from the filter chip 2, that is, the opening is wide at the top and narrow at the bottom, so as to facilitate the electrical connection between the redistribution layer 6 and the electrode 23. In another embodiment of the utility model, please refer to Fig.11 As shown, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 may also be equal to the cross-sectional area on the side away from the filter chip 2 .

[0114] In one embodiment of the present utility model, please refer to Fig.41 As shown, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 (only the filter substrate 21 and the electrode 23 are shown in the figure) is smaller than the cross-sectional area on the side away from the filter chip 2, that is, the opening of the isolation layer 5 is a structure that is wide at the top and narrow at the bottom, so as to facilitate the electrical connection between the redistribution layer 6 and the electrode 23. In another embodiment of the utility model, please refer to Fig.11 As shown, the cross-sectional area of ​​the opening of the isolation layer 5 at the side close to the filter chip 2 may also be equal to the cross-sectional area at the side away from the filter chip 2 .

[0115] In one embodiment of the utility model, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is greater than or equal to the cross-sectional area of ​​the opening of the retaining wall 24 at the corresponding position on the side away from the filter chip 2, so as to completely expose the electrode 23 exposed by the retaining wall 24.

[0116] In one embodiment of the present utility model, please refer to Fig. 20 As shown, the multiplexer module further includes a shielding layer 3, which at least covers the back and side walls of the filter chip 2 to increase electromagnetic shielding. In this embodiment, the shielding layer 3 can also expose part of the plastic packaging layer 4 to ensure the bonding force between the intermediate plastic packaging structure and the redistribution layer 6, thereby increasing the reliability of the module.

[0117] In summary, the multiplexer module provided by the utility model includes an intermediate plastic packaging structure, the intermediate plastic packaging structure includes multiple filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chip, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chip; at least one redistribution layer located on the intermediate plastic packaging structure, the redistribution layer includes multiple metal circuit layers and a dielectric layer isolating the multiple metal circuit layers, and the metal circuit layer is electrically connected to the front of the filter chip; a pad located on the redistribution layer, and the pad is electrically connected to the metal circuit layer. The utility model adopts at least one redistribution layer to provide higher cavity strength, which can resist cavity collapse in the subsequent secondary plastic packaging process; the utility model can combine WLP filter production and fan-out packaging to realize a multiplexer module, which can effectively reduce the complexity of multiplexer module production and reduce the filter wafer breakage rate. At the same time, the multiplexer module provided by the utility model can achieve a smaller three-dimensional size and can obtain a wider range of applications.

[0118] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation to the scope of the utility model. Any changes and modifications made by ordinary technicians in the field of the utility model based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A multiplexer module, characterized in that: include: An intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips; At least one redistribution layer located on the intermediate plastic packaging structure, the redistribution layer comprising a plurality of metal circuit layers and a dielectric layer isolating the plurality of metal circuit layers, the metal circuit layer being electrically connected to the front side of the filter chip; as well as A pad is located on the redistribution layer, and is electrically connected to the metal circuit layer.

2. The multiplexer module according to claim 1, characterized in that: An IDT and electrodes on both sides of the IDT are formed on the front of the filter chip; the IDT is located in the cavity, the retaining wall and the isolation layer both have openings to expose at least part of the electrodes, and the redistribution layer is electrically connected to the electrodes.

3. The multiplexer module according to claim 2, characterized in that: The thickness of the retaining wall is greater than the sum of the thickness of the interdigital transducer and the thickness of the electrode.

4. The multiplexer module according to claim 2, characterized in that: The cross-sectional area of ​​the opening of the retaining wall at a side close to the filter chip is smaller than or equal to the cross-sectional area at a side away from the filter chip.

5. The multiplexer module according to claim 4, characterized in that: The cross-sectional area of ​​the opening of the isolation layer at a side close to the filter chip is smaller than or equal to the cross-sectional area at a side away from the filter chip.

6. The multiplexer module according to claim 5, characterized in that: The cross-sectional area of ​​the opening of the isolation layer at a side close to the filter chip is greater than or equal to the cross-sectional area of ​​the opening of the retaining wall at a corresponding position at a side away from the filter chip.

7. The multiplexer module according to any one of claims 1 to 6, characterized in that: The multiplexer module further includes a shielding layer, and the shielding layer at least covers the back side and side wall of the filter chip.

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