Shifting register, driving circuit, display substrate and display device

Abstract

The utility model provides a shift register, a driving circuit, a display substrate and a display device, and relates to the technical field of display. The shift register comprises an input circuit which is configured to control the potential of a first node under the control of a first input signal from a first input end and a second input signal from a second input end; the control circuit is configured to control the potential of the second node to be different from the potential of the first node under the control of the potential of the first node, a second input signal and a reset signal from a reset end; and the output circuit is configured to output a scanning signal under the control of the potentials of the first node and the second node.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a shift register, a driving circuit, a display substrate and a display device. Background Art

[0002] The gate drive circuit (Gate on Array, GOA) integrated on the array substrate scans the pixel array of the display panel row by row to provide a control electrode drive signal. Common GOA circuits use inverter modules, such as Darlington inverters. This inverter module causes a DC path between the high and low levels connected to the GOA circuit, thereby affecting the stability of the GOA circuit. Utility Model Content

[0003] The utility model provides a shift register, a driving circuit, a display substrate and a display device.

[0004] According to a first aspect, the utility model provides a shift register, comprising: an input circuit, configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit, configured to control the potential of the second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; and an output circuit, configured to output a scan signal under the control of the potentials of the first node and the second node.

[0005] For example, the control circuit controls the potential of the second node under the control of the potential of the first node, the second input signal and the reset signal from the reset terminal, and is configured to: charge the second node with the first voltage of the first power supply under the control of the first level of the first node, the reset signal and the second input signal; and pull down the potential of the second node under the control of the second level of the first node.

[0006] For example, the control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; wherein the control electrode of the first transistor is electrically connected to the second input terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the control electrode of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to the first power supply, and the second electrode of the second transistor is electrically connected to the control electrode of the third transistor; the first electrode of the third transistor is electrically connected to the first power supply, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to the second power supply; and the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the third power supply.

[0007] For example, the control circuit further includes a first capacitor; wherein a first end of the first capacitor is electrically connected to the first power source, and a second end of the first capacitor is electrically connected to the control electrode of the third transistor.

[0008] For example, the control circuit further includes a first capacitor; wherein a first end of the first capacitor is electrically connected to the control electrode of the third transistor, and a second end of the first capacitor is electrically connected to the third power supply.

[0009] For example, the output circuit includes: a shift signal output terminal configured to output a shift signal.

[0010] For example, the output circuit includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units.

[0011] According to a second aspect, the utility model provides a driving circuit, comprising a plurality of cascaded shift registers provided by embodiments of the utility model.

[0012] For example, the first input terminal of the nth shift register is electrically connected to the shift signal output terminal of the n-2th shift register, and the second input terminal of the nth shift register is electrically connected to the shift signal output terminal of the n+2th shift register, where n is a positive integer.

[0013] According to a third aspect, the utility model provides a display device, comprising a display panel; and a driving circuit as provided in an embodiment of the utility model; wherein the display panel comprises a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0014] According to a fourth aspect, the utility model provides a display substrate, comprising: a shift register; and a compensation circuit, configured to compensate for an input signal or an output signal of the shift register to obtain a plurality of scanning signals to control the relative difference between the fall times of the plurality of scanning signals.

[0015] For example, the compensation circuit is configured to compensate for the input signal of the shift register to obtain multiple scanning signals: compensate for multiple clock signals from multiple clock terminals to control the relative difference between the fall times of the multiple clock signals, obtain multiple compensated clock signals, so that the shift register outputs multiple scanning signals based on the multiple compensated clock signals.

[0016] For example, the compensation circuit includes a plurality of compensation sub-circuits, and the number of the plurality of compensation sub-circuits is the same as the number of the plurality of clock terminals.

[0017] For example, each compensation sub-circuit in the multiple compensation sub-circuits includes a compensation resistor and a compensation capacitor; wherein the first end of the compensation resistor is electrically connected to the clock end, and the second end of the compensation resistor is electrically connected to the shift register; and the first end of the compensation capacitor is electrically connected to the clock end, and the second end of the compensation capacitor is electrically connected to the fourth power supply.

[0018] For example, the compensation circuit includes: multiple clock signal lines, configured to compensate for multiple clock signals to obtain multiple compensated clock signals; wherein the length of one clock signal line among the multiple clock signal lines is smaller than the length of the remaining clock signal lines among the multiple clock signal lines, or the width of one clock signal line among the multiple clock signal lines is larger than the width of the length of the remaining clock signal lines among the multiple clock signal lines.

[0019] For example, the shift register includes a plurality of driving capacitors, the number of the plurality of driving capacitors is the same as the number of the plurality of clock terminals; wherein the capacitance of one driving capacitor among the plurality of driving capacitors is smaller than the capacitance of the remaining driving capacitors among the plurality of driving capacitors.

[0020] For example, the compensation circuit includes multiple output signal lines, which are configured to compensate for the output signals of the shift register to obtain multiple scanning signals; wherein the length of one of the multiple output signal lines is smaller than the length of the remaining output signal lines among the multiple output signal lines, or the width of one of the multiple output signal lines is larger than the width of the length of the remaining output signal lines among the multiple output signal lines.

[0021] For example, the shift register includes: an input circuit, configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit, configured to control the potential of a second node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; and an output circuit, configured to output a scan signal under the control of the potentials of the first node and the second node.

[0022] According to a fifth aspect, the utility model further provides a display device, comprising a display substrate as provided in an embodiment of the utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of a shift register according to an embodiment of the utility model;

[0024] Figure 2A is a schematic structural diagram of a shift register according to another embodiment of the utility model;

[0025] Figure 2B is a schematic structural diagram of a shift register according to another embodiment of the utility model;

[0026] Figure 2C is a schematic structural diagram of a shift register according to another embodiment of the utility model;

[0027] Figure 3 is a schematic diagram of signal timing of a shift register according to an embodiment of the utility model;

[0028] Figure 4A is a schematic diagram of voltage and current in an exemplary shift register;

[0029] Figure 4B is a schematic diagram of voltage and current in a shift register according to an embodiment of the utility model;

[0030] Figure 5 is a schematic structural diagram of a driving circuit according to an embodiment of the utility model;

[0031] Figure 6 is a schematic structural diagram of a display device according to an embodiment of the utility model;

[0032] Figure 7 is a flow chart of a driving method according to an embodiment of the utility model;

[0033] Figure 8 is a schematic structural diagram of a display substrate according to an embodiment of the utility model;

[0034] Fig. 9is a schematic structural diagram of a display substrate according to another embodiment of the utility model;

[0035] Fig. 10A is a schematic diagram of brightness of a display panel driven by a shift register before compensation;

[0036] Fig. 10B is a schematic diagram of the brightness of a display panel driven by a shift register after compensation according to an embodiment of the utility model;

[0037] Fig.11A is a capacitance matching schematic diagram of the capacitor C2 according to an embodiment of the utility model;

[0038] Fig. 11B is a capacitance matching diagram of capacitors C3 to C6 according to an embodiment of the utility model;

[0039] Fig. 12A is a simulation schematic diagram of an output signal before capacitor matching according to an embodiment of the utility model;

[0040] Fig. 12B is a simulation schematic diagram of the output signal after capacitor matching according to an embodiment of the utility model;

[0041] Fig.13 is a compensation schematic diagram of a signal line according to an embodiment of the utility model;

[0042] Fig.14A is a schematic structural diagram of a display substrate according to an embodiment of the utility model;

[0043] Fig. 14B is a schematic structural diagram of a display substrate according to another embodiment of the utility model;

[0044] FIG. 15A to FIG. 15D for Fig.14A The layered layout of the display substrate is shown;

[0045] FIG. 16A to FIG. 16D for Fig. 14B The layered layout of the display substrate is shown;

[0046] Fig.17 is a schematic structural diagram of a display device according to another embodiment of the utility model; and

[0047] Fig.18 is a flow chart of a driving method according to another embodiment of the utility model. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical scheme and advantages of the embodiment of the utility model clearer, the technical scheme in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all. Based on the described embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the utility model. It should be noted that throughout the drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the utility model, but are only examples of the embodiments of the utility model. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the utility model. It should be noted that the shapes and sizes of the components in the figure do not reflect the actual size and proportion, but only illustrate the contents of the embodiment of the utility model.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0050] In addition, in the description of the embodiments of the present invention, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless method.

[0051] The source and drain of the switch transistor used in the embodiment of the utility model are symmetrical, so the source and drain can be interchanged. In the embodiment of the utility model, according to its function, the control electrode can be called the control electrode, one of the source and the drain can be called the first electrode, and the other of the source and the drain can be called the second electrode.

[0052] It should be noted that in the description of the embodiments of the present utility model, the symbol OUTPUT can represent both a scan signal and an output end of the scan signal, and b can also represent the level of the scan signal. Similarly, the symbol INPUT can represent both an input signal and an input end of the input signal, the symbol VDD can represent both a power supply and a voltage provided by the power supply, and the symbol VGL can represent both a power supply and a voltage provided by the power supply. For example, the power supply VGL can provide a low voltage, such as grounding. The power supply VDD can provide a high level. The following embodiments are the same, and similar parts will not be repeated.

[0053] Figure 1 It is a schematic diagram of the structure of a shift register according to an embodiment of the utility model.

[0054] like Figure 1 As shown, the shift register 100 includes an input circuit 110 , a control circuit 120 , and an output circuit 130 .

[0055] In the embodiment of the utility model, the input circuit 110 is electrically connected to the first input terminal INPUT1 and the second input terminal INPUT2, the control circuit 120 is electrically connected to the second input terminal INPUT2 and the reset terminal RST, and the output circuit 130 is electrically connected to the output terminal OUTPUT.

[0056] The input circuit 110 and the control circuit 120 are electrically connected to a first node Q, the input circuit 110 and the output circuit 130 are electrically connected to the first node Q, and the control circuit 220 and the output circuit 130 are electrically connected to a second node QB.

[0057] In the embodiment of the utility model, the input circuit 110 is configured to control the potential of the first node Q under the control of the first input signal INPUT1 from the first input terminal INPUT1 and the second input signal INPUT2 from the second input terminal INPUT2. The control circuit 120 is configured to control the potential of the second node QB to be different from the potential of the first node Q under the control of the potential of the first node Q, the second input signal INPUT2 and the reset signal RST from the reset terminal RST. The output circuit 130 is configured to output the scan signal OUTPUT under the control of the potentials of the first node Q and the second node QB.

[0058] For example, when the first node Q is at a low level, the control circuit 120 controls the second node QB to be at a high level. When the first node Q is at a high level, the control circuit 120 controls the second node QB to be at a low level.

[0059] In the embodiment of the utility model, the control circuit 120 can be an inverter of the shift register 100. The control circuit 120 is also electrically connected to power supplies providing high level and low level, respectively, and the potential of the first node Q, the second input signal INPUT2 and the reset signal RST control the conduction and cutoff of the control circuit 120.

[0060] In the embodiment of the present invention, under the control of the first level of the first node Q, the reset signal RST and the second input signal INPUT2, the control circuit 220 charges the second node QB through the first voltage of the first power supply. Under the control of the second level of the first node Q, the control circuit 120 pulls down the level of the second node QB.

[0061] In the embodiment of the utility model, the first level is a low level, the second level is a high level, and the first voltage provided by the first power supply is a high level. The control circuit 120 is also electrically connected to the second power supply, and the second voltage provided by the second power supply is a low level.

[0062] When the level of any one of the reset signal RST and the second input signal INPUT2 is high, the first power supply is connected to the second node QB, and the control circuit 220 charges the second node QB through the first voltage of the first power supply, so that the second node QB is high. At this time, under the control of the low level of the first node Q, the second node QB is disconnected from the second power supply. In this case, the second node QB is high, and the second node QB is connected to the first power supply and disconnected from the second power supply.

[0063] When the levels of the reset signal RST and the second input signal INPUT2 are both low, the first power supply is disconnected from the second node QB. Under the high level control of the first node Q, the second power supply is connected to the second node QB, and the control circuit 220 pulls down the level of the second node QB so that the second node QB is low. In this case, the second node QB is low, and the second node QB is connected to the second power supply and disconnected from the first power supply.

[0064] In the embodiment of the utility model, under the control of the level of the first node Q, the second input signal INPUT2 and the reset signal RST, a DC path can be avoided between the two power supplies providing high level and low level, thereby avoiding leakage in the shift register 100 and improving the stability of the shift register 100.

[0065] Figure 2A , Figure 2B and Figure 2C It is a schematic structural diagram of a shift register according to another embodiment of the utility model.

[0066] like Figure 2A As shown, the shift register 200a includes an input circuit 210a, a control circuit 220a and an output circuit 230a.

[0067] In the embodiment of the utility model, the input circuit 210a includes transistors M1 to M13, transistor M19, transistor M20, transistor M34 and capacitor C1, wherein transistor M11 and transistor M34 are dual-gate transistors. The control circuit 220a includes transistors M14 to M18, and transistors M14 to M18 form an inverter. The output circuit 230a includes transistors M21 to M33 and capacitors C2 to C6. Transistors M1 to M34 are all N-type transistors.

[0068] In the embodiment of the utility model, the control electrodes of transistor M1 and transistor M2 are electrically connected to the selection control signal terminal OE, the first electrode of transistor M1 is electrically connected to the first input terminal CR(N-2), the second electrode of transistor M1 is electrically connected to the first electrode of transistor M2, and the second electrode of transistor M2 is electrically connected to node H.

[0069] The first electrode of transistor M3 is electrically connected to the first electrode of transistor M2, the second electrode of transistor M3 is electrically connected to power supply VDD1, and the control electrode of transistor M3 is electrically connected to node H. The first end of capacitor C1 is electrically connected to node H, and the second end is electrically connected to power supply VDD1.

[0070] A first electrode of the transistor M4 is electrically connected to the clock terminal CLKA, a control electrode of the transistor M4 is electrically connected to the node H, and a second electrode of the transistor M4 is electrically connected to a first electrode of the transistor M5. A second electrode of the transistor M5 is electrically connected to a first electrode of the transistor M6, and a second electrode of the transistor M6 is electrically connected to a first node Q. The control electrode of the transistor M5 and the control electrode of the transistor M6 are electrically connected to the clock terminal CLKA.

[0071] The control electrode of transistor M7 and the control electrode of transistor M8 are electrically connected to the first input terminal CR(N-2). The first electrode of transistor M7 is electrically connected to the power supply VDD1, and the second electrode of transistor M7 is electrically connected to the first electrode of transistor M8. The second electrode of transistor M8 is electrically connected to the first node Q, and the control electrode of transistor M341 and the control electrode of transistor M342 are electrically connected to the power supply VDD3. The first electrode of transistor M341 is electrically connected to the power supply VDD3, the second electrode of transistor M341 is electrically connected to the first electrode of transistor M342, and the second electrode of transistor M342 is electrically connected to the first electrode of transistor M8.

[0072] The control electrode of transistor M9 and the control electrode of transistor M10 are electrically connected to the reset terminal RST. The first electrode of transistor M9 is electrically connected to the first node Q, and the second electrode of transistor M9 is electrically connected to the first electrode of transistor M10 and the first electrode of transistor M6. The second electrode of transistor M10 is electrically connected to the power supply VGL1, and the control electrode of transistor M341 and the control electrode of transistor M342 are electrically connected to the power supply VDD3. The first electrode of transistor M341 is electrically connected to the power supply VDD3, the second electrode of transistor M341 is electrically connected to the first electrode of transistor M342, and the second electrode of transistor M342 is electrically connected to the first electrode of transistor M8.

[0073] The control electrodes of transistor M111 and transistor M112 are electrically connected to the first node Q. The first electrode of transistor M111 is electrically connected to the power supply VDD1, the second electrode of transistor M111 is electrically connected to the first electrode of transistor M112, and the second electrode of transistor M112 is electrically connected to the first electrode of transistor M10.

[0074] The control electrodes of transistor M12 and transistor M13 are electrically connected to the second input terminal CR(N+2). The first electrode of transistor M12 is electrically connected to the first node Q, the second electrode of transistor M12 is electrically connected to the first electrode of transistor M13, and the second electrode of transistor M13 is electrically connected to the first electrode of transistor M10.

[0075] The control electrodes of the transistor M19 and the transistor M20 are electrically connected to the second node QB. The first electrode of the transistor M19 is electrically connected to the first node Q, the second electrode of the transistor M19 is electrically connected to the first electrode of the transistor M20, and the second electrode of the transistor M20 is electrically connected to the power supply VGL1 of the transistor M10.

[0076] In the embodiment of the present invention, the control electrode of the transistor M14 is electrically connected to the second input terminal CR(N+2), the first electrode of the transistor M14 is electrically connected to the power supply VDD2, and the second electrode of the transistor M14 is electrically connected to the control electrode of the transistor M16.

[0077] The control electrode of transistor M15 is electrically connected to the reset terminal RST, the first electrode of transistor M15 is electrically connected to the power supply VDD2, the second electrode of transistor M15 is electrically connected to the control electrode of transistor M16, the first electrode of transistor M16 is electrically connected to the power supply VDD2, and the second electrode of transistor M16 is electrically connected to the second node QB.

[0078] The control electrode of the transistor M17 is electrically connected to the first node Q, the first electrode of the transistor M17 is electrically connected to the control electrode of the transistor M16, and the second electrode of the transistor M17 is electrically connected to the power supply VGL3. The control electrode of the transistor M18 is electrically connected to the first node Q, the first electrode of the transistor M18 is electrically connected to the second node QB, and the second electrode of the transistor M18 is electrically connected to the power supply VGL1.

[0079] In the embodiment of the utility model, the output circuit 230a includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units. For example, the plurality of output terminals include an output terminal OUT(N), an output terminal OUT(N+1), an output terminal OUT(N+2), and an output terminal OUT(N+3). The output terminal OUT(N), the output terminal OUT(N+1), the output terminal OUT(N+2), and the output terminal OUT(N+3) can be used to drive four rows of sub-pixels.

[0080] It should be noted that the present invention does not limit the number of output terminals.

[0081] The control electrodes of the transistors M21, M23, M25, M27 and M29 are electrically connected to the first node Q. A first electrode of the transistor M21 is electrically connected to the clock terminal CLKD1, and a second electrode of the transistor M21 is electrically connected to the shift signal output terminal CR(N), which is configured to output the shift signal CR(N).

[0082] The first electrode of transistor M23 is electrically connected to the clock terminal CLK1, and the second electrode of transistor M23 is electrically connected to the output terminal OUT(N). The first electrode of transistor M25 is electrically connected to the clock terminal CLK2, and the second electrode of transistor M25 is electrically connected to the output terminal OUT(N+1). The first electrode of transistor M27 is electrically connected to the clock terminal CLK3, and the second electrode of transistor M27 is electrically connected to the output terminal OUT(N+2). The first electrode of transistor M29 is electrically connected to the clock terminal CLK4, and the second electrode of transistor M29 is electrically connected to the output terminal OUT(N+3).

[0083] A first end of the capacitor C2, a first end of the capacitor C3, a first end of the capacitor C4, a first end of the capacitor C5, and a first end of the capacitor C6 are electrically connected to the first node Q. A second end of the capacitor C2 is electrically connected to the shift signal output terminal CR(N). A second end of the capacitor C3 is electrically connected to the output terminal OUT(N). A second end of the capacitor C4 is electrically connected to the output terminal OUT(N+1). A second end of the capacitor C5 is electrically connected to the output terminal OUT(N+2). A second end of the capacitor C6 is electrically connected to the output terminal OUT(N+3).

[0084] The control electrodes of transistors M22, M24, M26, M28, and M30 are electrically connected to the second node QB. The second electrodes of transistors M22, M24, M26, M28, and M30 are electrically connected to the power supply VGL2.

[0085] The first pole of transistor M22 is electrically connected to the output terminal CR(N), and the shift signal output terminal CR(N) is configured to output the shift signal CR(N). The first pole of transistor M24 is electrically connected to the output terminal OUT(N). The first pole of transistor M26 is electrically connected to the output terminal OUT(N+1). The first pole of transistor M27 is electrically connected to the output terminal OUT(N+2). The first pole of transistor M30 is electrically connected to the output terminal OUT(N+3).

[0086] The control electrode of the transistor M31 is electrically connected to the clock terminal CLKA. The first electrode of the transistor M31 is electrically connected to the first electrode of the transistor M32, the second electrode of the transistor M32 is electrically connected to the power supply VGL1, and the control electrode of the transistor M32 is electrically connected to the node H. The control electrode of the transistor M33 is electrically connected to the clock terminal CLKA. The control electrode of the transistor M33 is electrically connected to the first input terminal CR(N-2), the first electrode of the transistor M33 is electrically connected to the second node QB, and the second electrode of the transistor M33 is electrically connected to the power supply VGL1.

[0087] like Figure 2B As shown, the shift register 200b includes an input circuit 210b, a control circuit 220b and an output circuit 230b.

[0088] In the embodiment of the present invention, the structures of the input circuit 210b and the output circuit 230b are similar to those of the input circuit 210a and the output circuit 230a described above, and are not described again for the sake of brevity.

[0089] In the embodiment of the present invention, the control circuit 220b further includes a capacitor C7 based on the control circuit 220a described above. A first terminal of the capacitor C7 is electrically connected to the power source VDD2, and a second terminal of the capacitor C7 is electrically connected to the control electrode of the transistor M16.

[0090] like Figure 2C As shown, the shift register 200c includes an input circuit 210c, a control circuit 220c and an output circuit 230c.

[0091] In the embodiment of the present invention, the structures of the input circuit 210c and the output circuit 230c are similar to those of the input circuit 210a and the output circuit 230a described above, respectively, and are not described again for the sake of brevity.

[0092] In the embodiment of the present invention, the control circuit 220c further includes a capacitor C7 based on the control circuit 220a described above.

[0093] In the embodiment of the present invention, a first end of the capacitor C7 is electrically connected to the control electrode of the transistor M16, and a second end of the capacitor C7 is electrically connected to the power source VGL1.

[0094] Figure 3 1 is a schematic diagram of signal timing of a shift register according to an embodiment of the utility model.

[0095] Figure 3The signal timing diagram corresponding to a frame of display picture is shown. The signal period corresponding to a frame of display picture includes a display period and a blanking period. During the display period of a frame of display picture, the shift register provides a scanning drive signal for a scanning transistor, and during the blanking period of a frame of display picture, the shift register provides a sensing drive signal for a sensing transistor.

[0096] like Figure 3 As shown, the clock terminals CLK1 to CLK12 are respectively the clock terminals to which three cascaded shift registers are connected, and the clock terminals CLK1 to CLK12 provide clock signals CLK1 to CLK12 for the three cascaded shift registers. For example, the shift registers can be Figure 2A , Figure 2B and Figure 2C The shift register shown in the figure, each shift register includes four output terminals, which are electrically connected to four clock terminals respectively. The clock terminals CLKD1 to CLKD3 are electrically connected to the transistors M21 of the three shift registers respectively. The timing of the clock signals CLKD1 to CLKD3 provided by the clock terminals CLKD1 to CLKD3 is respectively the same as the timing of the shift signal CR(N) output by the Nth stage shift register, the shift signal CR(N+1) output by the N+1th stage shift register and the shift signal CR(N+2) output by the N+2th stage shift register.

[0097] exist Figure 2A In the shift register 200a shown, the second input signal provided by the second input terminal CR(N+2) electrically connected to the control electrode of the transistor M14 can be a reset signal of the pixel row corresponding to the output terminal OUT(n). The reset terminal RST electrically connected to the control electrode of the transistor M15 can be an overall reset signal of the cascaded multiple shift registers 200a.

[0098] When the reset signal RST is at a high level, the shift signal CR(N+2) (second input signal) is at a low level. Under the control of the high level of the reset signal RST, the transistor M15 is turned on. The transistor M14 is turned off by the second input signal CR(N+2). The voltage VDD2 is applied to the control electrode of the transistor M16 through the transistor M15, and the transistor M16 is turned on. The voltage VDD2 charges the second node QB through the transistor M16.

[0099] When the reset signal RST is at a high level, the selection control signal OE and the first input signal CR(N-2) are at a low level. The transistors M1, M2, M7 and M8 are turned off. At this time, the potential of the first node Q is at a low level. The transistors M17 and M18 are turned off by the low level of the first node Q.

[0100] When the reset signal RST and the second input signal CR(N+2) are both at low level, transistors M14, M15 and M16 are turned off. Since the potential of the first node Q remains at a low level at this time, transistors M17 and M18 are turned off, and the potential of the second node QB remains at a high level.

[0101] When the reset signal RST is at a low level and the first input signal CR(N-2) is at a high level, the transistors M7 and M8 are turned on. The voltage VDD1 charges the first node Q through the transistors M7 and M8, the potential of the first node Q is at a high level, and the transistors M17 and M18 are turned on. Since the reset signal RST and the second input signal CR(N+2) are both at a low level, the transistors M14, M15, and M16 are turned off. At this time, the potential of the second node QB gradually decreases until the potential of the second node QB is pulled down to a low level.

[0102] When the potential of the first node Q becomes low again, the second input signal CR(N+2) is high, transistors M14 and M16 are turned on, transistors M17 and M18 are turned off, and the potential of the second node QB is high.

[0103] exist Figure 2B In the shift register 200b shown, when the reset signal RST is at a high level, the second input signal CR(N+2) is at a low level. Under the control of the high level of the reset signal RST, the transistor M15 is turned on. The transistor M14 is turned off by the second input signal CR(N+2). The voltage VDD2 is applied to the control electrode of the transistor M16 through the transistor M15, and the transistor M16 is turned on. The voltage VDD2 charges the capacitor C7 and the second node QB through the transistor M16.

[0104] When the reset signal RST is at a high level, the selection control signal OE and the first input signal CR(N-2) are at a low level. The transistors M1, M2, M7 and M8 are turned off. At this time, the potential of the first node Q is at a low level. The transistors M17 and M18 are turned off by the low level of the first node Q.

[0105] When the reset signal RST and the second input signal CR(N+2) are both at low level, transistors M14, M15 and M16 are turned off. Since the potential of the first node Q is kept at low level at this time, transistors M17 and M18 are turned off. Capacitor C7 keeps the potential of the second node QB at high level.

[0106] When the reset signal RST is at a low level and the first input signal CR(N-2) is at a high level, the transistor M7 and the transistor M8 are turned on. The voltage VDD1 charges the first node Q through the transistor M7 and the transistor M8, and the potential of the first node Q is at a high level, and the transistor M17 and the transistor M18 are turned on. Since the reset signal RST and the second input signal CR(N+2) are both at a low level, the transistor M14, the transistor M15 and the transistor M16 are turned off. At this time, the voltage of the capacitor C7 is released through the transistor M17 and the transistor M18, and the potential of the second node QB gradually decreases until the potential of the second node QB is pulled down to a low level.

[0107] When the potential of the first node Q becomes low again, the second input signal CR(N+2) is high, transistors M14 and M16 are turned on, transistors M17 and M18 are turned off, and the potential of the second node QB is high.

[0108] Figure 2C The shift register 200c shown is Figure 2B The working principle of the shift register 200 b shown is similar and will not be described again for the sake of simplicity.

[0109] In one example, the control electrodes of transistors M14 and M15 are electrically connected to the power supply VDD2, the first electrode of transistor M14 is electrically connected to the power supply VDD2, the second electrode of transistor M14 is electrically connected to the first electrode of transistor M15, the second electrode of transistor M15 is electrically connected to the control electrode of transistor M16, the first electrode of transistor M16 is electrically connected to the power supply VDD2, and the second electrode of transistor M16 is electrically connected to the second node QB. The control electrodes of transistors M17 and M18 are electrically connected to the first node Q, the first electrode of transistor M17 is electrically connected to the control electrode of transistor M16, and the second electrode of transistor M17 is electrically connected to the power supply VGL3. The first electrode of transistor M18 is electrically connected to the second node QB, and the second electrode of transistor M18 is electrically connected to the power supply VGL1.

[0110] In the shift register of the example, the power supply VDD2 provides a voltage of high level. Under the control of the voltage VDD2 from the power supply VDD2, the transistor M14 and the transistor M15 are turned on, and the voltage VDD2 is applied to the control electrode of the transistor M16 through the transistor M14 and the transistor M15, so that the transistor M16 is turned on. In the case where the input signal CR(N-2) provided by the input terminal CR(N-2) is high level, the high level is applied to the first node Q. Under the control of the high level of the first node Q, the transistor M17 and the transistor M18 are turned on. The voltage VDD2 is applied to the second node QB through the transistor M16, and the second node QB is connected to the power supply VGL1. Since the power supply VGL1 provides a voltage of low level and the potential of the second node QB is high level, a path is formed between the high level and the low level to generate a large current. This will cause the transistor in the Darlington inverter circuit to burn out, thereby affecting the stability of the shift register 100.

[0111] Since the transistor M14 and the transistor M15 in the example shift register are always in the on state, when the transistor M17 is turned on, a path is formed between the high level and the low level. Based on the problems existing in the example shift register, the shift register provided by the utility model controls the on and off of the transistor M14 and the transistor M15 based on the second input signal INPUT2 and the reset signal RST, thereby avoiding the formation of a DC path between the two power supplies providing the high level and the low level, thereby avoiding leakage in the shift register provided by the utility model, and improving the stability of the shift register.

[0112] Figure 4A is a schematic diagram of voltage and current in an example shift register. Figure 4B It is a schematic diagram of voltage and current in a shift register according to an embodiment of the utility model.

[0113] Figure 4A Figure (a) and Figure 4B Figure (a) shows the voltage change of the second node QB, Figure 4A Figure (b) and Figure 4B Figure (b) shows the voltage change of the first node Q point. Figure 4A Figure (c) and Figure 4B Figure (c) in FIG. 1 shows the current change at the source of the transistor M17, that is, the current change from the power supply VDD2 to the power supply VGL3. Figure 4A Figure (d) and Figure 4B Figure (d) in FIG. 1 shows the current change at the source of the transistor M18, that is, the current change from the power supply VDD2 to the power supply VGL1.

[0114] like Figure 4AAs shown, when the potential of the first node Q is at a high level, the maximum value of the transient current of the current flowing from the power supply VDD2 to the power supply VGL3 is 80uA, and the maximum value of the transient current flowing from the power supply VDD2 to the power supply VGL1 is 37uA.

[0115] like Figure 4B As shown, when the potential of the first node Q is at a high level, the maximum value of the transient current from the power supply VDD2 to the power supply VGL3 is 50uA, and the maximum value of the transient current from the power supply VDD2 to the power supply VGL1 is 16uA. Figure 4A compared to, Figure 4B The instantaneous current maximum value in the shift register shown is reduced.

[0116] In shift register 200a, shift register 200b and shift register 200c, when the potential of the first node Q is at a high level, large current will not exist in shift register 200a, shift register 200b and shift register 200c for a long time, reducing the risk of transistors in shift register 200a, shift register 200b and shift register 200c being burned.

[0117] Figure 5 It is a schematic diagram of the structure of a driving circuit according to an embodiment of the utility model.

[0118] like Figure 5 As shown, the driving circuit 500 includes N cascaded shift registers, where N is a positive integer greater than 1. The N shift registers include a shift register ST1, a shift register ST2, a shift register ST3, . . . , a shift register STN.

[0119] In the embodiment of the utility model, the shift register can be any one of the shift register 100, the shift register 200a, the shift register 200b and the shift register 200c mentioned above. For example, the N shift registers are all the shift register 200a. For example, the N shift registers are all the shift register 200b. No further details will be given here.

[0120] In an embodiment of the utility model, in the cascaded N shift registers, the first input terminal INPUT1 of the n-th shift register is electrically connected to the shift signal output terminal CR(N-2) of the n-2-th shift register, and the second input terminal INPUT of the n-th shift register is electrically connected to the shift signal output terminal CR(N+2) of the n+2-th shift register, where n is a positive integer less than N.

[0121] For example, the first input signal terminal INPUT1 of the third-stage shift register ST3 is electrically connected to the shift signal output terminal CR1 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the third-stage shift register ST2 is electrically connected to the shift signal output terminal CR5 of the fifth-stage shift register.

[0122] In the embodiment of the utility model, the first input signal terminal INPUT1 of the first stage shift register ST1 is electrically connected to the scan trigger signal terminal STV, and the second input signal terminal INPUT2 of the Nth stage shift register STN is electrically connected to the anti-static terminal ESD.

[0123] In the embodiment of the utility model, the reset terminal RST of the cascaded N shift registers is electrically connected to the reset terminal rst, and the selection control signal terminal OE is electrically connected to the selection control signal terminal oe. The clock terminal CLKD1 is electrically connected to the clock terminal clkd, and the clock terminal CLKA is electrically connected to the clock terminal clka. The clock terminal CLK1 is electrically connected to the clock signal terminal clk1, the clock terminal CLK2 is electrically connected to the clock signal terminal clk2, the clock terminal CLK3 is electrically connected to the clock signal terminal clk3, and the clock terminal CLK4 is electrically connected to the clock signal terminal clk4.

[0124] Figure 6 It is a schematic structural diagram of a display device according to an embodiment of the utility model.

[0125] As shown in FIG. 12 , a display device 600 may include a display panel 610 and a driving circuit 620 .

[0126] In the embodiment of the present invention, the driving circuit 610 may be the driving circuit 500 described above, which will not be described in detail herein.

[0127] In the embodiment of the present invention, the display panel 610 includes a plurality of sub-pixel units Pixel arranged in an array, and the driving circuit 610 is used to drive the sub-pixel units Pixel.

[0128] It should be noted that the number of sub-pixel units included in the display panel 610 is only for illustrative purposes, and the present invention does not limit the number of sub-pixel units.

[0129] Figure 7 It is a flow chart of a driving method according to an embodiment of the utility model.

[0130] like Figure 7 As shown, the driving method may include operations S710 to S730.

[0131] In the embodiment of the present invention, the driving method can be applied to the shift register 100, the shift register 200a, the shift register 200b and the shift register 200c described above.

[0132] In operation S710, a potential of a first node is controlled by an input circuit under the control of a first input signal from a first input terminal and a second input signal from a second input terminal.

[0133] In operation S720, the potential of the second node is controlled by the control circuit under the control of the potential of the first node, the second input signal, and the reset signal from the reset terminal.

[0134] In operation S730, a scan signal is output through an output circuit under the control of the potentials of the first node and the second node.

[0135] In the embodiment of the present invention, operations S710 to S730 are similar to the operations performed by the shift register 200a, the shift register 200b, and the shift register 200c described above, and are not described in detail herein.

[0136] Figure 8 It is a schematic structural diagram of a display substrate according to an embodiment of the utility model.

[0137] like Figure 8 , the display substrate 800 includes a compensation circuit 810 and a shift register 820 .

[0138] In the embodiment of the present invention, the compensation circuit 810 is configured to compensate the input signal or the output signal of the shift register 810 to obtain a plurality of scanning signals, so as to control the relative difference between the falling times of the plurality of scanning signals.

[0139] Figure 8 The number of input signals received and output signals output by the shift register 810 shown is for illustration only.

[0140] In an embodiment of the utility model, the shift register 820 may include: an input circuit, configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit, configured to control the potential of a second node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; and an output circuit, configured to output a scan signal under the control of the potentials of the first node and the second node.

[0141] In the embodiment of the present invention, the shift register 820 may be the shift register 100, the shift register 200a, the shift register 200b and the shift register 200c described above, which will not be described in detail for the sake of brevity.

[0142] In an embodiment of the utility model, the compensation circuit 810 is used to compensate the input signal or output signal of the shift register 810, so as to control the relative difference between the fall times of multiple input signals, or control the relative difference between the fall times of multiple output signals, thereby reducing the relative difference between the fall times of multiple scanning signals driving the pixel circuit.

[0143] In an embodiment of the utility model, the compensation circuit 810 compensates the input signal of the shift register 820 to obtain multiple scanning signals which are configured as follows: compensating multiple clock signals from multiple clock terminals to control the relative difference between the fall times of the multiple clock signals to obtain multiple compensated clock signals, so that the shift register 820 outputs multiple scanning signals based on the multiple compensated clock signals.

[0144] For example, in the shift register 200a, the transistors M21, M23, M25, M27, and M29 share the first node Q. The capacitors C2, C3, C4, C5, and C6 have a bootstrap effect, and can enhance the level of the first node Q. However, since the clock signals CLK1, CLK2, CLK3, and CLK4 are transmitted in sequence, the bootstrap degrees of the first node Q are different, so the falling times TF of the scanning signals OUT(N), OUT(N+1), OUT(N+2), and OUT(N+3) are also different.

[0145] Since the falling time TF of the scanning signal OUT(N), the scanning signal OUT(N+1), the scanning signal OUT(N+2) and the scanning signal OUT(N+3) are different, when the same data voltage is written to the four rows of sub-pixels in the pixel circuit respectively under the driving of the scanning signal OUT(N), the scanning signal OUT(N+1), the scanning signal OUT(N+2) and the scanning signal OUT(N+3), the current of the scanning signal is different, which will make the brightness of the sub-pixels in different rows different. In this case, bright lines and dark lines will appear on the display screen.

[0146] To avoid this phenomenon, the compensation circuit 810 can compensate the clock signals CLK1, CLK2, CLK3, CLK4 of the clock terminals CLK1, CLK2, CLK3, CLK4 electrically connected to the shift register 200a to increase the fall time TF of the clock signals CLK1, CLK2, CLK3, CLK4. Driven by the compensated clock signal, the fall time of the four scanning signals can be increased, thereby reducing the relative difference between the fall times of the four scanning signals. The relative difference is the ratio between the difference between the fall times of the four scanning signals and the fall time of any scanning signal.

[0147] For example, before the clock signal is compensated by the compensation circuit 810, the falling time of the clock signal CLK1 is 400ns and the falling time of the clock signal CLK2 is 440ns. At this time, the difference between the falling time of the clock signal CLK1 and the falling time of the clock signal CLK2 is 40ns, and the relative difference is 40 / 400=10%.

[0148] After the clock signal is compensated by the compensation circuit 810, the falling time of the clock signal CLK1 increases to 450ns and the falling time of the clock signal CLK2 increases to 480ns. At this time, the difference between the falling time of the clock signal CLK1 and the falling time of the clock signal CLK2 is 30ns, and the relative difference is 30 / 450=6.7%.

[0149] In the embodiment of the utility model, the compensation circuit 810 can be integrated on the driving chip together with the shift register 820. The compensation circuit 810 can also be externally connected to the driving chip, and the shift register 820 is integrated on the driving chip.

[0150] In an embodiment of the utility model, by compensating the clock signal through the compensation circuit 810 and increasing the difference between the fall times of multiple clock signals, the relative difference between the fall times of multiple scanning signals can be reduced, thereby reducing the difference between the multiple scanning signals and improving the brightness difference between different sub-pixel rows in the pixel circuit.

[0151] Fig. 9 It is a structural schematic diagram of a display substrate according to another embodiment of the utility model.

[0152] like Fig. 9 , the display substrate 900 includes a compensation circuit 910 and a shift register 920 .

[0153] In the embodiment of the present invention, when the shift register 920 includes multiple output terminals, the compensation circuit 910 includes multiple compensation sub-circuits, and the number of the multiple compensation sub-circuits is the same as the number of the multiple clock terminals.

[0154] For example, the shift register 200a described above includes four output terminals, so the compensation circuit 910 is electrically connected to four clock terminals, and the compensation circuit 910 includes four compensation sub-circuits.

[0155] In the embodiment of the present invention, each compensation subcircuit in the plurality of compensation subcircuits includes a compensation resistor and a compensation capacitor. For example, the compensation subcircuit 911 includes a compensation resistor R1 and a compensation capacitor C1, and the compensation subcircuit 912 includes a compensation resistor R2 and a compensation capacitor C2.

[0156] In the embodiment of the utility model, the first end of the compensation resistor R1 is electrically connected to the clock terminal CLK1, and the second end of the compensation resistor R1 is electrically connected to the shift register 920. The first end of the compensation capacitor C1 is electrically connected to the clock terminal CLK1, and the second end of the compensation capacitor C1 is electrically connected to the power supply VDD.

[0157] A first end of the compensation resistor R2 is electrically connected to the clock terminal CLK2, and a second end of the compensation resistor R2 is electrically connected to the shift register 920. A first end of the compensation capacitor C2 is electrically connected to the clock terminal CLK2, and a second end of the compensation capacitor C2 is electrically connected to the power supply VDD.

[0158] The power sources electrically connected to the compensation capacitors C1 and C2 may be the same or different.

[0159] In the embodiment of the utility model, the clock signal is externally compensated by the compensation circuit 910, so that the fall time of all clock signals is increased, thereby increasing the fall time of the output scanning signal. The resistance of the compensation resistor and the capacitance of the compensation capacitor in the compensation subcircuit can be determined by formula (1):

[0160]

[0161] τ represents the difference between the falling times of the scanning signals, in seconds. R is the resistance of the compensation resistor, in ohms. C is the capacitance of the compensation capacitor, in Ω. V0 is the initial voltage value of the compensation capacitor, and V1 is the voltage after the compensation capacitor is charged or released. V t is the voltage on the compensation capacitor at time t.

[0162] Formula (1) can be used to determine the values ​​of the resistance of the corresponding compensation resistor and the capacitance of the corresponding compensation capacitor when the difference in the falling time of the scanning signal is τ. The resistances of the compensation resistors included in each of the multiple compensation subcircuits can be equal or unequal. The capacitances of the compensation capacitors included in each of the multiple compensation subcircuits can be equal or unequal.

[0163] In the embodiment of the utility model, a compensation resistor and a compensation capacitor may be arranged on the printed circuit board, so as to perform external compensation on the clock signal.

[0164] Fig. 10A The diagram is a schematic diagram of the brightness of a display panel driven by a shift register before compensation. Fig. 10B It is a schematic diagram of the brightness of a display panel driven by a shift register after compensation according to an embodiment of the utility model. Fig. 10A and Fig. 10BThe luminance of the sub-pixels in the first row to the twelfth row of the pixel circuit is shown. The solid line shows the luminance of the sub-pixels obtained by actual measurement, and the dotted line shows the luminance of the sub-pixels obtained by simulation. For example, Fig. 10A The brightness of the display panel driven by the shift register 920 alone is shown. Fig. 10B The brightness of the display panel driven by the compensation circuit 910 and the shift register 920 is shown.

[0165] Fig. 10A Figure (a) and Fig. 10B Figure (a) shows the brightness of the sub-pixel at 32 gray levels. Fig. 10A Figure (b) and Fig. 10B Figure (b) in FIG. 1 shows the brightness of a sub-pixel at gray level 63. FIG. Fig. 10A Figure (c) and Fig. 10B Figure (c) in FIG. 1 shows the brightness of the sub-pixel at 128 gray levels. Fig. 10A Figure (d) and Fig. 10B Figure (d) in FIG. 1 shows the brightness of a sub-pixel at 255 gray levels.

[0166] like Fig. 10A As shown, the measured results are similar to the simulation structure. The brightness of the 4th row sub-pixels, the 8th row sub-pixels and the 12th row sub-pixels is larger than the brightness of the adjacent row sub-pixels. It can be seen that the difference between the fall time TF of the scanning signal driving the 4th row sub-pixels and the fall time TF of the scanning signal driving the adjacent row sub-pixels is large. The difference between the fall time TF of the scanning signal driving the 8th row sub-pixels and the fall time TF of the scanning signal driving the adjacent row sub-pixels is large. The difference between the fall time TF of the scanning signal driving the 12th row sub-pixels and the fall time TF of the scanning signal driving the adjacent row sub-pixels is large.

[0167] like Fig. 10B As shown, the measured results are similar to the simulation structure. The brightness difference between the first row of sub-pixels to the twelfth row of sub-pixels is small. It can be seen that the difference between the falling time of the scanning signal driving the first row of sub-pixels to the twelfth row of sub-pixels is small.

[0168] Fig.11A is a capacitance matching diagram of the capacitor C2 according to an embodiment of the utility model. Fig. 11B is a schematic diagram of capacitance matching of capacitors C3 to C6 according to an embodiment of the utility model.

[0169] For example, Fig.11A FIG. 1 is a schematic diagram showing the change between the falling time of the scanning signal output by the shift register 920 and the capacitance of the capacitor C2 . Fig. 11BA schematic diagram showing the change between the falling time of the scanning signal output by the shift register 920 and the capacitance of the capacitors C3 to C6 is shown.

[0170] In the embodiment of the utility model, capacitor C2 is electrically connected to the shift signal output section CR(N), and capacitor C2 is a cascade capacitor. Capacitors C3 to C6 are electrically connected to the output terminal OUT(N) to the output terminal OUT(N+3), respectively, and capacitors C3 to C6 are driving capacitors. By matching the capacitors C2 to C6, the difference between the fall times of multiple output signals can be reduced.

[0171] In the embodiment of the utility model, the number of driving capacitors is the same as the number of clock terminals. By setting the capacitance of capacitors C2 to C6, the influence of capacitive coupling on the clock signal can be reduced, thereby reducing the difference between the falling times of the scanning signals.

[0172] In an embodiment of the present invention, the capacitance of one of the plurality of driving capacitors is smaller than the capacitance of the remaining driving capacitors in the plurality of driving capacitors. Fig. 10A , the difference between the falling time of the scanning signal for driving the 4th row of sub-pixels and the falling time of other scanning signals is large. Therefore, the capacitance of the driving capacitor electrically connected to the output end of the scanning signal for driving the 4th row of sub-pixels is smaller than that of other driving capacitors.

[0173] Fig.11A The figure shows the change of the fall time of the four scanning signals when the capacitors C3 to C6 are fixed to 0 and only the capacitance of the capacitor C2 is changed. When the capacitor C2 is less than 4pF, the difference between the fall times of the four scanning signals decreases as the capacitance of the capacitor C2 increases. When the capacitor C2 is greater than 4pF, the difference between the fall times of the four scanning signals increases as the capacitance C2 increases. When the capacitor C2 is equal to 4pF, the difference in the fall time of the four scanning signals is the smallest.

[0174] Fig. 11B The middle figure (a) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C4, C5 and C6 are fixed at 0, and only the capacitance of C3 is changed. Fig. 11B The middle figure (b) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C3, C5 and C6 are fixed at 0, and only the capacitance of capacitor C4 is changed. Fig. 11BThe middle figure (c) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C3, C4 and C6 are fixed at 0, and only the capacitance of capacitor C5 is changed. Fig. 11B The middle figure (d) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitances of capacitors C3, C4 and C5 are fixed at 0, and only the capacitance of capacitor C6 is changed.

[0175] exist Fig. 11B In Figure (a), when the capacitance C3 < 0.5 pF, the difference between the fall times of the four scanning signals decreases as the capacitance of the capacitor C3 increases. When the capacitance C3 > 0.5 pF, the difference between the fall times of the four scanning signals increases as the capacitance of the capacitor C3 increases. When the capacitance C3 = 0.5 pF, the difference in the fall times of the four scanning signals is the smallest.

[0176] In Figure (b) of Figure ¨B, when the capacitance C4 is less than 0.5 pF, the difference between the falling times of the four scanning signals decreases as the capacitance of the capacitor C3 increases. When the capacitance C4 is greater than 0.5 pF, the difference between the falling times of the four scanning signals increases as the capacitance of the capacitor C4 increases. When the capacitance C4 is equal to 0.5 pF, the difference in the falling times of the four scanning signals is the smallest.

[0177] exist Fig. 11B In Figure (c), when the capacitance C5 < lpF, the difference between the falling times of the four scanning signals decreases as the capacitance of the capacitor C3 increases. When the capacitance C5> lpF, the difference between the falling times of the four scanning signals increases as the capacitance of the capacitor C5 increases. When the capacitance C5 = lpF, the difference in the falling times of the four scanning signals is the smallest.

[0178] exist Fig. 11B In FIG. 5( d ), when the capacitance C6>0 pF, the difference between the falling times of the four scanning signals increases as the capacitance of the capacitor C6 increases. When the capacitance C6=0 pF, the difference between the falling times of the four scanning signals is the smallest.

[0179] In the embodiment of the utility model, according to the difference in brightness of the sub-pixels in the first row to the fourth row, it can be determined that the difference between the falling times of the scanning signals used to drive the sub-pixels in the first row to the fourth row is small, and the difference between the falling time of the scanning signal used to drive the sub-pixels in the fourth row and the falling time of the scanning signals of the sub-pixels in the first three rows is large, so the capacitance of the capacitor C3, the capacitor C4 and the capacitor C5 can be increased, so that the coupling capacity of the capacitor C3, the capacitor C4 and the capacitor C5 is increased, and the falling time TF of the scanning signal becomes longer accordingly. At the same time, the capacitance of the capacitor C6 is reduced, the coupling capacity of the capacitor C6 is reduced, and the falling time TF of the scanning signal becomes shorter accordingly.

[0180] Therefore, after matching, the capacitance C2=4pF, after matching, the capacitance C3=0.5pF, after matching, the capacitance C4=0.5pF, after matching, the capacitance C5=1pF, and after matching, the capacitance C6=0pF. The capacitance after matching is C2>C5>C3=C4>C6.

[0181] Fig. 12A It is a simulation schematic diagram of the output signal before capacitor matching according to an embodiment of the utility model. Fig. 12B It is a simulation schematic diagram of the output signal after capacitor matching according to an embodiment of the utility model.

[0182] Fig. 12A and Fig. 12B The voltage changes of the first node Q, the scan signal OUT(1), the scan signal OUT(2), the scan signal OUT(3) and the scan signal OUT(4) in the shift register are shown. Fig. 12A and Fig. 12B The red waveform in the middle shows the voltage change of the first node Q. Fig. 12A and Fig. 12B The dark blue waveform is the voltage change of the scan signal OUT(1). Fig. 12A and Fig. 12B The green waveform in the middle is the voltage change of the scan signal OUT(2). Fig. 12A and Fig. 12B The light blue waveform in the middle is the voltage change of the scan signal OUT(3). Fig. 12A and Fig. 12B The purple waveform in the middle is the voltage change of the scanning signal OUT(4).

[0183] The bootstrap degree of the first node Q when each scan signal is output is determined according to the voltage of the first node Q when the scan signals OUT(1), OUT(2), OUT(3) and OUT(4) are at high level.

[0184] like Fig. 12AAs shown, the bootstrap degree of the first node Q corresponding to the scan signal OUT(1), the scan signal OUT(2), the scan signal OUT(3) and the scan signal OUT(4) is different. The bootstrap degree of the first node Q corresponding to the scan signal OUT(4) is smaller than the bootstrap degree of the first node Q corresponding to the scan signal OUT(1), the scan signal OUT(2) and the scan signal OUT(3).

[0185] The falling times of the scanning signals OUT(1), OUT(2), OUT(3) and OUT(4) are also different. The falling times of the scanning signals OUT(1), OUT(2), OUT(3) and OUT(4) are 428.53 ns, 432.99 ns, 439.13 ns and 480.67 ns respectively, and the maximum difference ΔTF between the falling times of the four scanning signals is 480.67-428.53=52.14 ns.

[0186] like Fig. 12B As shown, the difference between the voltages of the first node Q corresponding to the scan signal OUT(1), the scan signal OUT(2), the scan signal OUT(3) and the scan signal OUT(4) is reduced, and the difference in the bootstrap degree of the first node Q corresponding to the scan signal OUT(1), the scan signal OUT(2), the scan signal OUT(3) and the scan signal OUT(4) is small. The falling times of the scan signal OUT(1), the scan signal OUT(2), the scan signal OUT(3) and the scan signal OUT(4) are 427.4ns, 430.62ns, 431.29ns and 457.19ns respectively, and the maximum difference ΔTF between the falling times of the four scan signals is 457.19-427.4=29.79ns. After the capacitor matching, the difference in the falling time is reduced from 52.14ns to 22.35ns, and the difference is reduced by 43%.

[0187] In one embodiment, the compensation circuit includes a plurality of output signal lines, which are electrically connected to a plurality of output terminals respectively, and are configured to compensate the output signal of the shift register to obtain a plurality of scanning signals and output the plurality of scanning signals.

[0188] In the embodiment of the present utility model, reference Fig. 10A , the difference between the falling time of the scanning signal for driving the 4th row of sub-pixels and the falling time of other scanning signals is large. Therefore, the length of the output signal line that outputs the scanning signal for driving the 4th row of sub-pixels is less than the length of the remaining output signal lines among the multiple output signal lines, and the width of the output signal line that outputs the scanning signal for driving the 4th row of sub-pixels is greater than the width of the length of the remaining output signal lines among the multiple output signal lines.

[0189] In the embodiment of the utility model, the length and width of the output signal line can be adjusted on the periphery line glass (PLG) of the glass substrate to achieve RC compensation of the PLG line before entering the GOA area. Since the output signal lines are usually arranged from the outside to the inside, the lengths of the output signal lines are different. The resistance of the output signal line can be determined by formula (2):

[0190]

[0191] R represents the resistance of the output signal line, L represents the length of the output signal line, S represents the width of the output signal line, R s The square resistance of the output signal lines is the same. When the width and length of the output signal lines are different, the resistance of each output signal line is different.

[0192] The resistance of the output signal line has a great influence on the AC signal, and the resistance of the output signal line will affect the fall time and signal voltage of the scanning signal. When the shift register is electrically connected to multiple output signal lines, since the shift register is more sensitive to the fall time of the scanning signal, the multiple output signal lines can be designed with unequal widths in the display screen.

[0193] For example, for the output signal line arranged on the outside, since the length L of the output signal line is longer, the width S of the output signal line is increased, thereby reducing the resistance of the output signal line. For the output signal line arranged on the inside, since the length L of the output signal line is shorter, the width S of the output signal line is reduced, thereby increasing the resistance of the output signal line.

[0194] Through software simulation, the resistance of the output signal line is extracted, and the length and width of all output signal lines are fine-tuned.

[0195] In an embodiment of the utility model, the compensation circuit includes a plurality of clock signal lines. The plurality of clock signal lines are electrically connected to a plurality of clock terminals respectively, and are used to input a plurality of clock signals into a shift register. The plurality of clock signal lines are configured to compensate the plurality of clock signals to obtain a plurality of compensated clock signals.

[0196] In the embodiment of the present utility model, reference Fig. 10A , the difference between the falling time of the scanning signal for driving the 4th row of sub-pixels and the falling time of other scanning signals is large. Therefore, the length of the clock signal line electrically connected to the clock terminal CLK4 described above is less than the length of the remaining clock signal lines among the multiple clock signal lines, and the width of the clock signal line electrically connected to the clock terminal CLK4 described above is greater than the width of the length of the remaining clock signal lines among the multiple clock signal lines.

[0197] The resistance of the plurality of clock signal lines is extracted through software simulation, and the lengths and widths of all the plurality of clock signal lines are fine-tuned to adjust the resistance of the plurality of clock signal lines.

[0198] Fig.13 4 is a compensation diagram of a signal line according to an embodiment of the utility model.

[0199] like Fig.13 As shown in Figure (a), Figure (a) shows the original state of the signal line. When the resistance of the signal line needs to be increased, the length of the signal line can be increased by the routing method shown in Figure (b), thereby increasing the resistance of the signal line. When the resistance of the signal line and the capacitor need to be increased at the same time, a metal layer can be added to the upper or lower layer of the signal line to compensate for the capacitance, as shown in Figure (c).

[0200] In PLG, RC compensation can be performed on the clock signal on the upper layer of the DC signal (power supply such as VGL / VDD), because the DC signal does not generate jumps and is not easily affected by capacitance and generates noise.

[0201] Fig.14A It is a schematic structural diagram of a display substrate according to an embodiment of the utility model. Fig. 14B It is a structural schematic diagram of a display substrate according to another embodiment of the utility model.

[0202] Fig.14A and Fig. 14B The layout of the transistor M23 , the transistor M25 , the transistor M27 , the transistor M29 , the output signal line L1 , the output signal line L2 , the output signal line L3 , and the output signal line L4 in the display substrate is shown.

[0203] The output signal line L1 is electrically connected to the transistor M23 , the output signal line L2 is electrically connected to the transistor M25 , the output signal line L3 is electrically connected to the transistor M27 , and the output signal line L4 is electrically connected to the transistor M29 .

[0204] like Fig.14A As shown, the positions of transistor M23, transistor M25, transistor M27 and transistor M29 are different, transistor M23 and transistor M29 are close to the output end, and transistor M25 and transistor M27 are far away from the output end. In order to ensure that the resistances of output signal line L1, output signal line L2, output signal line L3 and output signal line L4 are close, the length of output signal line L2 and output signal line L3 can be padded so that the lengths of output signal line L1, output signal line L2, output signal line L3 and output signal line L4 are equal.

[0205] The output signal lines L2 and L3 can be bent in the blank area of ​​the PLG to increase the length of the output signal lines L2 and L3 to avoid the influence of high-frequency signals. When the space of the PLG is limited, the lines can also be routed on the upper layer of the DC signal line (the signal line connected to the power supply).

[0206] In the shift register, since the falling time of the scanning signal OUT(4) is relatively long, the resistance and capacitance to be compensated can be calculated according to formula (1) and the falling time difference, so as to fine-tune the output signal line L4 for RC compensation. Fig.13 The wiring method shown.

[0207] The capacitors and resistors for compensating the output signal lines L1, L2, L3 and L4 may be different, and the routing lengths of the output signal lines L1, L2, L3 and L4 on the layout may also be different.

[0208] Since there are RC loads on the output signal lines L1, L2, L3 and L4, when providing scanning signals for a display screen with a larger size, there will be differences between the scanning signals provided to the sub-pixels at the far and near ends.

[0209] For example, the driving circuit composed of the shift register can be distributed on the left and right sides of the pixel array. The sub-pixels located on the two sides of each row of sub-pixels in the pixel array are closer to the corresponding shift register, so the sub-pixels located on the two sides are considered to be near-end pixels. The sub-pixels located in the middle of each row of sub-pixels are far away from the corresponding shift register, so the sub-pixels located in the middle are considered to be far-end pixels.

[0210] pass Fig. 14B The wiring arrangement shown changes the resistance of output signal line L1, output signal line L2, output signal line L3 and output signal line L4 to compensate for near and far terminal pixels.

[0211] As shown in FIG14 , the resistance of the output signal lines L1, L2, L3 and L4 is increased by increasing the length of the output signal lines L1, L2, L3 and L4. When the resistance of the output signal lines L1, L2, L3 and L4 is increased, the relative difference between the output signal lines L1, L2, L3 and L4 can be reduced, thereby reducing the difference in the scanning signals received by the near and far terminal pixels.

[0212] For example, capacitance compensation can also be performed through overlapping area. When there is an overlapping area between the output signal line and the metal layer, overlapping capacitance can be generated. When a hole is dug in the lower layer of the output signal line, the overlapping capacitance can be reduced.

[0213] FIG. 15A to FIG. 15D for Fig.14A The layered layout of the display substrate is shown.

[0214] Fig.15A Shows Fig.14A The shield layer of the display substrate is shown. Fig. 15B Shows Fig.14A The active layer of the display substrate is shown. Fig. 15C Shows Fig.14A The gate insulator (GateInsulator, G1) layer of the display substrate shown, Fig.15D Shows Fig.14A The gate layer of the display substrate is shown.

[0215] FIG. 16A to FIG. 16D for Fig. 14B The layered layout of the display substrate is shown.

[0216] Fig.16A Shows Fig. 14B The shield layer of the display substrate is shown. Fig. 16B Shows Fig. 14B The active layer of the display substrate is shown. Fig. 16C Shows Fig. 14B The gate insulator (GI) layer of the display substrate shown in FIG. Fig.16D Shows Fig. 14B The gate layer of the display substrate is shown.

[0217] Fig.17 FIG. 1 is a schematic diagram of the structure of a display device according to another embodiment of the utility model.

[0218] like Fig.17 As shown, the display device 1700 includes a display substrate 1710 .

[0219] In the embodiment of the present invention, the display substrate 1710 may be the display substrate 800 or the display substrate 900 described above, which will not be described in detail for the sake of brevity.

[0220] Fig.18 is a flow chart of a driving method according to another embodiment of the utility model.

[0221] like Fig.18 As shown, the driving method may include operation S1810.

[0222] In the embodiment of the present invention, the driving method can be applied to the display substrate 800 and the display substrate 900 described above.

[0223] In operation S1810, an input signal or an output signal of a shift register is compensated by a compensation circuit to obtain a plurality of scan signals so as to control relative differences between falling times of the plurality of scan signals.

[0224] In the embodiment of the present invention, operation S18710 is similar to the operation performed by the display substrate 800 and the display substrate 900 described above, and will not be described in detail here.

[0225] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the utility model. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0226] It will be understood by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0227] The embodiments of the present invention are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A shift register, characterized in that: include: an input circuit configured to control the potential of the first node under the control of a first input signal from the first input terminal and a second input signal from the second input terminal; a control circuit configured to control the potential of the second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; as well as The output circuit is configured to output a scan signal under the control of the potentials of the first node and the second node.

2. The shift register according to claim 1, characterized in that: The control circuit controls the potential of the second node under the control of the potential of the first node, the second input signal and the reset signal from the reset terminal, and is configured as follows: Under the control of the first level of the first node, the reset signal and the second input signal, charging the second node by the first voltage of the first power supply; as well as Under the control of the second level of the first node, the potential of the second node is pulled down.

3. The shift register according to claim 1 or 2, characterized in that: The control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; Wherein, the control electrode of the first transistor is electrically connected to the second input terminal, the first electrode of the first transistor is electrically connected to a first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; The control electrode of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to the first power supply, and the second electrode of the second transistor is electrically connected to the control electrode of the third transistor; A first electrode of the third transistor is electrically connected to a first power source, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to a second power source; and A control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the second node, and a second electrode of the fifth transistor is electrically connected to a third power source.

4. The shift register according to claim 3, characterized in that: The control circuit also includes a first capacitor; The first end of the first capacitor is electrically connected to the first power source, and the second end of the first capacitor is electrically connected to the control electrode of the third transistor.

5. The shift register according to claim 3, characterized in that: The control circuit also includes a first capacitor; The first end of the first capacitor is electrically connected to the control electrode of the third transistor, and the second end of the first capacitor is electrically connected to the third power supply.

6. The shift register according to claim 1, characterized in that: The output circuit comprises: The shift signal output terminal is configured to output a shift signal.

7. The shift register according to claim 1, characterized in that: The output circuit includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units.

8. A driving circuit, characterized in that: The invention comprises a plurality of shift registers as claimed in any one of claims 1 to 7 connected in cascade.

9. The driving circuit according to claim 8, characterized in that: The first input terminal of the nth shift register is electrically connected to the shift signal output terminal of the n-2th shift register, and the second input terminal of the nth shift register is electrically connected to the shift signal output terminal of the n+2th shift register, where n is a positive integer.

10. A display device, characterized in that: include: Display panel; as well as The driving circuit according to claim 8 or 9; Wherein, the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

11. A display substrate, characterized in that: include: Shift register; as well as The compensation circuit is configured to compensate the input signal or the output signal of the shift register to obtain a plurality of scanning signals so as to control the relative difference between the falling times of the plurality of scanning signals.

12. The display substrate according to claim 11, characterized in that: The compensation circuit compensates the input signal of the shift register to obtain multiple scan signals, which are configured to: compensate multiple clock signals from multiple clock terminals to control the relative difference between the fall times of the multiple clock signals to obtain multiple compensated clock signals, so that the shift register outputs the multiple scan signals based on the multiple compensated clock signals.

13. The display substrate according to claim 12, characterized in that: The compensation circuit includes a plurality of compensation sub-circuits, and the number of the plurality of compensation sub-circuits is the same as the number of the plurality of clock terminals.

14. The display substrate according to claim 13, characterized in that: Each of the plurality of compensation subcircuits comprises a compensation resistor and a compensation capacitor; Wherein, a first end of the compensation resistor is electrically connected to a clock end, and a second end of the compensation resistor is electrically connected to the shift register; and A first terminal of the compensation capacitor is electrically connected to the clock terminal, and a second terminal of the compensation capacitor is electrically connected to a fourth power supply.

15. The display substrate according to claim 12, characterized in that: The compensation circuit comprises: A plurality of clock signal lines, configured to compensate the plurality of clock signals to obtain a plurality of compensated clock signals; Among them, the length of one clock signal line among the multiple clock signal lines is smaller than the length of the remaining clock signal lines among the multiple clock signal lines, or the width of one clock signal line among the multiple clock signal lines is larger than the width of the length of the remaining clock signal lines among the multiple clock signal lines.

16. The display substrate according to claim 12, characterized in that: The shift register comprises a plurality of driving capacitors, the number of the plurality of driving capacitors being the same as the number of the plurality of clock terminals; The capacitance of one driving capacitor among the plurality of driving capacitors is smaller than the capacitance of the remaining driving capacitors among the plurality of driving capacitors.

17. The display substrate according to claim 11 or 12, characterized in that: The compensation circuit comprises: A plurality of output signal lines, configured to compensate the output signal of the shift register to obtain the plurality of scanning signals; The length of one of the multiple output signal lines is smaller than the length of the remaining output signal lines, or the width of one of the multiple output signal lines is larger than the width of the remaining output signal lines.

18. The display substrate according to claim 11, characterized in that: The shift register comprises: an input circuit configured to control the potential of the first node under the control of a first input signal from the first input terminal and a second input signal from the second input terminal; a control circuit configured to control the potential of the second node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; and The output circuit is configured to output a scan signal under the control of the potentials of the first node and the second node.

19. A display device, characterized in that: include: A display substrate as claimed in any one of claims 11 to 18.

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