Chip packaging body, working assembly and computing equipment

Abstract

The utility model provides a chip packaging body, a working assembly and a computing device, and relates to the technical field of semiconductor chips, the chip packaging body comprises a substrate and at least one chip layer carried by the substrate, and each chip layer comprises at least one chip; at least one first test bonding pad is arranged on the upper surface of the substrate, each first test bonding pad is electrically connected with at least one chip layer through the substrate, and the chip layers electrically connected with different first test bonding pads are not completely consistent; each first test bonding pad is used for testing whether the corresponding electric connection is normal or not, so that failure analysis is carried out on at least part of the chip layer based on a test result. In the embodiment, whether the chip layer fails is determined through the test bonding pad arranged on the substrate, so that the fault position is positioned, failure analysis is carried out, the failure analysis cost can be reduced, and the failure analysis period can be shortened.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor chips, and in particular to a chip package, a working component and a computing device. Background Art

[0002] With the development of semiconductor integrated circuits, semiconductor chips have been widely used. The higher the integration of semiconductor chips, the more complex the packaging scheme, including multi-chip packaging, such as package-on-package (PoP), chip-on-wafer-on-substrate (CoWoS), etc. In addition, there are also packaging methods such as system-in-a-package (SIP).

[0003] After packaging multiple chips, if one of the chips, the connection relationship or the substrate fails, it is difficult to locate the fault point, which makes it extremely difficult to analyze the cause of the failure and greatly increases the cost and cycle of failure analysis. Summary of the invention

[0004] The embodiments of the utility model provide a chip package, a working component and a computing device to solve the problems of high cost and long cycle of failure analysis after chip packaging.

[0005] In a first aspect, an embodiment of the utility model provides a chip package, comprising: a substrate, at least one chip layer carried by the substrate, each chip layer comprising at least one chip;

[0006] At least one first test pad is disposed on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent;

[0007] Each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test result.

[0008] In one implementation, at least one second test pad is provided on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent. Each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad based on the test results.

[0009] In one implementation, the upper surface of the top chip layer is electrically connected to a connecting pad disposed on the upper surface of the substrate, and the connecting pad is electrically connected to a first test pad. The first test pad is used to test whether the electrical connection between the upper surface of the top chip layer and the connecting pad is normal, so as to perform failure analysis on the top chip layer based on the test results.

[0010] In one implementation, the chip package further includes a redistribution layer disposed between the at least one chip layer and the substrate.

[0011] In one implementation, a third test pad is provided on the upper surface of the substrate. The third test pad forms an electrical connection between the substrate and the redistribution layer. The third test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the redistribution layer based on the test results.

[0012] In one implementation, at least one chip layer includes a logic chip layer and a memory chip layer, the logic chip layer includes at least one logic processing die, and the memory chip layer includes at least one memory die.

[0013] In one implementation, the material of the test pad is nickel-gold-plated copper.

[0014] In one implementation, the shape of the test pad is any one of the following:

[0015] Round, oval, square, rectangular or hexagonal.

[0016] In a second aspect, an embodiment of the utility model provides a working component, including:

[0017] A chip package according to any embodiment of the present invention;

[0018] A printed circuit board is provided with a chip package on one side of the printed circuit board.

[0019] In one implementation, there are multiple chip packages.

[0020] In one implementation, at least some of the plurality of chip packages are connected to each other.

[0021] In a third aspect, an embodiment of the present utility model provides a computing device, including:

[0022] Working components of any embodiment of the utility model;

[0023] Power supply module.

[0024] In one implementation, there are multiple working components.

[0025] In one implementation, at least some of the plurality of working components are interconnected.

[0026] Compared with the prior art, the utility model has the following advantages:

[0027] The utility model provides a chip package, a working component and a computing device, wherein the chip package comprises a substrate, at least one chip layer carried by the substrate, and each chip layer comprises at least one chip; at least one first test pad is arranged on the upper surface of the substrate, and each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. In this embodiment, the test pads arranged on the substrate are used to determine whether the chip layer is failed, so as to locate the fault position and perform failure analysis, which can reduce the cost of failure analysis and shorten the cycle of failure analysis. The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the utility model and should not be regarded as limiting the scope of the utility model.

[0029] Figure 1 A schematic diagram of a chip package provided by an embodiment of the present invention.

[0030] Figure 2 A schematic diagram of a chip package provided by an embodiment of the present invention.

[0031] Figure 3 A schematic diagram of a chip package provided by an embodiment of the present invention.

[0032] Figure 4 A schematic diagram of a chip package provided by an embodiment of the present invention.

[0033] Figure 5 A schematic diagram of a chip package provided by an embodiment of the present invention.

[0034] Figure 6 It is a schematic diagram of an ASIC chip test according to an embodiment of the present utility model.

[0035] Figure 7FIG. 4 is a schematic diagram of an HBM chip test according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the concept or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary in nature and not restrictive.

[0037] To facilitate understanding of the technical solution of the embodiment of the utility model, the following is an explanation of the related technologies of the embodiment of the utility model. The following related technologies can be combined arbitrarily with the technical solution of the embodiment of the utility model as optional solutions, and they all belong to the protection scope of the embodiment of the utility model.

[0038] Embodiment 1

[0039] The utility model embodiment provides a chip package, Figure 1 Schematic diagram of a chip package provided by an embodiment of the present utility model. Figure 1 As shown, the chip package provided by the embodiment of the utility model includes: a substrate 110, at least one chip layer 120 carried by the substrate 110, each chip layer 120 includes at least one chip; at least one first test pad 130 is provided on the upper surface of the substrate, each first test pad 130 is electrically connected to at least one chip layer 120 through the substrate 110, and the chip layers 120 electrically connected to different first test pads 110 are not completely consistent; each first test pad 110 is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer 120 based on the test results.

[0040] The chip layer may include one or more chips, and the specific functions and specific number of the chips may be determined as needed. The chip layers electrically connected to different first test pads are not completely consistent, that is, the multiple chip layers electrically connected to two different first test pads may overlap.

[0041] For example, Figure 1 As shown, in this embodiment, the chip layer 120 includes two chips: a high bandwidth memory (HBM) chip and an application specific integrated circuit (ASIC) chip. The HBM chip and the ASIC chip, and the HBM chip, the ASIC chip and the substrate are electrically connected through a connection layer, and the connection layer can be electrically connected through a through-silicon via (TSV) technology.

[0042] Among them, the use of through-silicon via (TSV) technology can realize vertical electrical connection of multiple chips. Through-silicon via technology makes vertical conduction between chips and wafers, and realizes vertical electrical interconnection of through-silicon vias by filling conductive materials such as copper, tungsten, and polysilicon, thereby realizing 3D advanced packaging. Through advanced packaging, the integration of electronic components can be greatly improved, and the geometric size and weight of the package can be reduced. Overcome the shortcomings of the existing two-dimensional system-in-a-package (2D-System In a Package, 2D-SIP) and three-dimensional package stacking (Package on Package, POP) systems, and meet the requirements of microelectronic products for multi-function and miniaturization. In addition, since TSV technology can greatly shorten the length of electrical interconnection, it can well solve problems such as signal delay that appear in two-dimensional system-on-chip technology and improve electrical performance. Through TSV interconnection, different functional chips (such as RF, memory, logic, digital and MEMS, etc.) can be integrated together to realize the multi-function of electronic components.

[0043] In practical applications, the first test pad 110 is electrically connected to the chip layer 120 , a pin (PIN) or a solder ball of the substrate, and a test signal is applied to the first test pad 110 to test whether the chip layer 120 is failed.

[0044] Among them, there may be multiple first test pads, including but not limited to: a first test pad for testing the substrate, a first test pad for testing the chip layer, a first test pad for testing the substrate and the chip layer, and may also include a first test pad for testing each chip and the connection layer of the chip layer. For example, the chip layer includes two chips and corresponding connection layers, and each chip and the corresponding connection layer are tested through a first test pad, and two first test pads can be set on the substrate. By setting multiple first test pads on the substrate, it is possible to implement separate power supply control testing and power-on testing of each chip in the chip layer, thereby achieving failure analysis of chips at all levels through the additional first test pads.

[0045] Exemplarily, the material of the first test pad includes but is not limited to nickel-plated gold copper. The shape of the first test pad can be any shape, for example, can include any of the following: circular, elliptical, square, rectangular or hexagonal.

[0046] Optionally, at least one chip layer includes a logic chip layer and a memory chip layer, the logic chip layer includes at least one logic processing die, and the memory chip layer includes at least one memory die. The logic chip layer is an integrated circuit used to perform logic operations, processing and generating outputs based on input logic signals. These chips include various types of logic gates (such as AND gates, OR gates, NOT gates, etc.), complex combinational logic circuits, and sequential logic circuits. Logic chips can be used to build more complex digital circuits, such as counters, registers, multiplexers, decoders, etc. The memory chip layer is an integrated circuit used to store data. Data can be stored for a long time or temporarily as needed, and the data can remain unchanged when the data is read and written.

[0047] The specific test sequence can be determined according to specific needs. In one example, first determine whether the substrate is failed, compare the current value tested by the test pad used to test the substrate with the preset current value, and determine whether the substrate is failed based on the comparison result. If the substrate is not failed, then test whether the chip layer is failed in the same way. If it is failed, then determine the target chip with failed chip layer.

[0048] In the related art, for multi-chip packaging, more PINs / balls are required for functional configuration and testing, resulting in a lack of pins / balls for failure analysis. Failure analysis needs to locate the problem of a single chip or the connection relationship between the chip in the system package and other chips or substrates, and the number of available PINs / balls is insufficient. In the embodiment of the utility model, the first test pad set on the substrate is used to locate the fault position and perform failure analysis, which solves the problem of insufficient number of PINs / balls, can reduce the cost of failure analysis and shorten the cycle of failure analysis.

[0049] The chip package provided by the embodiment of the utility model includes a substrate, at least one chip layer carried by the substrate, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. In this embodiment, the first test pad provided on the substrate is used to determine whether the chip layer is failed, thereby locating the fault position and performing failure analysis, which can reduce the cost of failure analysis and shorten the cycle of failure analysis.

[0050] Embodiment 2

[0051] The present utility model provides a chip package, such as Figure 2As shown, the chip package provided by the embodiment of the utility model includes: a substrate 110, at least one chip layer 120 carried by the substrate 110, each chip layer 120 includes at least one chip; at least one first test pad 130 is arranged on the upper surface of the substrate, each first test pad 130 is electrically connected to at least one chip layer 120 through the substrate 110, and the chip layers 120 electrically connected to different first test pads 110 are not completely consistent; each first test pad 110 is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer 120 based on the test results. In addition, at least one second test pad 140 is arranged on the upper surface of the substrate 110; each second test pad 140 is electrically connected to a functional pad 150 arranged on the lower surface of the substrate 110 through the substrate 110, and the functional pads electrically connected to different second test pads 140 are inconsistent, and each second test pad 140 is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results.

[0052] Optionally, at least one chip layer includes a logic chip layer and a memory chip layer, the logic chip layer includes at least one logic processing die, and the memory chip layer includes at least one memory die. The logic chip layer is an integrated circuit used to perform logic operations, processing and generating outputs based on input logic signals. These chips include various types of logic gates (such as AND gates, OR gates, NOT gates, etc.), complex combinational logic circuits, and sequential logic circuits. Logic chips can be used to build more complex digital circuits, such as counters, registers, multiplexers, decoders, etc. The memory chip layer is an integrated circuit used to store data. Data can be stored for a long time or temporarily as needed, and the data can remain unchanged when the data is read and written.

[0053] Among them, the first test pad is arranged on the upper surface of the substrate, electrically connected to the chip layer, and is used to determine whether the function of the chip layer or the substrate fails according to the first current value; the chip layer includes at least one chip and at least one connection layer corresponding to each chip, and the connection layer is used to realize the electrical connection between the corresponding chip and other chips or the substrate; the substrate is electrically connected to the chip layer and the first test pad, and is used to carry the chip layer and the first test pad. Among them, the connection layer can be electrically connected through the through-silicon via (TSV) technology. Through-silicon via (TSV) technology can be used to realize vertical electrical connection of multiple chips. Through-silicon via technology makes vertical conduction between chips and between wafers, and realizes vertical electrical interconnection of through-silicon vias by filling conductive materials such as copper, tungsten, and polysilicon, thereby realizing 3D advanced packaging. Through advanced packaging, the integration of electronic components can be greatly improved, and the geometric size and weight of the package can be reduced. It overcomes the shortcomings of the existing 2D-System In a Package (2D-SIP) and 3D Package on Package (POP) systems and meets the requirements of microelectronic products for multi-function and miniaturization. In addition, since TSV technology can greatly shorten the length of electrical interconnection, it can well solve the problems of signal delay and other problems that appear in 2D system-on-chip technology and improve electrical performance. Through TSV interconnection, different functional chips (such as RF, memory, logic, digital and MEMS, etc.) can be integrated together to realize the multi-function of electronic components.

[0054] Wherein, the second test pad is electrically connected to the functional pad, and the functional pad is an electrical connection point provided to realize certain functions of the circuit. The functional pad can have a variety of shapes and sizes, depending on their purpose and the required connection type. The second test pad is electrically connected to the functional pad, and a test signal can be applied to test whether the chip function corresponding to the functional pad fails. The number of functional pads can be set according to specific needs, and the utility model does not limit it. Exemplarily, the material of the second test pad includes but is not limited to nickel-plated gold copper. The shape of the second test pad can be any shape, for example, it can include any of the following: circular, oval, square, rectangular or hexagonal.

[0055] The chip package provided by the embodiment of the utility model includes a substrate, at least one chip layer carried by the substrate, and each chip layer includes at least one chip; at least one first test pad is arranged on the upper surface of the substrate, and each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. At least one second test pad is arranged on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent, and each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results. In this embodiment, the first test pad arranged on the substrate is used to determine whether the chip layer fails, and the second test pad arranged on the substrate is used to determine whether the corresponding function of the chip layer fails, so as to locate the fault position and perform failure analysis, which can reduce the cost of failure analysis and shorten the cycle of failure analysis.

[0056] Embodiment 3

[0057] The present utility model provides a chip package, such as Figure 3 As shown, the chip package provided by the embodiment of the utility model includes: a substrate 110, at least one chip layer 120 carried by the substrate 110, each chip layer 120 includes at least one chip; at least one first test pad 130 is provided on the upper surface of the substrate, each first test pad 130 is electrically connected to at least one chip layer 120 through the substrate 110, and the chip layers 120 electrically connected to different first test pads 110 are not completely consistent; each first test pad 110 is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer 120 based on the test results. In addition, the chip package also includes a re-distributed layer (RDL), which is deployed between at least one chip layer and the substrate. A third test pad 160 is provided on the upper surface of the substrate, and the third test pad 160 is electrically connected to the re-distributed layer through the substrate, and the third test pad 160 is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the re-distributed layer based on the test results.

[0058] Optionally, at least one chip layer includes a logic chip layer and a memory chip layer, the logic chip layer includes at least one logic processing die, and the memory chip layer includes at least one memory die. The logic chip layer is an integrated circuit used to perform logic operations, processing and generating outputs based on input logic signals. These chips include various types of logic gates (such as AND gates, OR gates, NOT gates, etc.), complex combinational logic circuits, and sequential logic circuits. Logic chips can be used to build more complex digital circuits, such as counters, registers, multiplexers, decoders, etc. The memory chip layer is an integrated circuit used to store data. Data can be stored for a long time or temporarily as needed, and the data can remain unchanged when the data is read and written.

[0059] Among them, the redistribution layer plays the role of horizontal electrical extension and interconnection. The redistribution layer is used to achieve electrical connection between the chip layer and the substrate. RDL deposits a metal layer and a corresponding dielectric layer on the surface of the chip (wafer), and forms metal wiring, and rearranges the input and output (IO) ports to form a surface array arrangement. The chip in this embodiment adopts a system-level package (System In a Package, SIP), and the SIP can be a planar 2D package of a multi-chip module (Multi-chip Module, MCM), and can also reuse the structure of a 3D package to effectively reduce the package area. And its internal bonding technology can be a simple wire bonding (Wire Bonding), or a flip chip bonding (FlipChip), or a mixture of the two.

[0060] The chip package provided by the embodiment of the utility model includes a substrate, at least one chip layer carried by the substrate, each chip layer includes at least one chip; at least one first test pad is arranged on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. At least one second test pad is arranged on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent, and each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results. The chip package also includes a redistribution layer, which is disposed between at least one chip layer and the substrate. A third test pad is arranged on the upper surface of the substrate, and the third test pad is electrically connected to the redistribution layer through the substrate, and the third test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the redistribution layer based on the test results. In this embodiment, a first test pad set on the substrate is used to determine whether the chip layer has failed, and a third test pad set on the substrate is used to determine whether the redistribution layer has failed, thereby locating the fault position and performing failure analysis, which can reduce the failure analysis cost and shorten the failure analysis cycle.

[0061] Embodiment 4

[0062] The present utility model provides a chip package, such as Figure 4 As shown, the chip package provided by the embodiment of the utility model includes: a substrate 110, at least one chip layer 120 carried by the substrate 110, each chip layer 120 includes at least one chip; at least one first test pad 130 is provided on the upper surface of the substrate, each first test pad 130 is electrically connected to at least one chip layer 120 through the substrate 110, and the chip layers 120 electrically connected to different first test pads 110 are not completely consistent; each first test pad 110 is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer 120 based on the test results. The upper surface of the top chip layer is electrically connected to the connection pad 170 provided on the upper surface of the substrate, and the connection pad 170 is electrically connected to a first test pad 130, and the first test pad 130 is used to test whether the electrical connection between the upper surface of the top chip layer and the connection pad is normal, so as to perform failure analysis on the top chip layer based on the test results.

[0063] Optionally, at least one chip layer includes a logic chip layer and a memory chip layer, the logic chip layer includes at least one logic processing die, and the memory chip layer includes at least one memory die. The logic chip layer is an integrated circuit used to perform logic operations, processing and generating outputs based on input logic signals. These chips include various types of logic gates (such as AND gates, OR gates, NOT gates, etc.), complex combinational logic circuits, and sequential logic circuits. Logic chips can be used to build more complex digital circuits, such as counters, registers, multiplexers, decoders, etc. The memory chip layer is an integrated circuit used to store data. Data can be stored for a long time or temporarily as needed, and the data can remain unchanged when the data is read and written.

[0064] The chip package provided by the embodiment of the utility model includes a substrate, at least one chip layer carried by the substrate, each chip layer includes at least one chip; at least one first test pad is arranged on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. At least one second test pad is arranged on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent, and each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results. The chip package also includes a redistribution layer, which is disposed between at least one chip layer and the substrate. A third test pad is arranged on the upper surface of the substrate, and the third test pad is electrically connected to the redistribution layer through the substrate, and the third test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the redistribution layer based on the test results. In this embodiment, the top chip layer is electrically connected to the connection pads set on the substrate. The top chip layer is subjected to failure analysis through the first test pads set on the substrate to locate the fault position, thereby reducing the failure analysis cost and shortening the failure analysis cycle.

[0065] In practical applications, when performing failure analysis on a chip package, a first test signal is applied to a test pad used to test a substrate, and a comparison is made between the first current value and the preset current value to determine whether the function of the substrate has failed. If the substrate has not failed, it is determined that the chip layer has failed; the test pads corresponding to the multiple chips in the chip layer are used to determine whether each chip and the corresponding connection layer have failed. If it is determined that one of the chips and the corresponding connection layer has failed, it may be a chip failure, or it may be a chip connection layer failure. The chip is determined as a target chip, and the test pads set on the target chip are further used to determine whether the target chip has failed. Specifically, after unsealing, the packaging material outside the target chip is removed to obtain the exposed target chip, and the target chip is fixed on the substrate by patch glue. A second test signal is applied to the test pad corresponding to the target chip. The second test signal is a test signal related to the function of the target chip. According to the comparison result of the second current value and the preset current value, the target chip is tested to see whether it is normal. Among them, the second test signal can be a test signal related to the function of the target chip.

[0066] In one example, if Figure 5 As shown in FIG. 1 , the chip package includes four levels: the first level substrate, the second level RDL layer, the third level ASIC chip, and the fourth level HBM chip. 1-2, 2-3, and 3-4 represent the connection layers of each level, respectively.

[0067] If the test pad corresponding to the SIO_ASIC_1 interface fails, the possible failed layers include layer 1, layer 1-2, layer 2, layer 2-3 and layer 3. The test pad corresponding to the SIO_ASIC_2 interface is used to test whether layer 1, layer 1-2 and layer 2 have failed. If they have not failed, the possible failed layers are layer 2-3 and layer 3. In order to confirm whether the ASIC chip of layer 3 has failed, the ASIC chip is tested through test pad 1 set on the ASIC chip. Among them, the test pad corresponding to the SIO_ASIC_2 interface is a bumping pad, and the test pad 1 set on the ASIC chip is an aluminum pad with an opening size that is led out using a wire bond process. The test pad corresponding to the SIO_ASIC_2 interface and the test pad 1 set on the ASIC chip are connected by wires. As Figure 6 As shown, after unpacking, the packaging material outside the chip is removed to obtain the exposed chip inside the chip, and the ASIC chip is fixed on the substrate by patch glue to test whether the ASIC chip is normal.

[0068] In the same way, if the test pad corresponding to the SIO_HBM_1 interface fails, the possible failed layers include layer 1, layer 1-2, layer 2, layer 2-3, layer 3, layer 3-4, and layer 4. Test layer 1, layer 1-2, and layer 2 for failure through the test pad corresponding to the SIO_HBM_2 interface. If they are not failed, the possible failed layers are layer 2-3, layer 3, layer 3-4, and layer 4. If the ASIC chip tested in layer 3 does not fail, in order to confirm whether the HBM chip in layer 4 fails, the HBM chip is tested for failure through the test pad 2 set on the HBM chip. The test pad corresponding to the SIO_HBM_2 interface is a bumping pad, and the test pad 2 set on the HBM chip is an aluminum pad with an opening size and a lead-out process using a wirebond process. The test pad corresponding to the SIO_HBM_2 interface and the test pad 2 set on the HBM chip are connected via a wire. Figure 7 As shown, after unpacking, remove the packaging material outside the chip, obtain the exposed chip inside the chip, fix the HBM chip on the substrate with patch glue, and test whether the HBM chip is normal.

[0069] Embodiment 5

[0070] The embodiment of the utility model provides a chip package, and the chip package provided by the embodiment of the utility model includes: a substrate, a chip layer, a first test pad and a first packaging layer. The substrate carries at least one chip layer, and each chip layer includes at least one chip; at least one first test pad is arranged on the upper surface of the substrate, and each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results.

[0071] The first packaging layer is used to package the substrate, the chip layer and the first test pad. The first packaging layer includes a plastic sealant or a heat dissipation cover.

[0072] In actual applications, when packaging the chip, a full packaging method is used to burn special data or security requirements, and the first test pad is built into the chip test system package to avoid user-side erroneous operations to change the internal data of the chip and ensure chip safety.

[0073] Embodiment 6

[0074] The embodiment of the utility model provides a chip package, and the chip package provided by the embodiment of the utility model includes: a substrate, a chip layer, a first test pad and a second packaging layer. The substrate carries at least one chip layer, and each chip layer includes at least one chip; at least one first test pad is arranged on the upper surface of the substrate, and each first test pad forms an electrical connection with at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. The second packaging layer is used to package the area on the substrate except the first test pad. The second packaging layer includes a plastic sealant or a heat dissipation cover.

[0075] In practical applications, an incomplete packaging method can also be used to encapsulate the part outside the first test pad and expose the first test pad. When failure analysis is required, the test pad can be exposed for electrical testing using the Failure Analysis (FA) technique, without damaging the key parts of the chip itself.

[0076] Embodiment 7

[0077] The embodiment of the utility model provides a working component, comprising: a chip package according to any embodiment of the utility model; and a printed circuit board, wherein the chip package is arranged on one side of the printed circuit board.

[0078] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer including at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layers based on the test results.

[0079] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer including at least one chip; at least one first test pad is disposed on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layers based on the test results. In addition, at least one second test pad is disposed on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent, and each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results.

[0080] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. In addition, the chip package also includes a re-distributed layer (RDL), which is deployed between at least one chip layer and the substrate. A third test pad is provided on the upper surface of the substrate, the third test pad is electrically connected to the re-distributed layer through the substrate, and the third test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the re-distributed layer based on the test results.

[0081] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer including at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layers based on the test results. The upper surface of the top chip layer is electrically connected to the connection pad provided on the upper surface of the substrate, and the connection pad is electrically connected to a first test pad, and the first test pad is used to test whether the electrical connection between the upper surface of the top chip layer and the connection pad is normal, so as to perform failure analysis on the top chip layer according to the test results.

[0082] In one implementation, a chip package includes: a substrate, a chip layer, a first test pad, and a first packaging layer. The substrate carries at least one chip layer, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. The first packaging layer is used to package the substrate, the chip layer, and the first test pad. The first packaging layer includes a plastic sealant or a heat dissipation cover.

[0083] In one implementation, a chip package includes: a substrate, a chip layer, a first test pad, and a second packaging layer. The substrate carries at least one chip layer, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. The second packaging layer is used to package the area on the substrate except the first test pad. The second packaging layer includes a plastic sealant or a heat dissipation cover.

[0084] In one implementation, there are multiple chip packages.

[0085] In one implementation, at least some of the plurality of chip packages are connected to each other.

[0086] Embodiment 8

[0087] An embodiment of the utility model provides a computing device, including: a working component of any embodiment of the utility model; and a power supply module.

[0088] The working components include: a chip package according to any embodiment of the present utility model; and a printed circuit board, with the chip package arranged on one side of the printed circuit board.

[0089] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer including at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layers based on the test results.

[0090] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer including at least one chip; at least one first test pad is disposed on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layers based on the test results. In addition, at least one second test pad is disposed on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent, and each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results.

[0091] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. In addition, the chip package also includes a re-distributed layer (RDL), which is deployed between at least one chip layer and the substrate. A third test pad is provided on the upper surface of the substrate, the third test pad is electrically connected to the re-distributed layer through the substrate, and the third test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the re-distributed layer based on the test results.

[0092] In one implementation, a chip package includes: a substrate, at least one chip layer carried by the substrate, each chip layer including at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layers based on the test results. The upper surface of the top chip layer is electrically connected to the connection pad provided on the upper surface of the substrate, and the connection pad is electrically connected to a first test pad, and the first test pad is used to test whether the electrical connection between the upper surface of the top chip layer and the connection pad is normal, so as to perform failure analysis on the top chip layer according to the test results.

[0093] In one implementation, a chip package includes: a substrate, a chip layer, a first test pad, and a first packaging layer. The substrate carries at least one chip layer, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. The first packaging layer is used to package the substrate, the chip layer, and the first test pad. The first packaging layer includes a plastic sealant or a heat dissipation cover.

[0094] In one implementation, a chip package includes: a substrate, a chip layer, a first test pad, and a second packaging layer. The substrate carries at least one chip layer, each chip layer includes at least one chip; at least one first test pad is provided on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test results. The second packaging layer is used to package the area on the substrate except the first test pad. The second packaging layer includes a plastic sealant or a heat dissipation cover.

[0095] In one implementation, there are multiple working components.

[0096] In one implementation, at least some of the plurality of working components are interconnected.

[0097] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0098] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0099] In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0100] In the present utility model, unless otherwise clearly stipulated and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0101] The disclosure above provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0102] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A chip package, characterized in that: include: A substrate, and at least one chip layer carried by the substrate, each chip layer comprising at least one chip; At least one first test pad is disposed on the upper surface of the substrate, each first test pad is electrically connected to at least one chip layer through the substrate, and the chip layers electrically connected to different first test pads are not completely consistent; Each first test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on at least part of the chip layer based on the test result.

2. The chip package according to claim 1, characterized in that: At least one second test pad is provided on the upper surface of the substrate; each second test pad is electrically connected to a functional pad arranged on the lower surface of the substrate through the substrate, and the functional pads electrically connected to different second test pads are inconsistent. Each second test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the corresponding functional pad according to the test results.

3. The chip package according to claim 1, wherein: The upper surface of the top chip layer is electrically connected to the connecting pads arranged on the upper surface of the substrate, and the connecting pads are electrically connected to a first test pad. The first test pad is used to test whether the electrical connection between the upper surface of the top chip layer and the connecting pads is normal, so as to perform failure analysis on the top chip layer according to the test results.

4. The chip package according to claim 1, wherein: The chip package further includes a redistribution layer disposed between the at least one chip layer and the substrate.

5. The chip package according to claim 4, characterized in that: A third test pad is provided on the upper surface of the substrate, and the third test pad forms an electrical connection between the substrate and the redistribution layer. The third test pad is used to test whether the corresponding electrical connection is normal, so as to perform failure analysis on the redistribution layer based on the test result.

6. The chip package according to claim 1, wherein: The at least one chip layer includes a logic chip layer and a memory chip layer. The logic chip layer includes at least one logic processing die, and the memory chip layer includes at least one memory die.

7. The chip package according to any one of claims 1 to 6, characterized in that: The material of the test pad is nickel-gold-plated copper.

8. The chip package according to any one of claims 1 to 6, characterized in that: The shape of the test pad is any of the following: Round, oval, square, rectangular or hexagonal.

9. A working component, characterized in that: include: The chip package according to any one of claims 1 to 8; A printed circuit board, the chip package is arranged on one side of the printed circuit board.

10. The working assembly according to claim 9, characterized in that: There are multiple chip packages.

11. The working assembly according to claim 10, characterized in that: At least parts of the plurality of chip packages are connected to each other.

12. A computing device, characterized in that: include: The working component according to any one of claims 9 to 11; Power supply module.

13. The computing device according to claim 12, characterized in that The number of the working components is multiple.

14. The computing device according to claim 13, characterized in that At least some of the plurality of working components are connected to each other.

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