Bidirectional blocking device
By connecting the two transistor dies face to face vertically and connecting them with conductive channels, the problems of large area and high on-resistance of traditional bidirectional blocking devices are solved, and the device is miniaturized and low on-resistance is achieved.
Patent Information
- Application Number
- CN202421341242.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-12
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-06-12
AI Technical Summary
When traditional bidirectional blocking devices realize bidirectional blocking function, the area is large and the on-resistance is difficult to reduce, especially during the packaging stage.
Vertical assembly of the resistive switch tube is achieved by connecting the transistor dies with two first surfaces opposite to each other in vertically in series face to face, and connecting the source and gate with conductive channels.
It effectively reduces the on-resistance and package area of the bidirectional blocking device, realizes the miniaturization of the device, and ensures low on-resistance.
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Figure CN222600974U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic components, in particular to a bidirectional blocking device. Background Art
[0002] Due to the parasitic body diode structure of the MOS tube itself, it is not suitable for use as a bidirectional blocking switch. So, for scenarios where bidirectional blocking is required, the usual practice is to use two MOS tubes connected in series head-to-head to achieve bidirectional blocking, such as Figure 1 Therefore, traditionally, the required bidirectional blocking switch function is realized by using a planar series structure of two MOS tubes during the assembly stage. Naturally, its area is twice that of a MOS tube with the same on-resistance; or, a trench gate structure is used to arrange the two ends of the switch on the device structure on both sides of the trench gate, such as Figure 2 As shown, although this structure has a smaller area than two MOS tubes connected in series, it still has a large area because the lead-out ends of the two drain electrodes are in the same plane, and the on-resistance introduced by the package is also difficult to reduce. Utility Model Content
[0003] In view of the above problems, the purpose of the utility model is to provide a bidirectional blocking device, in which two first surfaces are arranged opposite to each other, and the transistor cores corresponding to the source and gate of the first surfaces are connected in series face to face in a direction perpendicular to the core surface through an intermediate conductive channel, thereby effectively reducing the on-resistance and packaging area of the bidirectional blocking device.
[0004] According to one aspect of the utility model, a bidirectional blocking device is provided, comprising: a first transistor die and a second transistor die, respectively comprising a first surface and a second surface, the first surface being provided with a source and a gate, and the second surface being provided with a drain; a source conductive channel connected to the source of the first transistor die and the second transistor die; a gate conductive channel connected to the source of the first transistor die and the second transistor die, wherein the first surfaces of the first transistor die and the second transistor die are arranged opposite to each other, and at least part of the source conductive channel extends laterally between the first surfaces of the first transistor die and the second transistor die, and contacts the source of the first transistor die and the second transistor die.
[0005] Optionally, at least part of the gate conductive path extends laterally between the first surfaces of the first transistor die and the second transistor die, contacting the gates of the first transistor die and the second transistor die.
[0006] Optionally, the source conductive path and the gate conductive path each include a connected bonding region and a lead region, the bonding region extending laterally between the first surfaces of the first transistor die and the second transistor die.
[0007] Optionally, the source of the first transistor die and the source of the second transistor die are bonded to each other via the bonding area of the source conductive channel and are led out via the lead area of the source conductive channel; the gate of the first transistor die and the gate of the second transistor die are bonded to each other via the bonding area of the gate conductive channel and are led out via the lead area of the gate conductive channel.
[0008] Optionally, the shape of the bonding area of the source conductive channel matches the shape of the source of the first transistor die and / or the second transistor die; the shape of the bonding area of the gate conductive channel matches the shape of the gate of the first transistor die and / or the second transistor die.
[0009] Optionally, a bonding region of the source conductive channel is spaced a predetermined distance from a bonding region of the gate conductive channel.
[0010] Optionally, the bonding region of the source conductive channel and the bonding region of the gate conductive channel are separated by an insulating layer.
[0011] Optionally, the source conductive path and the gate conductive path are copper tapes.
[0012] Optionally, it also includes: a first drain conductive channel, located on the second surface of the first transistor die and connected to the drain of the first transistor die; a second drain conductive channel, located on the second surface of the second transistor die and connected to the drain of the second transistor die.
[0013] Optionally, the first drain conductive path and the second drain conductive path both include a connected bonding region and a lead region.
[0014] Optionally, the drain of the first transistor die is bonded to the bonding area of the first drain conductive channel and is led out through the lead area of the first drain conductive channel; the drain of the second transistor die is bonded to the bonding area of the second drain conductive channel and is led out through the lead area of the second drain conductive channel.
[0015] Optionally, the lead areas of the source conductive channel, the gate conductive channel, the first drain conductive channel and the second drain conductive channel lead the source, drain and gate of the first transistor die and the second transistor die to the plane where the first drain conductive channel or the second drain conductive channel is located.
[0016] Optionally, the first transistor die and the second transistor die are any one selected from a vertical trench gate transistor die, a planar gate transistor die, an SGT transistor die, a super junction transistor die, and a SiC transistor die.
[0017] The bidirectional blocking device provided by the utility model assembles two transistor tube cores that are arranged opposite to each other on the first surface face to face vertically, thereby forming a resistance switch tube that can be used as a bidirectional blocking device. Since the two transistor tube cores are vertically connected in series, the external dimensions of the resistance switch tube can be effectively reduced. At the same time, the two transistor tube cores are connected in series by a conductive channel, which can also ensure a lower on-resistance, especially avoiding or reducing the on-resistance introduced by the traditional package, so that the resistance switch tube of the present application can not only achieve the miniaturization of the device, but also have a low on-resistance. Furthermore, the bidirectional blocking device of the present application is realized by using the conductive channel technology in the assembly stage, which can not only greatly reduce the difficulty of process development, but also can better utilize the existing ultra-low on-resistance transistor tube core technology, that is, it can achieve bidirectional blocking and ensure the miniaturization of the package and the lower on-resistance.
[0018] Furthermore, in the bidirectional blocking device of the present application, the two transistor dies therein can be simultaneously replaced with different types of transistor dies to adapt to different application requirements. For example, if a higher withstand voltage is required, a super junction transistor die or a SiC transistor die can be selected. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0020] Figure 1 and Figure 2 A circuit diagram and a cross-sectional view of a semiconductor device according to the prior art are shown;
[0021] Figure 3 A schematic diagram of the three-dimensional structure of a bidirectional blocking device according to an embodiment of the utility model is shown;
[0022] Figure 4 A top view of the bonding layer of two transistor dies in a bidirectional blocking device according to an embodiment of the utility model is shown;
[0023] Figure 5 A top view of the bonding surfaces of two transistor dies in a bidirectional blocking device according to an embodiment of the utility model is shown;
[0024] Figure 6A top view of two transistor dies in a bidirectional blocking device according to an embodiment of the present invention during the manufacturing process is shown. DETAILED DESCRIPTION
[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0026] The specific implementation of the utility model is further described in detail below in conjunction with the drawings and embodiments.
[0027] Figure 3 A schematic diagram of the three-dimensional structure of a bidirectional blocking device according to an embodiment of the utility model is shown; Figure 4 A top view of the bonding layer of two transistor dies in a bidirectional blocking device according to an embodiment of the utility model is shown; Figure 5 A top view of the bonding surfaces of two transistor dies in a bidirectional blocking device according to an embodiment of the utility model is shown; Figure 6 A top view showing two transistor dies in a bidirectional blocking device according to an embodiment of the present invention manufactured on the same wafer is shown.
[0028] refer to Figure 3 The bidirectional blocking device 100 of the present application includes: a first transistor die 110 , a second transistor die 120 , a source conductive channel 130 , a gate conductive channel 140 , a first drain conductive channel 150 , and a second drain conductive channel 160 .
[0029] The first transistor die 110 and the second transistor die 120 each include a first surface and a second surface opposite to each other, the first surface is provided with a source and a gate, for example, and the second surface is provided with a drain, for example. In the bidirectional blocking device 100, the first surfaces of the first transistor die 110 and the second transistor die 120 are arranged opposite to each other, and at least part of the source conductive channel 130 and at least part of the gate conductive channel 140 extend laterally between the first surfaces of the first transistor die 110 and the second transistor die 120, so that the bonding area on the source conductive channel 130 between the first transistor die 110 and the second transistor die 120 can be bonded to the source of the first transistor die 110 and the second transistor die 120 to achieve electrical connection, and the bonding area on the gate conductive channel 140 between the first transistor die 110 and the second transistor die 120 can also be bonded to the gate of the first transistor die 110 and the second transistor die 120 to achieve electrical connection. In the bidirectional blocking device 100 of the present application, the first transistor die 110 and the second transistor die 120 are connected in series in a direction perpendicular to the surface of the die. Figure 1 .
[0030] Specifically, in the present application, in order to enable the source conductive channel 130 and the gate conductive channel 140 to be accurately electrically connected to the source and gate of the first transistor die 110 and the second transistor die 120, when the first transistor die 110 and the second transistor die 120 are arranged opposite to each other on the first surface, the source of the first transistor die 110 at least partially overlaps with the source of the second transistor die 120, and the gate of the first transistor die 110 at least partially overlaps with the gate of the second transistor die 120, so that the bonding area on the source conductive channel 130 extending laterally between the first surfaces of the first transistor die 110 and the second transistor die 120 is simultaneously bonded to the source of the first transistor die 110 and the second transistor die 120, and the bonding area on the gate conductive channel 140 is simultaneously bonded to the gate of the first transistor die 110 and the second transistor die 120. In addition, it is also necessary to ensure that the source conductive channel 130 is not in electrical contact with the gate, and the gate conductive channel 140 is not in electrical contact with the source.
[0031] Further, refer to Figure 5 , shows an embodiment in which the layouts of the source and the gate in the first surfaces of the first transistor die 110 and the second transistor die 120 are set to be mirror images, that is, the size, shape, and position of the source 111 of the first transistor die 110 and the source 121 of the second transistor die 120 are mirror images of each other, and the size, shape, and position of the gate 112 of the first transistor die 110 and the gate 122 of the second transistor die 120 are mirror images of each other, so that when the first surfaces of the first transistor die 110 and the second transistor die 120 are arranged relative to each other for assembly, the source 111 of the first transistor die 110 corresponds to the source 121 of the second transistor die 120, and the gate 112 of the first transistor die 110 corresponds to the gate 122 of the second transistor die 120.
[0032] In other embodiments, the layouts of the source and gate on the first surface of the first transistor die 110 and the second transistor die 120 may not be mirror images, as long as the functions of the source conductive channel 130 and the gate conductive channel 140 described above can be achieved. The following description will be based on the layout of the source and gate on the first surface of the first transistor die 110 and the second transistor die 120 being mirror images.
[0033] Furthermore, the source conductive channel 130 and the gate conductive channel 140 also serve as bonding layers, and both the first surface and the second surface thereof can be bonded, so that the first surface of the first transistor die 110 and the first surface of the second transistor die 120 are bonded via the source conductive channel 130 and the gate conductive channel 140. At the same time, due to the functions of the conductive channels themselves and the circuit requirements of the bidirectional blocking device 100, the source conductive channel 130 and the gate conductive channel 140 between the first surface of the first transistor die 110 and the first surface of the second transistor die 120 are separated by a predetermined distance or separated by an insulating layer.
[0034] Specifically, in this embodiment, the source conductive channel 130, the gate conductive channel 140, the first drain conductive channel 150 and the second drain conductive channel 160 all include connected bonding areas and lead areas. Figure 4 As shown, the bonding area of the source conductive channel 130 is located between the first surfaces of the first transistor die 110 and the second transistor die 120, and is bonded to the source 111 of the first transistor die 110 and the source 121 of the second transistor die 120. The lead area serves as a lead-out structure of the bonding area to lead the source of the first transistor die 110 and the second transistor die 120 to a suitable position. The bonding area of the gate conductive channel 140 is located between the first surfaces of the first transistor die 110 and the second transistor die 120, and is bonded to the gate 112 of the first transistor die 110 and the gate 122 of the second transistor die 120. The lead area serves as a lead-out structure of the bonding area to lead the gate of the first transistor die 110 and the second transistor die 120 to a suitable position. The first drain conductive channel 150 is located on the second surface of the first transistor die 110 and is bonded to the drain of the first transistor die 110. Specifically, the bonding area of the first drain conductive channel 150 is bonded to the drain of the second surface of the first transistor die 110, and the lead area serves as a lead-out structure of the bonding area to lead the drain of the first transistor die 110 to a suitable position. The second drain conductive channel 160 is located on the second surface of the second transistor die 120 and is bonded to the drain of the second transistor die 120. Specifically, the bonding area of the second drain conductive channel 160 is bonded to the drain of the second surface of the second transistor die 120, and the lead area serves as a lead-out structure of the bonding area to lead the drain of the second transistor die 120 to a suitable position.
[0035] In this embodiment, the lead regions of the source conductive channel 130, the gate conductive channel 140, the first drain conductive channel 150 and the second drain conductive channel 160 lead the source, drain and gate of the first transistor die 110 and the second transistor die 120 to the same horizontal plane, for example, the plane where the first drain conductive channel 150 or the second drain conductive channel 160 is located, for example, Figure 3 .
[0036] In this embodiment, the source conductive channel 130 and the gate conductive channel 140 are, for example, made of copper tape, and the two surfaces of the copper tape are bonded to the first transistor die 110 and the second transistor die 120 respectively. In this embodiment, the copper tape packaging technology not only meets the characteristics of high on-resistance and high thermal conductivity, but also has a low thermal expansion coefficient, which plays an important role in improving the reliability of the bidirectional blocking device 100. At the same time, the first transistor die 110 and the second transistor die 120 with mirror-symmetrical layouts are face-to-face stacked and assembled, so that the gate and the source are sintered together on the two surfaces of the bonding area on the copper tape, and the source and the gate are respectively led out by the lead-out area, and the two drains are respectively led out by two layers of copper tape, so that the bidirectional blocking device formed by the first transistor die 110 and the second transistor die 120 can be realized.
[0037] In other embodiments, the source conductive channel 130, the gate conductive channel 140, the first drain conductive channel 150, and the second drain conductive channel 160 may also be implemented in other ways to achieve the same function. For example, a substrate may be used as a conductive channel. The substrate itself is an insulator, but "bonding areas and lead areas" are made on its first and second surfaces respectively, and the corresponding bonding areas are electrically connected, so that the source of the first transistor die 110 is electrically connected to the source of the second transistor die 120, and the gate of the first transistor die 110 is electrically connected to the gate of the second transistor die 120. Furthermore, without considering the cost, the function of the conductive channel can also be implemented by combining ball planting and wire bonding, so that the first transistor die 110 and the second transistor die are connected in series as described above.
[0038] Furthermore, the first transistor die 110 and the second transistor die 120 are both unpackaged crystal chips, and in order to obtain the first transistor die 110 and the second transistor die 120 whose patterns on the first surface are mirror images of each other, and also in order to better maintain the consistency of the first transistor die 110 and the second transistor die 120, such as threshold, transconductance, on-resistance and other parameters, the mirrored first transistor die 110 and the second transistor die 120 can be put together and processed and manufactured in the same wafer at the same time, that is, in the process of manufacturing the transistor die, the first transistor die 110 and the second transistor die 120 can be designed as a group of transistor die, and multiple groups of transistor die can be included on a wafer. There are scribe lines (such as Figure 6 ), so that each transistor die group can be separated in the subsequent assembly process. At the same time, there is also a scribe line between the first transistor die 110 and the second transistor die 120 in a transistor die group, so that the first transistor die 110 and the second transistor die 120 can be cut into independent transistor dies. After that, the first surfaces of the mirrored first transistor die 110 and the second transistor die 120 are arranged opposite to each other, and bonded to the bonding areas on the opposite sides of the source conductive channel 130 and the gate conductive channel 140. Then, similarly, copper tape is used as the drain conductive channel of the first transistor die 110 and the second transistor die 120, and the source, gate and drain of the first transistor die 110 and the second transistor die 120 are led out to the same horizontal plane through the lead areas of each conductive channel to form a bidirectional blocking device 100.
[0039] In the present application, the first transistor die 110 and the second transistor die 120 are two transistor dies of the same model, for example, they may be any one of trench gate VDMOS, planar gate MOS, SGT MOS, Super Junction MOS (Sj MOS), and SiC MOS.
[0040] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A bidirectional blocking device, characterized in that: include: The first transistor die and the second transistor die respectively include a first surface and a second surface, the first surface is provided with a source and a gate, and the second surface is provided with a drain; A source conductive channel electrically connected to the source electrodes of the first transistor die and the second transistor die; a gate conductive channel electrically connected to the gates of the first transistor die and the second transistor die, The first surfaces of the first transistor die and the second transistor die are arranged opposite to each other, and at least part of the source conductive channel extends laterally between the first surfaces of the first transistor die and the second transistor die, and is in electrical contact with the sources of the first transistor die and the second transistor die.
2. The bidirectional blocking device according to claim 1, characterized in that: At least a portion of the gate conductive path extends laterally between the first surfaces of the first transistor die and the second transistor die in electrical contact with the gates of the first transistor die and the second transistor die.
3. The bidirectional blocking device according to claim 2, characterized in that: The source conductive path and the gate conductive path each include a connected bonding region and a lead region, the bonding region extending laterally between the first surfaces of the first transistor die and the second transistor die.
4. The bidirectional blocking device according to claim 3, characterized in that: The source of the first transistor die and the source of the second transistor die are bonded to each other via the bonding region of the source conductive channel and are led out via the lead region of the source conductive channel; The gate of the first transistor die and the gate of the second transistor die are bonded to each other via the bonding region of the gate conductive path and are led out via the lead region of the gate conductive path.
5. The bidirectional blocking device according to claim 4, characterized in that: The shape of the bonding area of the source conductive channel matches the shape of the source of the first transistor die and / or the second transistor die; the shape of the bonding area of the gate conductive channel matches the shape of the gate of the first transistor die and / or the second transistor die.
6. The bidirectional blocking device according to claim 5, characterized in that: A predetermined distance exists between the bonding region of the source conductive channel and the bonding region of the gate conductive channel.
7. The bidirectional blocking device according to claim 5, characterized in that: The bonding region of the source conductive channel and the bonding region of the gate conductive channel are separated by an insulating layer.
8. The bidirectional blocking device according to claim 1, characterized in that: The source conductive path and the gate conductive path are formed of copper tapes.
9. The bidirectional blocking device according to claim 4, characterized in that: Also includes: A first drain conductive channel, located on the second surface of the first transistor die and electrically connected to the drain of the first transistor die; The second drain conductive channel is located on the second surface of the second transistor die and is electrically connected to the drain of the second transistor die.
10. The bidirectional blocking device according to claim 9, characterized in that: The first drain conductive path and the second drain conductive path each include a connected bonding region and a lead region.
11. The bidirectional blocking device according to claim 10, characterized in that: The drain of the first transistor core is bonded to the bonding area of the first drain conductive channel and is led out through the lead area of the first drain conductive channel; the drain of the second transistor core is bonded to the bonding area of the second drain conductive channel and is led out through the lead area of the second drain conductive channel.
12. The bidirectional blocking device according to claim 11, characterized in that: The lead regions of the source conductive channel, the gate conductive channel, the first drain conductive channel and the second drain conductive channel lead the source, drain and gate of the first transistor die and the second transistor die to the plane where the first drain conductive channel or the second drain conductive channel is located.
13. The bidirectional blocking device according to claim 1, characterized in that: The first transistor die and the second transistor die are any one selected from a vertical trench gate transistor die, a planar gate transistor die, an SGT transistor die, a super junction transistor die, and a SiC transistor die.
Citation Information
Cited By
Bidirectional blocking semiconductor device and preparation method thereof
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