Multi-channel data processing equipment

Abstract

The utility model discloses a multi-channel data processing device which comprises a data processing carrier plate, a master control FPGA chip and a power interface are arranged on the data processing carrier plate, at least two groups of COMe female seats are arranged on the data processing carrier plate, the COMe female seats are electrically connected with other COMe female seats on the data processing carrier plate through PCB wires, and the COMe female seats are electrically connected with other COMe female seats through PCB wires. Each group of COMe female seats are used for being matched with COMe male seats on a group of FPGA data processing boards, a supporting piece is fixed on the data processing carrier board, a threaded hole is formed in the top end of the supporting piece, and the threaded hole is used for being matched with a fixing hole in the FPGA data processing board. According to the utility model, more data communication channels are provided, the communication rate bandwidth is greatly improved, equipment stacking is not needed, and the system complexity, the fault risk and the maintenance difficulty are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of high-speed data transmission processing, in particular to a multi-channel data processing device. Background Art

[0002] The application scope and market scope of data processing platforms are very wide. There are many types of existing data processing platforms, with large performance differences and no unified standard. With the increasing data communication rate bandwidth and communication data volume, the performance of many existing data processing platforms cannot meet application requirements, especially in multi-channel concurrent data transmission and processing applications. In order to meet performance requirements, multiple devices can only be stacked to improve performance. Although this can solve the performance problem, it will increase the complexity of the entire system, increase the risk of failure and difficulty of maintenance. Utility Model Content

[0003] The utility model aims to provide a multi-channel data processing device, which is used to solve the problem of increasing system complexity, failure risk and maintenance difficulty in the prior art of using multiple devices stacking to implement multi-channel concurrent data processing.

[0004] The utility model solves the above problems through the following technical solutions:

[0005] A multi-channel data processing device comprises a data processing carrier board, a main control FPGA chip and a power interface are arranged on the data processing carrier board, at least two groups of COMe female sockets are arranged on the data processing carrier board, the COMe female sockets are electrically connected to other COMe female sockets through PCB wiring on the data processing carrier board, each group of the COMe female sockets is used to cooperate with a group of COMe male sockets on an FPGA data processing board, a support member is fixed on the data processing carrier board, a threaded hole is arranged on the top of the support member, and the threaded hole is used to cooperate with the fixing hole on the FPGA data processing board.

[0006] A multi-channel data processing device includes an FPGA processing board. The FPGA processing board is connected to a data processing carrier board through a COMe connector. The data processing carrier board can connect two or more FPGA data processing boards to achieve multi-channel concurrent processing. The COMe mother socket is interconnected through PCB traces on the data processing carrier board to achieve communication between multiple FPGA data processing boards. Support members are used to highly support and fix the FPGA data processing board. The utility model can achieve multi-channel concurrent signal processing with one device, does not require equipment stacking, and reduces system complexity, failure risk and maintenance difficulty.

[0007] Furthermore, the data processing carrier board is also provided with a first network port unit, a debugging interface unit, a radio frequency interface unit, an indicator light unit, a communication interface unit and a reset button.

[0008] The setting of multiple types of interfaces facilitates the device to communicate with external devices and indicate the working status.

[0009] Furthermore, the data processing carrier board is fixed on the bottom plate of the chassis.

[0010] Furthermore, the power interface is arranged on the panel of the chassis, the first network port unit and the debugging interface unit extend to the panel of the chassis through corresponding interface connectors, the radio frequency interface unit is connected to the panel of the chassis through an SMA line, and the indicator light unit, the communication interface unit and the reset button extend to the panel of the chassis through an interface board.

[0011] The interface is externalized to facilitate connection with external devices / debugging / resetting and restarting devices / indicating device working status, etc.

[0012] Furthermore, the first network port unit includes at least one Gigabit network port and at least one 10G optical cage interface.

[0013] Furthermore, the communication interface unit is at least one RS232 interface.

[0014] Furthermore, a second network port unit is provided on the FPGA data processing board.

[0015] Furthermore, the second network port unit is at least one optical cage interface, and the optical cage interface extends to the panel through an optical cage connector.

[0016] Furthermore, the FPGA data processing board is provided with a power control circuit, and the FPGA on the FPGA data processing carrier board controls the power on and off of each FPGA data processing board. The access of the FPGA data processing board can be independently controlled by a switch to realize the channel cutting function.

[0017] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0018] (1) The utility model provides more data communication channels, greatly improves the communication rate bandwidth, does not require equipment stacking, and reduces system complexity, failure risk and maintenance difficulty.

[0019] (2) The number of channels of the utility model is adjustable, more flexible, and meets the requirements of low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of the utility model;

[0021] Figure 2 It is a plan view of the utility model in the chassis;

[0022] Figure 3 It is a structural diagram of the chassis panel;

[0023] Among them, 1-data processing carrier board; 2-FPGA data processing board; 3-interface board; 11-support; 12-COMe female socket; 13-power interface; 14-power management module; 15-time management module; 16-debugging interface; 17-Gigabit network port; 18-10G optical cage interface; 19-SMA; 21-fixing hole; 22-second network port unit; 23-COMe male socket; 31-reset button; 32-wiring harness connection interface; 33-indicator light unit; 34-communication interface unit. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below in conjunction with the embodiments, but the implementation manner of the present invention is not limited thereto.

[0025] Example:

[0026] Combined with Figure 1 As shown, a multi-channel data processing device includes a data processing carrier board 1, on which a main control FPGA chip and a power interface 13 are arranged, and at least 4 groups of COMe female sockets 12 are arranged on the data processing carrier board 1, and the COMe female sockets 12 are electrically connected to other COMe female sockets 12 on the data processing carrier board 1 through PCB wiring, and each group of the COMe female sockets 12 is used to cooperate with a group of COMe male sockets 23 on an FPGA data processing board 2, and a support member 11 is welded on the data processing carrier board 1, and a threaded hole is arranged on the top of the support member 11 (it can also be realized by directly welding a nut on the data processing carrier board 1), and the threaded hole is used to cooperate with the fixing hole 21 on the FPGA data processing board 2, and the FPGA data processing board 2 and the data processing carrier board 1 are plugged in through the COMe connector. Figure 2 shown.

[0027] The FPGA processing board is connected to the data processing carrier board through a COMe connector. The data processing carrier board 1 can connect two or more FPGA data processing boards 2 to achieve multi-channel concurrent processing. All the main control FPGA chips on the four FPGA data processing boards 2 can communicate with each other at high speed. The support member 11 is used to highly support and fix the FPGA data processing board 2. The utility model can achieve multi-channel signal concurrent processing with one device, without the need for device stacking, reducing system complexity, failure risk and maintenance difficulty.

[0028] The above four FPGA data processing boards 2 are completely identical. Each board contains two high-performance FPGA logic devices. The functions of the FPGA logic devices of each FPGA data processing board 2 are as follows:

[0029] 1) Realize high-speed interconnection and communication with another FPGA logic device on this board;

[0030] 2) Realize high-speed interconnection and communication with the other 6 FPGA logic devices of the FPGA data processing board 2;

[0031] 3) Conduct high-speed and low-speed signal interconnection and communication with the FPGA logic device of the data processing carrier board 1;

[0032] 4) Communicate with external fiber optic equipment through the optical cage interface;

[0033] 5) Realize high-speed data encoding and decoding, single-channel or multi-channel data forwarding, and feedback of communication status;

[0034] The data transmission carrier is designed with an FPGA logic device (a main control FPGA chip, which includes a power management module 14 and a time management module 15). The functions of the logic device are as follows:

[0035] 1) Configure the entire system clock to provide accurate clocks for all modules on the device;

[0036] 2) Manage the power supply of the entire system, including monitoring the voltage, current, and temperature of the equipment, and controlling the power switch of each FPGA data processing board 2;

[0037] 3) Manage and upgrade the eight FPGAs of the four FPGA data processing boards 2;

[0038] 4) Conduct high-speed and low-speed signal interconnection and communication with the eight FPGAs of the four FPGA data processing boards 2;

[0039] 5) Communicate with the external network through Gigabit Ethernet port 17;

[0040] 6) Realize 10G network interconnection communication with the external network through two 10G optical cage interfaces 18;

[0041] 7) The 4 LED lights on the control interface board 3 display the system status;

[0042] 8) Output debugging information or perform serial port control through the RS23234 interface on the interface board 3;

[0043] 9) The reset signal of the reset button 31 of the interface board 3 controls all boards to reset and perform self-reset.

[0044] The utility model does not improve the function of the FPGA chip of the board card, and directly applies the function of the FPGA in the board card in the prior art.

[0045] Furthermore, the data processing carrier board 1 is also provided with a first network port unit, a debugging interface 16 unit (including 2 debugging interfaces 16, used to debug all FPGAs), a radio frequency interface unit (SMA19 interface), an indicator light unit 33 (13 LED indicator lights, of which 8 LEDs are used to indicate the working status of the FPGAs on the 4 FPGA data processing boards 2, of which 4 LEDs are used to indicate the working status of the FPGAs on the data transmission carrier board, and the remaining 1 LED is used to indicate the power status), a communication interface unit 34 (2 RS232 interfaces) and a reset button 31. The first network port unit includes 2 Gigabit network ports 17 and 2 10G optical cage interfaces 18. The Gigabit network port 17 realizes the interconnection between the device and the external network or realizes the online upgrade of the main control chip of the FPGA data processing board 2 in the device. The 10G optical cage interface 18 is used for the data transmission carrier board to realize 10 Gigabit network communication with the external network.

[0046] The SMA19 interface is fixed to the front panel with an SMA19 straight-through connector, and then connected to the SMA19 connector of the data transmission carrier board with an RF coaxial cable. This interface is used to provide an external reference clock for the device.

[0047] The data transmission carrier board is provided with a clock management unit for realizing the clock synchronization of each board.

[0048] Furthermore, the data processing carrier board 1 is fixed to the bottom plate of the chassis, and the power interface 13 extends to the rear panel of the chassis to supply power to the entire device. The first network port unit and the debugging interface 16 unit extend to the panel of the chassis through corresponding interface connectors, the radio frequency interface unit is connected to the panel of the chassis through an SMA line, the indicator light unit 33, the communication interface unit 34 and the reset button 31 extend to the front panel of the chassis through the interface board 3, the interface board 3 is connected to the data transmission carrier board through a J63 connector and a cable, and the interface board 3 is fixed to the front panel by screws, as shown in FIG. Figure 3 Furthermore, the FPGA data processing board 2 is provided with a second network port unit 22, which is 8 optical cage interfaces, namely 8 optical fiber array interfaces, which use standard QSFP+2X2 optical cages. The four FPGA data processing boards 2 have a total of 32 optical cage interfaces, and all optical cage interfaces extend to the front panel through optical cage connectors.

[0049] Furthermore, a power switch is provided on the FPGA data processing board 2. The access of the FPGA data processing board 2 can be independently controlled by the switch to realize the channel trimming function. Channel trimming can also be performed by software through the main control FPGA of the data transmission carrier board, which is flexible and can also reduce power consumption.

[0050] The utility model supports 2-way Gigabit network ports, 34-way optical cage channel interfaces, a SAM port, an RS23234 serial port, and a debug port, wherein 2-way optical cage channel interfaces, 2-way Gigabit network interfaces, and 2-way debug ports are arranged on a data transmission carrier board, and the remaining 32-way optical cage channel interfaces are arranged on an FPGA data processing board 2. The utility model has multi-channel concurrent data transmission and processing capabilities, and can be used with various optical fiber devices.

[0051] Although the present invention is described herein with reference to the illustrative embodiments of the present invention, the above embodiments are merely preferred embodiments of the present invention, and the embodiments of the present invention are not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and implementations, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. A multi-channel data processing device, comprising a data processing carrier board, on which a main control FPGA chip and a power supply interface are arranged, characterized in that: At least two groups of COMe female sockets are arranged on the data processing carrier board, and the COMe female sockets are electrically connected with other COMe female sockets through PCB routing on the data processing carrier board. Each group of the COMe female sockets is used to cooperate with a group of COMe male sockets on the FPGA data processing board. A support member is fixed on the data processing carrier board, and a threaded hole is arranged on the top of the support member, and the threaded hole is used to cooperate with the fixing hole on the FPGA data processing board.

2. A multi-channel data processing device according to claim 1, characterized in that: The data processing carrier board is also provided with a first network port unit, a debugging interface unit, a radio frequency interface unit, an indicator light unit, a communication interface unit and a reset button.

3. A multi-channel data processing device according to claim 2, characterized in that: The data processing carrier board is fixed on the bottom plate of the chassis.

4. A multi-channel data processing device according to claim 3, characterized in that: The power interface is arranged on the panel of the chassis, the first network port unit and the debugging interface unit extend to the panel of the chassis through corresponding interface connectors, the radio frequency interface unit is connected to the panel of the chassis through an SMA line, and the indicator light unit, the communication interface unit and the reset button extend to the panel of the chassis through an interface board.

5. A multi-channel data processing device according to any one of claims 2 to 4, characterized in that: The first network port unit includes at least one Gigabit network port and at least one 10G optical cage interface.

6. A multi-channel data processing device according to claim 4, characterized in that: The communication interface unit is at least one RS232 interface.

7. A multi-channel data processing device according to claim 4, characterized in that: The FPGA data processing board is provided with a second network port unit.

8. A multi-channel data processing device according to claim 7, characterized in that: The second network port unit is at least one optical cage interface, and the optical cage interface extends to the panel through an optical cage connector.

9. A multi-channel data processing device according to claim 1, characterized in that: The FPGA data processing board is provided with a power control circuit, and the FPGA on the FPGA data processing carrier board controls the power on and off of each FPGA data processing board.

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