Display device

Abstract

A display device includes a substrate layer, a light emitting element, and a pixel circuit. The pixel circuit includes a first transistor, and the first transistor includes a metal oxide semiconductor pattern, a first gate electrode having a plurality of conductive layers, and a gate insulation pattern. An uppermost layer among the plurality of conductive layers is divided into a first portion adjacent to the drain region, a second portion adjacent to the source region, and a third portion between the first portion and the second portion. An upper surface of each of the first portion and the second portion may form a step with an upper surface of the third portion. The sum of the widths of the upper surfaces of the first and second portions may be less than the width of the upper surface of the third portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0063299 filed in the Korean Intellectual Property Office on May 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device, and more particularly, to a display device including an oxide transistor and a method of manufacturing the display device. Background Art

[0004] The display device includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel circuit for controlling the display element. The pixel circuit may include a plurality of transistors connected in an organizational structure.

[0005] A plurality of transistors may include a silicon semiconductor or a metal oxide semiconductor and further include electrodes and wires. The wires included in the transistors may be formed by patterning through an etching process. The process gas provided in the etching process may remain on the patterned wires and may cause corrosion to the wires. Therefore, various methods for preventing corrosion to the wires are being developed. Utility Model Content

[0006] The present disclosure may provide a display device having improved reliability and display quality.

[0007] The present disclosure also provides a method for manufacturing a display device.

[0008] An embodiment of a display device includes: a substrate layer; a light emitting element disposed on the substrate layer; and a pixel circuit disposed between the substrate layer and the light emitting element and electrically connected to the light emitting element, wherein the pixel circuit may include a first transistor. Here, the first transistor may include a metal oxide semiconductor pattern, a first gate and a gate insulation pattern. The metal oxide semiconductor pattern may include a drain region, a source region and a channel region disposed between the source region and the drain region. The first gate may be disposed on the metal oxide semiconductor pattern, overlapped with the channel region, and have a plurality of conductive layers. The gate insulation pattern may be disposed between the metal oxide semiconductor pattern and the first gate, and overlapped with the channel region. The uppermost layer among the plurality of conductive layers may be divided into a first portion adjacent to the drain region, a second portion adjacent to the source region, and a third portion located between the first portion and the second portion, each of the upper surface of the first portion and the upper surface of the second portion may form a step with the upper surface of the third portion, and in a cross section perpendicular to the substrate layer, the sum of the widths of the upper surface of the first portion and the upper surface of the second portion in one direction may be less than the width of the upper surface of the third portion in this direction.

[0009] In an embodiment, a side surface of the first gate electrode and a side surface of the gate insulation pattern may form a continuous inclined surface.

[0010] In an embodiment, the thickness of the third portion may be greater than the thickness of each of the first portion and the second portion.

[0011] In an embodiment, the first gate may include: a first layer disposed on the gate insulation pattern and including a first material; and a second layer disposed on the first layer and including a second material different from the first material, the first material having a resistivity lower than that of the second material.

[0012] In an embodiment, the first material may be aluminum and the second material may be titanium.

[0013] In an embodiment, the first gate may further include a third layer disposed between the gate insulating pattern and the first layer and including a third material different from the first material, the third material having a higher resistivity than the first material.

[0014] In an embodiment, the first material may be aluminum, and each of the second material and the third material may be titanium.

[0015] In an embodiment, the first layer may have a thickness greater than a thickness of the second layer and a thickness of the third layer.

[0016] In an embodiment, the third portion may include a first side surface adjacent to the first portion and a second side surface adjacent to the second portion, the first side surface may connect the upper surface of the first portion and the upper surface of the third portion, and the second side surface may connect the upper surface of the second portion and the upper surface of the third portion.

[0017] In an embodiment, the first transistor may further include a second gate, and the second gate may be disposed at a lower side of the metal oxide semiconductor pattern and electrically connected to the source region.

[0018] An embodiment of a method for manufacturing a display device includes: forming at least one transistor on a base substrate. The formation of the at least one transistor may include: forming a metal oxide semiconductor pattern on the base substrate; forming a preliminary insulating layer on the metal oxide semiconductor pattern; forming a conductive layer having an aluminum layer on the preliminary insulating layer; forming a photoresist pattern on the conductive layer; forming a first gate electrode from the conductive layer by using a first etching gas containing a chlorine-based gas; forming a gate insulating pattern from the preliminary insulating layer by using a second etching gas different from the first etching gas; and performing plasma surface treatment on the first gate electrode, the gate insulating pattern, and the photoresist pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention concept and together with the description are used to explain the principles of the present invention concept. In the accompanying drawings:

[0020] Figure 1 is a block diagram of a display device according to an embodiment of the present invention;

[0021] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention;

[0022] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present invention;

[0023] Figure 4 is a cross-sectional view of a transistor according to an embodiment of the present invention;

[0024] Figure 5A and Figure 5B are cross-sectional views each illustrating a partial configuration included in a transistor according to an embodiment of the present invention;

[0025] FIG. 6A to FIG. 6D is a cross-sectional view sequentially illustrating some operations of a method of manufacturing a display device according to an embodiment of the present utility model concept;

[0026] Figure 7 is a plan view of a manufacturing process system used in manufacturing a display device according to an embodiment;

[0027] FIG. 8A to FIG. 8C is a diagram showing TiF of a comparative example and an example x images of pollution assessment results;

[0028] Fig. 9A and Fig. 9B is a graph showing leakage current evaluation results of a comparative example and an example; and

[0029] Fig. 10A and Fig. 10B are images showing bright spot defect evaluation results of the comparative example and the example. DETAILED DESCRIPTION

[0030] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be comprehensive and complete and will fully convey the scope of the present invention to those skilled in the art.

[0031] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another element, it can be directly set on, directly connected to or coupled to the other element, or intervening elements can be set therebetween.

[0032] The same reference numerals or symbols refer to the same elements throughout. In the accompanying drawings, the thickness, proportions and sizes of the elements are exaggerated in order to effectively describe the technical content. As used herein, the word "or" means a logical "or", so unless the context indicates otherwise, "A, B or C" means "A and B and C", "A and B but not C", "A and C but not B", "B and C but not A", "A but not B and not C", "B but not A and not C", and "C but not A and not B".

[0033] It will be understood that although the terms "first", "second", etc. can be used to describe various elements, components, regions, layers or parts in this article, these elements, components, regions, layers or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part without departing from the scope of the present invention. Similarly, the second element, component, region, layer or part can be referred to as the first element, component, region, layer or part. As used in this article, the singular form "one" and "the (described)" are intended to also include plural forms unless the context clearly indicates otherwise.

[0034] In addition, terms such as "below", "on the lower side", "above", or "on the upper side" may be used to describe the relationship of elements illustrated in the drawings. These terms have relative concepts and are described based on directions indicated in the drawings.

[0035] It will be further understood that when used in this specification, the terms "comprises", "comprising" and "having" (and variations thereof) indicate the presence of stated features, integers, steps, operations, elements, parts or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts or groups thereof.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0037] Hereinafter, embodiments of the present inventive concept will be described with reference to the accompanying drawings.

[0038] Figure 1 1 is a block diagram of a display device DD according to an embodiment of the present invention. The display device DD includes a timing control unit TC, a scan drive circuit SDC, a data drive circuit DDC and a display panel DP. In this embodiment, the display panel DP is illustrated as an emissive display panel. The emissive display panel may include an organic light emitting display panel or an inorganic light emitting display panel.

[0039] The timing control unit TC receives an input image signal, converts the input image signal so that its data format is compatible with the interface specification of the data driving circuit DDC, and thus generates image data D-RGB. The timing control unit TC outputs the image data D-RGB and various control signals DCS and SCS.

[0040] The scan drive circuit SDC receives a scan control signal SCS from the timing control unit TC. The scan control signal SCS may include a vertical start signal for starting the operation of the scan drive circuit SDC, a clock signal for determining the output timing of the signal, etc. The scan drive circuit SDC generates a plurality of scan signals and sequentially outputs these signals through the corresponding scan signal lines SL11 to SL1n. In addition, the scan drive circuit SDC generates a plurality of emission control signals in response to the scan control signal SCS, and outputs the plurality of emission control signals through the corresponding emission signal lines EL1 to ELn.

[0041] Figure 1 It is illustrated that a plurality of scan signals and a plurality of emission control signals are output from one scan drive circuit SDC, but the embodiments of the present invention are not limited thereto. According to the embodiments of the present invention, the display device DD may include a plurality of scan drive circuits. In addition, according to the embodiments of the present invention, a drive circuit for generating a plurality of scan signals for output and a drive circuit for generating a plurality of emission control signals for output may be formed separately.

[0042] The data driving circuit DDC receives the data control signal DCS and the image data D-RGB from the timing control unit TC. The data driving circuit DDC converts the image data D-RGB into a data signal and outputs the data signal through a plurality of data lines DL1 to DLm to be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data D-RGB.

[0043] The display panel DP may include a plurality of groups of scan signal lines. Figure 1 The first group of scan signal lines SL11 to SL1n is exemplarily illustrated. The emissive display panel DP includes emission signal lines EL1 to ELn, data lines DL1 to DLm, first to second to third and fourth voltage lines VL1 to VL2 to VL3 to VL4 and a plurality of pixels PX.

[0044] The first group of scan signal lines SL11 to SL1n may extend in a first direction DR1 and may be arranged in a second direction DR2 crossing the first direction DR1. The data lines DL1 to DLm may cross the first group of scan signal lines SL11 to SL1n.

[0045] The first voltage line VL1 receives a first power supply voltage ELVSS. The second voltage line VL2 receives a second power supply voltage ELVDD. The second power supply voltage ELVDD has a level higher than the level of the first power supply voltage ELVSS. The third voltage line VL3 receives a reference voltage Vref (hereinafter, the first voltage). The fourth voltage line VL4 receives an initialization voltage Vint (hereinafter, the second voltage). The first voltage Vref has a level lower than the level of the second power supply voltage ELVDD. The second voltage Vint has a level lower than the level of the second power supply voltage ELVDD. In the present embodiment, the second voltage Vint may have a level lower than the level of the first voltage Vref and the level of the first power supply voltage ELVSS.

[0046] At least one of the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, and the fourth voltage line VL4 may include at least one of a line extending in the first direction DR1 and a line extending in the second direction DR2. Even if the line extending in the first direction DR1 and the line extending in the second direction DR2 of the voltage line are arranged Figure 3 Different layers among the plurality of insulating layers 10 to 30 shown in the figure may also be electrically connected to each other.

[0047] As above, reference has been made Figure 1 The display device DD according to the embodiment is described, but the display device DD according to the embodiment of the present invention is not limited thereto. According to the configuration of the pixel circuit, a signal line may be further added or omitted. In addition, the relationship of the electrical connection between the pixel PX and the signal line may be changed.

[0048] The plurality of pixels PX may include a plurality of groups for generating light of different colors. For example, a red pixel generating red light, a green pixel generating green light, and a blue pixel generating blue light may be included. The light-emitting element of the red pixel, the light-emitting element of the green pixel, and the light-emitting element of the blue pixel may include light-emitting layers formed of different materials.

[0049] The pixel circuit may include a plurality of transistors and at least one capacitor. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the transistors of the pixel circuit.

[0050] Figure 2 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present invention. Figure 2 The first group of scanning signal lines SL11 to SL1n (see FIG. Figure 1 ) and is connected to a plurality of data lines DL1 to DLm (see Figure 1) in the j-th data line DLj (or the first data line). The pixel PXij is connected to the i-th scan signal line SL2i in the second group of scan signal lines, and is connected to the i-th scan signal line SL3i in the third group of scan signal lines.

[0051] In the present embodiment, the pixel PXij may include a pixel circuit including a first transistor T1 to a fifth transistor T5, a first capacitor C1 and a second capacitor C2, and a light emitting element OLED. In the present embodiment, the first transistor T1 to the fifth transistor T5 are described as N-type transistors. However, the embodiments of the present invention are not limited thereto, and at least one of the first transistor T1 to the fifth transistor T5 may be a P-type transistor. In addition, according to the embodiments of the present invention, at least one of the first transistor T1 to the fifth transistor T5 may be omitted, or an additional transistor may be further included in the pixel PXij.

[0052] In the present embodiment, each of the first transistor T1 to the fifth transistor T5 is illustrated to include two gates, but at least one transistor may include only one gate. The upper gates G2-1, G3-1, G4-1, and G5-1 of the second transistor T2 to the fifth transistor T5 are illustrated to be electrically connected to the lower gates G2-2, G3-2, G4-2, and G5-2, but the embodiments of the present invention are not limited thereto. The lower gates G2-2, G3-2, G4-2, and G5-2 of the second transistor T2 to the fifth transistor T5 may be floating electrodes.

[0053] In the present embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. A node to which the gate G1-1 (hereinafter, the first gate or the first upper gate) of the first transistor T1 is connected may be defined as a first node ND1, and a node to which the source S1 of the first transistor T1 is connected may be defined as a second node ND2.

[0054] The light emitting element OLED includes a first electrode electrically connected to the second node ND2, a second electrode receiving the first power voltage ELVSS, and a light emitting layer disposed between the first electrode and the second electrode. The light emitting element OLED will be described in detail later.

[0055] The first transistor T1 is electrically connected between a second voltage line VL2 receiving a second power supply voltage ELVDD and a second node ND2. The first transistor T1 may include a source S1 (or a first source), a drain D1 (or a first drain), a channel region (or a semiconductor region), and a first upper gate G1-1 connected to the second node ND2. The first upper gate G1-1 may be electrically connected to the first node ND1. The first transistor T1 may further include a gate G1-2 (hereinafter, a first lower gate) connected to the second node ND2. The first transistor T1 controls a driving current of the light emitting element OLED based on the charging capacity of the first capacitor C1.

[0056] The second transistor T2 is electrically connected between the j-th data line DLj and the first node ND1. The second transistor T2 may include a source S2 (or a second source) connected to the first node ND1, a drain D2 (or a second drain) connected to the j-th data line DLj, a channel region, and a gate G2-1 (hereinafter, a second upper gate) connected to the first group i-th scan signal line SL1i. The second transistor T2 may further include a gate G2-2 (hereinafter, a second lower gate) electrically connected to the second upper gate G2-1. The third transistor T3 to the fifth transistor T5, which will be described later, may include upper gates G3-1, G4-1, and G5-1 corresponding to the second upper gate G2-1 and the second lower gate G2-2, respectively, and lower gates G3-2, G4-2, and G5-2. The second transistor T2 provides the data voltage to the first capacitor C1.

[0057] The third transistor T3 is electrically connected between the first node ND1 and the third voltage line VL3 receiving the first voltage Vref. The third transistor T3 may include a drain D3 (hereinafter, a third drain) connected to the first node ND1, a source S3 (hereinafter, a third source) connected to the third voltage line VL3, a channel region, and a third upper gate G3-1 connected to the second group i-th scan signal line SL2i. The third transistor T3 may further include a third lower gate G3-2 electrically connected to the third upper gate G3-1.

[0058] The fourth transistor T4 is electrically connected between the fourth voltage line VL4 receiving the second voltage Vint and the second node ND2. The fourth transistor T4 may include a drain D4 (hereinafter, a fourth drain) connected to the second node ND2, a source S4 (hereinafter, a fourth source) connected to the fourth voltage line VL4, a channel region, and a fourth upper gate G4-1 connected to the third group i-th scan signal line SL3i. The fourth transistor T4 may further include a fourth lower gate G4-2 electrically connected to the fourth upper gate G4-1.

[0059] The fifth transistor T5 is electrically connected between the second voltage line VL2 and the first drain D1 or the first source S1. In the present embodiment, the fifth transistor T5 may include a source S5 (hereinafter, the fifth source) connected to the second voltage line VL2, a drain D5 (hereinafter, the fifth drain) connected to the first drain D1, a channel region, and a fifth upper gate G5-1 connected to the i-th emission signal line ELi. The fifth transistor T5 may further include a fifth lower gate G5-2 electrically connected to the fifth upper gate G5-1.

[0060] The first capacitor C1 is electrically connected between the first node ND1 and the second node ND2. The first capacitor C1 includes a first electrode E1-1 connected to the first node ND1 and a second electrode E1-2 connected to the second node ND2.

[0061] The second capacitor C2 is electrically connected between the second voltage line VL2 and the second node ND2. The second capacitor C2 includes a first electrode E2-1 connected to the second voltage line VL2 and a second electrode E2-2 connected to the second node ND2.

[0062] Figure 3 is a cross-sectional view of a display panel DP according to an embodiment of the present invention. Figure 3 The diagram shows Figure 2 A cross section of a portion corresponding to the partial structure of the pixel PXij shown in FIG.

[0063] refer to Figure 3 , the display panel DP may include a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFE. The display panel DP may further include a functional layer such as an anti-reflection layer or a refractive index control layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layer as described below may include an organic layer and / or an inorganic layer.

[0064] The insulating layer, the semiconductor layer, and the conductive layer are formed by a coating process, a deposition process, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography and etching processes. Through these processes, semiconductor patterns, conductive patterns, signal lines, etc. are formed. Patterns set in the same layer may be formed by the same process.

[0065] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and the material is not particularly limited. The synthetic resin layer may include at least one of an acrylate resin, a methacrylate resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc. The base layer BL may include a first polyimide layer, a second polyimide layer, and an inorganic layer disposed between the first polyimide layer and the second polyimide layer.

[0066] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of layers. The multilayer inorganic layer may be composed of a barrier layer BRL and a buffer layer BFL to be described later. The barrier layer BRL and the buffer layer BFL may be selectively provided.

[0067] The barrier layer BRL prevents foreign matter from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these layers may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0068] A conductive layer (hereinafter, a first conductive layer) is disposed on the barrier layer BRL. The first conductive layer may include a plurality of conductive patterns. Figure 3 Some patterns of the first conductive layer are illustrated. A first lower gate G1-2, a second lower gate G2-2, and a first conductive pattern P1 are illustrated as examples of conductive patterns included in the first conductive layer.

[0069] The first conductive pattern P1 defines Figure 2 The first electrode E1 - 1 of the first capacitor C1 is shown in FIG. Figure 3 The first conductive pattern P1 and the first upper gate G1-1 are illustrated as being spaced apart from each other, but the first conductive pattern P1 and the first upper gate G1-1 may be electrically connected to each other. The first conductive pattern P1 and the first upper gate G1-1 may be connected to each other through conductive patterns provided at different layers, or may have an integral shape on a plane. The first lower gate G1-2 may be electrically connected to the second electrode E1-2 of the first capacitor C1. Meanwhile, in this specification, the first lower gate G1-2 may be referred to as a second gate.

[0070] The buffer layer BFL may be disposed on the barrier layer BRL to cover the first lower gate G1-2, the second lower gate G2-2, and the first conductive pattern P1. The buffer layer BFL improves the bonding force between the base layer BL and the semiconductor pattern or the conductive pattern. The buffer layer BFL may include at least one of a silicon oxide layer and a silicon nitride layer. When the buffer layer BFL includes both the silicon oxide layer and the silicon nitride layer, the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0071] The semiconductor layer is disposed on the buffer layer BFL. The semiconductor layer may include a plurality of semiconductor patterns. In the present embodiment, the semiconductor pattern may be a metal oxide semiconductor pattern SP. The metal oxide semiconductor pattern SP may include a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the metal oxide semiconductor pattern SP may include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) and an oxide thereof. The metal oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc.

[0072] The metal oxide semiconductor pattern SP may include a plurality of regions distinguished depending on whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, the reduced region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter, the unreduced region). The reduced region substantially serves as a source region, a drain region, or a signal transmission region of a transistor. The unreduced region substantially corresponds to a channel region (or a semiconductor region or an active region) of a transistor. In other words, a portion of the semiconductor pattern may be a channel region of a transistor, and another portion may be a source region or a drain region of a transistor, and another portion may be a signal transmission region.

[0073] In essence, a first upper gate G1-1 to be described later defines a channel region A1 of the first transistor T1, and a second upper gate G2-1 to be described later defines a channel region A2 of the second transistor T2. The length of the channel region A1 of the first transistor T1 may be determined to correspond to the width of the first upper gate G1-1, and the length of the channel region A2 of the second transistor T2 may be determined to correspond to the width of the second upper gate G2-1.

[0074] The source or drain region itself can be a reference Figure 2The source or drain of each of the transistors T1 to T5 described above. The source or drain of the transistors T1 to T5 may include a source region or a drain region of the aforementioned semiconductor pattern and a conductive pattern connected to the source region or the drain region. Hereinafter, for ease of description, the source region and the drain region of the metal oxide semiconductor pattern SP will be referred to as a source and a drain, respectively.

[0075] like Figure 3 As shown in FIG, the first transistor T1 includes a metal oxide semiconductor pattern SP having a source S1, a channel region A1, and a drain D1. The source S1 and the drain D1 of the first transistor T1 extend from the channel region A1 in opposite directions. The source S2, the channel region A2, and the drain D2 of the second transistor T2 are also formed by the metal oxide semiconductor pattern.

[0076] The aforementioned first lower gate G1-2 and the second lower gate G2-2 may have the function of a light shielding pattern. The first lower gate G1-2 and the second lower gate G2-2 may be respectively disposed at the lower sides of the channel region A1 of the first transistor T1 and the channel region A2 of the second transistor T2, and thus, may block light incident thereto from the outside. The light shielding pattern prevents external light from changing the voltage-current characteristics of each of the first transistor T1 and the second transistor T2.

[0077] The second conductive pattern P2 overlapping the first conductive pattern P1 in the thickness direction DR3 may be disposed on the buffer layer BFL. The second conductive pattern P2 defines Figure 2 4. A second electrode E1-2 of the first capacitor C1 and a second electrode E2-2 of the second capacitor C2 are shown in FIG.

[0078] The first insulating layer 10 is disposed on the buffer layer BFL. In the present embodiment, the first insulating layer 10 is not formed on the entire area of ​​the display panel DP, but only overlaps with the channel region of the transistor. However, the embodiments of the present invention are not limited thereto, and the first insulating layer 10 may also overlap with a specific conductive pattern to be described later. The first insulating layer 10 may include a plurality of insulating patterns. Figure 3 The first insulating pattern 10 - 1 and the second insulating pattern 10 - 2 are exemplarily illustrated. Figure 3 Unlike that shown in , according to an embodiment of the present invention, the first insulating layer 10 may not be patterned. In this case, the first insulating layer 10 may cover the metal oxide semiconductor pattern SP. The first insulating pattern 10-1 and the second insulating pattern 10-2 overlap with the first upper gate G1-1 and the second upper gate G2-1 to be described later, respectively. In addition, although not illustrated in the drawings, an insulating pattern overlapping with the second conductive pattern P2 may also be provided on the buffer layer BFL.

[0079] A conductive layer (hereinafter, a second conductive layer) is provided on the first insulating layer 10. The second conductive layer may include a plurality of conductive patterns each overlapping the first insulating layer 10. Figure 3 The first upper gate G1-1 and the second upper gate G2-1 are illustrated as examples of the conductive pattern of the second conductive layer. The edges of the conductive pattern of the second conductive layer and the edges of the insulating pattern of the first insulating layer 10 that overlap each other on a plane may be aligned. That is, the side surface of the conductive pattern of the second conductive layer and the side surface of the insulating pattern of the first insulating layer 10 may form a continuous inclined surface. For example, the edge of the first upper gate G1-1 and the edge of the first insulating pattern 10-1 may be aligned, and the edge of the second upper gate G2-1 and the edge of the second insulating pattern 10-2 may be aligned.

[0080] A second insulating layer 20 covering the first upper gate G1-1, the second upper gate G2-1, and the second conductive pattern P2 is disposed on the buffer layer BFL. The second insulating layer 20 may be an inorganic layer or an organic layer, and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may cover the source S1 and the drain D1 of the first transistor T1, and cover the source S2 and the drain D2 of the second transistor T2. The second insulating layer 20 may cover the side surface of each of the first insulating pattern 10-1 and the second insulating pattern 10-2.

[0081] The third insulating layer 30 is disposed on the second insulating layer 20. In the present embodiment, the third insulating layer 30 may be an organic layer. The third insulating layer 30 may have a single-layer structure, but the structure is not particularly limited. The third insulating layer 30 may also have a multi-layer structure. In an embodiment, the thickness of the third insulating layer 30 may be greater than the thickness of the second insulating layer 20, but the embodiments of the present invention are not limited thereto.

[0082] A conductive layer (hereinafter, third conductive layer) is disposed on the third insulating layer 30. The third conductive layer may include a plurality of conductive patterns. The third conductive layer may include a plurality of connection electrodes CNE1, CNE2, and CNE3, a first data line DLj, and a third conductive pattern P3.

[0083] The first connection electrode CNE1 may be connected to the source S1 of the first transistor T1 through a first contact hole H1 passing through the second insulating layer 20 and the third insulating layer 30, and may be connected to the first lower gate G1-2 through a second contact hole H2 passing through the buffer layer BFL and the second insulating layer 20 and the third insulating layer 30. The second connection electrode CNE2 is connected to the drain D1 of the first transistor T1 through a third contact hole H3 passing through the second insulating layer 20 and the third insulating layer 30. The third connection electrode CNE3 is connected to the second upper gate G2-1 through a fourth contact hole H4 passing through the second insulating layer 20 and the third insulating layer 30, and is connected to the second lower gate G2-2 through a fifth contact hole H5 passing through the buffer layer BFL and the second insulating layer 20 and the third insulating layer 30.

[0084] The first data line DLj is connected to the second drain electrode D2 through a sixth contact hole H6 passing through the second insulating layer 20 and the third insulating layer 30. The third conductive pattern P3 defines Figure 2 The first electrode E2-1 of the second capacitor C2 is shown in FIG.

[0085] The fourth insulating layer 40 covering the third conductive layer is disposed on the third insulating layer 30. In the present embodiment, the fourth insulating layer 40 may be an organic layer and may have a single-layer structure, but is not particularly limited thereto. The fourth insulating layer 40 may also have a multi-layer structure.

[0086] The light emitting element OLED and the pixel defining layer PDL may be disposed on the fourth insulating layer 40. The light emitting element OLED may include a first electrode AE, a hole control layer HCL, a light emitting layer EML, an electron control layer ECL, and a second electrode CE.

[0087] The first electrode AE ​​of the light emitting element OLED is disposed on the fourth insulating layer 40. The first electrode AE ​​may be an anode. The pixel defining layer PDL is disposed on the fourth insulating layer 40. The first electrode AE ​​is connected to the first connection electrode CNE1 through a seventh contact hole H7 passing through the fourth insulating layer 40.

[0088] The opening OP of the pixel definition film PDL exposes at least a portion of the first electrode AE. The opening OP of the pixel definition film PDL may define a light emitting area PXA. For example, a plurality of pixels PX (see Figure 1 ) can be set in a specific rule on the display panel DP (see Figure 1 ). A region in which a plurality of pixels PX are disposed may be defined as a pixel region, and one pixel region may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA.

[0089] The hole control layer HCL is disposed on the first electrode AE. The hole control layer HCL may be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. A common layer such as the hole control layer HCL may be commonly formed across a plurality of pixels PX. The hole control layer HCL may include a hole transport layer and a hole injection layer. In addition, the hole control layer HCL may further include an electron blocking layer.

[0090] The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be disposed only in a region corresponding to the opening OP. The light emitting layer EML may be formed to correspond to a plurality of pixels PX (see Figure 1 ) are separated. In the present embodiment, the patterned light-emitting layer EML is exemplarily illustrated, but the light-emitting layer EML may be commonly disposed in the light-emitting area PXA and the non-light-emitting area NPXA. The commonly disposed light-emitting layer EML may generate white light or blue light. In addition, the light-emitting layer EML may have a multilayer structure.

[0091] The electron control layer ECL is disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. In addition, the electron control layer ECL may further include a hole blocking layer. The second electrode CE is disposed on the electron control layer ECL. The electron control layer ECL and the second electrode CE are commonly disposed in the light emitting area PXA and the non-light emitting area NPXA.

[0092] The encapsulation layer TFE is disposed on the second electrode CE. The encapsulation layer TFE is commonly disposed in the light-emitting area PXA and the non-light-emitting area NPXA. In this embodiment, the encapsulation layer TFE directly covers the second electrode CE. According to an embodiment of the present invention, a capping layer directly covering the second electrode CE may be further provided. According to an embodiment of the present invention, the stacked structure of the light-emitting element OLED may also have a structure in which the light-emitting element OLED is Figure 3 The structure shown in the figure is an upside-down structure.

[0093] The encapsulation layer TFE includes an inorganic layer and / or an organic layer. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. According to an embodiment of the present invention, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. According to an embodiment of the present invention, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0094] Figure 4 is a cross-sectional view of a transistor according to an embodiment of the present invention. Figure 5A and Figure 5B are cross-sectional views each illustrating a partial configuration included in a transistor according to an embodiment of the present inventive concept. Figure 4 The diagram shows Figure 3A cross-sectional view corresponding to the first transistor T1 in FIG. Figure 5A and Figure 5B The diagram includes Figure 4 An enlarged view of a first upper gate G1 - 1 (hereinafter, first gate) in the first transistor T1 in FIG.

[0095] refer to Figure 4 , the buffer layer BFL may include a first buffer layer BFL1, and further include a second buffer layer BFL2. For example, the buffer layer BFL may include a first buffer layer BFL1 disposed on the barrier layer BRL, and further include a second buffer layer BFL2 disposed between the barrier layer BRL and the first buffer layer BFL1. In an embodiment, the first buffer layer BFL1 may be a silicon oxide layer, and the second buffer layer BFL2 may be a silicon nitride layer.

[0096] The metal oxide semiconductor pattern SP of the first transistor T1 may be disposed on the buffer layer BFL. The metal oxide semiconductor pattern SP may be disposed on the first buffer layer BFL1 which is a silicon oxide layer. The source S1, the channel region A1, and the drain D1 of the first transistor T1 may be formed by the metal oxide semiconductor pattern SP. In cross section, the source S1 and the drain D1 may extend from the channel region A1 in opposite directions.

[0097] The first insulating pattern 10-1 may be disposed on the buffer layer BFL. The first insulating pattern 10-1 overlaps at least a portion of the metal oxide semiconductor pattern SP. The first insulating pattern 10-1 may overlap the channel region A1 of the metal oxide semiconductor pattern SP. The first insulating pattern 10-1 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. For example, the first insulating pattern 10-1 may include silicon oxide (SiO x ). The first insulating pattern 10 - 1 may be referred to as a gate insulating pattern.

[0098] The first upper gate G1-1 is disposed on the first insulating pattern 10-1. The first upper gate G1-1 overlaps at least a portion of the metal oxide semiconductor pattern SP. For example, the first upper gate G1-1 overlaps the channel region A1 of the metal oxide semiconductor pattern SP.

[0099] The first upper gate G1-1 may include a lower surface G1-B adjacent to the first insulating pattern 10-1 and an upper surface G1-U opposite to the lower surface G1-B and spaced apart from the first insulating pattern 10-1. The lower surface G1-B of the first upper gate G1-1 may be a surface in contact with the first insulating pattern 10-1. The upper surface G1-U of the first upper gate G1-1 may form steps SA and SB.

[0100] The first upper gate G1-1 may include a plurality of conductive layers stacked in the thickness direction DR3. The first upper gate G1-1 may have steps SA and SB on the uppermost layer among the plurality of conductive layers. The first upper gate G1-1 may form steps SA and SB on the upper surface of the uppermost layer among the plurality of conductive layers. The steps SA and SB of the first upper gate G1-1 may be formed on the edge of the first upper gate G1-1 in an etching process to be described later. The uppermost layer of the first upper gate G1-1 may be a layer disposed farthest from the first insulating pattern 10-1 among the plurality of conductive layers included in the first upper gate G1-1. At the same time, the lowermost layer of the first upper gate G1-1 may be a layer adjacent to the first insulating pattern 10-1 among the plurality of conductive layers included in the first upper gate G1-1.

[0101] In cross section, the uppermost layer of the first upper gate G1-1 may have a first step SA at a position adjacent to the source S1 and a second step SB at a position adjacent to the drain D1. The first step SA and the second step SB formed in the same etching process of the first upper gate G1-1 may have substantially the same shape.

[0102] The second insulating layer 20 is disposed on the first insulating pattern 10-1 and covers the first upper gate G1-1. The second insulating layer 20 tightly covers the first upper gate G1-1 without protruding at portions of the first step SA and the second step SB. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but embodiments of the present invention are not limited thereto.

[0103] Figure 5A The first upper gate G1-1 including two conductive layers is exemplarily illustrated, and Figure 5B The first upper gate G1 - 1 including three conductive layers is exemplarily illustrated.

[0104] refer to Figure 5A , the first upper gate G1-1 may include a first layer G1-1a disposed on the first insulating pattern 10-1 and a second layer G1-1b disposed above the first layer G1-1a. In addition, the first upper gate G1-1 may further include a conductive layer disposed below the first layer G1-1a. For example, Figure 5B As shown in FIG. 1 , the first upper gate G1-1 may further include a third layer G1-1c located below the first layer G1-1a. The third layer G1-1c may be disposed between the first layer G1-1a and the first insulating pattern 10-1.

[0105] The first layer G1-1a may include a first material having conductivity. The first layer G1-1a may have a resistance lower than that of the second layer G1-1b and the third layer G1-1c. The first layer G1-1a may have a resistance of about 0.5Ω or less. For example, the first material may include aluminum (Al). The first layer G1-1a may be an aluminum layer, but embodiments of the present invention are not limited thereto.

[0106] The conductivity of the first layer G1-1a may substantially determine the conductivity of the first upper gate G1-1. Therefore, since the material constituting the first layer G1-1a has a relatively low resistivity, the first upper gate G1-1 having a low resistance characteristic may be formed. According to the embodiment of the present invention, the display panel DP (see Figure 1 ) high speed driving may be possible and RC delay may be easily overcome, and thus, a high resolution display panel DP (see Figure 1 ) may be possible. Therefore, the display device DD (see Figure 1 )’s display characteristics and can reduce power consumption.

[0107] The second layer G1-1b may be disposed on the first layer G1-1a. The second layer G1-1b includes a second material. The second material may have conductivity. The second material may be different from the first material. The second material may be relatively higher in rigidity than the first material. In forming a contact hole (eg, Figure 3 During the dry etching process of H1, H2 and H3 in the embodiment of the present invention, the second layer G1-1b can block the first layer G1-1a from being contacted by the etching gas. Accordingly, damage to the first layer G1-1a can be prevented. Compared with the first material, the second material can have a higher corrosion resistance to the etching gas. For example, when the etching gas is fluorine-based and the first layer G1-1a includes aluminum, the second layer G1-1b can include titanium (Ti), but the embodiments of the present invention are not limited thereto. The thickness of the second layer G1-1b can be less than the thickness of the first layer G1-1a.

[0108] The third layer G1-1c is disposed below the first layer G1-1a. The third layer G1-1c may be disposed separately from the second layer G1-1b, with the first layer G1-1a therebetween. In an embodiment, when the first upper gate G1-1 includes the first to third layers G1-1a, G1-1b, and G1-1c, the third layer G1-1c may be disposed adjacent to the metal oxide semiconductor pattern SP and may contact the first insulating pattern 10-1. The third layer G1-1c includes a third material. The third material may have electrical conductivity. The third material may be different from the first material and the same as the second material. For example, the third layer G1-1c may include titanium (Ti), but embodiments of the present invention are not limited thereto.

[0109] The first layer G1-1a may have a first thickness d1. The second layer G1-1b may have a second thickness d2, and the third layer G1-1c may have a third thickness d3. The second thickness d2 and the third thickness d3 may be substantially the same. The second thickness d2 and the third thickness d3 may be less than the first thickness d1.

[0110] refer to Figure 5A and Figure 5B , the first upper gate G1-1 may have a step on the uppermost layer due to an etching process to be described later. The first upper gate G1-1 may have a step on the second layer G1-1b corresponding to the uppermost layer.

[0111] The second layer G1-1b may include a lower surface G1-Bb in contact with the first layer G1-1a and an upper surface G1-Ub opposite to the lower surface G1-Bb. The upper surface G1-Ub of the second layer G1-1b may include a first surface G1-U1, a second surface G1-U2, and a third surface G1-U3 divided by steps. The first surface G1-U1 may be a surface provided between the second surface G1-U2 and the third surface G1-U3. The second surface G1-U2 may be adjacent to the drain region (e.g., Figure 4 The third surface G1-U3 may be adjacent to the source region (eg, Figure 4 In an embodiment, the second layer G1-1b may be divided into a first portion P11 including the second surface G1-U2, a second portion P12 including the third surface G1-U3, and a third portion P13 including the first surface G1-U1. The third portion P13 may include a first side surface G1-S1 and a second side surface G1-S2 connected to the first surface G1-U1. The first side surface G1-S1 may be adjacent to the first portion P11 and may connect the first surface G1-U1 and the second surface G1-U2 together. The second side surface G1-S2 may be adjacent to the second portion P12 and may connect the first surface G1-U1 and the third surface G1-U3 together.

[0112] In an embodiment, the second surface G1-U2 and the third surface G1-U3 may each have a height lower than that of the first surface G1-U1. Therefore, on the upper surface of the second layer G1-1b, the upper surface of the first portion P11 and the upper surface of the second portion P12 may form a step with the upper surface of the third portion P13, and the third portion P13 may have a thickness greater than that of the first portion P11 and the second portion P12.

[0113] On the second layer G1-1b, the first surface G1-U1 has a first width W1. The second surface G1-U2 may have a second width W2, and the third surface G1-U3 may have a third width W3. In an embodiment, the first width W1 may be greater than the second width W2 and the third width W3. According to an embodiment of the present invention, since the amount of loss of the photoresist pattern formed on the first gate by the etching process to be described later is minimized, the second width W2 and the third width W3 may each be significantly smaller than the first width W1. Therefore, the sum of the second width W2 and the third width W3 may be significantly smaller than the first width W1. This structure of the first gate is formed by an etching operation in a manufacturing process of a display device according to an embodiment to be described later, and thus, the display device DD according to the embodiment can provide excellent display quality.

[0114] In the following, reference will be made to FIG. 6A to FIG. 6D as well as Figure 7 A method of manufacturing a display panel according to an embodiment of the present inventive concept is described.

[0115] The method for manufacturing a display device according to an embodiment may include forming at least one transistor on a base substrate. In an embodiment, the formation of the at least one transistor may include forming a metal oxide semiconductor pattern, forming a preliminary insulating layer, forming a conductive layer, forming a photoresist pattern, forming a first gate electrode, forming a gate insulating pattern, and performing plasma surface treatment. By the method for manufacturing a display device according to an embodiment, the previously referenced Figure 3 , Figure 4 , Figure 5A and Figure 5B The display panel DP and the first transistor T1 are described.

[0116] In the method of manufacturing a display device according to an embodiment, at least one transistor to be formed on the base substrate may include the first transistor T1 described previously. Accordingly, the previous description of the first transistor T1 may also apply to the transistor to be formed on the base substrate.

[0117] The method for manufacturing a display device according to an embodiment may further include forming a light emitting element electrically connected to the metal oxide semiconductor pattern. Meanwhile, in the method for manufacturing a display device according to an embodiment, the previous description of the light emitting element OLED electrically connected to the metal oxide semiconductor pattern SP may also apply to the light emitting element.

[0118] FIG. 6A to FIG. 6D are cross-sectional views sequentially illustrating some operations of a method of manufacturing a display device according to an embodiment of the present inventive concept. FIG. 6A to FIG. 6D The formation of the previously described first transistor T1 in the method of manufacturing the display device according to the embodiment is exemplarily illustrated. FIG. 6A to FIG. 6D Each of the Figure 5B The corresponding cross section. Figure 7 is a plan view of a manufacturing process system used when manufacturing a display device according to an embodiment. Figure 7 A system used when forming a first gate electrode in a method of manufacturing a display device is schematically illustrated.

[0119] refer to Fig. 6A The formation of at least one transistor (hereinafter, the formation of the transistor) includes forming a metal oxide semiconductor pattern SP on the base substrate BS. For example, the metal oxide semiconductor pattern SP may be formed on the base substrate BS by depositing indium gallium zinc oxide (IGZO). The metal oxide semiconductor pattern SP may be formed on the base substrate BS by depositing indium gallium zinc oxide (IGZO) by physical vapor deposition or chemical vapor deposition. The base substrate BS may include Figure 3 , the layers of the base layer BL, the barrier layer BRL, and the buffer layer BFL are illustrated in FIG, but embodiments of the present inventive concept are not limited thereto.

[0120] like Fig. 6A As shown in FIG. 1 , the formation of the transistor may further include forming a preliminary insulating layer INS on the metal oxide semiconductor pattern SP. The preliminary insulating layer INS may be formed by depositing or coating an insulating material. In this embodiment, the preliminary insulating layer INS may be formed with Figure 3 The first insulating layer 10 shown in FIG. 1 corresponds to the first insulating layer 10 shown in FIG. 1 , but embodiments of the present inventive concept are not limited thereto.

[0121] In addition, the formation of the transistor may further include forming a conductive layer PG1-1 on the preliminary insulating layer INS. The conductive layer PG1-1 may include a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3. The first metal layer ML1 may be formed on the preliminary insulating layer INS. The second metal layer ML2 may be formed on the first metal layer ML1, and the third metal layer ML3 may be formed on the second metal layer ML2.

[0122] In an embodiment, the first to third metal layers ML1, ML2, and ML3 may be respectively Figure 5B For example, the first metal layer ML1 may correspond to the third layer G1-1c, the second metal layer ML2 may correspond to the first layer G1-1a, and the third metal layer ML3 may correspond to the second layer G1-1b.

[0123] The first to third metal layers ML1, ML2, and ML3 may each be formed by depositing a conductive material. The first metal layer ML1 may include the aforementioned third material. For example, the third material may include titanium, but the embodiments of the present inventive concept are not limited thereto.

[0124] The second metal layer ML2 may include the aforementioned first material. The second metal layer ML2 may include a material having a low resistivity. The second metal layer ML2 may have a resistance of about 0.5Ω or less. The second metal layer ML2 may include a material having a resistance of about 3×10 -8 The second metal layer ML2 may have a thickness greater than that of the first metal layer ML1 .

[0125] The third metal layer ML3 is formed on the second metal layer ML2. The third metal layer ML3 may include the aforementioned second material. The third metal layer ML3 may include the same material as the first metal layer ML1. For example, the third metal layer ML3 may include titanium, but the embodiments of the present invention are not limited thereto.

[0126] In an embodiment, the formation of the transistor may further include forming a photoresist pattern PR on the conductive layer PG1-1. The photoresist pattern PR may be used as a mask in an etching process to be described later.

[0127] Although not illustrated in the drawings, in forming the photoresist pattern PR, a photoresist layer may be formed by applying a photoresist material onto the conductive layer PG1-1, and then, through an exposure process, the photoresist layer may be patterned to form the photoresist pattern PR. The photoresist material may be a negative photoresist material or a positive photoresist material.

[0128] refer to Figure 6B, the formation of the transistor may further include forming a first gate. The first gate may be formed by the conductive layer PG1-1. In an embodiment, the first gate may be formed by a first etching process in which the conductive layer PG1-1 is dry-etched by providing a first etching gas EG1. In the first etching process, a portion of the conductive layer PG1-1 that is not covered by the photoresist pattern PR used as a mask may be etched by the first etching gas EG1. In an embodiment, the first to third metal layers ML1, ML2, and ML3 of the conductive layer PG1-1 may be formed by being patterned simultaneously through a mask for the photoresist pattern PR. Accordingly, the patterned first to third metal layers ML1, ML2, and ML3 may have side surfaces that are aligned in cross section. That is, the patterned first to third metal layers ML1, ML2, and ML3 may have side surfaces that form a continuous slope. However, this is an example, and the first to third metal layers ML1, ML2, and ML3 may have side surfaces that are not aligned in cross section.

[0129] The first etching gas EG1 may include a chlorine-based gas to improve etching efficiency. The chlorine-based gas may include chlorine (Cl 2 ) gas and boron trichloride (BCl 3 ) gases. At this time, the chlorine-based gas provided as the first etching gas EG1 may be in the form of chloride ions (Cl - ) remains on the surface of the first gate, and chloride ions (Cl - ) may cause corrosion to the first gate. For example, chloride ions (Cl - ) may react with aluminum included in the second metal layer ML2 to form byproducts such as and cause corrosion to the first gate. Therefore, the method of manufacturing a display device according to an embodiment of the present invention may include removing chloride ions (Cl - ). Chloride ion (Cl - ) can be processed by plasma post-treatment device RPA (see Fig.6D ) is removed and will be referenced later Fig.6D Description of the chloride ion (Cl - ) removal.

[0130] refer to Figure 6C The formation of the transistor according to the embodiment of the present invention may further include the formation of a gate insulation pattern. The gate insulation pattern may be formed by a preliminary insulation layer INS. In an embodiment, the gate insulation pattern may be formed by providing an etching gas to the preliminary insulation layer INS before the plasma surface treatment is performed. During the plasma surface treatment, chloride ions (Cl - ) can be supplied by providing water vapor (H 2O) Plasma post-treatment device RPA (see Fig.6D ) is removed, and in this process, a portion of the photoresist pattern PR may be removed due to water vapor (H 2 O) plasma. In the method for manufacturing a display device according to an embodiment, since the preliminary insulating layer INS is etched before the plasma surface treatment is performed, it is possible to form a gate insulating pattern with a minimum loss of the photoresist pattern PR. Accordingly, the amount of byproducts deposited on the surface of the gate insulating pattern can be significantly reduced, thereby preventing leakage current from occurring between the first gate and the metal oxide semiconductor pattern SP. The byproducts may be TiF generated due to damage to the uppermost layer (e.g., the third metal layer ML3) of the first gate by the etching gas. x The non-volatile material may be used, but the embodiments of the present invention are not limited thereto.

[0131] The gate insulating pattern may be formed by a second etching process in which the preliminary insulating layer INS is dry-etched by providing a second etching gas EG2. In the process for dry-etching the preliminary insulating layer INS, the photoresist pattern PR and the conductive layer PG1-1 that has been etched by the first etching process are used as masks, and portions of the preliminary insulating layer INS that are not covered by the photoresist pattern PR and the conductive layer PG1-1 may be etched by the second etching gas EG2. In an embodiment, the conductive layer PG1-1 and the preliminary insulating layer INS after etching may have side surfaces that are aligned in cross section. For example, the conductive layer PG1-1 and the preliminary insulating layer INS after etching may have side surfaces that form a continuous slope.

[0132] In an embodiment, the preliminary insulating layer INS may include silicon oxide (SiO x ). Accordingly, the second etching gas EG2 may be different from the first etching gas EG1 used in the first etching process (see Figure 6B The second etching gas EG2 may include tetrafluoromethane (CF 4 ) gas and oxygen (O 2 ) gas. By using tetrafluoromethane (CF 4 ) gas and oxygen (O 2 ) gas can have an excellent etching profile in terms of uniformity, side tilt angle, etc. At the same time, the second etching gas EG2 is not necessarily limited to tetrafluoromethane (CF 4 ) gas or oxygen (O 2 ) gas, and the type may vary according to aluminum oxide, titanium oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, etc. included in the preliminary insulating layer INS.

[0133] refer to Fig.6DThe formation of the transistor according to the embodiment of the present invention may further include chloride ions (Cl - ) removal. - ) may be removed by performing plasma surface treatment on the first gate, the gate insulation pattern, and the photoresist pattern PR. The plasma surface treatment is used to prevent corrosion of the first to third metal layers ML1, ML2, and ML3 and the preliminary insulation layer INS etched by the first etching process and the second etching process, and may be performed on the first gate and the gate insulation pattern formed after the first etching process and the second etching process, and on the photoresist pattern PR.

[0134] For example, after the first etching process, the chloride ions (Cl - ) byproduct RS may remain on the surface of the conductive layer PG1-1 not covered by the photoresist pattern PR. - ) may cause corrosion to the first gate, so in the formation of the transistor according to the embodiment, the byproduct RS can be removed by performing surface treatment on the first gate, the gate insulation pattern and the photoresist pattern PR through a plasma post-treatment apparatus RPA.

[0135] In an embodiment, the plasma post-treatment device RPA may include a process gas generator VZ and a plasma generator RPG. The process gas generator VZ and the plasma generator RPG may be connected via a gas pipeline PG. The process gas generator VZ may generate a process gas and provide the process gas to the plasma generator RPG via the gas pipeline PG. The process gas provided to the plasma generator RPG may be water vapor H 2 Although not shown in the drawings, the plasma post-treatment device RPA may be disposed in a chamber. The chamber may provide a space for a plasma surface treatment process to be performed. During the plasma surface treatment process, the internal space of the chamber may be tightly closed from the outside. The chamber may include at least one outlet for exhausting internal gas.

[0136] For example, the plasma generator RPG may receive water vapor from the process gas generator VZ to generate plasma. The plasma generator RPG may generate a large amount of plasma radicals RD to be provided to the etched conductive layer PG1-1, the etched preliminary insulating layer INS, and the photoresist pattern PR. The radicals RD may include OH, H, or O, and may be ejected from the plasma generator RPG to the entire area of ​​the upper surface of the base substrate BS on which the conductive layer PG1-1, the preliminary insulating layer INS, etc. are disposed. In an embodiment, the radicals RD react with chloride ions (Cl 2) remaining on the surface of the etched conductive layer PG1-1, etc. -) and are discharged to the outside of the chamber in the form of hydrochloric acid (HCl). In addition, the free radicals RD can help improve the ashing ability of removing the photoresist pattern PR in a subsequent process.

[0137] Although not illustrated in the drawings, the formation of the transistor may further include removing the photoresist pattern PR after the plasma surface treatment is performed. The photoresist pattern PR may be removed by a wet etching process by providing an etching solution. In addition, the formation of the transistor may further include cleaning the surface of the first gate after the first etching process and the second etching process and the plasma surface treatment are performed.

[0138] refer to Figure 7 , the formation of the transistor described previously can be performed by a single system (1 system) process. The single system (1 system) process can be formed by a process system VC. An internal space for a first etching process, a second etching process, and a plasma surface treatment process to be performed can be defined in the process system VC. The process system VC can be a vacuum chamber and can include first to third chambers CEC, CIC, and RPC and a transfer chamber TC.

[0139] In an embodiment, in a single system (1 system) process, the above-mentioned first etching process and second etching process and plasma surface treatment process can be performed in the first to third chambers CEC, CIC and RPC. The single system process can be performed along the first forward direction PS. The first forward direction PS may mean that the process is performed in the order of the first chamber CEC, the second chamber CIC and the third chamber RPC. For example, a first etching process for forming a first gate electrode can be performed in the first chamber CEC. A second etching process for forming a gate insulation pattern can be performed in the second chamber CIC. In addition, a plasma surface treatment process for applying surface treatment to the first gate electrode, etc. can be performed in the third chamber RPC. In addition, the movement between the first to third chambers CEC, CIC and RPC can be performed through the transfer chamber TC.

[0140] In a single-system (1-system) process, a first etching process, a second etching process, and a surface treatment process can be respectively performed in different chambers in the same equipment, and these processes can be continued without vacuum interruption through a load locking system LC between the first to third chambers CEC, CIC, and RPC.

[0141] In the method for manufacturing a display device according to an embodiment of the present invention, a plasma surface treatment process for preventing corrosion of the first gate electrode can be performed after a first etching process for forming the first gate electrode and a second etching process for forming the gate insulating pattern. Accordingly, the amount of loss of the photoresist pattern PR can be reduced, thereby preventing the byproduct RS containing chloride ions from remaining on the surface of the first gate electrode and the gate insulating pattern. Therefore, in the method for manufacturing a display device according to an embodiment, the occurrence of leakage current between the metal oxide semiconductor pattern SP and the first gate electrode is prevented, and therefore, a display device with improved display quality and reliability can be manufactured.

[0142] Table 1 and FIG. 8A to FIG. 10B The display device formed by the method of manufacturing a display device according to the embodiment of the present invention and the display device formed by the manufacturing method according to the comparative example are evaluated. In Table 1, the example corresponds to a transistor manufactured by sequentially performing a first etching process and a second etching process and then performing a plasma surface treatment, and a display device including the transistor. In particular, the example is compared with the display device formed by the method of manufacturing a display device according to the embodiment of the present invention. FIG. 6A to FIG. 6D The transistor manufactured by the described process sequence corresponds to a display device including the transistor.

[0143] Meanwhile, in Table 1, the comparative example corresponds to a transistor manufactured by a method for manufacturing a display device different from the example in process sequence and a display device including the transistor. In the comparative example, the aforementioned first etching process is performed, then a plasma surface treatment process is performed, and then a second etching process is performed. In the example and the comparative example of Table 1, all other conditions are the same in the process except for the process sequence.

[0144] FIG. 8A to FIG. 8C is a diagram showing TiF of a comparative example and an example x Image of the results of the contamination assessment. Fig. 8A and Figure 8B is a TEM image of a transistor of a comparative example, and Figure 8C is a TEM image of an example transistor.

[0145] Fig. 9A and Fig. 9B are graphs showing the results of leakage current evaluation of the comparative example and the example, respectively. Fig. 9A is a graph showing voltage-current characteristics of a comparative example, and Fig. 9B is a graph showing voltage-current characteristics of an example. Fig. 10A and Fig. 10B are images showing the results of bright spot defect evaluation of the comparative example and the example, respectively. Fig. 10A is an image showing the result of bright spot defect evaluation of a comparative example, and Fig. 10B are images showing the results of bright spot defect evaluation of an example.

[0146] [Table 1]

[0147]

[0148] Reference Table 1, Fig. 8A , Figure 8B , Fig. 9A and Fig. 10A It can be seen that in the display device of the comparative example, TiF x contamination, and leakage current occurs between the metal oxide semiconductor pattern and the first gate, thereby generating a bright spot defect.

[0149] In comparison, see Table 1. Figure 8C , Fig. 9B and Fig. 10B It can be seen that in the display device of the example manufactured by performing the first etching process and the second etching process according to the embodiment of the present invention and then performing the plasma surface treatment, no TiF deposition occurs on the surface of the transistor. x The contamination is eliminated, and therefore, leakage current does not occur between the metal oxide semiconductor pattern and the first gate electrode. Therefore, it is seen that the exemplary display device does not have a bright spot defect.

[0150] According to the method of manufacturing a display device according to an embodiment, by reducing the amount of photoresist loss in the gate etching process, it is possible to prevent byproducts from adhering to the surfaces of the gate and the gate insulating layer, and thus prevent leakage current from occurring between the oxide semiconductor pattern and the gate, thereby manufacturing a display device with improved display quality and reliability.

[0151] The display device according to the embodiment may provide excellent display quality through the foregoing method of manufacturing the display device.

[0152] Although the embodiments of the present invention have been described, it will be understood that the present invention should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present invention as claimed.

[0153] Therefore, the scope of the inventive concept should not be limited to the contents described in the specific embodiments of the specification, but should be defined by the claims.

Claims

1. A display device, comprising: basal layer; A light emitting element is disposed on the base layer; as well as a pixel circuit disposed between the base layer and the light emitting element and electrically connected to the light emitting element, Wherein, the pixel circuit comprises a first transistor, The first transistor comprises: A metal oxide semiconductor pattern having a drain region, a source region, and a channel region disposed between the source region and the drain region; a first gate, disposed on the metal oxide semiconductor pattern, overlapping the channel region, and having a plurality of conductive layers; and a gate insulating pattern disposed between the metal oxide semiconductor pattern and the first gate and overlapping the channel region, The uppermost layer among the plurality of conductive layers is divided into a first portion adjacent to the drain region, a second portion adjacent to the source region, and a third portion between the first portion and the second portion, Each of the upper surface of the first portion and the upper surface of the second portion forms a step with the upper surface of the third portion, and In a cross section perpendicular to the base layer, a sum of widths of the upper surface of the first portion and the upper surface of the second portion in one direction is smaller than a width of the upper surface of the third portion in the one direction.

2. The display device according to claim 1, wherein: A side surface of the first gate and a side surface of the gate insulation pattern form a continuous inclined surface.

3. The display device according to claim 1, wherein: The third portion has a thickness greater than a thickness of each of the first portion and the second portion.

4. The display device according to claim 1, wherein: The first gate comprises: a first layer disposed on the gate insulating pattern and comprising a first material; and a second layer disposed on the first layer and comprising a second material different from the first material, The first material has a resistivity lower than a resistivity of the second material.

5. The display device according to claim 4, wherein: The first material is aluminum and the second material is titanium.

6. The display device according to claim 4, wherein: The first gate further includes a third layer disposed between the gate insulating pattern and the first layer and including a third material different from the first material, The third material has a resistivity higher than the resistivity of the first material.

7. The display device according to claim 6, wherein: The first material is aluminum, and Each of the second material and the third material is titanium.

8. The display device according to claim 6, wherein: The first layer has a thickness greater than a thickness of the second layer and a thickness of the third layer.

9. The display device according to claim 6, wherein: The second layer is divided into a first portion adjacent to the drain region, a second portion adjacent to the source region, and a third portion between the first portion and the second portion, and Each of an upper surface of the first portion and an upper surface of the second portion forms a step with an upper surface of the third portion.

10. The display device according to any one of claims 1 to 9, wherein: The third portion includes a first side surface adjacent to the first portion and a second side surface adjacent to the second portion, The first side surface connects the upper surface of the first portion and the upper surface of the third portion, and The second side surface connects the upper surface of the second portion and the upper surface of the third portion.

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