Connecting device and testing device
By designing a probe card with the same pad spacing as the device under test of the photonic integrated circuit chip, the problems of low efficiency and complex operation of traditional multi-probe test are solved, and efficient and accurate electrical performance testing is achieved.
Patent Information
- Application Number
- CN202420823548.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-04-19
AI Technical Summary
In traditional solutions, multiple DC probes are used to test electrical performance of devices to be tested with complex structures or large numbers of test devices in photonic integrated circuit chips, which are low test efficiency, complex operation and difficult to achieve.
A connection device is provided, including a photonic integrated circuit chip and a probe card. The probe pin interval of the probe card is consistent with the pad interval of the device to be tested. The multiple probe pins of the probe card are connected to the pads of the device to be tested of the photonic integrated circuit chip, and are used to transmit incoming and outgoing DC signals to test the electrical performance of the device to be tested.
By combining multiple DC probes into one probe card, the efficiency of test operations is improved, the operation process is simplified, and the accuracy of test results is ensured.
Smart Images
Figure CN222636201U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of electrical testing, and in particular to a connection device and a testing device. Background Art
[0002] A DC probe is a commonly used testing tool that can contact components in a circuit to measure parameters such as DC current and voltage, and then test the electrical performance of the components. It has important applications in DC electrical testing of photonic integrated circuit chips, such as IV curve testing of photodiodes.
[0003] When the structure of the devices to be tested in the photonic integrated circuit chip is complex or the number is large, the traditional solution is to use multiple DC probes for testing. At this time, it is necessary to reasonably adjust the positions of multiple probes, the test efficiency is low, the operation is complicated, and it is not easy to implement. Utility Model Content
[0004] The embodiments of the present application provide a connection device and a test device to solve the problems of low test efficiency, complex operation and difficulty in implementation when multiple DC probes are used in traditional solutions to test the electrical performance of devices with complex structures or a large number in photonic integrated circuit chips.
[0005] In a first aspect, an embodiment of the present application provides a connection device, including a photonic integrated circuit chip and a probe card; the photonic integrated circuit chip is provided with at least one device to be tested, the device to be tested includes a plurality of pads, the probe card includes a probe card body and a plurality of probe pins provided on the probe card body, and the interval between two adjacent probe pins in the plurality of probe pins is consistent with the interval between two adjacent pads in the plurality of pads of the at least one device to be tested;
[0006] The plurality of probe pins of the probe card are correspondingly connected to the plurality of pads of at least one device to be tested in the photonic integrated circuit chip;
[0007] Among them, in the probe card, the probe pin connected to the pad corresponding to the positive pole of the device under test is connected to the signal providing component, and is used to transmit the DC signal provided by the signal providing component to the corresponding device under test, and in the probe card, the probe pin connected to the pad corresponding to the negative pole of the device under test is used to transmit the DC signal from the device under test, and the DC signal transmitted into the device under test and the DC signal transmitted from the device under test are used to test the electrical properties of the device under test.
[0008] Optionally, an adapter is further included, the adapter including a housing and a plurality of connection terminals extending out of the housing at both ends, the connection terminals including a positive connection terminal and a negative connection terminal;
[0009] The first end of the positive terminal is connected to the probe pin, and the second end is connected to the signal providing component, so as to transmit the DC signal provided by the signal providing component to the corresponding device under test through the connected probe pin;
[0010] The first end of the negative electrode terminal is connected to the probe pin and is used to transmit the direct current signal from the device under test.
[0011] Optionally, a plurality of positive electrode terminals form a row, and a plurality of negative electrode terminals form a row.
[0012] Optionally, a groove is provided at the second end of the housing, and a notch is provided on a single side wall of the groove;
[0013] A row of wiring terminals close to the notch is a positive wiring terminal, and a row of wiring terminals away from the notch is a negative wiring terminal;
[0014] Alternatively, a row of connection terminals close to the notch is a negative connection terminal, and a row of connection terminals away from the notch is a positive connection terminal.
[0015] Optionally, the interval between two adjacent positive electrode terminals is consistent with the interval between two adjacent probe pins, and the interval between two adjacent negative electrode terminals is consistent with the interval between two adjacent probe pins.
[0016] Optionally, leads and test components are also included;
[0017] The second end of the negative electrode terminal is connected to the test component through the lead wire, and is used to transmit the DC signal transmitted from the device under test to the test component through the lead wire;
[0018] The testing component is used to test the electrical performance of the device under test based on the direct current signal.
[0019] Optionally, leads and test components are also included;
[0020] In the probe card, the probe pin connected to the pad corresponding to the negative electrode of the device under test is connected to the test component through the lead wire, and is used to transmit the DC signal transmitted from the device under test to the test component through the lead wire;
[0021] The testing component is used to test the electrical performance of the device under test based on the direct current signal.
[0022] Optionally, the signal providing component and the testing component include a source meter.
[0023] In a second aspect, an embodiment of the present application provides a test device, comprising a signal providing component, a photonic integrated circuit chip, a probe card, and a test component, wherein the photonic integrated circuit chip is provided with at least one device to be tested, the device to be tested comprises a plurality of pads, the probe card comprises a probe card body and a plurality of probe pins arranged on the probe card body, and the interval between two adjacent probe pins in the plurality of probe pins is consistent with the interval between two adjacent pads in the plurality of pads of the at least one device to be tested;
[0024] The signal providing component is used to provide a direct current signal;
[0025] The multiple probe pins of the probe card are connected to the multiple pads of at least one device under test in the photonic integrated circuit chip; wherein, in the probe card, the probe pin connected to the pad corresponding to the positive electrode of the device under test is connected to the signal providing component, and is used to transmit the direct current signal provided by the signal providing component to the corresponding device under test, and the probe pin connected to the pad corresponding to the negative electrode of the device under test in the probe card is connected to the test component, and is used to transmit the direct current signal transmitted from the device under test to the test component;
[0026] The testing component is used to test the electrical performance of the device under test based on the direct current signal.
[0027] Optionally, an adapter is further included, the adapter including a housing and a plurality of connection terminals extending out of the housing at both ends, the connection terminals including a positive connection terminal and a negative connection terminal;
[0028] The first end of the positive terminal is connected to the probe pin, and the second end is connected to the signal providing component, so as to transmit the DC signal provided by the signal providing component to the corresponding device under test through the connected probe pin;
[0029] The first end of the negative electrode terminal is connected to the probe pin, and the second end is connected to the test component, so as to transmit the direct current signal transmitted from the device under test to the test component.
[0030] The connection device provided in the embodiment of the present application includes a photonic integrated circuit chip and a probe card. At least one device to be tested may be arranged in the photonic integrated circuit chip, and each device to be tested may include multiple pads. The probe card may include a probe card body and multiple probe pins arranged on the probe card body. The interval between two adjacent probe pins in the multiple probe pins may be consistent with the interval between two adjacent pads in the multiple pads of at least one device to be tested. The multiple probe pins of the probe card can be correspondingly connected to the multiple pads of at least one device to be tested in the photonic integrated circuit chip; wherein, in the probe card, the probe pin connected to the pad corresponding to the positive electrode of the device to be tested can be connected to the signal providing component to transmit the DC signal provided by the signal providing component to the corresponding device to be tested, and in the probe card, the probe pin connected to the pad corresponding to the negative electrode of the device to be tested can be used to transmit the DC signal from the device to be tested. The DC signal transmitted into the device to be tested and the DC signal transmitted from the device to be tested can be used to test the electrical properties of the device to be tested. By setting up a probe card, the probe card includes multiple probe pins, which is equivalent to merging multiple DC probes on one probe card. The spacing between the probe pins on the probe card is consistent with the spacing between the pads of the device to be tested, which is adapted to the structure of the device to be tested and can improve the test operation efficiency while ensuring the accuracy of the test results.
[0031] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0033] Figure 1 A schematic structural diagram of an embodiment of a device under test and a probe card provided by the present application is shown;
[0034] Figure 2 A schematic structural diagram of another embodiment of a device under test and a probe card provided by the present application is shown;
[0035] Figure 3 A schematic structural diagram of another embodiment of a device under test and a probe card provided by the present application is shown;
[0036] Figure 4 A schematic structural diagram of an embodiment of an adapter provided by the present application is shown. DETAILED DESCRIPTION
[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0038] In some structures described in the specification and claims of this application and the above drawings, multiple structural parts appearing in a specific order are included, and the serial numbers of these structural parts, such as 101, 102, etc., are only used to distinguish different structural parts. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different structural parts, etc., and do not represent the order of precedence, nor do they limit the "first" and "second" to be different types.
[0039] The embodiments of the present application can be applied to the field of electrical testing, especially the field of electrical testing using a DC probe. A DC probe is a commonly used testing tool that can contact components in a circuit to measure parameters such as DC current and voltage, and then test the electrical performance of the components. It has important applications in DC electrical testing of photonic integrated circuit chips, such as IV curve testing of photodiodes.
[0040] When the structure of the devices to be tested in the photonic integrated circuit chip is complex or the number is large, the traditional solution is to use multiple DC probes for testing. At this time, it is necessary to reasonably adjust the positions of multiple probes, which is complicated and difficult to implement.
[0041] In order to solve the above technical problems, the inventors have proposed the technical solution of the present application, providing a connection device and a test device, including a photonic integrated circuit chip and a probe card; at least one device to be tested is arranged in the photonic integrated circuit chip, and the device to be tested includes a plurality of pads; the probe card includes a probe card body and a plurality of probe pins arranged on the probe card body, and the interval between two adjacent probe pins in the plurality of probe pins is consistent with the interval between two adjacent pads in the plurality of pads of the at least one device to be tested; the plurality of probe pins of the probe card are correspondingly connected to the plurality of pads of at least one device to be tested in the photonic integrated circuit chip; wherein, in the probe card, the probe pin connected to the pad corresponding to the positive electrode of the device to be tested is connected to a signal providing component, and is used to transmit the DC signal provided by the signal providing component to the corresponding device to be tested, and in the probe card, the probe pin connected to the pad corresponding to the negative electrode of the device to be tested is used to transmit the DC signal from the device to be tested, and the DC signal transmitted into the device to be tested and the DC signal transmitted from the device to be tested are used to test the electrical properties of the device to be tested.
[0042] By setting up a probe card, the probe card includes multiple probe pins, which is equivalent to merging multiple DC probes on one probe card. The spacing between the probe pins on the probe card is consistent with the spacing between the pads of the device to be tested, which is adapted to the structure of the device to be tested and can improve the test operation efficiency while ensuring the accuracy of the test results.
[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0044] The present application provides a connection device, which may include a photonic integrated circuit chip and a probe card. The photonic integrated circuit chip may be provided with at least one device to be tested, and each device to be tested may include a plurality of pads. The probe card may include a probe card body and a plurality of probe pins provided on the probe card body.
[0045] The number and layout of the probe pins in the probe card may be consistent with the number and layout of the pads in the device under test. Specifically, the interval between two adjacent probe pins in the plurality of probe pins may be consistent with the interval between two adjacent pads in the plurality of pads of at least one device under test.
[0046] Specifically, the plurality of probe pins of the probe card may be connected correspondingly to the plurality of pads of at least one device to be tested in the photonic integrated circuit chip.
[0047] On this basis, when conducting tests, the probe pins in the probe card connected to the pads corresponding to the positive pole of the device under test can be connected to the signal providing component to transmit the DC signal provided by the signal providing component to the corresponding device under test, and the probe pins in the probe card connected to the pads corresponding to the negative pole of the device under test can be used to transmit the DC signal out of the device under test.
[0048] The direct current signal transmitted into the device under test and the direct current signal transmitted from the device under test can be used to test the electrical performance of the device under test.
[0049] For ease of understanding, Figure 1 FIG. 1 shows a schematic diagram of the structure of a device under test and a probe card according to an embodiment of the present invention. Figure 1As shown, the device under test includes two photodiodes, 11 and 12. Photodiode 11 includes two pads, 111 and 112, respectively, and pad 111 corresponds to the positive electrode, and pad 112 corresponds to the negative electrode. Photodiode 12 includes two pads, 121 and 122, respectively, and pad 121 corresponds to the positive electrode, and pad 122 corresponds to the negative electrode. The intervals between the four pads are all 100um.
[0050] At this time, the probe card may include a probe card body (not shown) and four probe pins disposed on the body, namely 101, 102, 103 and 104. The intervals between the four probe pins are also 100 um.
[0051] Specifically, the probe pin 101 can be connected to the pad 111, the probe pin 102 can be connected to the pad 112, the probe pin 103 can be connected to the pad 121, and the probe pin 104 can be connected to the pad 122. The probe pins 101 and 103 can be connected to the signal providing component, respectively used to transmit the DC signal to the photodiodes 11 and 12, and the probe pins 102 and 104 can be used to transmit the DC signal in the photodiodes 11 and 12, respectively, so as to perform electrical performance testing based on the DC signal. The specific test process can be set according to actual needs without limitation.
[0052] Figure 2 FIG. 2 shows a schematic diagram of the structure of another embodiment of a device under test and a probe card. Figure 2 As shown, the device under test includes a resistor 2, and the resistor 2 includes four pads, namely 21, 22, 23 and 24. The interval between the pads 21 and 22, and the interval between the pads 23 and 24 are both 110um, and the interval between the pads 21 and 23, and the interval between the pads 22 and 24 are both 100um.
[0053] At this time, the probe card may include a probe card body and four probe pins arranged on the body, namely 201, 202, 203 and 204. The interval between the probe pins 201 and 202 and the interval between the probe pins 203 and 204 are both 110um, and the interval between the probe pins 201 and 203 and the interval between the probe pins 202 and 204 are both 100um.
[0054] Specifically, probe pin 201 can be connected to pad 21, probe pin 202 can be connected to pad 22, probe pin 203 can be connected to pad 23, and probe pin 204 can be connected to pad 24. The pad corresponding to the positive electrode and the pad corresponding to the negative electrode of the resistor can be set according to actual needs without limitation.
[0055] Figure 3FIG. 2 shows a schematic diagram of the structure of another embodiment of a device under test and a probe card. Figure 3 As shown, the photonic integrated circuit chip includes 2×2 multimode interference couplers, 31 and 37, 1-to-2 beam splitters, 32 and 33, a beam combiner 38, phase shifters, 34, 35 and 36, and a photodetector 39. The device under test includes phase shifters 34, 36 and 35, and a photodetector 39. The phase shifter 34 includes three pads, namely 341, 342 and 343, the pad 342 corresponds to the positive electrode, and the pads 341 and 343 correspond to the negative electrode. The phase shifter 36 includes three pads, namely 361, 362 and 363, the pad 362 corresponds to the positive electrode, and the pads 361 and 363 correspond to the negative electrode. The phase shifter 35 includes three pads, namely 351, 352 and 353, the pad 352 corresponds to the positive electrode, and the pads 351 and 353 correspond to the negative electrode. The photodetector 39 includes three pads, namely 391, 392 and 393, the pad 392 corresponds to the positive electrode, and the pads 391 and 393 correspond to the negative electrode. The positions of the twelve pads are shown in the figure, and the interval between two adjacent pads is 100um.
[0056] At this time, the probe card may include a probe card body and twelve probe pins disposed on the body, which are 301-309 and 401-403 respectively. The intervals between the twelve probe pins are also 100 um.
[0057] Specifically, probe pin 301 can be connected to pad 341, probe pin 302 can be connected to pad 342, probe pin 303 can be connected to pad 343, probe pin 304 can be connected to pad 361, probe pin 305 can be connected to pad 362, probe pin 306 can be connected to pad 363, probe pin 307 can be connected to pad 351, probe pin 308 can be connected to pad 352, probe pin 309 can be connected to pad 353, probe pin 401 can be connected to pad 391, probe pin 402 can be connected to pad 392, and probe pin 403 can be connected to pad 393. Probe pins 302, 305, 308 and 402 can be connected to the signal providing component, and are respectively used to transmit DC signals into phase shifters 34, 36, 35 and photodetector 39. Probe pins 301 and 303 can transmit the DC signal in phase shifter 34, probe pins 304 and 306 can transmit the DC signal in phase shifter 36, probe pins 307 and 309 can transmit the DC signal in phase shifter 35, and probe pins 401 and 403 can transmit the DC signal in photodetector 39, so as to perform electrical performance testing based on DC signals. The specific testing process can be set according to actual needs without restriction.
[0058] The connection device provided in the embodiment of the present application includes a photonic integrated circuit chip and a probe card. At least one device to be tested may be arranged in the photonic integrated circuit chip, and each device to be tested may include multiple pads. The probe card may include a probe card body and multiple probe pins arranged on the probe card body. The interval between two adjacent probe pins in the multiple probe pins may be consistent with the interval between two adjacent pads in the multiple pads of at least one device to be tested. The multiple probe pins of the probe card can be correspondingly connected to the multiple pads of at least one device to be tested in the photonic integrated circuit chip; wherein, in the probe card, the probe pin connected to the pad corresponding to the positive electrode of the device to be tested can be connected to the signal providing component to transmit the DC signal provided by the signal providing component to the corresponding device to be tested, and in the probe card, the probe pin connected to the pad corresponding to the negative electrode of the device to be tested can be used to transmit the DC signal from the device to be tested. The DC signal transmitted into the device to be tested and the DC signal transmitted from the device to be tested can be used to test the electrical properties of the device to be tested. By setting up a probe card, the probe card includes multiple probe pins, which is equivalent to merging multiple DC probes on one probe card. The spacing between the probe pins on the probe card is consistent with the spacing between the pads of the device to be tested, which is adapted to the structure of the device to be tested and can improve the test operation efficiency while ensuring the accuracy of the test results.
[0059] In practical applications, when performing direct current electrical testing, the above device may also include leads and test components.
[0060] At this time, in the probe card, the probe pin connected to the pad corresponding to the negative electrode of the device under test can be connected to the test component through the lead wire, so as to transmit the DC signal transmitted from the device under test to the test component through the lead wire.
[0061] The test assembly can be used to test the electrical performance of the device under test based on a direct current signal.
[0062] The implementation of the test components can be set based on actual needs without any restrictions.
[0063] In order to improve the adaptability of the probe card to various structures to be tested, in some embodiments, the above-mentioned device may further include an adapter.
[0064] The adapter may include a shell and a plurality of connection terminals extending out of the shell at both ends, which may include a positive connection terminal and a negative connection terminal.
[0065] Specifically, the first end of the positive terminal can be connected to the probe pin, and the second end can be connected to the signal providing component, so as to transmit the DC signal provided by the signal providing component to the corresponding device under test through the connected probe pin.
[0066] The first end of the negative terminal can be connected to a probe pin to transmit a direct current signal from the device under test.
[0067] By setting up an adapter, it is possible to change the way the probe card is used by changing the way the cable is connected. For example, Figure 3 The probe card with twelve probe pins shown can use an adapter to use only four probe pins or eight probe pins to test the corresponding structure to be tested, without redesigning the probe card, thereby improving the adaptability of the probe card to a variety of structures to be tested, saving costs, and facilitating use.
[0068] In some embodiments, a plurality of positive terminals in the adapter may form a row, and a plurality of negative terminals may form a row.
[0069] In some embodiments, a groove may be provided at the second end of the housing of the adapter, and a notch may be provided on a single side wall of the groove.
[0070] At this time, a row of wiring terminals close to the notch can be set as positive wiring terminals, and a row of wiring terminals away from the notch can be set as negative wiring terminals;
[0071] Alternatively, a row of wiring terminals close to the notch is a negative wiring terminal, and a row of wiring terminals away from the notch is a positive wiring terminal.
[0072] By arranging a notch on a single side wall of the groove of the connector housing, the positive and negative poles of the connecting terminal can be distinguished, thereby achieving correct connection of the adapter.
[0073] For ease of understanding, Figure 4 The schematic diagram of the structure of an embodiment of an adapter is shown, which may include a housing 401 and a plurality of connection terminals 402. A notch 4011 is provided on a single side wall of the groove of the housing 401.
[0074] In some embodiments, the interval between two adjacent positive terminals can be consistent with the interval between two adjacent probe pins, and the interval between two adjacent negative terminals can be consistent with the interval between two adjacent probe pins, so as to achieve adaptation with the probe card and the structure to be tested.
[0075] In some embodiments, the above device may further include leads and test components.
[0076] At this time, the second end of the negative electrode terminal can be connected to the test component through a lead wire, so as to transmit the DC signal transmitted from the device under test to the test component through the lead wire.
[0077] The test assembly can be used to test the electrical performance of the device under test based on a direct current signal.
[0078] In one or more of the above embodiments, both the signal providing component and the testing component may be implemented as source meters.
[0079] The present application also provides a testing device, which may include a signal providing component, a photonic integrated circuit chip, a probe card, and a testing component. The photonic integrated circuit chip may be provided with at least one device to be tested, each device to be tested may include a plurality of pads, and the probe card may include a probe card body and a plurality of probe pins provided on the probe card body.
[0080] The number and layout of the probe pins in the probe card may be consistent with the number and layout of the pads in the device under test. Specifically, the interval between two adjacent probe pins in the plurality of probe pins may be consistent with the interval between two adjacent pads in the plurality of pads of at least one device under test.
[0081] The signal providing component can be used to provide a DC signal.
[0082] The multiple probe pins of the probe card can be connected to the multiple pads of at least one device to be tested in the photonic integrated circuit chip.
[0083] Among them, in the probe card, the probe pin connected to the pad corresponding to the positive pole of the device under test can be connected to the signal providing component, which is used to transmit the DC signal provided by the signal providing component to the corresponding device under test, and in the probe card, the probe pin connected to the pad corresponding to the negative pole of the device under test can be connected to the test component, which is used to transmit the DC signal transmitted from the device under test to the test component.
[0084] The test component can be used to test the electrical performance of the device under test based on a direct current signal.
[0085] By setting up a probe card, the probe card includes multiple probe pins, which is equivalent to merging multiple DC probes on one probe card. The spacing between the probe pins on the probe card is consistent with the spacing between the pads of the device to be tested, which is adapted to the structure of the device to be tested and can improve the test operation efficiency while ensuring the accuracy of the test results.
[0086] In some embodiments, the above device may further include an adapter.
[0087] The adapter may include a shell and a plurality of connection terminals extending out of the shell at both ends, which may include a positive connection terminal and a negative connection terminal.
[0088] Specifically, the first end of the positive terminal can be connected to the probe pin, and the second end can be connected to the signal providing component, so as to transmit the DC signal provided by the signal providing component to the corresponding device under test through the connected probe pin.
[0089] The first end of the negative electrode terminal can be connected to the probe pin, and the second end is connected to the test component, so as to transmit the direct current signal transmitted from the device under test to the test component.
[0090] It is clear to those skilled in the art that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative labor.
[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A connection device, characterized in that: The invention comprises a photonic integrated circuit chip and a probe card; the photonic integrated circuit chip is provided with at least one device to be tested, the device to be tested comprises a plurality of pads, the probe card comprises a probe card body and a plurality of probe pins arranged on the probe card body, and the interval between two adjacent probe pins among the plurality of probe pins is consistent with the interval between two adjacent pads among the plurality of pads of the at least one device to be tested; The plurality of probe pins of the probe card are correspondingly connected to the plurality of pads of at least one device to be tested in the photonic integrated circuit chip; Among them, in the probe card, the probe pin connected to the pad corresponding to the positive pole of the device under test is connected to the signal providing component, and is used to transmit the DC signal provided by the signal providing component to the corresponding device under test, and in the probe card, the probe pin connected to the pad corresponding to the negative pole of the device under test is used to transmit the DC signal from the device under test, and the DC signal transmitted into the device under test and the DC signal transmitted from the device under test are used to test the electrical properties of the device under test.
2. The device according to claim 1, characterized in that Also included is an adapter, the adapter comprising a housing and a plurality of connection terminals extending out of the housing at both ends, the connection terminals comprising a positive connection terminal and a negative connection terminal; The first end of the positive terminal is connected to the probe pin, and the second end is connected to the signal providing component, so as to transmit the DC signal provided by the signal providing component to the corresponding device under test through the connected probe pin; The first end of the negative electrode terminal is connected to the probe pin and is used to transmit the direct current signal from the device under test.
3. The device according to claim 2, characterized in that A plurality of positive electrode terminals form a row, and a plurality of negative electrode terminals form a row.
4. The device according to claim 3, characterized in that The second end of the housing is provided with a groove, and a single side wall of the groove is provided with a notch; A row of wiring terminals close to the notch is a positive wiring terminal, and a row of wiring terminals away from the notch is a negative wiring terminal; Alternatively, a row of connection terminals close to the notch is a negative connection terminal, and a row of connection terminals away from the notch is a positive connection terminal.
5. The device according to claim 3, characterized in that The interval between two adjacent positive electrode terminals is consistent with the interval between the two adjacent probe pins, and the interval between two adjacent negative electrode terminals is consistent with the interval between the two adjacent probe pins.
6. The device according to claim 2, characterized in that Also includes leads and test components; The second end of the negative electrode terminal is connected to the test component through the lead wire, and is used to transmit the DC signal transmitted from the device under test to the test component through the lead wire; The testing component is used to test the electrical performance of the device under test based on the direct current signal.
7. The device according to claim 1, characterized in that Also includes leads and test components; In the probe card, the probe pin connected to the pad corresponding to the negative electrode of the device under test is connected to the test component through the lead wire, and is used to transmit the DC signal transmitted from the device under test to the test component through the lead wire; The testing component is used to test the electrical performance of the device under test based on the direct current signal.
8. The device according to any one of claims 5 to 6, characterized in that: The signal providing component and the testing component include a source meter.
9. A testing device, characterized in that: The invention comprises a signal providing component, a photonic integrated circuit chip, a probe card, and a test component, wherein the photonic integrated circuit chip is provided with at least one device to be tested, the device to be tested comprises a plurality of pads, the probe card comprises a probe card body and a plurality of probe pins arranged on the probe card body, and the interval between two adjacent probe pins among the plurality of probe pins is consistent with the interval between two adjacent pads among the plurality of pads of the at least one device to be tested; The signal providing component is used to provide a direct current signal; The multiple probe pins of the probe card are connected to the multiple pads of at least one device under test in the photonic integrated circuit chip; wherein, in the probe card, the probe pin connected to the pad corresponding to the positive electrode of the device under test is connected to the signal providing component, and is used to transmit the direct current signal provided by the signal providing component to the corresponding device under test, and the probe pin connected to the pad corresponding to the negative electrode of the device under test in the probe card is connected to the test component, and is used to transmit the direct current signal transmitted from the device under test to the test component; The testing component is used to test the electrical performance of the device under test based on the direct current signal.
10. The device according to claim 9, characterized in that Also included is an adapter, the adapter comprising a housing and a plurality of connection terminals extending out of the housing at both ends, the connection terminals comprising a positive connection terminal and a negative connection terminal; The first end of the positive terminal is connected to the probe pin, and the second end is connected to the signal providing component, so as to transmit the DC signal provided by the signal providing component to the corresponding device under test through the connected probe pin; The first end of the negative electrode terminal is connected to the probe pin, and the second end is connected to the test component, so as to transmit the direct current signal transmitted from the device under test to the test component.