Semiconductor device

Abstract

In one embodiment of the present disclosure, a semiconductor device is provided. The method includes forming a nanostructured channel region, forming a gate opening surrounding the nanostructured channel region, forming an oxide layer on an exposed surface of the nanostructured channel region in the gate opening, depositing a diffusion barrier layer on the oxide layer, depositing a first dielectric layer on the nanostructured channel region, and forming a second dielectric layer on the first dielectric layer. A doping process is performed on the diffusion barrier layer and the first dielectric layer to form a doped diffusion barrier layer and a doped dielectric layer, and a conductive layer is deposited on the doped dielectric layer.

Description

Technical Field

[0001] The embodiments of the utility model relate to semiconductor technology, and more particularly to semiconductor devices. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor transistors (MOSFETs), fin field effect transistors (FinFETs), and gate-all-around (GAA). This miniaturization increases the complexity of semiconductor manufacturing processes. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor device to solve at least one of the above problems.

[0004] The present disclosure provides a semiconductor device, comprising: a substrate; a nanostructure channel region, arranged on the substrate; and a gate structure, comprising: an oxide layer surrounding the nanostructure channel region; a doped diffusion barrier layer, located on the oxide layer; a dipole layer, arranged between the oxide layer and the doped diffusion barrier layer; and a doped dielectric layer, arranged on the doped diffusion barrier layer.

[0005] According to one embodiment of the present invention, the doped diffusion barrier layer includes a metal oxide having a Gibbs free energy of formation, which is lower than the Gibbs free energy of formation of a metal oxide of the doped dielectric layer.

[0006] According to one embodiment of the present invention, the thickness of the doped diffusion barrier layer is 0.3 nm to 0.5 nm.

[0007] According to one embodiment of the present invention, the doped diffusion barrier layer includes a plurality of rare earth metal dopants.

[0008] According to one embodiment of the present invention, a metal dopant concentration in the doped diffusion barrier layer is higher than a metal dopant concentration in the doped dielectric layer.

[0009] According to one embodiment of the present invention, the thickness of the oxide layer is 0.4 nm to 0.8 nm.

[0010] According to one embodiment of the present invention, the gate structure further includes a work function metal layer disposed on the doped dielectric layer.

[0011] According to one embodiment of the present invention, the gate structure further includes a gate metal filling layer disposed on the work function metal layer.

[0012] According to one embodiment of the present invention, the gate structure further includes a conductive cap layer disposed on the doped dielectric layer, the work function metal layer and the gate metal filling layer.

[0013] According to one embodiment of the present invention, the gate structure further includes an insulating cover layer disposed on the conductive cover layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The embodiments of the present invention are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various elements may be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention.

[0015] Figure 1A Isometric views of semiconductor devices having different gate structures are illustrated according to some embodiments.

[0016] Figure 1B-Figure 1E Cross-sectional views of semiconductor devices having different gate structures are illustrated according to some embodiments.

[0017] Figure 1F Device characteristics of semiconductor devices having different gate structures are illustrated according to some embodiments.

[0018] Figure 2 is a flow chart of a method for manufacturing a semiconductor device having different gate structures according to some embodiments.

[0019] Figure 3A-Figure 20B Cross-sectional views of semiconductor devices with different gate structures at various stages of their manufacturing process are illustrated according to some embodiments.

[0020] Fig.21 Device characteristics of semiconductor devices having different gate structures at stages of their fabrication process are illustrated according to some embodiments.

[0021] Exemplary embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0022] The reference numerals are as follows:

[0023] 100:Semiconductor device

[0024] 102N: N-type GAA FET

[0025] 102P: P-type GAA FET

[0026] 104:Substrate

[0027] 106N: Fin base

[0028] 106P: Fin base

[0029] 110N: Source / Drain region

[0030] 110P: Source / Drain Region

[0031] 112N1-112N3: Gate structure

[0032] 112P1-112P3: Gate structure

[0033] 113:Internal spacer

[0034] 114: Gate spacer

[0035] 116: Shallow trench isolation (STI) area

[0036] 117: Etch stop layer (ESL)

[0037] 118: Inter-Layer Dielectric (ILD) layer

[0038] 112B1-112B3: Gate structure

[0039] 121N: Nanostructured channel region

[0040] 112N1-112N3: Gate structure

[0041] 121P: Nanostructured channel region

[0042] 121P1-121P3: Gate structure

[0043] 122: interfacial oxide (IL) layer

[0044] 123N1-123N3: Diffusion barrier layer

[0045] 123P1-123P3: Diffusion barrier layer

[0046] 124N1-124N3: HK gate dielectric layer

[0047] 124P1-124P3: HK gate dielectric layer

[0048] 125N1-125N3: HK-doped gate dielectric layer

[0049] 125P1-125P3: HK-doped gate dielectric layer

[0050] 126:WFM layer

[0051] 127N1-127N3: Undoped HK gate dielectric layer

[0052] 127P1-127P3: Undoped HK gate dielectric layer

[0053] 128: Gate metal filling layer

[0054] 130: Conductive cover layer

[0055] 132: Insulation cover

[0056] 134: Concentration distribution

[0057] 136: Concentration distribution

[0058] 200: Method

[0059] 205: Operation

[0060] 210: Operation

[0061] 215: Operation

[0062] 220: Operation

[0063] 225: Operation

[0064] 230: Operation

[0065] 235: Operation

[0066] 240: Operation

[0067] 245: Operation

[0068] 321: Nanostructured layer

[0069] 321N: Polysilicon structure

[0070] 321P: Polysilicon structure

[0071] 412N1-412N3: Gate opening

[0072] 412P1-412P3: Gate opening

[0073] 523: Diffusion barrier layer

[0074] 523N1-523N3: Diffusion barrier layer

[0075] 523P1-523P3: Diffusion barrier layer

[0076] 525: first HK gate dielectric layer

[0077] 525N1-525N3: HK gate dielectric layer

[0078] 525P1-525P3: HK gate dielectric layer

[0079] 646: doping source layer

[0080] 846: doping source layer

[0081] 1046: doping source layer

[0082] 1248: doping source layer

[0083] 1448: Doping source layer

[0084] 1648: Doping source layer

[0085] 2026: WFM layer

[0086] 2027: Second HK gate dielectric layer

[0087] 2134:Concentration distribution

[0088] 2136:Concentration distribution

[0089] 2228: Gate metal filling layer

[0090] AA: Section Line

[0091] BB: Cutting line

[0092] CC: Cutting Line

[0093] DD: Section line

[0094] EE: Sectioning

[0095] FF: Section line DETAILED DESCRIPTION

[0096] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the illustration of the embodiments of the utility model. Of course, the above are only examples and are not intended to limit the embodiments of the utility model. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the utility model may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0097] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0098] It should be noted that references to "one embodiment," "an embodiment," "exemplary embodiments," "exemplary embodiments," etc. in the illustrative book indicate that the described embodiment may include specific components, structures, or characteristics, but not every embodiment necessarily includes the specific components, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Furthermore, when specific components, structures, or characteristics are described in conjunction with an embodiment, whether or not explicitly described, those skilled in the art should be able to recognize that such components, structures, or characteristics may be incorporated into other implementations.

[0099] It should be understood that the phraseology or terminology herein is for the purpose of description and not limitation, so that the phraseology or terminology of the present specification will be interpreted by those skilled in the relevant art based on the teachings herein.

[0100] In some embodiments, the terms "about" and "substantially" may mean that a given value varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% variation). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0101] The fin structures disclosed herein can be patterned by any suitable method. For example, the fin structures can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with a pitch smaller than that obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0102] The gate-all-around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with a pitch smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0103] A fully wrapped gate field effect transistor (GAA FET) may include a fin base disposed on a substrate, a stack of nanostructure channel regions disposed on the fin base, and a gate structure surrounding each nanostructure channel region. The gate voltage that turns on the GAAFET, the threshold voltage (Vt), may depend on the effective work function (EWF) value of the semiconductor material of the nanostructure channel region and / or the GAAFET gate structure. For example, for an N-type GAA FET ("NFET"), reducing the gap between the EWF value of the NFET gate structure of the NFET nanostructure channel region and the conduction band energy of the material (e.g., 4.1 eV for silicon (Si) or 3.8 eV for silicon germanium (SiGe)) can reduce the threshold voltage of the NFET. For a P-type GAAFET ("PFET"), reducing the gap between the EWF value of the PFET gate structure of the PFET nanostructure channel region and the valence band energy of the material (e.g., 5.2 eV for Si or 4.8 eV for SiGe) can reduce the threshold voltage of the PFET. The EWF value of the gate structure may depend on the thickness and / or material composition of each layer of the gate structure. Therefore, GAA FETs with different threshold voltages can be fabricated by adjusting the thickness and / or material composition of the gate structure.

[0104] Due to the increased demand for multifunctional low-power portable devices, there is an increased demand for GAA FETs with low threshold voltages, such as threshold voltages between about 200 mV and about 400 mV (referred to as "low threshold voltage"), threshold voltages between about 100 mV and about 200 mV (referred to as "ultra-low threshold voltage"), and threshold voltages below about 100 mV (referred to as "extremely low threshold voltage"). One approach to implementing a multi-threshold voltage device with low, ultra-low and / or extremely low threshold voltages in a GAA FET may be to have different work function metal (WFM) layer thicknesses greater than about 4 nm (e.g., about 5 nm to about 10 nm) in a gate structure. However, different WFM layer thicknesses may be limited by the geometry of the GAA FET gate structure. For example, the thickness of the WFM layer may be limited by the spacing between the nanostructure channel regions of the GAA FET. Moreover, as GAA FETs continue to scale, depositing different WFM layer thicknesses becomes increasingly challenging. The continuous scaling of GAA FETs also increases the challenge of preventing the nanostructured channel region from being oxidized during the GAA FET thermal treatment process. The oxidation of the nanostructured channel region increases the thickness of the interfacial oxide (IL) layer of the gate structure on the nanostructured channel region, thereby reducing the gate performance of the GAA FET.

[0105] To address the above challenges, the present disclosure provides an example method for forming a GAA FET with improved IL layer thickness distribution control and with different gate structures configured to provide different threshold voltages on the same substrate. The example method forms NFETs and PFETs with a miniaturized IL layer of about 0.4nm to about 0.8nm for reducing the effective capacitance thickness (capacitance effective thickness, CET), thereby increasing the FET drive current. In addition, the example method forms NFETs and PFETs with substantially equal thickness WFM layers and extremely low, ultra-low and / or low threshold voltages on the same substrate. Compared with other methods of forming GAA FETs of similar size and threshold voltage on the same substrate, these example methods can be more cost-effective (e.g., reducing costs by about 20% to about 30%) and time-efficient (e.g., reducing time by about 15% to about 20%) in manufacturing reliable GAA FET gate structures with different threshold voltages. In addition, compared with other methods of forming GAA FETs with similar threshold voltages, these example methods can form GAA FET gate structures with much smaller sizes (e.g., thinner gate stacks).

[0106] In some embodiments, the gate structure of the NFET and the PFET may include a diffusion barrier layer disposed on the IL layer. During the thermal process of the NFET and the PFET, the diffusion barrier layer may prevent or minimize the diffusion of oxygen atoms from the cap layer (e.g., a high dielectric constant (high-K, HK) gate dielectric layer) into the nanostructure channel region. Preventing or minimizing the diffusion of oxygen atoms may prevent or minimize the oxidation of the nanostructure channel region. Therefore, by using a diffusion barrier layer, the IL layer may be sufficiently maintained at a thickness of about 0.4 nm to about 0.8 nm during the execution of different thermal processes in the manufacture of the NFET and the PFET. In some embodiments, in order to fully control the thickness distribution of the IL layer, the diffusion barrier layer may include a metal oxide having a lower Gibbs free energy of formation than the metal oxide of the HK gate dielectric layer (e.g., hafnium oxide (HfO2)). In some embodiments, such a metal oxide of the diffusion barrier layer may include aluminum oxide (Al2O3), lanthanum oxide (La2O3), scandium oxide (Sc2O3), yttrium oxide (Y2O3), gadolinium oxide (Gd2O3), magnesium oxide (MgO), calcium oxide (CaO), or zirconium silicate (ZrSiO4). In some embodiments, the diffusion barrier layer may have a thickness of about 0.3 nm to about 0.5 nm to sufficiently prevent or minimize the diffusion of oxygen atoms without affecting device size and manufacturing cost.

[0107] In some embodiments, NFETs and PFETs having different gate structure configurations but having substantially equal thicknesses of WFM layers can be formed on the same substrate to achieve different threshold voltages. Different gate structures can have diffusion barrier layers and HK gate dielectric layers doped with different types and / or concentrations of metal dopants. Different types and / or concentrations of metal dopants can induce dipoles of different polarities and / or concentrations at the interface between the diffusion barrier layer and the IL layer ("barrier-IL interface"). Dipoles of different polarities and / or concentrations result in gate structures with different EWF values. Since the EWF values ​​of the gate structures correspond to the threshold voltages of the NFETs and PFETs, gate structures with different EWF values ​​result in different threshold voltages for the NFETs and PFETs on the same substrate. Therefore, controlling the type and / or concentration of metal dopants in the diffusion barrier layer and the HK gate dielectric layer can adjust the EWF values ​​of the NFET and PFET gate structures, and thus the threshold voltages of the NFET and PFET can be adjusted without changing the WFM layer thickness.

[0108] Figure 1A An isometric view of a semiconductor device 100 having an N-type GAA FET 102N (“NFET 102N”) and a P-type GAA FET 102P (“PFET 102P”) is illustrated in accordance with some embodiments. Figure 1B According to some embodiments, NFET 102N is illustrated along Figure 1A Cross-section diagram along line AA. Figure 1C A cross-sectional view of the PFET 102P along line BB of FIG. 1 is illustrated according to some embodiments. Figure 1B and Figure 1C For simplicity, the example is not shown in Figure 1A 2 is a cross-sectional view of a semiconductor device 100 with an additional structure illustrated in FIG. Figure 1D yes Figure 1B An enlarged view of gate regions 112A1, 112A2 and 112A3. Figure 1E yes Figure 1C An enlarged view of gate regions 112B1, 112B2 and 112B3. Figure 1D and Figure 1E For simplicity, the example is not shown in Figure 1B and Figure 1C Unless otherwise specified, the discussion of the same elements applies to each other.

[0109] refer to Figure 1A-Figure 1C In some embodiments, the semiconductor device 100 may be formed on a substrate 104, wherein the NFET 102N and the PFET 102P are formed on different regions of the substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed between the NFET 102N and the PFET 102P on the substrate 104. The substrate 104 may be a semiconductor material such as Si, germanium (Ge), SiGe, a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 104 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic). The semiconductor device 100 may also include a gate spacer 114, a shallow trench isolation (STI) region 116, an etch stop layer (ESL) 117, and an inter-layer dielectric (ILD) layer 118. In some embodiments, the gate spacers 114 , the STI regions 116 , the ESL 117 , and the ILD layer 118 may include insulating materials such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide.

[0110] refer to Figure 1A and Figure 1BIn some embodiments, NFET 102N may include (i) a fin base 106N, (ii) a source / drain region 110N disposed on the fin base 106N, (iii) gate structures 112N1-112N3 disposed on a portion of the fin base 106N not covered by the source / drain region 110N, and (iv) a nanostructure channel region 121N surrounded by the gate structures 112N1-112N3. Figure 1A and Figure 1C In some embodiments, the PFET 102P may include (i) a fin base 106P, (ii) a source / drain region 110P disposed on the fin base 106P, (iii) gate structures 112P1-112P3 disposed on portions of the fin base 106P not covered by the source / drain region 110P, and (iv) a nanostructure channel region 121P surrounded by the gate structures 112P1-112P3. As used herein, the term "nanostructure" defines a structure, layer, and / or region having a horizontal dimension (e.g., along the X-axis and / or the Y-axis) and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the nanostructure channel region 121 may be in the form of a nanosheet, nanowire, nanorod, nanotube, or other suitable nanostructure shape. In some embodiments, fin bases 106N and 106P may include a material similar to substrate 104 and extend along the X-axis.

[0111] In some embodiments, the source / drain region 110N may include an epitaxially grown semiconductor material, such as Si, and an N-type dopant, such as phosphorus and other suitable N-type dopant. In some embodiments, the source / drain region 110P may include an epitaxially grown semiconductor material, such as Si and SiGe, and a P-type dopant, such as boron and other suitable P-type dopant.

[0112] In some embodiments, the nanostructure channel regions 121N and 121P may include semiconductor materials similar to or different from the substrate 104. In some embodiments, the nanostructure channel regions 121N and 121P may include silicon (Si), silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds or other suitable semiconductor materials. Although the rectangular cross-sections of the nanostructure channel regions 121N and 121P are shown, the nanostructure channel regions 121N and 121P may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular or polygonal). In some embodiments, the nanostructure channel regions 121N and 121P may be separated from each other by a distance of about 8nm to about 12nm along the Z axis. In some embodiments, each of the nanostructure channel regions 121N and 121P may have a thickness of about 5nm to about 8nm along the Z axis. In some embodiments, each of the nanostructure channel regions 121N and 121P may have a width of about 15 nm to about 50 nm along the X axis. In some embodiments, the NFET-PFET 102N- 102P may be FinFETs and have a fin region (not illustrated) instead of the nanostructure channel region 121 .

[0113] In some embodiments, the portions of the gate structures 112N1-112N3 surrounding the nanostructure channel region 121N may be electrically isolated from the adjacent source / drain region 110N by the inner spacer 113. Similarly, the portions of the gate structures 112P1-112P3 surrounding the nanostructure channel region 121P may be electrically isolated from the adjacent source / drain region 110P by the inner spacer 113. The inner spacer 113 may include a material similar to the gate spacer 114. In some embodiments, the NFET 102N and the PFET 102P may be FinFETs and have fin regions (not illustrated) instead of the nanostructure channel regions 121N and 121P.

[0114] refer to Figure 1B and Figure 1DIn some embodiments, the gate structures 112N1-112N3 and 112P1-112P3 may be multi-layer structures. In some embodiments, the gate structures 112N1-112N3 may include (i) an IL layer 122, (ii) a diffusion barrier layer 123N1-123N3 disposed on the IL layer 122, (iii) a HK gate dielectric layer 124N1-124N3 disposed on the diffusion barrier layer 123N1-123N3, (iv) a WFM layer 126 disposed on the HK gate dielectric layer 124N1-124N3, (v) a gate metal filling layer 128 disposed on the WFM layer 126, (vi) a conductive cap layer 130 disposed on the HK gate dielectric layer 124N1-124N3, the WFM layer 126 and the gate metal filling layer 128, and (vii) an insulating cap layer 132 disposed on the conductive cap layer 130.

[0115] refer to Figure 1C and Figure 1E In some embodiments, the gate structures 112P1-112P3 may include (i) an IL layer 122, (ii) a diffusion barrier layer 123P1-123P3 disposed on the IL layer 122, (iii) a HK gate dielectric layer 124P1-124P3 disposed on the diffusion barrier layer 123P1-123P3, (iv) a WFM layer 126 disposed on the HK gate dielectric layer 124P1-124P3, (v) a gate metal filling layer 128 disposed on the WFM layer 126, (vi) a conductive cap layer 130 disposed on the HK gate dielectric layer 124P1-124P3, the WFM layer 126 and the gate metal filling layer 128, and (vii) an insulating cap layer 132 disposed on the conductive cap layer 130.

[0116] refer to Figure 1B-Figure 1E In some embodiments, the IL layer 122 may include SiO2, silicon germanium oxide (SiGeO x ) or germanium oxide (GeO2). In some embodiments, the IL layer 122 may have a thickness of about 0.4 nm to about 0.8 nm. Within this thickness range of the IL layer 122, sufficient CET for high FET drive current and low leakage current can be obtained without affecting the device size and manufacturing cost. Since the IL layer 122 is disposed on the nanostructure channel regions 121N and 121P, the thickness distribution of the IL layer 122 is susceptible to oxidation of the nanostructure channel regions 121N and 121P during the manufacturing process of the NFET 102N and the PFET 102P. The use of diffusion barrier layers 123N1-123N3 and 123P1-123P2 on the IL layer 122 can prevent or minimize such oxidation of the nanostructure channel regions 121N and 121P.

[0117] The diffusion barrier layers 123N1-123N3 and 123P1-123P2 may prevent or minimize oxygen atoms from diffusing from the capping layers (e.g., HK gate dielectric layers 124N1-124N3 and 124P1-124P3) into the nanostructure channel regions 121N and 121P and the PFET 102P during the thermal process of the NFET 102N. Preventing or minimizing the diffusion of oxygen atoms may prevent or minimize oxidation of the nanostructure channel regions 121N and 121P. As such, by using the diffusion barrier layers 123N1-123N3 and 123P1-123P2, the IL layer 122 may be sufficiently maintained at a thickness of about 0.4 nm to about 0.8 nm during the different thermal processes performed in the fabrication of the NFET 102N and the PFET 102P.

[0118] In some embodiments, in order to fully control the thickness distribution of the IL layer 122, the diffusion barrier layers 123N1-123N3 and 123P1-123P2 may include a metal oxide having a lower Gibbs formation free energy than the metal oxide (e.g., hafnium oxide (HfO2)) of the HK gate dielectric layers 124N1-124N3 and 124P1-124P3. In some embodiments, the metal oxide of the diffusion barrier layers 123N1-123N3 and 123P1-123P2 may include Al2O3, La2O3, Sc2O3, Y2O3, Gd2O3, MgO, CaO, or ZrSiO4. In some embodiments, the metal atoms of the metal oxide of the diffusion barrier layers 123N1-123N3 and 123P1-123P2 may have a concentration distribution 134, such as Figure 1F As shown, across Figure 1D The CC line and Figure 1E A small distribution of metal atoms of the metal oxide of the diffusion barrier layers 123N1-123N3 and 123P1-123P2 may exist as metal dopants in the IL layer 122 and the HK gate dielectric layers 124N1-124N3 and 124P1-124P3, such as Figure 1F As described in detail below, during the fabrication of the gate structures 112N1-112N3 and 112P1-112P3, these metal dopants may diffuse from the diffusion barrier layers 123N1-123N3 and 123P1-123P2 into the IL layer 122 and the HK gate dielectric layers 124N1-124N3 and 124P1-124P3. In some embodiments, the diffusion barrier layers 123N1-123N3 and 123P1-123P2 may have a thickness of about 0.3 nm to about 0.5 nm to sufficiently prevent or minimize the diffusion of oxygen atoms without affecting device size and manufacturing cost.

[0119] refer to Figure 1B-Figure 1EIn some embodiments, the HK gate dielectric layers 124N1-124N3 and 124P1-124P3 may include (i) doped HK gate dielectric layers 125N1-125N3 and 125P1-125P3, and (ii) undoped HK gate dielectric layer 127 disposed on the doped HK gate dielectric layers 125N1-125N3 and 125P1-125P3. In some embodiments, the doped HK gate dielectric layers 125N1-125N3 and 125P1-125P3 and the undoped HK gate dielectric layer 127 may include a high dielectric constant (high-k) dielectric material, such as HfO2, titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), or hafnium silicate (HfSiO4).

[0120] refer to Figure 1D , the diffusion barrier layers 123N1-123N3 and the doped HK gate dielectric layers 125N1-125N3 may further include a metal dopant that induces the formation of a dipole layer 140N1-140N3 having an N-type dipole (“N-dipole”) at the barrier-IL interface N1-N3. In some embodiments, the dipole layer 140N1-140N3 may be disposed in the diffusion barrier layers 123N1-123N3 and closer to the barrier-IL interface N1-N3 than at the barrier-IL interface N1-N3. In some embodiments, the metal dopant of the N-type dipole in the diffusion barrier layers 123N1-123N3 and the doped HK gate dielectric layers 125N1-125N3 may include rare-earth metals (REMs), such as lanthanum (La), yttrium (Y), cerium (Ce), ytterbium (Yb), and erbium (Er). In some embodiments, the N-type dipoles of the dipole layers 140N1 - 140N3 may include metal ions from the metal dopants in the diffusion barrier layers 123N1 - 123N3 and oxygen ions from the material of the IL layer 122 of the NFET 102N.

[0121] In some embodiments, the diffusion barrier layers 123N1 - 123N3 and the doped HK gate dielectric layers 125N1 - 125N3 may include the same metal but different concentrations of metal dopants to induce N-type dipoles in the same type of dipole layers 140N1 - 140N3 and at different concentrations. Since the metal doping concentration is proportional to the N dipole concentration, which is inversely proportional to the threshold voltage of the NFET gate structure, (i) the diffusion barrier layer 123N1 and the doped HK gate dielectric layer 125N1 have a higher metal doping concentration than the diffusion barrier layers 123N2-123N3 and the doped HK gate dielectric layers 125N2-125N3 to form the gate structure 112N1 having a threshold voltage lower than the gate structures 112N2 and 112N3, and (ii) the diffusion barrier layer 123N2 and the doped HK gate dielectric layer 125N2 have a higher metal doping concentration than the diffusion barrier layer 123N3 and the doped HK gate dielectric layer 125N3 to form the gate structure 112N2 having a threshold voltage lower than the gate structure 112N3. Therefore, the threshold voltage across different NFET gate structures (e.g., gate structures 112N1-112N3) on the same substrate can vary with different concentrations of the same polarity dipole (e.g., N-type dipole). In some embodiments, the metal dopants in the diffusion barrier layers 123N1-123N3 and the doped HK gate dielectric layers 125N1-125N3 may have a cross Figure 1D The dopant concentration profile 136 of the CC line is as follows: Figure 1F As shown. The metal doping concentration of the N-type dipole in the diffusion barrier layers 123N1-123N3 may be higher than the metal doping concentration in the doped HK gate dielectric layers 125N1-125N3. The peak concentration of the metal dopant of the N-type dipole may be in the diffusion barrier layers 123N1-123N3 and closer to the barrier-IL interface N1-N3, as shown. Figure 1F shown.

[0122] refer to Figure 1E, the diffusion barrier layers 123P1-123P3 and the doped HK gate dielectric layers 125P1-125P3 may further include metal dopants that induce the formation of dipole layers 140P1-140P3 having a P-type dipole at the barrier-IL interface P1-P3. In some embodiments, the dipole layers 140P1-140P3 may be disposed in the diffusion barrier layers 123P1-123P3 and closer to the barrier-IL interface P1-P3 rather than on the barrier-IL interface P1-P3. In some embodiments, the metal dopants in the diffusion barrier layers 123P1-123P3 and the doped HK gate dielectric layers 125P1-125P3 may include zinc (Zn), germanium (Ge), aluminum (Al), titanium (Ti), or vanadium (V). In some embodiments, the P-type dipoles of the dipole layers 140P1 - 140P3 may include metal ions from the metal dopants in the diffusion barrier layers 123P1 - 123P3 and oxygen ions from the material of the IL layer 122 of the PFET 102P.

[0123] In some embodiments, the diffusion barrier layers 123P1 - 123P3 and the doped HK gate dielectric layers 125P1 - 125P3 may include the same metal but different concentrations of metal dopants to induce P-type dipoles in the same type of dipole layers 140P1 - 140P3 and at different concentrations. Since the metal doping concentration is proportional to the P-type dipole concentration, which is inversely proportional to the threshold voltage of the PFET gate structure, (i) the diffusion barrier layer 123P3 and the doped HK gate dielectric layer 125P3 have a higher metal doping concentration than the diffusion barrier layers 123P1-123P2 and the doped HK gate dielectric layers 125P1-125P2 to form a gate structure 112P3 having a threshold voltage lower than the gate structures 112P1 and 112P2, and (ii) the diffusion barrier layer 123P2 and the doped HK gate dielectric layer 125P2 have a higher metal doping concentration than the diffusion barrier layer 123P1 and the doped HK gate dielectric layer 125P1 to form a gate structure 112P2 having a threshold voltage lower than the gate structure 112P1. Therefore, the threshold voltage across different PFET gate structures (e.g., gate structures 112P1-112P3) on the same substrate can vary with different concentrations of the same polarity dipole (e.g., P-type dipole). In some embodiments, the metal dopants in the diffusion barrier layers 123P1-123P2 and the HK-doped gate dielectric layers 125P1-125P2 may have a cross Figure 1E The dopant concentration profile 136 of the DD line is as follows: Figure 1FAs shown. The metal dopant concentration of the P-type dipole in the diffusion barrier layers 123P1-123P2 may be higher than the metal dopant concentration in the HK-doped gate dielectric layers 125P1-125P2. The peak concentration of the metal dopant of the P-type dipole may be in the diffusion barrier layers 123P1-123P2 and closer to the barrier-IL interface P1-P3, as shown. Figure 1F shown.

[0124] In some embodiments, the WFM layer 126 of the gate structures 112N1-112N3 and 112P1-112P3 may include the same N-type WFM ("nWFM") layer 126 or P-type WFM ("pWFM") layer 126. In some embodiments, the WFM layer 126 of the gate structures 112N1-112N3 may include nWFM 126 and the gate structures 112P1-112P3 may include pWFM 126. The nWFM layer 126 may include a metal or a metal-containing material having a work function value closer to the conduction band energy than the valence band energy of the material of the nanostructure channel region 121N-121P. In some embodiments, the nWFM layer 126 may have a work function value less than about 4.5 eV. The pWFM layer 126 may include a metal or a metal-containing material having a work function value closer to the valence band energy than the conduction band energy of the material of the nanostructure channel region 121N-121P. In some embodiments, the pWFM layer 126 may have a work function value equal to or greater than about 4.5 eV.

[0125] In some embodiments, the nWFM layer 126 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped Ti, aluminum-doped TiN, aluminum-doped Ta, aluminum-doped TaN, or other suitable Al-based materials. In some embodiments, the pWFM layer 126 may include a metal, metal nitride, or metal alloy that is substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, tantalum copper (Ta-Cu), molybdenum nitride (MoN), molybdenum (Mo), and tungsten (W).

[0126] In some embodiments, the gate metal filling layer 128 may include a suitable conductive material, such as W, Ti, Al, Mo, silver (Ag), ruthenium (Ru), copper (Cu), cobalt (Co), iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. The insulating capping layer 132 may protect the underlying conductive capping layer 130 from structural and / or compositional degradation during subsequent processes of the semiconductor device 100. In some embodiments, the insulating capping layer 132 may include a nitride material such as SiN, and may have a thickness of about 5 nm to about 10 nm to fully protect the underlying conductive capping layer 130. The conductive capping layer 130 may provide a conductive interface between the gate metal filling layer 128 and a gate contact structure (not illustrated) to electrically connect the gate metal filling layer 128 to the gate contact structure without forming a gate contact structure directly above or within the gate metal filling layer 128. In some embodiments, the conductive capping layer 130 may include a metal material, such as W, Ru, Ir, Mo, and combinations thereof, or other suitable metal materials.

[0127] Figure 2 1 is a flow chart of an example method 200 for fabricating NFET 102N and PFET 102P according to some embodiments. For purposes of illustration, reference will be made to a method for fabricating NFET 102N and PFET 102P. Figure 3A-Figure 20B The example manufacturing process of NFET 102N and PFET 102P shown in FIG. Figure 2 According to some embodiments, Figures 3A-20A The NFET 102N is manufactured at different stages along Figure 1A The cross-section diagram of line AA, Figure 3B-Figure 20B The PFET 102P is manufactured at different stages along Figure 1A The operations may be performed in a different order, or not at all, depending on the particular application. It should be noted that method 200 may not produce a complete NFET 102N and PFET 102P. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes may only be briefly described here. Figure 3A-Figure 20B Zhongyu Figure 1A-1E Components in a component have the same annotation.

[0128] Reference Figure 2 In operation 205, a superlattice structure is formed on the fin base, and a polysilicon structure is formed on the superlattice structure for NFET and PFET. Figure 3A and Figure 3BAs described, superlattice structures 320N and 320P are formed on fin bases 106N and 106P, respectively, and polysilicon structures 312N and 312P are formed on superlattice structures 320N and 320P, respectively. Superlattice structure 320N may include nanostructure layers 121N and 321 arranged in an alternating configuration. Similarly, superlattice structure 320P may include nanostructure layers 121P and nanostructure layers 321 arranged in an alternating configuration. In some embodiments, nanostructure layer 321 includes a material different from nanostructure layers 121N and 121P. Nanostructure layer 321 is also referred to as "sacrificial layer 321". In subsequent processes, polysilicon structures 312N and 312P and sacrificial layer 321 may be replaced in a gate replacement process to form gate structures 112N1-112N3 and 112P1-112P3.

[0129] Reference Figure 2 In operation 210, source / drain regions are formed on the fin base. For example, as shown in FIG. Figure 3A and Figure 3B As described, source / drain regions 110N and 110P are formed on fin bases 106N and 106P, respectively. In some embodiments, source / drain regions 110N and 110P may be epitaxially grown on fin bases 106N and 106P. Before forming source / drain regions 110N and 110P, inner spacers 113 may be formed in superlattice structures 320N and 320P, such as Figure 3A and Figure 3B After forming the source / drain regions 110N and 110P, an ESL 117 and an ILD layer 118 may be formed. Figure 3A and Figure 3B shown.

[0130] refer to Figure 2 In operation 215, a gate opening is formed. For example, as shown in FIG. Figure 4A and Figure 4B As described above, gate openings 412N1-412N3 and 412P1-412P3 are formed. Figure 3A and Figure 3B The polysilicon structures 312N and 312P and the sacrificial layer 321 are removed from the structure to form gate openings 412N1 - 412N3 and 412P1 - 412P3.

[0131] Reference Figure 2 In operation 220, an IL layer is formed in the gate opening. For example, as shown in FIG. Figure 5A and Figure 5BAs described, the IL layer 122 is formed in the gate openings 412N1-412N3 and 412P1-412P3. In some embodiments, the IL layer 122 can be formed by performing a wet oxidation process on the exposed surfaces of the nanostructure channel regions 121N and 121P and the fin bases 106N and 106P in the gate openings 412N1-412N3 and 412P1-412P3. The wet oxidation process can oxidize the tops of the nanostructure channel regions 121N-121P and the fin bases 106N-106P to form the IL layer 122.

[0132] In some embodiments, the wet oxidation process may include exposing the surfaces of the nanostructure channel regions 121N and 121P and the fin bases 106N and 106P in the gate openings 412N1-412N3 and 412P1-412P3 to an oxidizing solution mixture of dilute hydrochloric acid (HCl), hydrogen peroxide (H2O2), and deionized (DI) water for a period of about 20 seconds to about 100 seconds. In some embodiments, the volume ratio between the diluted HCl, H2O2, and deionized water in the oxidizing solution mixture (HCl:H2O2:DI) may be about 1:1:50 to about 2:1:100. Within this range of the volume ratio of HCl, H2O2, and deionized water, the growth of the IL layer 122 may be sufficiently controlled to achieve a thickness of about 0.4 to about 0.8 nm, and have a higher film density than that achieved with other oxidation processes. Furthermore, within this volume ratio range, the IL layer 122 can be grown with reduced oxygen trap densities at the interfaces between the IL layer 122 and the nanostructured channel regions 121N-121P and between the IL layer 122 and the HK gate dielectric layers 124N1-124N3 and 124P1, compared to results achieved with other oxidation processes. The reduced interfacial oxygen trap densities can reduce device current leakage and improve gate performance.

[0133] Reference Figure 2 In operation 225, a diffusion barrier layer is deposited on the IL layer. Figure 5A and Figure 5BAs described, a diffusion barrier layer 523 having diffusion barrier layer portions ("barrier portions") 523N1-523N3 and 523P1-523P3 is deposited on the IL layer 122 in the gate openings 412N1-412N3 and 412P1-412P3. In subsequent processes, the barrier portions 523N1-523N3 and 523P1-523P3 form diffusion barrier layers 123N1-123N3 and 123P1-123P3. The deposition of the diffusion barrier layer 523 may include depositing a metal oxide including a metal oxide having a lower Gibbs free energy of formation than the metal oxide (e.g., HfO2) in the HK gate dielectric layers 124N1-124N3 and 124P1-124P3. In some embodiments, depositing the metal oxide may include depositing a layer of Al2O3, La2O3, Sc2O3, Y2O3, Gd2O3, MgO, CaO, or ZrSiO4 on the IL layer 122 in a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, depositing the metal oxide may include depositing a metal oxide having a thickness of about 0.3 nm to about 0.5 nm on the IL layer 122 to sufficiently prevent oxidation of the nanostructure channel regions 121N-121P and the fin bases 106N-106P without affecting the device manufacturing cost.

[0134] Reference Figure 2 In operation 230, a first HK gate dielectric layer is deposited on the diffusion barrier layer. Figure 5A and Figure 5B As described, a first HK gate dielectric layer 525 having HK gate dielectric layer portions ("HK portions") 525N1-525N3 and 525P1-525P3 is deposited on the diffusion barrier layer 523 in the gate openings 412N1-412N3 and 412P1-412P3. In subsequent processing, the HK portions 525N1-525N3 and 525P1-525P3 form doped HK gate dielectric layers 125N1-125N3 and 125P1-125P3. The deposition of the first HK dielectric layer 525 may include depositing a high dielectric constant (high-k) dielectric material having a thickness of about 1 nm to about 2 nm, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, and ZrSiO2.

[0135] refer to Figure 6A-Figure 20B Describe the operation 235-245 Figure 5A and Figure 5B The subsequent process of the structure. Figures 6A-20A yes Figure 5AAn enlarged view of the gate regions 112A1-112A3, Figure 5B-Figure 20B yes Figure 5B An enlarged view of the gate regions 112B1-112B3.

[0136] Reference Figure 2 In operation 235, a doping process is performed on the first HK gate dielectric layer and the diffusion barrier layer. Figures 6A-19B As described, a doping process is performed to dope the barrier portions 523N1-523N3 and the HK portions 525N1-525N3 in the gate openings 412N1-412N3 and simultaneously dope the barrier portions 523P1-523P3 and the HK portions 525P1-525P3 in the gate openings 412P1-412P3. The barrier portions 523N1-523N3 and the HK portions 525N1-525N3 are doped with a first type of metal dopant that induces an N-type dipole of the dipole layers 140N1-140N3. The barrier portions 523P1-523P3 and the HK portions 525P1-525P3 are doped with a second type of metal dopant that simultaneously induces a P-type dipole of the dipole layers 140P1-140P3. The first type and the second type of metal dopant are different from each other.

[0137] The doping process may include the following sequential operations: (i) depositing a doping source layer 646 on the HK portions 525N1-525N3 and 525P1-525P3, such as Fig. 6A and Figure 6B (ii) selectively removing the portion of the doping source layer 646 on the HK portions 525N2-525N3 and 525P1-525P3 using a photolithography patterning and etching process to form Fig. 7A and Figure 7B (iii) depositing a doping source layer 846 on the doping source layer 646 and the HK portions 525N2-525N3 and 525P1-525P3, as shown in FIG. Fig. 8A and Figure 8B (iv) selectively removing the portion of the doping source layer 846 on the HK portion 525N3 and 525P1-525P3 using a photolithography patterning and etching process to form Fig. 9A and Fig. 9B structure, (v) such as Fig. 10A and Fig. 10B As shown, depositing a doping source layer 1046 on the doping source layer 846 and the HK portions 525N3 and 525P1-525P3, (vi) selectively removing portions of the doping source layer 1046 on the HK portions 525P1-525P3 using a photolithography patterning and etching process to form Fig.11A and the structure of FIG. 11B, (vii) as Fig. 12A and Fig. 12BAs shown, depositing a doping source layer 1248 on the doping source layer 1046 and the HK portions 525P1-525P3, (viii) selectively removing the HK portions 525P1-525P2 and the doping source layer 1248 on the doping source layer 1046 using a photolithography patterning and etching process to form Fig.13A and Fig. 13B (ix) depositing a doping source layer 1448 on the doping source layers 1046 and 1248 and the HK portions 525P1-525P2, as shown in FIG. Fig.14A and Fig. 14B As shown, (x) using photolithography patterning and etching processes to selectively remove the HK portion 525P1 and the portion of the doping source layer 1448 on the doping source layer 1046 to form Fig.15A and Fig. 15B 16A and 16B, depositing a doping source layer 1648 on the doping source layers 1046 and 1448 and the HK portion 525P1, (xii) selectively removing a portion of the doping source layer 1648 on the doping source layer 1046 using a photolithography patterning and etching process to form Fig.17A and Fig. 17B structure, (xiii) Fig.17A and Fig. 17B The structure of FIG. 1 is subjected to a drive-in annealing process to form doped barrier portions 1823N1-1823N3 and 1823P1-1823P2 and doped HK portions 1825N1-1825N3 and 1825P1-1825P3, as shown in FIG. Fig.18A and Fig.18B As shown, (xiv) from Fig.18A and Fig.18B Remove the doping source layers 646, 846, 1046, 1248, 1448 and 1648 from the structure to form Fig.19A and Fig.19B The structure of , and (xv) Fig.19A and Fig.19B The structure is subjected to an annealing process.

[0138] although Figures 6A-19B The doping source layer of NFET 102N is illustrated as being formed before the doping source layer of PFET 102P, but the formation of the doping source layers of NFET 102N and PFET 102P may be performed in any order. In some embodiments, doping source layers 1248, 1448, and 1648 may be formed on HK portions 525P1-525P3 before forming doping source layers 646, 846, and 1046 on HK portions 525N1-525N3.

[0139] The deposition of each doping source layer 646, 846, and 1046 may include depositing a REM oxide, such as La2O3, Y2O3, cerium oxide (CeO2), ytterbium oxide (Yb2O3), and erbium oxide (Er2O3) in a CVD process or an ALD process. In some embodiments, each doping source layer 646, 846, and 1046 is formed by depositing a REM oxide layer of a metal oxide different from the diffusion barrier layer 523. In some embodiments, the deposition of each doping source layer 646, 846, and 1046 may include depositing a La2O3 layer when the diffusion barrier layer 523 is formed by depositing an Al2O3 layer. In some embodiments, without affecting the manufacturing cost of the device, depositing a REM oxide for each doping source layer 646, 846, and 1046 may include depositing a REM oxide having a thickness of about 1 nm to about 3 nm to fully dope the barrier portions 523N1-523N3 and the HK portions 525N1-525N3. In some embodiments, the doping source layers 646 , 846 , and 1046 may have the same REM oxide.

[0140] The deposition of each doping source layer 1248, 1448, and 1648 may include depositing a metal oxide, such as zinc oxide (ZnO), GeO2, Al2O3, titanium oxide (TiO2), and vanadium oxide (V2O3) in a CVD process or an ALD process. In some embodiments, each doping source layer 1248, 1448, and 1648 is formed by depositing a layer of a metal oxide that is different from the metal oxide of the diffusion barrier layer 523. In some embodiments, without affecting the manufacturing cost of the device, depositing the metal oxide for each doping source layer 1248, 1448, and 1648 may include depositing a metal oxide having a thickness of about 1 nm to about 3 nm to fully dope the barrier portions 523P1-523P3 and the HK portions 525P1-525P3. In some embodiments, the doping source layers 1248, 1448, and 1648 may have the same metal oxide.

[0141] Different numbers of dopant source layers are deposited on the HK portions 525N1-525N3 for doping the barrier portions 523N1-523N3, and the HK portions 525N1-525N3 have different concentrations of the first type metal dopant to induce different concentrations of N-type dipoles in the dipole layers 140N1-140N3. For example, a stack of three doping source layers 646, 846, and 1046 can inject a higher concentration of the first type metal dopant into the barrier portion 523N1 and the HK portion 525N1 than from a stack of two doping source layers 646 and 846 injected into the barrier portion 523N2 and the HK portion 525N2, and from one doping source layer 646 injected into the barrier portion 523N3 and the HK portion 525N3. Similarly, different numbers of doping source layers are deposited on the HK portions 525P1-525P3 to dope the barrier portions 523P1-523P3 and the HK portions 525P1-525P3 with different concentrations of the second type metal dopant to induce different concentrations of P-type dipoles in the dipole layers 140P1-140P3. For example, a stack of three doping source layers 1248, 1448, and 1648 can inject a higher concentration of the second type metal dopant into the barrier portion 523P2 and the HK portion 525P3 than from a stack of two doping source layers 1448 and 1648 injected into the barrier portion 523P3 and the HK portion 525P3, and from the doping source layer 1648 injected into the barrier portion 523P1 and the HK portion 525P1.

[0142] The drive-in annealing process can diffuse (i) metal atoms from the doping source layers 646, 846 and 1046 into the barrier portion 523N1 and the HK portion 525N1 to form the doped barrier portion 1823N1 and the HK portion 1825N1, (ii) metal atoms from the doping source layers 846 and 1046 into the barrier portion 523N2 and the HK portion 525N2 to form the doped barrier portion 1823N2 and the HK portion 1825N2, and (iii) metal atoms from the doping source layer 1046 into the barrier portion 523N3 and the HK portion 525N3 to form the doped barrier portion 1823N3 and the HK portion 1825N3. At the same time, the drive-in annealing process can diffuse (i) metal atoms from the doping source layers 1248, 1448 and 1648 into the barrier portion 523P3 and the HK portion 525P3 to form the doped barrier portion 1823P3 and the HK portion 1825P3, (ii) metal atoms from the doping source layers 1448 and 1648 into the barrier portion 523P2 and the HK portion 525P2 to form the doped barrier portion 1823P2 and the HK portion 1825P2, and (iii) metal atoms from the doping source layer 1648 into the barrier portion 523P1 and the HK portion 525P1 to form the doped barrier portion 1823P1 and the HK portion 1825P1.

[0143] The drive-in annealing process may include heating the substrate to a temperature of about 500° C. to about 700° C. in a nitrogen environment. Fig.17A and Fig. 17B The structure is annealed for a time of about 10 seconds to about 30 seconds. Before the drive-in annealing process, the metal atoms of the doping source layers 646, 846, 1046, 1248, 1448 and 1648 may have a cross Fig.17A EE line and Fig. 17B The concentration distribution of FF line 2136 is as follows Fig.21 After the drive-in annealing process, the metal dopants in the barrier portions 1823N1-1823N3 and 1823P1-1823P2 and the doped HK portions 1825N1-1825N3 and 1825P1-1825P3 may have a concentration profile 136, as shown in FIG. Figure 1F As shown, across Fig.18A The CC line and Fig.18B In some embodiments, the annealing process performed after removing the doping source layers 646, 846, 1046, 1248, 1448, and 1648 may be similar to the drive-in annealing process.

[0144] Before the drive-in annealing process, the metal atoms of the diffusion barrier layer 523 may have a concentration profile 2134, such as Fig.21 As shown, across Fig.17A EE line and Fig. 17B In some embodiments, the drive-in annealing process may cause some metal atoms of the metal oxide of the diffusion barrier layer 523 to diffuse into the HK portions 525N1-525N3 and 525P1-525P3 and the IL layer 122. Therefore, after the drive-in annealing process, the metal concentration profile 2134 (e.g., Fig.21 ) can be transformed into a metal concentration profile 134, such as Figure 1F .

[0145] Reference Figure 2 In operation 240, a second HK gate dielectric layer is deposited in the gate openings of the NFET and the PFET. Fig. 20A and Fig. 20BAs described, the second HK gate dielectric layer 2027 is deposited on the HK portions 525N1-525N3 and 525P1-525P3 in the gate openings 412N1-412N3 and 412P1-412P3. The deposition of the second HK gate dielectric layer 2027 may include depositing a layer of a high dielectric constant (high-k) dielectric material, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, and ZrSiO2, with a thickness of about 0.5 nm to about 1 nm. In subsequent processes, the second HK gate dielectric layer 2027 forms undoped HK gate dielectric layers 127N1-127N3 and 127P1-127P3.

[0146] Reference Figure 2 In operation 245, a WFM layer is deposited on the second HK gate dielectric layer and a gate metal fill layer is deposited on the WFM layer. Fig. 20A and Fig. 20B As depicted, the WFM layer 2026 is deposited on the second HK gate dielectric layer 2027 and the gate metal fill layer 2228 is deposited on the WFM layer 2026. In some embodiments, the deposition of the WFM layer 2026 may include depositing a pWFM layer or an nWFM layer on the second HK gate dielectric layer 2027. In some embodiments, the deposition of the WFM layer 2026 may include selectively forming an nWFM layer on a portion of the second HK gate dielectric layer 2027 of the NFET 102N and / or selectively forming a pWFM layer on a portion of the second HK gate dielectric layer 2027 of the PFET 102P. The deposition of the gate metal fill layer 2228 may be followed by a chemical mechanical polishing (CMP) process and an etching process on the gate structures 112N1-112N3 and 112P1-112P3 to form diffusion barrier layers 123N-123N3 and 123P1-123P2, HK gate dielectric layers 124N1-124N2 and 124P1-124P2, WFM layer 126 and gate metal fill layer 128, as shown in FIG. Figure 1B-Figure 1E After the etching process, a conductive capping layer 130 and an insulating capping layer 132 may be formed.

[0147] The present disclosure provides an example method of forming GAA FETs (e.g., GAA FETs 102N and 102P) with improved thickness profile control of an IL layer (e.g., IL layer 122) and having different gate structures (e.g., gate structures 112N1-112N3 and 112P1-112P3) configured to provide different threshold voltages on the same substrate (e.g., substrate 104). The example method forms NFETs and PFETs (e.g., NFET 102N and PFET 102P) with a scaled IL layer (e.g., IL layer 122) of about 0.4 nm to about 0.8 nm for a reduced capacitance effective thickness (CET), thereby increasing FET drive current. In addition, the example method forms NFETs and PFETs with substantially equal thickness WFM layers (e.g., WFM layer 126) on the same substrate and with very low, ultra-low and / or low threshold voltages. Compared to other methods of forming GAA FETs with similar size and threshold voltage on the same substrate, these example methods can be more cost-effective (e.g., reducing costs by about 20% to about 30%) and time-efficient (e.g., reducing time by about 15% to about 20%) in manufacturing GAA FET gate structures with different reliability. In addition, compared to other methods of forming GAA FETs with similar threshold voltage, these example methods can form GAA FET gate structures with much smaller size (e.g., thinner gate stacks).

[0148] In some embodiments, the gate structure of the NFET and the PFET may include a diffusion barrier layer (e.g., diffusion barrier layers 123N1-123N3 and 123P1-123P3) disposed on the IL layer (e.g., IL layer 122). The diffusion barrier layer may prevent or minimize the diffusion of oxygen atoms from the cap layer (e.g., HK gate dielectric layers 124N1-124N3 and 124P1-124P3) to the nanostructure channel region (e.g., nanostructure channel regions 121N and 121P) during the thermal process of the NFET and the PFET. Preventing or minimizing the diffusion of oxygen atoms may prevent or minimize the oxidation of the nanostructure channel region. Therefore, by using the diffusion barrier layer, the IL layer may be sufficiently maintained at a thickness of about 0.4 nm to about 0.8 nm during different thermal processes performed in the manufacture of the NFET and the PFET. In some embodiments, in order to fully control the thickness distribution of the IL layer, the diffusion barrier layer may include a metal oxide having a lower Gibbs free energy of formation than the metal oxide of the HK gate dielectric layer (e.g., HfO2). In some embodiments, such a metal oxide of the diffusion barrier layer may include Al2O3, La2O3, Sc2O3, Y2O3, Gd2O3, MgO, CaO, or ZrSiO4. In some embodiments, the diffusion barrier layer may have a thickness of about 0.3 nm to about 0.5 nm to sufficiently prevent or minimize the diffusion of oxygen atoms without affecting device size and manufacturing cost.

[0149] In some embodiments, NFETs and PFETs having different gate structure configurations but having substantially equal thicknesses of WFM layers may be formed on the same substrate to achieve different threshold voltages. Different gate structures may have diffusion barrier layers (e.g., diffusion barrier layers 123N1-123N3 and 123P1-123P3) and HK gate dielectric layers (e.g., HK gate dielectric layers 125N1-125N3 and 125P1-125P3) doped with different types and / or concentrations of metal dopants. Different types and / or concentrations of metal dopants may induce dipoles of different polarities and / or concentrations at the barrier-IL interface (e.g., barrier-IL interface N1-N3 and P1-P3). Dipoles of different polarities and / or concentrations result in gate structures with different EWF values. Since the EWF values ​​of the gate structures correspond to the threshold voltages of the NFETs and PFETs, gate structures with different EWF values ​​result in NFETs and PFETs with different threshold voltages on the same substrate. Therefore, controlling the type and / or concentration of metal dopants in the diffusion barrier layer and HK gate dielectric layer can adjust the EWF value of the NFET and PFET gate structures, and thus the threshold voltage of the NFET and PFET without changing the WFM layer thickness.

[0150] In some embodiments, a method is provided including forming a nanostructure channel region on a fin base, forming a gate opening around the nanostructure channel region, forming an oxide layer on an exposed surface of the fin base in the nanostructure channel region and the gate opening, depositing a diffusion barrier layer on the oxide layer, depositing a first dielectric layer on the diffusion barrier layer, performing a doping process on the diffusion barrier layer and the first dielectric layer to form a doped diffusion barrier layer and a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.

[0151] In some embodiments, a method is provided including forming first and second nanostructure channel regions on first and second fin bases, respectively, forming first and second gate openings surrounding the first and second nanostructure channel regions, respectively, performing an oxidation process on exposed surfaces of the first and second nanostructure channel regions, respectively depositing a diffusion barrier layer having first and second barrier portions in the first and second gate openings, respectively, performing a doping process on the first and second barrier portions to form a first second doped barrier portion having first and second metal dopants, respectively, and depositing a conductive layer on the first and second doped barrier portions.

[0152] In some embodiments, a semiconductor device is provided, including a substrate, a nanostructure channel region disposed on the substrate, and a gate structure. The gate structure includes an oxide layer surrounding the nanostructure channel region, a doped diffusion barrier layer on the oxide layer, a dipole layer disposed between the oxide layer and the doped diffusion barrier layer, and a doped dielectric layer disposed on the doped diffusion barrier layer.

[0153] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate; A nanostructure channel region is disposed on the substrate; as well as A gate structure comprising: an oxide layer surrounding the nanostructure channel region; a doped diffusion barrier layer located on the oxide layer; a dipole layer disposed between the oxide layer and the doped diffusion barrier layer; and A doped dielectric layer is disposed on the doped diffusion barrier layer.

2. The semiconductor device according to claim 1, wherein The doped diffusion barrier layer includes a metal oxide having a Gibbs formation free energy lower than a Gibbs formation free energy of a metal oxide of the doped dielectric layer.

3. The semiconductor device according to claim 1 or 2, wherein: The thickness of the doping diffusion barrier layer is 0.3nm to 0.5nm.

4. The semiconductor device according to claim 1, wherein: The thickness of the nanostructure channel region is 5 nm to 8 nm.

5. The semiconductor device according to claim 1, wherein: The width of the nanostructure channel region is 15 nm to 50 nm.

6. The semiconductor device according to claim 1, wherein: The thickness of the oxide layer is 0.4 nm to 0.8 nm.

7. The semiconductor device according to claim 1, wherein: The gate structure also includes a work function metal layer disposed on the doped dielectric layer.

8. The semiconductor device according to claim 7, wherein: The gate structure also includes a gate metal filling layer, which is arranged on the work function metal layer.

9. The semiconductor device according to claim 8, wherein: The gate structure also includes a conductive cap layer, which is disposed on the doped dielectric layer, the work function metal layer and the gate metal filling layer.

10. The semiconductor device according to claim 9, wherein: The gate structure also includes an insulating capping layer disposed on the conductive capping layer.

Images