Array substrate and display device
By introducing an electrostatic release structure into the array substrate, the static electricity is exported, which solves the problem of electrostatic release in metal traces and improves the yield and reliability of the product.
Patent Information
- Application Number
- CN202420898236.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-26
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-04-26
AI Technical Summary
Metal traces in the array substrate are prone to electrostatic discharge, resulting in short circuits and device damage, affecting product yield.
An array substrate is designed, including an electrostatic release structure arranged between the display area and the peripheral area, through which the electrostatic release structure is used to guide the static electricity to avoid the impact of electrostatic release on the metal trace.
It effectively avoids metal trace short circuits and device damage caused by static electricity release, and improves product yield and reliability.
Smart Images
Figure CN222638988U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of display technology, and particularly relates to an array substrate and a display device. Background Art
[0002] Tip discharge is a type of discharge that occurs at the sharp part of an object under the action of a strong electric field. In the design process of array substrates, the internal circuits are complex and often a large number of metal traces are laid out. Due to factors such as external static electricity and static electricity generated by the internal film layer, electrostatic discharge (ESD) is often prone to occur at the end of the metal traces, also known as tip discharge, which can easily lead to irreversible damage such as metal trace short circuits and device burnout, seriously affecting product yield. Utility Model Content
[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides an array substrate and a display device.
[0004] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is an array substrate, which has a display area and a peripheral area surrounding the display area; the array substrate comprises a base substrate, a plurality of gate lines arranged on the base substrate, a shift register arranged in the peripheral area, and an electrostatic release structure arranged on a side of the shift register close to the display area; the gate lines extend from the display area to the peripheral area;
[0005] The gate line is in the same layer as the electrostatic release structure, and the gate line has a first end close to the electrostatic release structure; the first end of the gate line is electrically connected to the output end of the shift register through a first switching structure; the orthographic projection of the electrostatic release structure on the base substrate does not overlap with the orthographic projection of the output end of the shift register on the base substrate.
[0006] In some embodiments, the shift register comprises at least a first capacitor; the first capacitor comprises a first plate and a second plate arranged opposite to each other;
[0007] The electrostatic release structure is electrically connected to the second electrode plate; the first end of the gate line is electrically connected to the first electrode plate through a first transfer structure.
[0008] In some embodiments, a first contour edge of an orthographic projection of the second electrode plate on the substrate surrounds a second contour edge of an orthographic projection of the first electrode plate on the substrate;
[0009] The electrostatic release structure and the second electrode plate connected thereto are an integrated structure.
[0010] In some embodiments, the array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate;
[0011] The first electrode plate includes a first main body and an inner concave portion arranged side by side in a column direction, and the inner concave portion is connected to the first main body as an integral structure; the first adapter structure is electrically connected to the first main body;
[0012] The orthographic projection of the inner recess on the base substrate and the orthographic projection of the electrostatic release structure on the base substrate are arranged side by side along the row direction; the first surface of the inner recess close to the display area is farther away from the display area than the second surface of the first main body close to the display area.
[0013] In some embodiments, the array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate;
[0014] The second electrode plate comprises a second main body and a protruding portion arranged side by side along a row direction, the second main body and the protruding portion are connected to form an integral structure, and the protruding portion is closer to the display area than the second main body;
[0015] The orthographic projections of the first electrode plate and the second main body on the base substrate overlap; the orthographic projection of the first electrode plate on the base substrate does not overlap with the orthographic projection of the protruding portion on the base substrate.
[0016] In some embodiments, the orthographic projection of the connection point between the first transfer structure and the first electrode plate on the second electrode plate is closer to the center of the second electrode plate than the connection point between the electrostatic release structure and the second electrode plate.
[0017] In some embodiments, the array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate;
[0018] The second electrode plate includes a third surface close to the display area, and a fourth surface and a fifth surface respectively connected to the third surface and arranged opposite to each other along the column direction;
[0019] For the first capacitors in two adjacent shift registers, one end of the third surface of the second electrode plate of one of them close to the fourth surface is connected to one of the electrostatic release structures; and the other end of the third surface of the second electrode plate of the other first capacitor close to the fifth surface is connected to another of the electrostatic release structures.
[0020] In some embodiments, the plurality of shift registers are divided into a plurality of groups, each shift register group comprising two adjacent shift registers;
[0021] For any group of the shift register groups, a line connecting the center of one of the second electrodes and the center of another of the second electrodes is a first line, and a center line passing through the center of the first line along the row direction is a symmetry axis, and the electrostatic release structure electrically connected to the two second electrodes is symmetrically arranged.
[0022] In some embodiments, the array substrate further includes a power signal line extending along the row direction, one power signal line is correspondingly arranged between two groups of the shift register groups, and is configured to provide the same power signal to two adjacent shift registers.
[0023] In some embodiments, the shortest distance between the electrostatic release structure and the first end of the gate line is between 15 μm and 50 μm.
[0024] In some embodiments, the outline shape of the orthographic projection of the electrostatic release structure on the substrate is any one of a triangle, a rectangle and a trapezoid; the first end includes a first side surface and a second side surface arranged opposite to each other in a column direction, and the second side surface is closer to the output end than the first side surface;
[0025] When the contour shape of the orthographic projection of the electrostatic release structure on the substrate is a triangle, a vertex of the triangle is close to the first end of the gate line on the substrate, and the shortest distance from the vertex to the extension surface of the second side surface in the row direction is a second spacing;
[0026] When the outline shape of the orthographic projection of the electrostatic release structure on the substrate is a rectangle, the short side of the rectangle is close to the first end of the gate line on the substrate, and the shortest distance from the center line extending in the row direction of the short side to the extension surface of the second side in the row direction is the second spacing;
[0027] When the contour shape of the positive projection of the electrostatic release structure on the substrate is a trapezoid, the top edge of the trapezoid is close to the first end of the gate line on the substrate, and the shortest distance from the center line extending along the row direction of the top edge to the extension surface of the second side in the row direction is the second spacing.
[0028] In some embodiments, the array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate;
[0029] The array substrate further includes a first common electrode and a plurality of second common electrodes; the first common electrode extends from the display area to the peripheral area and is electrically connected to each second common electrode through a first connecting via hole; one second common electrode is arranged corresponding to a row of pixel units.
[0030] In some embodiments, the second common electrode is disposed in the same layer as the gate line;
[0031] The gate line includes a first line and a second line; the first line extends from the display area to the peripheral area, and the first line is electrically connected to the second line through a second switching structure; the second line is electrically connected to the first electrode plate through the first switching structure;
[0032] The second routing line includes a plurality of sub-routing lines extending in different directions, and the plurality of sub-routing lines extending in different directions semi-circle the second common electrode.
[0033] In some embodiments, the first transfer structure includes a first transfer portion and a second transfer portion electrically connected to the first transfer portion; the first transfer portion is electrically connected to the first electrode plate, and the second transfer portion is electrically connected to the first end of the gate line;
[0034] An extending direction of the first transition portion is different from an extending direction of the second transition portion.
[0035] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising an array substrate as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 A schematic diagram of an array substrate provided in an embodiment of the present disclosure;
[0037] Figure 2 A circuit diagram of a shift register provided in an embodiment of the present disclosure;
[0038] Figure 3a It is a schematic diagram of the structure of the electrical connection between the gate line and the shift register in the related art;
[0039] Figure 3b for Figure 3a A-A' cross-sectional view of the structure;
[0040] Figure 3c for Figure 3a Schematic diagram of scanning electron microscopy (SEM) of the MM region in the structure;
[0041] Figure 4 A schematic diagram of a partial structure of an array substrate provided in an embodiment of the present disclosure;
[0042] Figure 5 for Figure 4 A cross-sectional view of the structure shown in the BB' direction;
[0043] Figure 6a A schematic diagram of a gate metal layer provided in an embodiment of the present disclosure;
[0044] Figure 6b A schematic diagram of a source-drain electrode layer provided in an embodiment of the present disclosure;
[0045] Figure 7 A schematic diagram of a local structure of an array substrate in Example 1 provided in an embodiment of the present disclosure;
[0046] Figure 8 A schematic diagram of a local structure of an array substrate in Example 2 provided in an embodiment of the present disclosure;
[0047] Fig. 9 A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure;
[0048] Fig.10 for Fig. 9 Enlarged view of the C-C' region;
[0049] Fig.11 A schematic diagram of the first example of an electrostatic release structure provided in an embodiment of the present disclosure;
[0050] Fig.12 A schematic diagram of the second example of the electrostatic release structure provided in the embodiment of the present disclosure;
[0051] Fig.13 This is a schematic diagram of the third example of the electrostatic release structure provided in the embodiment of the present disclosure. DETAILED DESCRIPTION
[0052] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.
[0053] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0054] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.
[0055] In the embodiment of the present disclosure, the first direction X, the second direction Y and the third direction Z intersect each other in pairs. In the present disclosure, the first direction X and the second direction Y are perpendicular to each other in the plane where the substrate is located, the first direction X is a horizontal direction (or an extension direction of the gate line Gate), the second direction Y is a vertical direction (or an extension direction of the data line Data), and the third direction Z is a vertical direction, which is perpendicular to the plane where the substrate is located, for illustration, but does not constitute a limitation to the present disclosure.
[0056] In the embodiments of the present disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a single patterning process. Depending on the specific pattern, the sequential patterning process may include multiple exposure, development or etching processes, and the specific patterns of the same layer formed may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
[0057] Before introducing the specific structure of the array substrate of the present disclosure, the application scenario and circuit structure of the array substrate provided by the present disclosure are first described in detail. The array substrate of the present disclosure is applied to liquid crystal display, that is, a liquid crystal array substrate. Figure 1As shown, the array substrate has a display area AA and a peripheral area BB surrounding the display area AA. The display area AA refers to the area of the array substrate where the image is actually displayed. The peripheral area BB refers to the area of various circuits and wirings in the array substrate for sending signals to the pixel unit 20. The array substrate includes a substrate substrate, a plurality of gate lines Gate, a plurality of data lines Data, and a plurality of shift registers 10 arranged on the substrate substrate. The gate lines Gate and the data lines Data intersect to define a plurality of pixel areas, each of which is provided with a pixel unit 20. The plurality of pixel units 20 are arranged in an array and are all located in the display area AA. The pixel unit 20 includes a plurality of sub-pixels and a pixel driving circuit for driving the sub-pixels. The pixel driving circuit includes a driving transistor T and a second capacitor C2. The first electrode of the driving transistor T is electrically connected to the data line Data, the second electrode circuit of the driving transistor T is connected to the first plate of the second capacitor C2, and the gate of the driving transistor T is electrically connected to the gate line Gate. The second plate of the second capacitor C2 is electrically connected to the first common electrode Vcom1.
[0058] The structure of the array substrate is described by taking the extension direction of each gate line Gate as the row direction X and the extension direction of each data line Data as the column direction Y as an example. The gate line Gate extends from the display area AA to the peripheral area BB along the row direction X, and is electrically connected to the gate integrated drive circuit (Gate On Array, GOA). Specifically, GOA includes a plurality of cascaded shift registers 10, and a gate line Gate is actually electrically connected to a shift register 10 to receive a gate scan signal; the data line Data extends from the display area AA to the peripheral area BB along the column direction Y, and is electrically connected to the source driver chip (Chip, IC) to receive a data voltage signal. When driving the sub-pixel for display, the gate scan signal can be written to the gate line Gate row by row according to the picture to be displayed, and the data voltage signal can be written to each data line Data at the same time, so that the pixel unit 20 in the array substrate is lit row by row.
[0059] like Figure 2 As shown in FIG. 1 , it is a circuit diagram of a shift register 10 of a liquid crystal array substrate, wherein the shift register 10 includes an input terminal INPUT, various transistors for driving the gate of the transistor T (such as transistors M1, M2, M3, etc., specifically as shown in FIG. Figure 2As shown), a first capacitor C1, a first output terminal OUT1 and a second output terminal OUT_C. Among them, the first output terminal OUT1 is electrically connected to the gate line Gate, and is used to provide a gate scan signal for the gate line Gate. OUT_C is a cascade output terminal, which is used to be electrically connected to the input terminal INPUT of the next stage shift register 10. The first plate of the first capacitor C1 is connected to the first output terminal OUT1 and the drain of the transistor M3, and the second plate of the first capacitor C1 is electrically connected to the gate of the transistor M3. The first plate of the first capacitor C1 and the drain of the transistor M3 are arranged in the same layer, and the second plate of the first capacitor C1 and the gate electrode of the transistor M3 are arranged in the same layer. The first capacitor C1 and the transistor M3 are both used to control the first output terminal OUT1 to output a gate scan signal.
[0060] In related technologies, such as Figure 3a and Figure 3b As shown, the gate line Gate extends from the display area AA to the peripheral area BB and is electrically connected to the GOA circuit located in the peripheral area BB. Specifically, the gate line Gate is electrically connected to the first electrode plate C11 of the first capacitor C1. At the connection position Q between the gate line Gate and the first electrode plate C11 of the first capacitor C1, the tip of the gate line Gate discharges. Figure 3a The direction indicated by the arrow in the middle is the electrostatic discharge direction of the gate line Gate. Figure 3c As shown, since the first plate C11 and the second plate C12 of the first capacitor C1 are arranged opposite to each other, the discharge at the tip of the gate line Gate will burn the insulating layer 30 between the first plate C11 and the second plate C12, thereby causing the gate line Gate and the second plate C12 to short-circuit, forming a defective horizontal line.
[0061] In view of this, embodiments of the present disclosure provide an array substrate that substantially eliminates one or more of the problems caused by limitations and defects of the related art.
[0062] Figure 4 A schematic diagram of a partial structure of an array substrate provided in an embodiment of the present disclosure is provided. Figure 5 for Figure 4 The cross-sectional view of the structure in the B-B' direction is shown in FIG. Figure 4 and Figure 5 As shown, the array substrate has a display area AA and a peripheral area BB surrounding the display area AA. The array substrate includes a base substrate 1, a plurality of gate lines Gate arranged on the base substrate 1, a shift register 10 arranged in the peripheral area BB, and an electrostatic release structure 40 arranged on a side of the shift register 10 close to the display area AA; the gate line Gate extends from the display area AA to the peripheral area BB.
[0063] The gate line Gate is in the same layer as the electrostatic release structure 40, and the gate line Gate has a first end N close to the electrostatic release structure 40, so that when static electricity accumulates at the tip of the gate line Gate, the electrostatic release structure 40 can induce the electrostatic release at the first end N. In one possible embodiment, the electrostatic release structure 40 can release the received static electricity to a metal pattern that has no effect on the shift register 10, such as including but not limited to a pattern in the second plate C12 of the first capacitor C1 in the shift register 10 that is not directly opposite to the first capacitor C1, or a redundant pattern of the gate of the transistor M3 in the shift register 10, etc. The "redundant pattern of the gate" can be understood as a position that has no effect on the gate of the control transistor M3. In another possible embodiment, the electrostatic release structure 40 is in a floating state, that is, there is no electrical signal.
[0064] Exemplarily, the material of the electrostatic release structure 40 is the same as that of the gate line Gate, and a pattern including the gate line Gate and the electrostatic release structure 40 can be obtained through a single preparation process.
[0065] The gate line Gate is in a different layer from the output terminal M of the shift register 10. The first terminal N of the gate line Gate is electrically connected to the output terminal M of the shift register 10 through the first switching structure 51; the orthographic projection of the electrostatic release structure 40 on the base substrate 1 does not overlap with the orthographic projection of the output terminal M of the shift register 10 on the base substrate 1.
[0066] Exemplarily, the shortest distance between the orthographic projection of the electrostatic release structure 40 on the substrate 1 and the orthographic projection of the output terminal M of the shift register 10 on the substrate 1 is recorded as the first distance L1, and the first distance L1 is not zero. Specifically, the first distance L1 is specifically represented by the straight-line distance between the orthographic projections of the point M1 and the point M2 on the substrate.
[0067] Exemplarily, there is a spacing between the orthographic projection of the electrostatic release structure 40 on the substrate 1 and the orthographic projection of the output terminal M of the shift register 10 on the substrate 1, which can be specifically manifested in that the two have a first shortest distance L11 in the column direction Y, and the two have a second shortest distance L12 in the row direction X. Both the first shortest distance L11 and the second shortest distance L12 are not zero.
[0068] In the disclosed embodiment, the static electricity released by the gate line Gate is conducted out through the electrostatic discharge structure 40, thereby avoiding the horizontal horizontal stripe defects caused by the static electricity at the end of the long gate line Gate. At the same time, there is a first spacing (L1 or L1') between the electrostatic discharge structure 40 and the output terminal M of the shift register 10 on the substrate 1. Even if the electrostatic discharge process may burn the insulating layer 30, it will not affect the output terminal M of the shift register 10 far away from the electrostatic release structure 40, and thus will not affect the normal transmission of the gate scanning signal.
[0069] In some embodiments, Figure 4 and Figure 5 As shown, the shift register 10 includes at least a first capacitor C1; the first capacitor C1 includes a first plate C11 and a second plate C12 arranged opposite to each other. Exemplarily, the second plate C12 is closer to the substrate 1 than the first plate C11. An insulating layer 30 is provided between the first plate C11 and the second plate C12.
[0070] The second plate C12 of the first capacitor C1 is electrically connected to the gate of the transistor M3. To facilitate wiring and save space, the second plate C12 is in the same layer as the gate of the transistor M3, that is, in the same layer as the gate line Gate. The first plate C11 of the first capacitor C1 is electrically connected to the drain of the transistor M3. To facilitate wiring and save space, the first plate C11 is in the same layer as the drain of the transistor M3, that is, in the same layer as the output terminal M of the shift register 10.
[0071] Figure 6a A schematic diagram of a gate metal layer provided in an embodiment of the present disclosure, Figure 6b A schematic diagram of a source-drain electrode layer provided in an embodiment of the present disclosure, such as Figure 6a and Figure 6b As shown, the array substrate includes a gate metal layer 01 and a source-drain electrode layer 02. A plurality of gate lines Gate, the gates of at least some transistors in the GOA circuit, the electrostatic release structure 40 and the second plate C12 of the first capacitor C1 are all located in the gate metal layer 01; the source, drain and the first plate C11 of the first capacitor C1 of at least some transistors in the GOA circuit are all located in the source-drain electrode layer 02.
[0072] like Figure 4 and Figure 5 As shown, the gate line Gate and the first electrode plate C11 are in different layers, and the first end N of the gate line Gate is electrically connected to the first electrode plate C11 through the first adapter structure 51. The first adapter structure 51 is electrically connected to the first end N of the gate line Gate through the via hole V1 penetrating the insulating layer 30. The first end N of the gate line Gate is the end of the gate line Gate away from the display area AA. The connection position between the first adapter structure 51 and the first electrode plate C11 is the output end M of the shift register 10 outputting the gate scanning signal.
[0073] Optionally, the first adapter structure 51 and the first electrode plate C11 are connected to form an integrated structure.
[0074] like Figure 4 and Figure 5 As shown, the electrostatic discharge structure 40 is electrically connected to the second plate C12, and is used to discharge static electricity to the second plate C12. Specifically, the electrostatic discharge structure 40 discharges static electricity to the virtual metal pattern 60 of the second plate C12 that has no effect on the first capacitor C1. The virtual metal pattern 60 of the second plate C12 can be understood as a pattern that has no overlap with the orthographic projection of the first plate C11 on the second plate C12.
[0075] Optionally, the orthographic projection of the first electrode plate C11 on the base substrate has no overlap with the orthographic projection of the electrostatic release structure 40 on the base substrate.
[0076] Optionally, the shortest distance (eg, L1 ′) from the edge contour of the orthographic projection of the first electrode plate C11 on the substrate to the edge contour of the orthographic projection of the electrostatic release structure 40 on the substrate is not zero.
[0077] In some embodiments, Figure 4 As shown, the first contour edge of the orthographic projection of the second electrode plate C12 on the base substrate 1 surrounds the second contour edge of the orthographic projection of the first electrode plate C11 on the base substrate 1. In other words, the orthographic projection of the second electrode plate C12 on the base substrate 1 completely wraps the orthographic projection of the first electrode plate C11 on the base substrate 1, which is conducive to shielding signal interference from other metal structures and ensuring the stability of the capacitor signal.
[0078] Exemplarily, the shortest distance L1 ′ between the first contour edge and the second contour edge is between 20 μm and 100 μm.
[0079] In some embodiments, the electrostatic release structure 40 and the second electrode plate C12 connected thereto are an integral structure. In the process preparation stage, a pattern including the electrostatic release structure 40 and the second electrode plate C12 can be formed by a single patterning process. The electrostatic release structure 40 and the second electrode plate C12 connected as an integral structure are more conducive to electrostatic release.
[0080] In some embodiments, Figure 7 This is a schematic diagram of a local structure of an array substrate under Example 1 provided in an embodiment of the present disclosure, such as Figure 7As shown, the first electrode plate C11 includes a first main body 11 and an inner recess 12 arranged side by side along the column direction Y, and the inner recess 12 is connected to the first main body 11 as an integral structure; the first adapter structure 51 is electrically connected to the first main body 11. The orthographic projection of the inner recess 12 on the base substrate 1 and the orthographic projection of the electrostatic release structure 40 on the base substrate 1 are arranged side by side along the row direction X; the first surface S1 of the inner recess 12 close to the display area AA is farther away from the display area AA than the second surface S2 of the first main body 11 close to the display area AA.
[0081] The overlapping position of the orthographic projection of the first electrode plate C11 and the second electrode plate C12 is used to form a capacitance signal. The pattern in the second electrode plate C12 that does not overlap with the orthographic projection of the first electrode plate C11 on the base substrate 1 is a virtual metal pattern 60, and the electrostatic discharge structure 40 is connected to the surface of the virtual metal pattern 60 close to the display area AA, and the electrostatic discharge structure 40 discharges static electricity to the virtual metal pattern 60.
[0082] This embodiment uses the electrostatic discharge structure 40 to release static electricity to the virtual metal pattern 60 that has no effect on the function, so as to avoid the horizontal horizontal stripes caused by static electricity at the end of the long gate line Gate. At the same time, the first pole plate C11 is concave to reserve an area to avoid static electricity release. Even if the electrostatic discharge process may burn the insulating layer 30, it will not cause the first pole plate C11 and the second pole plate C12 to short-circuit. Compared with the original first capacitor C1, this embodiment does not change the space occupied by the original first capacitor C1. At the same time, the original preparation process is not changed (mainly without adding the mask plate), so the process cost is not increased.
[0083] In some embodiments, Figure 8 This is a schematic diagram of a local structure of an array substrate in Example 2 provided in an embodiment of the present disclosure, Figure 8 The structure shown and Figure 7 The position of the virtual metal pattern 60 of the structure shown is different. Figure 8 As shown, the second electrode plate C12 includes a second main body 13 and a protrusion 14 arranged side by side along the row direction X, the second main body 13 and the protrusion 14 are connected as an integral structure, and the protrusion 14 is closer to the display area AA than the second main body 13. The orthographic projection of the second main body 13 on the base substrate 1 covers the orthographic projection of the first electrode plate C11 on the base substrate 1, and the first electrode plate C11 and the second main body 13 are used to form a capacitive signal. The orthographic projection of the first electrode plate C11 on the base substrate 1 does not overlap with the orthographic projection of the protrusion 14 on the base substrate 1. The protrusion 14 can be understood as the virtual metal pattern 60 of the second electrode plate C12 mentioned above. The electrostatic release structure 40 is connected to the surface of the protrusion 14 close to the display area AA, and the electrostatic release structure 40 is kept away from the first electrode plate C11 by the protrusion 14 to avoid the influence of electrostatic breakdown on the first electrode plate C11.
[0084] The received static electricity is introduced into the protruding portion 14 .
[0085] This embodiment uses the electrostatic discharge structure 40 to release static electricity to the protrusion 14 that has no effect on the function, avoiding the horizontal horizontal stripes caused by static electricity at the end of the long gate line Gate. At the same time, the first pole plate C11 is convex, and an area is reserved to avoid static electricity release. Even if the electrostatic discharge process may burn the insulating layer 30, it will not cause the first pole plate C11 and the second pole plate C12 to short-circuit, eliminating the effect of static electricity release on the first pole plate C11. Compared with the original first capacitor C1, this embodiment does not change the capacitance of the first capacitor C1. At the same time, this design does not change the original preparation process (mainly without adding a mask plate), so it does not increase the process cost.
[0086] In some embodiments, Figure 4 , Figure 7 and Figure 8 As shown, the orthographic projection of the connection point between the first adapter structure 51 and the first electrode plate C11 on the second electrode plate C12 is closer to the center of the second electrode plate C12 than the connection point between the electrostatic release structure 40 and the second electrode plate C12. It can be understood that the connection position between the first adapter structure 51 and the first electrode plate C11 is close to the center of the first electrode plate C11, which is convenient for signal transmission.
[0087] In some embodiments, Fig. 9 A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the second electrode plate C12 includes a third surface S3 close to the display area AA, and a fourth surface S4 and a fifth surface S5 respectively connected to the third surface S3 and arranged oppositely along the column direction Y; for the first capacitors C1 in two adjacent shift registers 10, one end of the third surface S3 of one second electrode plate C12 close to the fourth surface S4 is connected to an electrostatic release structure 40; and one end of the third surface S3 of the second electrode plate C12 of the other first capacitor C1 close to the fifth surface S5 is connected to another electrostatic release structure 40. It can be understood that the connection position of the electrostatic release structure 40 and the second electrode plate C12 is close to the top corner of the second electrode plate C12 to avoid the influence of electrostatic release on the transmission signal of the first capacitor C1 and other metal wirings.
[0088] In some embodiments, Fig. 9As shown, a plurality of shift registers 10 are divided into a plurality of groups, and each shift register group 10a includes two adjacent shift registers 10; for any shift register group 10a, the line connecting the center of one second electrode plate C12 and the center of another second electrode plate C12 is the first connection line O2, and the center line O1 passing through the center of the first connection line O2 along the row direction X is the symmetry axis, and the electrostatic release structure 40 electrically connected to the two second electrodes C12 is symmetrically arranged. Similarly, the center line O1 passing through the center of the first connection line O2 along the row direction X is the symmetry axis, and the two second electrodes C12 are also symmetrically arranged. Similarly, the center line O1 passing through the center of the first connection line O2 along the row direction X is the symmetry axis, and the two first electrodes C11 are also symmetrically arranged.
[0089] In this embodiment, for the first capacitor C1 in any group of shift register groups 10a, the second electrode plate C12 inside the first capacitor C1 and the electrostatic release structure 40 electrically connected to the second electrode plate C12 are symmetrically arranged, so that the occupied space of the shift register 10 can be reduced.
[0090] In some embodiments, Fig. 9 As shown, the array substrate further includes a power signal line VGL extending along the row direction X. A power signal line VGL is correspondingly arranged between the two shift register groups 10a and is configured to provide the same power signal to the two adjacent shift registers 10a.
[0091] For example, the power signal line VGL can be understood as the VGL power line in the GOA circuit, such as Figure 2 As shown, transistors M4, M13A and M17 provide low voltage signals. Specifically, Fig.10 for Fig. 9 The enlarged view of the C-C' region, such as Fig.10 and Figure 6b As shown, the power signal line VGL is located in the source-drain electrode layer 02 and is electrically connected to the drain 71 of the transistor M13A in the shift register 10. The source 72 of the transistor M13A is electrically connected to the first plate C11 of the first capacitor C1 located in the source-drain electrode layer 02. Figure 6a As shown, the gate 73 of the transistor M13A is located at the gate metal layer 01.
[0092] For each shift register 10 , a group of shift registers 10 share the same power signal line VGL, which saves the number of power signal lines VGL and layout space.
[0093] With the power signal line VGL as a symmetry axis, two transistors M13A adjacent to the power signal line VGL in the column direction Y are symmetrically arranged.
[0094] like Fig.10As shown, the array substrate further includes cascade routing, specifically, the cascade routing includes a first cascade sub-routing 81 located in the gate metal layer 01, and a second cascade sub-routing 82 located in the source-drain electrode layer 02. One end of the first cascade sub-routing 81 is electrically connected to the gate 73 of the transistor M13A in a shift register 10, and the other end is electrically connected to one end of the second cascade sub-routing 82 through a second connection via V2 that penetrates the insulating line 30. The other end of the second cascade sub-routing 82 is electrically connected to the first transfer structure 51 to which another shift register 10 is connected.
[0095] like Fig.10 As shown, the drain 71 and the source 72 of the transistor M13A are comb-shaped structures, wherein the drain 71 includes a first main body 711 and a plurality of first comb teeth 712 connected to the first main body 711; the source includes a second main body 721 and a plurality of second comb teeth 722 connected to the second main body 721. The plurality of first comb teeth 712 and the plurality of second comb teeth 722 are alternately arranged along the column direction Y. The orthographic projections of the first main body 711 and the second main body 712 on the substrate 1 do not overlap with the orthographic projection of the gate 73 on the substrate 1.
[0096] Since the channel of transistor M13A is relatively small in the row direction X, about 50 um, in order to achieve a wider channel, the above-mentioned comb structure design is adopted to increase the number of staggered groups of the first comb teeth 712 and the second comb teeth 722, thereby enlarging the channel width and avoiding the heat dissipation difference caused by one line affecting the transistor characteristics.
[0097] In some embodiments, the shortest distance between the electrostatic release structure 40 and the first end N of the gate line Gate is between 15 um and 50 um.
[0098] In some embodiments, the outline shape of the orthographic projection of the electrostatic release structure 40 on the base substrate 1 is any one of a triangle, a rectangle and a trapezoid.
[0099] Fig.11 This is a schematic diagram of the first example of the electrostatic release structure provided in the embodiment of the present disclosure, Fig.12 This is a schematic diagram of the second example of the electrostatic release structure provided in the embodiment of the present disclosure, Fig.13 This is a schematic diagram of the third example of the electrostatic release structure provided in the embodiment of the present disclosure.
[0100] The first end N includes a first side surface R1 and a second side surface R2 that are opposite to each other in the column direction Y. The second side surface R2 is closer to the output end M than the first side surface R1.
[0101] like Fig.11As shown, when the outline shape of the positive projection of the electrostatic release structure 40 on the base substrate 1 is a triangle, one vertex of the triangle is close to the first end N of the gate line Gate on the base substrate 1, and the shortest distance from the vertex to the extension surface of the second side surface R2 in the row direction X is the second spacing L2.
[0102] like Fig.12 As shown, when the outline shape of the orthographic projection of the electrostatic release structure 40 on the base substrate 1 is a rectangle, the short side of the rectangle is close to the first end N of the gate line Gate on the base substrate 1, and the shortest distance from the center line extending along the row direction X of the short side to the extension surface of the second side surface R2 in the row direction X is the second spacing L2. Optionally, the length of the short side of the rectangle is between 5um and 20um.
[0103] like Fig.13 It is shown that when the outline shape of the orthographic projection of the electrostatic release structure 40 on the base substrate 1 is a trapezoid, the top edge of the trapezoid is close to the first end N of the gate line Gate on the base substrate 1, and the shortest distance from the center line extending along the row direction X of the top edge to the extension surface of the second side surface R2 in the row direction X is the second spacing L2. Optionally, the length of the top edge of the trapezoid is between 5um and 20um.
[0104] Optionally, the second spacing L2 is smaller than the first shortest distance L11. Exemplarily, when L2=0, a vertex of the triangle is arranged opposite to the first end N of the gate line Gate on the substrate 1; the short side of the rectangle is arranged opposite to the first end N of the gate line Gate on the substrate 1; the top side of the trapezoid is arranged opposite to the first end N of the gate line Gate on the substrate 1, which is conducive to electrostatic discharge. Another exemplary method is that when L2 takes non-zero data between 0 and L11, it means that a vertex of the triangle is staggered with the first end N of the gate line Gate on the substrate 1 in the column direction; the short side of the rectangle is staggered with the first end N of the gate line Gate on the substrate 1 in the column direction; the top side of the trapezoid is staggered with the first end N of the gate line Gate on the substrate 1 in the column direction to avoid excessive electrostatic discharge and electrostatic breakdown.
[0105] In some embodiments, Figure 6a As shown, the array substrate also includes a first common electrode (not shown in the figure) and multiple second common electrodes Vcom2; the first common electrode extends from the display area AA to the peripheral area BB, and is electrically connected to each second common electrode Vcom2 through a first connecting via V0; a second common electrode Vcom2 is arranged corresponding to a row of pixel units 20.
[0106] The second common electrode Vcom2 is used to reduce the load of the first common electrode, thereby improving the uniformity of the common signal transmitted by the first common electrode corresponding to each pixel unit 20 .
[0107] In some embodiments, Figure 6a As shown, the second common electrode Vcom2 is arranged in the same layer as the gate line Gate; the gate line Gate includes a first line Gate1 and a second line Gate2; the first line Gate1 extends from the display area AA to the peripheral area BB, and the first line Gate1 and the second line Gate2 are electrically connected through a second switching structure (not shown in the figure); the second line Gate2 is electrically connected to the first electrode plate C11 through the first switching structure 51; the second line Gate2 includes multiple sections of sub-lines with different extension directions, which are used to avoid the second common electrode Vcom2. Specifically, the multiple sections of sub-lines with different extension directions semi-surround the second common electrode Vcom2. At the same time, the second common electrode Vcom2 is confined between two second lines Gate2 adjacent to each other along the column direction Y.
[0108] In some embodiments, Figure 6a As shown, the second routing line Gate2 includes multiple sections of sub-routing lines with different extension directions, wherein the multiple sections of sub-routing lines with different extension directions include a first sub-routing line Gate2-1 connected to the first end N and a second sub-routing line Gate2-2 connected to the first sub-routing line Gate2-1. The extension direction of the second sub-routing line Gate2-2 is the same as the extension direction of the first end N, for example, the row direction X. The extension direction of the first sub-routing line Gate2-1 is different from the extension direction of the second sub-routing line Gate2-2. For two adjacent second sub-routing lines Gate2-2 in the column direction Y, the first sub-routing line Gate2-1 connected to one of the second sub-routing lines Gate2-2 is protruded in a direction away from the other second sub-routing line Gate2-2. The angle between the connected first sub-routing line Gate2-1 and the second sub-routing line Gate2-2 is not 0. Since the distance between two adjacent second sub-routes Gate2 - 2 in the column direction Y is short, the first sub-routes Gate2 - 1 are provided to provide accommodation space for the setting of two adjacent first ends N, thereby avoiding affecting the electrostatic discharge of the adjacent first ends N.
[0109] Here, the extension directions of the multi-segment routing are different, which is conducive to the discharge of static electricity.
[0110] In some embodiments, Figure 7 and Figure 8 As shown, the first adapter structure 51 includes a first adapter portion 511 and a second adapter portion 512 electrically connected to the first adapter portion 511; the first adapter portion 511 is electrically connected to the first electrode plate C11, and the second adapter portion 512 is electrically connected to the first end N of the gate line Gate; the extension direction of the first adapter portion 511 is different from the extension direction of the second adapter portion 512.
[0111] Optionally, the extension direction of the first transfer portion 511 is the same as the extension direction of the gate line Gate, that is, the row direction X.
[0112] Optionally, an included angle of the orthographic projections of the first transition portion 511 and the second transition portion 512 on the base substrate 1 is between 10° and 80°.
[0113] In this embodiment, the second transition portion 512 is tilted to avoid the electrostatic release structure 40 , which is beneficial to realize electrostatic release between the first end N of the gate line Gate and the electrostatic release structure 40 .
[0114] In addition, the embodiment of the present disclosure further provides a display device, which includes the array substrate described in any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.
[0115] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.
Claims
1. An array substrate, comprising a display area and a peripheral area surrounding the display area; characterized in that: The array substrate comprises a base substrate, a plurality of gate lines arranged on the base substrate, a shift register arranged in the peripheral area, and an electrostatic release structure arranged on a side of the shift register close to the display area; the gate lines extend from the display area to the peripheral area; The gate line is in the same layer as the electrostatic release structure, and the gate line has a first end close to the electrostatic release structure; the first end of the gate line is electrically connected to the output end of the shift register through a first switching structure; the orthographic projection of the electrostatic release structure on the base substrate does not overlap with the orthographic projection of the output end of the shift register on the base substrate.
2. The array substrate according to claim 1, characterized in that: The shift register at least comprises a first capacitor; the first capacitor comprises a first plate and a second plate arranged opposite to each other; The electrostatic release structure is electrically connected to the second electrode plate; the first end of the gate line is electrically connected to the first electrode plate through a first transfer structure.
3. The array substrate according to claim 2, characterized in that: A first contour edge of the orthographic projection of the second electrode plate on the substrate surrounds a second contour edge of the orthographic projection of the first electrode plate on the substrate; The electrostatic release structure and the second electrode plate connected thereto are an integrated structure.
4. The array substrate according to claim 3, characterized in that: The array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate; The first electrode plate includes a first main body and an inner concave portion arranged side by side in a column direction, and the inner concave portion is connected to the first main body as an integral structure; the first adapter structure is electrically connected to the first main body; The orthographic projection of the inner recess on the base substrate and the orthographic projection of the electrostatic release structure on the base substrate are arranged side by side along the row direction; the first surface of the inner recess close to the display area is farther away from the display area than the second surface of the first main body close to the display area.
5. The array substrate according to claim 3, characterized in that: The array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate; The second electrode plate comprises a second main body and a protruding portion arranged side by side along a row direction, the second main body and the protruding portion are connected to form an integral structure, and the protruding portion is closer to the display area than the second main body; The orthographic projections of the first electrode plate and the second main body on the base substrate overlap; The orthographic projection of the first electrode plate on the base substrate has no overlap with the orthographic projection of the protrusion on the base substrate.
6. The array substrate according to claim 2, characterized in that: The orthographic projection of the connection point between the first adapter structure and the first electrode plate on the second electrode plate is closer to the center of the second electrode plate than the connection point between the electrostatic release structure and the second electrode plate.
7. The array substrate according to claim 6, characterized in that: The array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate; The second electrode plate includes a third surface close to the display area, and a fourth surface and a fifth surface respectively connected to the third surface and arranged opposite to each other along the column direction; For the first capacitors in two adjacent shift registers, one end of the third surface of the second electrode plate of one of them close to the fourth surface is connected to one of the electrostatic release structures; and the other end of the third surface of the second electrode plate of the other first capacitor close to the fifth surface is connected to another of the electrostatic release structures.
8. The array substrate according to claim 7, characterized in that: The plurality of shift registers are divided into a plurality of groups, each shift register group comprising two adjacent shift registers; For any group of the shift register groups, a line connecting the center of one of the second electrodes and the center of another of the second electrodes is a first line, and a center line passing through the center of the first line along the row direction is a symmetry axis, and the electrostatic release structure electrically connected to the two second electrodes is symmetrically arranged.
9. The array substrate according to claim 8, characterized in that: The array substrate further comprises a power signal line extending in the row direction. One power signal line is correspondingly arranged between two groups of shift registers and is configured to provide the same power signal to two adjacent shift registers.
10. The array substrate according to any one of claims 1 to 9, characterized in that: The shortest distance from the electrostatic release structure to the first end of the gate line is between 15 μm and 50 μm.
11. The array substrate according to claim 10, characterized in that: The outline shape of the orthographic projection of the electrostatic release structure on the substrate is any one of a triangle, a rectangle and a trapezoid; the first end includes a first side surface and a second side surface which are arranged opposite to each other in the column direction, and the second side surface is closer to the output end than the first side surface; When the contour shape of the orthographic projection of the electrostatic release structure on the substrate is a triangle, a vertex of the triangle is close to the first end of the gate line on the substrate, and the shortest distance from the vertex to the extension surface of the second side surface in the row direction is a second spacing; When the outline shape of the orthographic projection of the electrostatic release structure on the substrate is a rectangle, the short side of the rectangle is close to the first end of the gate line on the substrate, and the shortest distance from the center line extending in the row direction of the short side to the extension surface of the second side in the row direction is the second spacing; When the contour shape of the positive projection of the electrostatic release structure on the substrate is a trapezoid, the top edge of the trapezoid is close to the first end of the gate line on the substrate, and the shortest distance from the center line extending along the row direction of the top edge to the extension surface of the second side in the row direction is the second spacing.
12. The array substrate according to claim 2, characterized in that: The array substrate further comprises a plurality of pixel units arranged in an array and disposed on the base substrate; The array substrate further includes a first common electrode and a plurality of second common electrodes; the first common electrode extends from the display area to the peripheral area and is electrically connected to each second common electrode through a first connecting via hole; one second common electrode is arranged corresponding to a row of pixel units.
13. The array substrate according to claim 12, characterized in that: The second common electrode is arranged in the same layer as the gate line; The gate line includes a first line and a second line; the first line extends from the display area to the peripheral area, and the first line is electrically connected to the second line through a second switching structure; the second line is electrically connected to the first electrode plate through the first switching structure; The second routing line includes a plurality of sub-routing lines extending in different directions, and the plurality of sub-routing lines extending in different directions semi-circle the second common electrode.
14. The array substrate according to claim 2, characterized in that: The first transfer structure includes a first transfer portion and a second transfer portion electrically connected to the first transfer portion; the first transfer portion is electrically connected to the first electrode plate, and the second transfer portion is electrically connected to the first end of the gate line; An extending direction of the first transition portion is different from an extending direction of the second transition portion.
15. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 14.