Light emitting diode

Abstract

The present disclosure provides a light emitting diode, comprising: an epitaxial layer comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence from bottom to top, a plurality of grooves penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer; the ODR reflecting mirror is located on the side, away from the light-emitting layer, of the second semiconductor layer and comprises an insulating reflecting layer, a transmission medium layer and a metal reflecting layer, the insulating reflecting layer is located on the surface of the side, away from the light-emitting layer, of the second semiconductor layer, and a plurality of through holes penetrate through the insulating reflecting layer and expose the second semiconductor layer; the transmission dielectric layer covers the side walls of the through holes and / or the side walls of the grooves, and the metal reflection layer is located on the surface of the side, away from the second semiconductor layer, of the insulation reflection layer and fills the through holes. The transmission dielectric layer covers the side wall of the groove and the bottom of the groove and is separated from the metal reflecting layer on one side, far away from the second semiconductor layer, of the insulating reflecting layer; the substrate is located on the side, away from the epitaxial layer, of the ODR reflector or the first semiconductor layer is located on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a light emitting diode. Background Art

[0002] With the rapid development of light emitting diodes (LEDs) in mid-to-high-end applications such as automotive lighting and plant lighting, continuously improving the light efficiency of high-power LEDs is the key work direction of LED technology development. Among them, increasing the light extraction efficiency of LEDs is the core technical issue, and the key technical point lies in the optimization design of the reflector structure. Conventional reflector structures include metal reflectors, DBR (Distributed Bragg Reflector) reflectors and ODR (Omni-directional reflector) reflectors (composed of a dielectric layer and a highly reflective metal). Since the DBR reflector has a significant difference in reflectivity for light at different angles, the metal reflector and ODR reflector, which are less affected by the light output angle, are the most mainstream technical solutions for high-power LEDs. In the ODR reflector, the insulating dielectric layer needs to be perforated and then covered with a metal dielectric layer to achieve carrier distribution injection into the epitaxial layer. In order to ensure a good carrier distribution injection effect, it is necessary to design an array-distributed perforated structure in the ODR reflector. On the one hand, 4%-15% of the light reflection area will be lost. On the other hand, when light propagates in the three-dimensional structure of the device, the light reflectivity of the normal light outgoing from the side wall at the perforated position is relatively low, which reduces the luminous efficiency of the light-emitting diode. Utility Model Content

[0003] In view of the above problems, the purpose of the present disclosure is to provide a light emitting diode, aiming to improve the light reflectivity of the normal light emitted from the side wall of the array-distributed perforations of the ODR reflector, while maintaining good ohmic contact performance and carrier distribution injection effect on the epitaxial layer, thereby improving the luminous efficiency of the light emitting diode.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a light emitting diode, comprising:

[0005] An epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence from bottom to top, a plurality of grooves penetrating the second semiconductor layer and the light-emitting layer and exposing the first semiconductor layer;

[0006] An ODR reflector is located on a side of the second semiconductor layer away from the light-emitting layer, the ODR reflector comprises an insulating reflective layer, a transmissive dielectric layer and a metal reflective layer, the insulating reflective layer is located on a side of the second semiconductor layer away from the light-emitting layer, a plurality of perforations penetrate the insulating reflective layer and expose the second semiconductor layer, the transmissive dielectric layer covers the side walls of the plurality of perforations and / or the insulating reflective layer on the side walls of the grooves, the metal reflective layer is located on a side of the insulating reflective layer away from the second semiconductor layer and fills the plurality of perforations, the metal reflective layer also covers the transmissive dielectric layer on the side walls of the grooves and the bottom of the grooves, and the metal reflective layer located on a side of the insulating reflective layer away from the second semiconductor layer is separated from the metal reflective layer located on the side walls and the bottom of the grooves;

[0007] A substrate, the substrate is located on a side of the ODR reflector away from the epitaxial layer; or the first semiconductor layer is located on the substrate; and,

[0008] A first electrode and a second electrode are insulated from each other, the first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

[0009] Optionally, the transmissive medium layer also covers a surface of the insulating reflective layer on a side away from the second semiconductor layer.

[0010] Optionally, the ODR reflector further comprises:

[0011] The transmissive adhesion layer is located on a surface of the transmissive medium layer away from the insulating reflective layer, the metal reflective layer is located on a surface of the transmissive adhesion layer away from the transmissive medium layer, and the transmissive adhesion layer located on a side of the second semiconductor layer away from the light-emitting layer is separated from the transmissive adhesion layer located on the sidewall of the groove.

[0012] Optionally, it also includes:

[0013] An ohmic contact layer is located on a portion of the surface of the second semiconductor layer away from the light-emitting layer and is electrically connected to the second semiconductor layer. The through hole exposes the ohmic contact layer.

[0014] Optionally, the first semiconductor layer is located on the substrate, and the light emitting diode further comprises:

[0015] a second current spreading layer, located on the metal reflective layer and covering the metal reflective layer outside the groove;

[0016] a first isolation dielectric layer, located on the second current spreading layer, covering the second current spreading layer and the exposed insulating reflective layer, and exposing the groove;

[0017] a first current spreading layer, located on the first isolation dielectric layer, covering a portion of the first isolation dielectric layer and filling the groove, exposing a portion of the first isolation dielectric layer above the second current spreading layer;

[0018] a second isolation dielectric layer, located on the first current spreading layer, covering the first current spreading layer and the exposed first isolation dielectric layer;

[0019] The second isolation dielectric layer includes a first opening, the first opening exposes the first current spreading layer, and the first isolation dielectric layer and the second isolation dielectric layer include a second opening, the second opening exposes the second current spreading layer.

[0020] Optionally, the second electrode is located on the second isolation dielectric layer and is electrically connected to the second current spreading layer through the second opening, and the first electrode is located on the second isolation dielectric layer and is electrically connected to the first current spreading layer through the first opening.

[0021] Optionally, the substrate is located on a side of the ODR reflector away from the epitaxial layer, and the light emitting diode further comprises:

[0022] a second current spreading layer, located on a surface of the metal reflective layer away from the second semiconductor layer, and covering the metal reflective layer outside the groove;

[0023] A first isolation dielectric layer is located on a surface of the second current spreading layer away from the metal reflective layer, covers the second current spreading layer and the exposed insulating reflective layer, and exposes the groove;

[0024] A first current spreading layer, located on a surface of the first isolation dielectric layer away from the second current spreading layer and filling the groove;

[0025] The bonding layer is located on a surface of the first current spreading layer away from the first isolation dielectric layer, and the substrate is located on a surface of the bonding layer away from the first current spreading layer.

[0026] Optionally, a step exposing a portion of the second current spreading layer is formed at the periphery of the epitaxial layer and the ODR reflector, and the step penetrates the epitaxial layer and the ODR reflector, and the light emitting diode further comprises:

[0027] A passivation protection layer is located on a surface of the first semiconductor layer on a side away from the substrate, covers the first semiconductor layer and the sidewall of the step, and exposes a portion of the second current spreading layer. The second electrode is located on the step and is electrically connected to the exposed portion of the second current spreading layer. The first electrode is located on a surface of the substrate on a side away from the bonding layer.

[0028] Optionally, the insulating reflective layer includes a single-layer reflective layer and / or a multi-layer reflective layer formed by alternately stacking two reflective films with different refractive indices.

[0029] Optionally, the transmissive medium layer includes: one of: an Al2O3 layer, a MgF2 layer and a SnO2 layer, and the thickness of the transmissive medium layer includes: λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer, and n is the refractive index of the transmissive medium layer at the light emitting wavelength.

[0030] Optionally, the transmissive adhesion layer includes: an ITO layer, an Al2O3 layer, and the thickness of the transmissive adhesion layer includes: 1 nm to 100 nm.

[0031] According to the light-emitting diode provided by the embodiment of the present disclosure, the ODR reflector includes an insulating reflective layer, a transmissive dielectric layer and a metal reflective layer, a plurality of perforations penetrate the insulating reflective layer and expose the second semiconductor layer, the transmissive dielectric layer covers the side walls of the plurality of perforations, and the metal reflective layer fills the plurality of perforations. By setting the film thickness of the transmissive dielectric layer, a high-reflectivity ODR reflector structure is formed on the side walls of the perforations using the transmissive dielectric layer and the metal reflective layer with optical film thickness, and finally a light-emitting diode with an ODR reflector having a three-dimensional structure is obtained, which can realize a more extreme reflector design scheme, improve the light reflectivity of the ODR reflector in the normal direction of the side walls of the perforations distributed in the array, and at the same time maintain good ohmic contact performance and carrier distribution injection effect to the epitaxial layer, thereby improving the luminous efficiency of the light-emitting diode.

[0032] Furthermore, multiple grooves penetrate the second semiconductor layer and the light-emitting layer and expose the first semiconductor layer, the insulating reflective layer covers the second semiconductor layer and the side walls of the grooves, the transmissive medium layer covers the insulating reflective layer on the side walls of the grooves, and the metal reflective layer covers the transmissive medium layer on the side walls of the grooves and the bottom of the grooves. A high-reflectivity ODR reflector structure is formed on the side walls of the grooves using the transmissive medium layer and the metal reflective layer with optical film thickness, which improves the light reflectivity of the ODR reflector in the normal direction of the side walls of the array-distributed grooves, while maintaining good ohmic contact performance and carrier distribution injection effect on the epitaxial layer, thereby improving the luminous efficiency of the light-emitting diode.

[0033] Furthermore, the transmissive adhesive layer increases the adhesion between the metal reflective layer and the insulating reflective layer, thereby preventing the metal reflective layer from falling off and improving the process stability and reliability of the light emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1 A cross-sectional schematic diagram of a flip-chip light emitting diode according to an embodiment of the present disclosure is shown;

[0036] FIG. 2A to FIG. 2I A cross-sectional schematic diagram showing different stages of a method for manufacturing a flip-chip light-emitting diode according to an embodiment of the present disclosure;

[0037] Figure 3 A schematic cross-sectional view of a vertical light emitting diode according to an embodiment of the present disclosure is shown;

[0038] FIG. 4A to FIG. 4M Schematic cross-sectional views of different stages of a method for manufacturing a vertical light emitting diode according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0039] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0040] The specific implementation of the present disclosure is further described in detail below in conjunction with the drawings and examples.

[0041] Figure 1 FIG. 2 shows a cross-sectional schematic diagram of a flip-chip light-emitting diode according to an embodiment of the present disclosure. Figure 1As shown, the light emitting diode 1000 comprises: a substrate 100; an epitaxial layer 101, the epitaxial layer 101 is located on the substrate 100, the epitaxial layer 101 comprises a first semiconductor layer 11, a light emitting layer 12 and a second semiconductor layer 13 stacked in sequence from bottom to top, a plurality of grooves 14 penetrate the second semiconductor layer 13 and the light emitting layer 12 and expose the first semiconductor layer 11, and the grooves 14 are arranged in an array; an ODR reflector 300, located on the second semiconductor layer 13, the ODR reflector 300 comprises an insulating reflective layer 103, a transmissive medium layer 104 and a metal reflective layer 105, a plurality of through holes 15 penetrate the insulating reflective layer 103 and expose the second semiconductor layer 13, the through holes 15 are arranged in an array, and the transmissive medium layer 1 04 an insulating reflective layer 103 covering the side walls of the plurality of perforations 15 and the side walls of the plurality of grooves 14, a metal reflective layer 105 located on a surface of the side of the insulating reflective layer 103 away from the second semiconductor layer 13, covering the surface of the insulating reflective layer 103 and filling the plurality of perforations 15, a transmissive medium layer 104 covering the side walls of the grooves 14 and the bottom of the grooves 14, and the metal reflective layer 105 covering the side walls and the bottom of the grooves 14 is separated from the metal reflective layer 105 located above the second semiconductor layer 13 to prevent short circuit leakage; and a first electrode 20 and a second electrode 21 insulated from each other, the first electrode 20 is electrically connected to the first semiconductor layer 11, and the second electrode 21 is electrically connected to the second semiconductor layer 13.

[0042] In some embodiments, the substrate 100 is a transparent heterogeneous substrate, and its material can be any one of single crystal sapphire, AlN, Ga2O3, ZnO, and SiC, and its thickness can be 400μm to 1mm, but is not limited thereto. In some embodiments, the surface of the substrate 100 can be a mirror surface or a surface with micron-level / nano-level patterning. In one embodiment, the first semiconductor layer 11 is an N-type semiconductor layer, and the second semiconductor layer 13 is a P-type semiconductor layer. The light-emitting layer 12 is a multi-quantum well layer (MQW), and the multi-quantum well layer can be, for example, a combination of any two of GaN / InGaN / AlGaN. In one embodiment, the multi-quantum well layer can be an InGaN structure with different In components. The wavelength range corresponding to the light-emitting layer 12 is, for example, 440 nm to 540 nm. In one embodiment, the thickness of the epitaxial layer 101 includes 5μm to 10μm. In some embodiments, the insulating reflective layer 103 is a single-layer reflective layer, for example, a SiO2 layer. The thickness of the insulating reflective layer 103 is an integer multiple of λ / 4n, wherein λ is the emission wavelength of the light-emitting layer 12, and n is the refractive index of the insulating reflective layer 103 at the emission wavelength. For example, the emission wavelength is 460 nm, the refractive index of the insulating reflective layer 103 at the emission wavelength is about 1.47, and the film thickness of the insulating reflective layer 103 is about 625 nm. In other embodiments, the insulating reflective layer 103 may be a DBR reflective layer or a combination of a single-layer reflective layer and a DBR reflective layer. In some embodiments, the transmissive dielectric layer 104 includes one of an Al2O3 layer, a MgF2 layer, and a SnO2 layer, and the thickness of the transmissive dielectric layer 104 is λ / 4n, wherein λ is the emission wavelength of the light-emitting layer 12, and n is the refractive index of the transmissive dielectric layer 104 at the emission wavelength. In some embodiments, the metal reflective layer 105 includes a stack of Ag layers, TiW layers, and Ti layers. For example, the thicknesses of the Ag layer, the TiW layer, and the Ti layer are respectively and In some embodiments, the distance between the centers of two adjacent grooves 14 is 100 μm to 200 μm, and the diameter of the groove 14 is, for example, 60 μm.

[0043] In some embodiments, the second semiconductor layer 13 has an ohmic contact layer 102, which is located on a portion of the second semiconductor layer 13 and is electrically connected to the second semiconductor layer 13. The through hole 15 exposes the ohmic contact layer 102, and the metal reflective layer 105 is electrically connected to the ohmic contact layer 102. In some embodiments, the material of the ohmic contact layer 102 includes ITO, and the thickness of the ohmic contact layer 102 is, for example, 20 nm.

[0044] In some embodiments, the second current spreading layer 107 covers the metal reflective layer 105 located above the second semiconductor layer 13. For example, the second current spreading layer 107 includes a stack of Cr layer, Al layer, Ti layer, Pt layer and Ti layer, and the thicknesses of the Cr layer, Al layer, Ti layer, Pt layer and Ti layer are respectively and In some embodiments, the first isolation dielectric layer 109 is located on the second current spreading layer 107, covers the second current spreading layer 107 and the exposed insulating reflective layer 103, and exposes the sidewalls of the groove 14 and the metal reflective layer 105 at the bottom. For example, the first isolation dielectric layer 109 includes a SiO2 layer, and the thickness of the first isolation dielectric layer 109 is, for example, 1000 nm. In some embodiments, the first current spreading layer 108 is located on the first isolation dielectric layer 109, covers a portion of the first isolation dielectric layer 109 and fills the groove 14, and exposes a portion of the first isolation dielectric layer 109 above the second current spreading layer 107. In some embodiments, the second isolation dielectric layer 110 is located on the first current spreading layer 108, covers the first current spreading layer 108 and the exposed first isolation dielectric layer 109. For example, the second isolation dielectric layer 110 includes a SiO2 layer, and the thickness of the second isolation dielectric layer 110 is, for example, 1000 nm. The second isolation dielectric layer 110 includes a first opening 16, and the first opening 16 exposes the first current spreading layer 108. The first isolation dielectric layer 109 and the second isolation dielectric layer 110 include a second opening 17, and the second opening 17 exposes the second current spreading layer 107. In some embodiments, the second electrode 21 is located on the second isolation dielectric layer 110 and is electrically connected to the second current spreading layer 107 through the second opening 17; the first electrode 20 is located on the second isolation dielectric layer 110 and is electrically connected to the first current spreading layer 108 through the first opening 16. In some embodiments, the first electrode 20 and the second electrode 21 include a stack of Ti layers, Au layers, and Sn layers.

[0045] In other embodiments, the transmissive medium layer 104 may only cover the insulating reflective layer 103 on the sidewalls of the plurality of through holes 15 or the sidewalls of the plurality of grooves 14. In other embodiments, the transmissive medium layer 104 may also cover the side surface of the insulating reflective layer 103 away from the second semiconductor layer 13.

[0046] FIG. 2A to FIG. 2I The cross-sectional schematic diagrams of different stages of the method for manufacturing a flip-chip light-emitting diode according to an embodiment of the present disclosure are shown. FIG. 2A to FIG. 2I The manufacturing method of the flip-chip light emitting diode 1000 includes the following steps.

[0047] like Figure 2AAs shown, a substrate 100 is provided. The substrate 100 is, for example, a sapphire substrate, and the sapphire substrate is a nanoscale patterned sapphire substrate. An epitaxial layer 101 can be formed on the substrate 100 by a metal organic chemical vapor deposition process, a laser assisted molecular beam epitaxy process, a laser sputtering process, or a hydride vapor phase epitaxy process. The epitaxial layer 101 includes a first semiconductor layer 11, a light emitting layer 12, and a second semiconductor layer 13 stacked sequentially from bottom to top. In one embodiment, the first semiconductor layer 11 is an N-type semiconductor layer, and the second semiconductor layer 13 is a P-type semiconductor layer. The light emitting layer 12 is a multi-quantum well layer (MQW), and the multi-quantum well layer can be, for example, a combination of any two of GaN / InGaN / AlGaN. In one embodiment, the multi-quantum well layer can be an InGaN structure with different In components. The wavelength range corresponding to the light emitting layer 12 is, for example, 440nm to 540nm. The thickness of the epitaxial layer 101 includes 5μm to 10μm. By using photolithography and dry etching processes, etching is performed from the second semiconductor layer 13 to the surface or layer of the first semiconductor layer 11 to expose the first semiconductor layer 11, and array-distributed grooves 14 are formed in the second semiconductor layer 13 and the light-emitting layer 12. The spacing between the centers of adjacent grooves 14 includes 100 μm to 200 μm, and the diameter of the groove 14 is, for example, 60 μm. By using RPD reactive plasma deposition technology, an ohmic contact layer material layer is formed on the second semiconductor layer 13, and a rapid annealing treatment is performed, and then the ohmic contact layer 102 is patterned. The ohmic contact layer 102 is located on a portion of the second semiconductor layer 13 and is electrically connected to the second semiconductor layer 13. In some embodiments, the ohmic contact layer 102 is, for example, an ITO layer, and the thickness of the ohmic contact layer 102 is, for example, 20 nm.

[0048] Next, please refer to Figure 2B As shown, the insulating reflective layer material layer can be formed by PECVD (plasma enhanced chemical vapor deposition) technology, and the insulating reflective layer material layer is etched by photolithography and dry etching processes to form an insulating reflective layer 103. The insulating reflective layer 103 covers the ohmic contact layer 102, the exposed second semiconductor layer 13 and the sidewalls and bottom of the groove 14. The multiple perforations 15 distributed in an array penetrate the insulating reflective layer 103 and expose the ohmic contact layer 102, so that the subsequently formed metal reflective layer 105 is electrically connected to the ohmic contact layer 102. The insulating reflective layer 103 is, for example, a single-layer reflective layer, such as a SiO2 layer. The thickness of the insulating reflective layer 103 is an integer multiple of λ / 4n, where λ is the light emission wavelength of the light emitting layer 12, and n is the refractive index of the insulating reflective layer 103 at the light emission wavelength. For example, the light emission wavelength is 460nm, the refractive index of the insulating reflective layer 103 at the light emission wavelength is about 1.47, and the film thickness of the insulating reflective layer 103 is about 625nm.

[0049] Next, please refer to Figure 2C and 2DAs shown, a transmission medium layer 104 is formed. Figure 2C As shown, an ALD atomic layer deposition technique can be used to form a transmissive dielectric layer material on the insulating reflective layer 103, and the transmissive dielectric layer material covers the insulating reflective layer 103, the sidewalls and bottom of the through hole 15, and the sidewalls and bottom of the groove 14. Figure 2D As shown, the transmissive dielectric layer 104 outside the sidewalls of the groove 14 and the through hole 15 and the insulating reflective layer 103 at the bottom of the groove 14 are removed by photolithography and etching techniques, respectively exposing the first semiconductor layer 11 and the ohmic contact layer 102. The transmissive dielectric layer 104 includes one of an Al2O3 layer, a MgF2 layer, and a SnO2 layer, and the thickness of the transmissive dielectric layer 104 is λ / 4n, wherein λ is the light emission wavelength of the light emitting layer 12, and n is the refractive index of the transmissive dielectric layer 104 at the light emission wavelength.

[0050] Next, please refer to Figure 2E and Figure 2F As shown, a metal reflective layer 105 and a second current spreading layer 107 are formed. Figure 2E As shown, a metal reflective layer material layer is deposited on the surfaces of the insulating reflective layer 103, the transmissive medium layer 104, the first semiconductor layer 11 and the ohmic contact layer 102 by a deposition process. Figure 2F As shown, the metal reflective layer 105 is etched by photolithography and etching to separate the metal reflective layer 105 covering the sidewall and bottom of the groove 14 from the metal reflective layer 105 located above the second semiconductor layer 13 to prevent short circuit leakage. Next, a second current spreading layer material layer is formed above the metal reflective layer 105 by PVD technology. The second current spreading layer material layer is etched by photolithography and dry etching to form a second current spreading layer 107, which covers the metal reflective layer 105 above the second semiconductor layer 13. The metal reflective layer 105 includes a stack of Ag layers, TiW layers, and Ti layers. For example, the thicknesses of the Ag layer, the TiW layer, and the Ti layer are respectively and For example, the second current spreading layer 107 includes a stack of a Cr layer, an Al layer, a Ti layer, a Pt layer and a Ti layer, and the thicknesses of the Cr layer, the Al layer, the Ti layer, the Pt layer and the Ti layer are respectively and It is easy to understand that the metal reflective layer 105 is electrically connected to the ohmic contact layer 102 through the perforation 15. The metal reflective layer 105 is electrically connected to the first semiconductor layer 11 through the groove 14. The second current spreading layer 107 does not cover the groove 14 to achieve the subsequent electrical connection between the first current spreading layer 108 and the first semiconductor layer 11. It is easy to understand that the transmissive dielectric layer 104 on the sidewalls of the groove 14 and the perforation 15 increases the light reflectivity of the ODR reflector 300 in the normal direction of the sidewalls of the array-distributed grooves 14 and perforations 15. It is easy to understand that the metal reflective layer 105 between adjacent die units is separated from each other (not shown) to prevent short circuit leakage.

[0051] Next, please refer to Figure 2G As shown, a first isolation dielectric layer material layer is formed on the second current spreading layer 107 by using PECVD technology, and a first isolation dielectric layer 109 is formed by etching by using photolithography and dry etching technology. The first isolation dielectric layer 109 covers the second current spreading layer 107 and the exposed insulating reflective layer 103, and exposes the sidewall of the groove 14 and the metal reflective layer 105 at the bottom. The first isolation dielectric layer 109 includes a SiO2 layer, and the thickness of the first isolation dielectric layer 109 is, for example, 1000 nm.

[0052] Next, please refer to Figure 2H As shown, a first current spreading layer material layer is formed on the first isolation dielectric layer 109 by using PVD technology. The first current spreading layer material layer is etched by using photolithography and dry etching processes to form a first current spreading layer 108. The first current spreading layer 108 is located on the first isolation dielectric layer 109 and fills the groove 14, and exposes a portion of the surface of the first isolation dielectric layer 109 above the second current spreading layer 107, so that subsequent film layer openings can connect to the second current spreading layer 107. A second isolation dielectric layer material layer is formed on the first current spreading layer 108 by using PECVD technology, and is patterned by using photolithography and dry etching technology to form a second isolation dielectric layer 110. The second isolation dielectric layer 110 is located on the first current spreading layer 108, covering the first current spreading layer 108 and the exposed first isolation dielectric layer 109. The second isolation dielectric layer 110 includes a first opening 16, the first opening 16 exposes the first current spreading layer 108, and the first isolation dielectric layer 109 and the second isolation dielectric layer 110 include a second opening 17, the second opening 17 exposes the second current spreading layer 107. The second isolation dielectric layer 110 includes a SiO2 layer, and the thickness of the second isolation dielectric layer 110 is, for example, 1000 nm.

[0053] Next, please refer to Fig.2IAs shown, the first electrode 20 and the second electrode 21 are formed by photolithography and PVD technology. The second electrode 21 is electrically connected to the second current spreading layer 107 through the second opening 17, and the first electrode 20 is electrically connected to the first current spreading layer 108 through the first opening 16. In some embodiments, the first electrode 20 and the second electrode 21 include a stack of Ti layers, Au layers, and Sn layers. After the back side of the substrate 100 (i.e., the side away from the epitaxial layer 101) is thinned and separated by dicing / splitting, the preparation of the flip-chip light-emitting diode is completed.

[0054] In the light-emitting diode provided by the present disclosure, the ODR reflector 300 includes an insulating reflective layer 103, a transmissive medium layer 104 and a metal reflective layer 105, a plurality of perforations 15 penetrate the insulating reflective layer 103 and expose the second semiconductor layer 13, the transmissive medium layer 104 covers the side walls of the plurality of perforations 15, and the metal reflective layer 105 fills the plurality of perforations 15. By setting the transmissive medium layer 104, a high-reflectivity ODR reflector structure is formed on the side walls of the perforations 15 using the transmissive medium layer 104 and the metal reflective layer 105 with optical film thickness, and finally a light-emitting diode with an ODR reflector having a three-dimensional structure is obtained, which can realize a more extreme reflector design scheme, improve the light reflectivity of the ODR reflector in the normal direction of the side walls of the array-distributed perforations 15, and at the same time maintain good ohmic contact performance and carrier distribution injection effect on the epitaxial layer 101, thereby improving the luminous efficiency of the light-emitting diode.

[0055] Furthermore, multiple grooves 14 penetrate the second semiconductor layer 13 and the light-emitting layer 12 and expose the first semiconductor layer 11, the insulating reflective layer 103 covers the second semiconductor layer 13 and the side walls of the grooves 14, the transmissive medium layer 104 covers the insulating reflective layer 103 on the side walls of the grooves 14, and the metal reflective layer 105 covers the transmissive medium layer 104 on the side walls of the grooves 14 and the bottom of the grooves 14. On the side walls of the grooves 14, a high-reflectivity ODR reflector structure is formed by using the optically thick transmissive medium layer 104 and the metal reflective layer 105, which improves the light reflectivity of the ODR reflector in the normal direction of the side walls of the array-distributed grooves 14, while maintaining good ohmic contact performance and carrier distribution injection effect on the epitaxial layer 101, thereby improving the luminous efficiency of the light-emitting diode.

[0056] Figure 3 It should be noted that since the vertical light emitting diode is formed by first forming an epitaxial layer and an ODR reflector on a growth substrate, then bonding a bonding substrate to the side of the ODR reflector away from the growth substrate, and finally removing the growth substrate, and the epitaxial layer and the ODR reflector are introduced in the embodiment of the present disclosure in the order of formation, Figure 3 It is introduced from top to bottom, that is, in the following embodiments, Figure 3 The structure shown is rotated 180 degrees before being described.

[0057] like Figure 3 As shown, the light emitting diode 2000 includes: an epitaxial layer 101, the epitaxial layer 101 includes a first semiconductor layer 11, a light emitting layer 12 and a second semiconductor layer 13 stacked in sequence from bottom to top, a plurality of grooves 14 penetrate the second semiconductor layer 13 and the light emitting layer 12 and expose the first semiconductor layer 11, and the grooves 14 are arranged in an array; an ODR reflector 300, which is located on the surface of the second semiconductor layer 13 away from the light emitting layer 12, the ODR reflector 300 includes an insulating reflective layer 103, a transmissive medium layer 104 and a metal reflective layer 105, the insulating reflective layer 103 is located on the surface of the second semiconductor layer 13 away from the light emitting layer 12, a plurality of through holes 15 penetrate the insulating reflective layer 103 and expose the second semiconductor layer 13, the through holes 15 are arranged in an array, and the transmissive medium layer 104 covers the side walls of the plurality of through holes 15 and the side walls of the plurality of grooves 14 The insulating reflective layer 103 and the metal reflective layer 105 are located on the side surface of the insulating reflective layer 103 away from the second semiconductor layer 13, covering the surface of the insulating reflective layer 103 and filling a plurality of perforations 15, and the transmissive medium layer 104 covering the side wall of the groove 14 and the bottom of the groove 14, and the metal reflective layer 105 covering the side wall and the bottom of the groove 14 is separated from the metal reflective layer 105 located on the side surface of the insulating reflective layer 13 away from the second semiconductor layer 13 to prevent short circuit leakage; the bonding layer 120 is located on the side of the ODR reflector 300 away from the epitaxial layer 101; the substrate 200 is located on the side surface of the bonding layer 120 away from the epitaxial layer 101; and the first electrode 20 and the second electrode 21 are insulated from each other, the first electrode 20 is electrically connected to the first semiconductor layer 11, and the second electrode 21 is electrically connected to the second semiconductor layer 13.

[0058] In some embodiments, the substrate 200 is a conductive substrate, and its material can be any one of a silicon substrate and a metal substrate, and its thickness can be 400μm to 1mm, but is not limited thereto. In one embodiment, the first semiconductor layer 11 is an N-type semiconductor layer, and the second semiconductor layer 13 is a P-type semiconductor layer. The light-emitting layer 12 is a multi-quantum well layer (MQW), and the multi-quantum well layer can be, for example, a combination of any two of GaN / InGaN / AlGaN. In one embodiment, the multi-quantum well layer can be an InGaN structure with different In components. The wavelength range corresponding to the light-emitting layer 12 is, for example, 440nm to 540nm. In one embodiment, the thickness of the epitaxial layer 101 includes 5μm to 10μm. In some embodiments, the transmission medium layer 104 includes one of an Al2O3 layer, a MgF2 layer, and a SnO2 layer, and the thickness of the transmission medium layer 104 is λ / 4n, wherein λ is the emission wavelength of the light-emitting layer, and n is the refractive index of the transmission medium layer at the emission wavelength. In some embodiments, the metal reflective layer 105 includes a stack of Ag layer, TiW layer, Pt layer and Ti layer. The thicknesses of the Ag layer, TiW layer, Pt layer and Ti layer are respectively and

[0059] In some embodiments, the transmissive dielectric layer 104 may also only cover the insulating reflective layer 103 on the sidewalls of the plurality of perforations 15 or the sidewalls of the plurality of grooves 14. In some embodiments, the transmissive dielectric layer 104 also covers the surface of the insulating reflective layer 103 on one side away from the second semiconductor layer 13. The metal reflective layer 105 is located on the surface of the transmissive dielectric layer 104 on one side away from the second semiconductor layer 13, covers the surface of the transmissive dielectric layer 104 and fills the plurality of perforations 15, covers the transmissive dielectric layer 104 on the sidewalls of the grooves 14, and covers the bottom of the grooves 14. The metal reflective layer 105 covering the sidewalls and bottom of the grooves 14 is separated from the metal reflective layer 105 located on the side of the insulating reflective layer 103 away from the second semiconductor layer 13 to prevent short circuit leakage.

[0060] In some embodiments, the spacing between the centers of two adjacent grooves 14 includes 100 μm to 200 μm, and the diameter of the groove 14 is, for example, 60 μm. In some embodiments, the insulating reflective layer 103 includes a single-layer reflective layer 103a and a multilayer reflective layer 103b formed by alternating two reflective films with different refractive indices. The single-layer reflective layer 103a is located between the multilayer reflective layer 103b and the second semiconductor layer 13. The perforation 15 penetrates the single-layer reflective layer 103a and the multilayer reflective layer 103b, and the single-layer reflective layer 103a and the multilayer reflective layer 103b form a two-step structure in the perforation 15. The single-layer reflective layer 103a covers the sidewall of the groove 14. It can be understood that in other embodiments, the insulating reflective layer 103 may also only include a single-layer reflective layer 103a, the perforation 15 penetrates the single-layer reflective layer 103a, and the single-layer reflective layer 103a covers the sidewall of the groove 14. Alternatively, it may only include the multilayer reflective layer 103b, the perforation 15 penetrates the multilayer reflective layer 103b, and the multilayer reflective layer 103b covers the side wall of the groove 14. The thickness of each single layer in the single-layer reflective layer 103a or the multilayer reflective layer 103b is an integer multiple of λ / 4n, wherein λ is the light emission wavelength of the light emitting layer 12, and n is the refractive index of the single layer at the light emission wavelength. The material of the single-layer reflective layer 103a may be one or more combinations of MgF2, SiO2, and Al2O3. The low refractive index material in the multilayer reflective layer 103b may be one of MgF2, CaF2, SiO2, and Al2O3, and the high refractive index material may be one of TiO2, Ta2O5, and Nb2O5. The number of pairs of low refractive index materials and high refractive index materials in the multilayer reflective layer 103b is, for example, not less than 6 pairs. Preferably, the bottom layer (the layer closest to the second semiconductor layer 13) in the multilayer reflective layer 103b is a low refractive index material.

[0061] In some embodiments, the second semiconductor layer 13 has an ohmic contact layer 102 on one side of the surface away from the light emitting layer 12, the ohmic contact layer 102 is electrically connected to the second semiconductor layer 13, the through hole 15 exposes the ohmic contact layer 102, and the metal reflective layer 105 is electrically connected to the ohmic contact layer 102. In some embodiments, the material of the ohmic contact layer 102 includes ITO, and the thickness of the ohmic contact layer 102 is, for example, 15 nm.

[0062] In some embodiments, the ODR reflector 300 further includes a transmissive adhesive layer 106, and the metal reflective layer 105 covers the transmissive adhesive layer 106. The transmissive adhesive layer 106 is located on a side surface of the transmissive medium layer 104 away from the insulating reflective layer 103, and the metal reflective layer 105 is located on a side surface of the transmissive adhesive layer 106 away from the transmissive medium layer 104. In some embodiments, the transmissive adhesive layer 106 includes one of an ITO layer and an Al2O3 layer, and the thickness of the transmissive adhesive layer 106 includes 1 nm to 100 nm, for example, 2 nm. The transmissive adhesive layer 106 covering the sidewall of the groove 14 is separated from the transmissive adhesive layer 106 located on a side of the second semiconductor layer 13 away from the light emitting layer 12 to prevent short circuit leakage.

[0063] In some embodiments, the second current spreading layer 107 is located on the surface of the metal reflective layer 105 away from the second semiconductor layer 13, and covers the metal reflective layer 105 outside the groove 14. For example, the second current spreading layer 107 includes a stack of a Ti layer, an Au layer, a Pt layer, and a Ti layer, and the thicknesses of the Ti layer, the Au layer, the Pt layer, and the Ti layer are and In some embodiments, the first isolation dielectric layer 109 is located on the surface of the second current spreading layer 107 away from the second semiconductor layer 13, covers the second current spreading layer 107, the exposed transmissive dielectric layer 104 and the transmissive adhesion layer 106, exposes the groove 14, and the groove 14 is filled with a metal pillar 18. In some embodiments, the first isolation dielectric layer 109 includes a stacked structure of a SiO2 layer, a SiON layer and a SiO2 layer, and the thickness of the first isolation dielectric layer 109 is, for example, 600 nm. The metal pillar 18 includes a stacked layer consisting of a Ti layer, an Al layer and a TiW layer. In some embodiments, the first current spreading layer 108 is located on the surface of the first isolation dielectric layer 109 away from the epitaxial layer 101, covers the first isolation dielectric layer 109 and the metal pillar 18. In some embodiments, the first current spreading layer 108 includes a stacked layer consisting of a Ti layer, an Al layer, a Pt layer and a Ti layer, and the thicknesses of the Ti layer, the Al layer, the Pt layer and the Ti layer are respectively and In other embodiments, the first current spreading layer 108 and the metal pillar 18 may also be an integrated structure, that is, the first current spreading layer 108 is located on the surface of the first isolation dielectric layer 109 away from the epitaxial layer 101 and fills the groove 14 .

[0064] In some embodiments, the bonding layer 120 is located between the substrate 200 and the first current spreading layer 108. For example, the substrate 200 is a bonding substrate, the material of the substrate 200 is, for example, Si, and the thickness of the substrate 200 is, for example, 1 mm. The material of the bonding layer 120 is, for example, NiSn. In some embodiments, the first electrode 20 is located on the surface of the substrate 200 away from the bonding layer 120, and is electrically connected to the first current spreading layer 108. For example, the material of the first electrode 20 is, for example, a stack of Ti layer, Pt layer, and Au layer. In some embodiments, on the side of the substrate 200 away from the first electrode 20, a step 112 is formed at the periphery of the epitaxial layer 101 and the ODR reflector 300, and the step 112 penetrates the epitaxial layer 101 and the ODR reflector 300 and exposes a portion of the surface of the second current spreading layer 107. The passivation protection layer 111 is located on the side of the first semiconductor layer 11 away from the substrate 200, covers the sidewalls of the first semiconductor layer 11 and the step 112, and exposes a portion of the second current spreading layer 107. The second electrode 21 is located on the step 112 and is electrically connected to the exposed portion of the second current spreading layer 107. For example, the material of the second electrode 21 includes a stack of Ti layer, Ni layer and Au layer, and the thickness of the second electrode 21 is, for example, 1 um.

[0065] FIG. 4A to FIG. 4M The cross-sectional schematic diagrams of different stages of the method for manufacturing a vertical light emitting diode according to an embodiment of the present disclosure are shown. FIG. 4A to FIG. 4M , the manufacturing method of the vertical light emitting diode 2000 includes the following steps.

[0066] like Figure 4A As shown, a substrate 100 is provided. The substrate 100 is a growth substrate, and the substrate 100 is, for example, a Si substrate, and the Si substrate is a nanoscale patterned Si substrate. An epitaxial layer 101 can be formed on the substrate 100 by a metal organic chemical vapor deposition process, a laser assisted molecular beam epitaxy process, a laser sputtering process, or a hydride vapor phase epitaxy process, and the epitaxial layer 101 includes a first semiconductor layer 11, a light emitting layer 12, and a second semiconductor layer 13 stacked in sequence from bottom to top. The thickness of the epitaxial layer 101 includes 5 μm to 10 μm. By using photolithography and dry etching processes, the second semiconductor layer 13 is etched to the surface or layer of the first semiconductor layer 11 to expose the first semiconductor layer 11, and an array of grooves 14 is formed in the second semiconductor layer 13 and the light emitting layer 12. The spacing between the centers of adjacent grooves 14 includes 100 μm to 200 μm, and the diameter of the groove 14 is, for example, 60 μm. An ohmic contact layer material layer is formed on the second semiconductor layer 13 by using RPD reactive plasma deposition technology, and a rapid annealing process is performed, and then patterning is performed to form an ohmic contact layer 102. The ohmic contact layer 102 is located on a portion of the second semiconductor layer 13 and is electrically connected to the second semiconductor layer 13. The ohmic contact layer 102 is, for example, an ITO layer, and the thickness of the ohmic contact layer 102 is, for example, 15 nm.

[0067] Next, please refer to Figure 4B As shown, an insulating reflective layer 103 is formed. The insulating reflective layer 103 includes a single-layer reflective layer 103a and a multi-layer reflective layer 103b formed by alternating two reflective films with different refractive indices. The single-layer reflective layer material layer and the multi-layer reflective layer material layer can be formed by using ion beam assisted electron beam physical vapor deposition (EB PVD) technology, and the single-layer reflective layer material layer and the multi-layer reflective layer material layer are etched by photolithography and dry etching processes to form a perforation 15 to form the single-layer reflective layer 103a and the multi-layer reflective layer 103b. The perforation 15 penetrates the single-layer reflective layer 103a and the multi-layer reflective layer 103b, and the multi-layer reflective layer 103b is located on the single-layer reflective layer 103a. The single-layer reflective layer 103a and the multi-layer reflective layer 103b form a two-step structure in the perforation 15. The single-layer reflective layer 103a covers the ohmic contact layer 102, the second semiconductor layer 13, and the sidewalls of the groove 14, and the multi-layer reflective layer 103b covers the single-layer reflective layer 103a above the second semiconductor layer 13, and does not cover the single-layer reflective layer 103a on the sidewalls of the groove 14. It can be understood that in other embodiments, the insulating reflective layer 103 may also only include the single-layer reflective layer 103a, the perforation 15 penetrates the single-layer reflective layer 103a, and the single-layer reflective layer 103a covers the ohmic contact layer 102, the second semiconductor layer 13, and the sidewalls of the groove 14. Alternatively, it may only include the multi-layer reflective layer 103b, the perforation 15 penetrates the multi-layer reflective layer 103b, and the multi-layer reflective layer 103b covers the ohmic contact layer 102, the second semiconductor layer 13, and the sidewalls of the groove 14. The thickness of each single layer in the single-layer reflective layer 103a or the multi-layer reflective layer 103b is an integer multiple of λ / 4n, where λ is the light emission wavelength of the light-emitting layer 12, and n is the refractive index of the single layer at the light emission wavelength. The material of the single-layer reflective layer 103a can be one or more combinations of MgF2, SiO2, and Al2O3. The low refractive index material in the multi-layer reflective layer 103b can be one of MgF2, CaF2, SiO2, and Al2O3, and the high refractive index material can be one of TiO2, Ta2O5, and Nb2O5. The number of stacked pairs of low refractive index material and high refractive index material in the multi-layer reflective layer 103b is, for example, not less than 6 pairs. Preferably, the bottom layer (the layer closest to the second semiconductor layer 13) in the multi-layer reflective layer 103b is a low refractive index material.

[0068] Next, please refer to Figures 4C to 4E As shown, a transmissive medium layer 104 and a transmissive adhesive layer 106 are formed. Figure 4C As shown, a transmissive dielectric layer material can be formed on the insulating reflective layer 103 by using CVD chemical vapor deposition technology, and the transmissive dielectric layer material covers the insulating reflective layer 103, the sidewalls and bottom of the through hole 15, and the sidewalls and bottom of the groove 14. Next, please refer to Figure 4DAs shown, a transmissive adhesive layer material can be formed on the transmissive dielectric layer material by using CVD chemical vapor deposition technology, and the transmissive adhesive layer material covers the transmissive dielectric layer material. Figure 4E As shown, the transmissive medium layer 104 and the transmissive adhesive layer 106 at the bottom of the groove 14 and the through hole 15 are removed by photolithography and etching techniques, respectively exposing the first semiconductor layer 11 and the ohmic contact layer 102. In some embodiments, the transmissive medium layer 104 and the transmissive adhesive layer 106 can be combined into the same film layer, and the film layer adopts an optical film thickness design.

[0069] Next, please refer to Figure 4F As shown, a metal reflective layer 105 is formed. A metal reflective layer material layer is deposited on the surfaces of the transmissive adhesion layer 106, the first semiconductor layer 11 and the ohmic contact layer 102 by a deposition process. The metal reflective layer material layer and the transmissive adhesion layer 106 are patterned by photolithography and etching processes. The transmissive adhesion layer 106 is located on the transmissive dielectric layer 104. The transmissive dielectric layer 104 covers the insulating reflective layer 103, the sidewalls of the through-holes 15 and the sidewalls of the grooves 14. The transmissive adhesion layer 106 covers a portion of the transmissive dielectric layer 104 above the second semiconductor layer 13, the transmissive dielectric layer 104 on the sidewalls of the through-holes 15 and the transmissive dielectric layer 104 on the sidewalls of the grooves 14. The metal reflective layer 105 covers the transmissive adhesion layer 106 above the second semiconductor layer 13, fills a plurality of through-holes 15, covers the transmissive adhesion layer 106 on the sidewalls of the grooves 14 and the bottom of the grooves 14. For example, the metal reflective layer 105 includes a stack of Ag layers, TiW layers, Pt layers and Ti layers. The thicknesses of the Ag layer, TiW layer, Pt layer and Ti layer are and It is easy to understand that the metal reflective layer 105 is electrically connected to the ohmic contact layer 102 through the perforation 15, and the metal reflective layer 105 is electrically connected to the first semiconductor layer 11 through the groove 14. It is easy to understand that the transmissive medium layer 104 on the sidewalls of the groove 14 and the perforation 15 increases the light reflectivity of the ODR reflector 300 in the normal direction of the sidewalls of the array-distributed grooves 14 and the perforations 15. It is easy to understand that the metal reflective layer 105 and the transmissive adhesion layer 106 covering the sidewalls and bottom of the groove 14 are separated from the metal reflective layer 105 and the transmissive adhesion layer 106 located above the second semiconductor layer 13 to prevent short circuit leakage.

[0070] Next, please refer to Figure 4GAs shown, a second current spreading layer material layer is formed on the metal reflective layer 105 by using PVD technology. The second current spreading layer material layer is patterned by photolithography and dry etching processes to form a second current spreading layer 107. The second current spreading layer 107 covers the metal reflective layer 105 above the second semiconductor layer 13. The second current spreading layer 107 does not cover the groove 14 to achieve electrical connection between the subsequent metal column 18 and the first semiconductor layer 11. For example, the second current spreading layer 107 includes a stack of a Ti layer, an Au layer, a Pt layer and a Ti layer, and the thicknesses of the Ti layer, the Au layer, the Pt layer and the Ti layer are respectively and

[0071] Next, please refer to Figure 4H As shown, a first isolation dielectric layer material layer is formed on the second current spreading layer 107 by using PECVD technology, and a first isolation dielectric layer 109 is patterned by using photolithography and dry etching technology. The first isolation dielectric layer 109 covers the second current spreading layer 107 and the exposed transmission dielectric layer 104, exposing the sidewall of the groove 14 and the metal reflective layer 105 at the bottom. The first isolation dielectric layer 109 includes a stacked structure of a SiO2 layer, a SiON layer and a SiO2 layer, and the thickness of the first isolation dielectric layer 109 is, for example, 600 nm.

[0072] Next, please refer to Fig. 4I As shown, a metal pillar 18 is deposited in the groove 14 by using PVD technology, photolithography and dry etching process to compensate for the height difference. The metal pillar 18 includes a stacked layer consisting of a Ti layer, an Al layer and a TiW layer.

[0073] Next, please refer to Figure 4J and 4K As shown, the first current spreading layer 108 is formed on the first isolation dielectric layer 109 by PVD technology. The first current spreading layer 108 is located on the first isolation dielectric layer 109, covering the first isolation dielectric layer 109 and the metal pillar 18. The bonding substrate 200 is bonded to the first current spreading layer 108, and the substrate 100 is removed. In some embodiments, a bonding layer 120 can be formed on the first current spreading layer 108 and the bonding substrate 200 by electron beam evaporation technology, and then the first current spreading layer 108 is bonded to the bonding substrate 200 by bonding technology. For example, the material of the bonding substrate 200 is Si, and the thickness is 1 mm. The material of the bonding layer 120 is NiSn, for example. For example, the first current spreading layer 108 includes a stack of a Ti layer, an Al layer, a Pt layer and a Ti layer, and the thicknesses of the Ti layer, the Al layer, the Pt layer and the Ti layer are respectively and In other embodiments, the first current spreading layer 108 and the metal pillar 18 may also be an integrated structure, that is, the first current spreading layer 108 is located on the surface of the first isolation dielectric layer 109 away from the epitaxial layer 101 and fills the groove 14 .

[0074] Next, please refer to Figure 4L As shown, a step 112 exposing part of the second current spreading layer 107 is formed on the periphery of the epitaxial layer 101 and the ODR reflector 300 by photolithography and dry etching processes. Exemplarily, a Cl-based dry etching technique is used to etch a portion of the thickness (for example, 1um) of the first semiconductor layer 11 to reduce the influence of defects on the surface of the first semiconductor layer 11 on the absorption of the light output and the electrical characteristics of the device. Then, the epitaxial layer 101 and the ODR reflector 300 outside the light-emitting area are removed by photolithography and Cl-based dry etching techniques to form a step 112 exposing part of the second current spreading layer 107. Finally, the surface of the first semiconductor layer 11 is roughened. Exemplarily, a hot solution of KOH with a concentration of 6 mol / L is used to treat the first semiconductor layer 11 at 70°C to form a roughened surface. A passivation protection layer material layer is formed on the side of the first semiconductor layer 11 away from the substrate 200 by PECVD technology, and the passivation protection layer material layer is patterned by photolithography and dry etching processes to form a passivation protection layer 111. The passivation protection layer 111 covers a side of the first semiconductor layer 11 away from the substrate 200 and a sidewall of the step 112 , exposing a portion of the second current spreading layer 107 .

[0075] Next, please refer to Figure 4M As shown, a second electrode 21 is formed on the step 112 by using photolithography and PVD technology, and the second electrode 21 is electrically connected to the exposed portion of the second current spreading layer 107. For example, the material of the second electrode 21 includes a stack of a Ti layer, a Ni layer and an Au layer, and the thickness of the second electrode 21 is, for example, 1um. The back side of the substrate 200 (i.e., the side away from the ODR reflector 300) is thinned. For example, the substrate 200 is thinned to 150um. A first electrode 20 is formed on the surface of the side of the substrate 200 away from the ODR reflector 300, and the first electrode 20 is electrically connected to the first current spreading layer 108. For example, the material of the first electrode 20 includes a stack of a Ti layer, a Pt layer and an Au layer. After scribing / splitting separation, the preparation of the vertical light-emitting diode is completed.

[0076] In the light-emitting diode provided by the present disclosure, the transmissive adhesion layer 106 increases the adhesion between the metal reflective layer 105 and the insulating reflective layer 103, thereby preventing the metal reflective layer 105 from falling off and improving the process stability and reliability of the light-emitting diode.

[0077] The embodiments of the present disclosure are described above, and these embodiments do not describe all the details in detail, nor do they limit the present disclosure to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modifications based on the present disclosure. The present disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A light emitting diode, characterized in that: include: An epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence from bottom to top, a plurality of grooves penetrating the second semiconductor layer and the light-emitting layer and exposing the first semiconductor layer; an ODR reflector, located on a side of the second semiconductor layer away from the light-emitting layer, the ODR reflector comprising an insulating reflective layer, a transmissive dielectric layer and a metal reflective layer, the insulating reflective layer being located on a side of the second semiconductor layer away from the light-emitting layer, a plurality of perforations penetrating the insulating reflective layer and exposing the second semiconductor layer, the transmissive dielectric layer covering the side walls of the plurality of perforations and / or the side walls of the plurality of grooves of the insulating reflective layer, the metal reflective layer being located on a side of the insulating reflective layer away from the second semiconductor layer and filling the plurality of perforations, the metal reflective layer also covering the transmissive dielectric layer on the side walls of the grooves and the bottom of the grooves, and the metal reflective layer located on a side of the insulating reflective layer away from the second semiconductor layer and being separated from the metal reflective layer located on the side walls and the bottom of the grooves; A substrate, the substrate is located on a side of the ODR reflector away from the epitaxial layer; or the first semiconductor layer is located on the substrate; and, A first electrode and a second electrode are insulated from each other, the first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

2. The light emitting diode according to claim 1, characterized in that: The transmissive medium layer also covers a surface of the insulating reflective layer that is away from the second semiconductor layer.

3. The light emitting diode according to claim 1 or 2, characterized in that: The ODR reflector further comprises: The transmissive adhesion layer is located on a surface of the transmissive medium layer away from the insulating reflective layer, the metal reflective layer is located on a surface of the transmissive adhesion layer away from the transmissive medium layer, and the transmissive adhesion layer located on a side of the second semiconductor layer away from the light-emitting layer is separated from the transmissive adhesion layer located on the sidewall of the groove.

4. The light emitting diode according to claim 1, characterized in that: Also includes: An ohmic contact layer is located on a portion of the surface of the second semiconductor layer away from the light-emitting layer and is electrically connected to the second semiconductor layer. The through hole exposes the ohmic contact layer.

5. The light emitting diode according to claim 1, characterized in that: The first semiconductor layer is located on the substrate, and the light emitting diode further comprises: a second current spreading layer, located on the metal reflective layer and covering the metal reflective layer outside the groove; a first isolation dielectric layer, located on the second current spreading layer, covering the second current spreading layer and the exposed insulating reflective layer, and exposing the groove; a first current spreading layer, located on the first isolation dielectric layer, covering a portion of the first isolation dielectric layer and filling the groove, exposing a portion of the first isolation dielectric layer above the second current spreading layer; a second isolation dielectric layer, located on the first current spreading layer, covering the first current spreading layer and the exposed first isolation dielectric layer; The second isolation dielectric layer includes a first opening, the first opening exposes the first current spreading layer, and the first isolation dielectric layer and the second isolation dielectric layer include a second opening, the second opening exposes the second current spreading layer.

6. The light emitting diode according to claim 5, characterized in that: The second electrode is located on the second isolation dielectric layer and is electrically connected to the second current spreading layer through the second opening. The first electrode is located on the second isolation dielectric layer and is electrically connected to the first current spreading layer through the first opening.

7. The light emitting diode according to claim 1, characterized in that: The substrate is located on a side of the ODR reflector away from the epitaxial layer, and the light emitting diode further comprises: a second current spreading layer, located on a surface of the metal reflective layer away from the second semiconductor layer, and covering the metal reflective layer outside the groove; A first isolation dielectric layer is located on a surface of the second current spreading layer away from the metal reflective layer, covers the second current spreading layer and the exposed insulating reflective layer, and exposes the groove; A first current spreading layer, located on a surface of the first isolation dielectric layer away from the second current spreading layer and filling the groove; The bonding layer is located on a surface of the first current spreading layer away from the first isolation dielectric layer, and the substrate is located on a surface of the bonding layer away from the first current spreading layer.

8. The light emitting diode according to claim 7, characterized in that: A step exposing a portion of the second current spreading layer is formed at the periphery of the epitaxial layer and the ODR reflector, and the step penetrates the epitaxial layer and the ODR reflector. The light emitting diode further includes: A passivation protection layer is located on a surface of the first semiconductor layer on a side away from the substrate, covers the first semiconductor layer and the sidewall of the step, and exposes a portion of the second current spreading layer. The second electrode is located on the step and is electrically connected to the exposed portion of the second current spreading layer. The first electrode is located on a surface of the substrate on a side away from the bonding layer.

9. The light emitting diode according to claim 1, characterized in that: The insulating reflective layer includes a single-layer reflective layer and / or a multi-layer reflective layer formed by alternately stacking two reflective films with different refractive indices.

10. The light emitting diode according to claim 1, characterized in that: The transmission medium layer includes: one of: an Al2O3 layer, a MgF2 layer and a SnO2 layer, and the thickness of the transmission medium layer includes: λ / 4n, wherein λ is the light-emitting wavelength of the light-emitting layer, and n is the refractive index of the transmission medium layer at the light-emitting wavelength.

11. The light emitting diode according to claim 3, characterized in that: The transmissive adhesion layer includes: one of an ITO layer and an Al2O3 layer, and the thickness of the transmissive adhesion layer includes: 1nm to 100nm.

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