Semiconductor device structure

Abstract

A semiconductor device structure includes a first source / drain feature, a first interlayer dielectric layer disposed over the first source / drain feature, a first conductive feature extending through the first interlayer dielectric layer and in electrical contact with the first source / drain feature, and a second conductive feature disposed over the first source / drain feature. Wherein the first conductive feature has an L-shaped profile with respect to a plan view of the semiconductor device structure. The structure also includes a gate electrode layer extending through the first interlayer dielectric layer and disposed adjacent to the first conductive feature, wherein a top surface of the first conductive feature is substantially coplanar with a top surface of the gate electrode layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to a semiconductor device. Background Art

[0002] As the semiconductor industry has advanced to nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as fin field-effect transistors (FinFETs). FinFET devices typically include semiconductor fins with a high aspect ratio and channels and source / drain regions formed therein. Taking advantage of the increased surface area of ​​the channel, gates are formed above and along the sides of the fin structure (e.g., wrapping around) to produce faster, more reliable, and better controlled semiconductor transistor devices. However, as the size decreases, the critical dimension (CD) between adjacent contact parts becomes smaller. In order to achieve high performance of integrated circuits (ICs), higher resistance and parasitic capacitance due to the smaller CD of adjacent contact parts in the back-end-of-line (BEOL) process has become a key issue. Utility Model Content

[0003] The present disclosure aims to provide a semiconductor device structure to solve at least one of the above problems.

[0004] One embodiment is a semiconductor device structure, the structure comprising a first source / drain feature, a first interlayer dielectric layer disposed above the first source / drain feature, a first conductive feature extending through the first interlayer dielectric layer and in electrical contact with the first source / drain feature, wherein the first conductive feature has an L-shaped profile relative to a plan view of the semiconductor device structure. The structure also includes a gate electrode layer extending through the first interlayer dielectric layer and disposed adjacent to the first conductive feature, wherein a top surface of the first conductive feature is substantially coplanar with a top surface of the gate electrode layer.

[0005] In some embodiments, the semiconductor device structure further includes: a second interlayer dielectric layer, disposed above the first interlayer dielectric layer; and an abutment contact, having a top surface and a bottom surface, the abutment contact extending through the second interlayer dielectric layer and contacting the top surface of the first conductive component and the top surface of the gate electrode layer.

[0006] In some embodiments, a bottom surface of the abutting contact, a top surface of the first conductive component, and a top surface of the gate electrode layer are substantially coplanar.

[0007] In some embodiments, the first conductive component includes a first portion having a first width and a second portion having a second width, the second width being smaller than the first width.

[0008] In some embodiments, the first portion is disposed closer to the gate electrode layer than the second portion.

[0009] In some embodiments, the first portion of the first conductive component is in direct contact with the gate electrode layer.

[0010] In some embodiments, the semiconductor device structure further includes: a gate dielectric layer disposed between the first portion of the first conductive component and the gate electrode layer, and the gate dielectric layer is in direct contact with the first portion of the first conductive component and the gate electrode layer.

[0011] Another embodiment is a semiconductor device structure, the structure including a first source / drain component disposed above a substrate, a butted contact disposed above the first source / drain component. The butted contact includes a first portion including a first material and a second portion including a second material. The structure also includes a first conductive component disposed between the first source / drain component and the first portion of the butted contact, and a gate electrode layer disposed adjacent to the first conductive component and in contact with the second portion of the butted contact.

[0012] In some embodiments, the semiconductor device structure further comprises: a second source / drain component;

[0013] A via contact component is disposed on the second source / drain component; and a second conductive component is disposed between the second source / drain component and the via contact, wherein a top surface of the via contact component is substantially coplanar with a top surface of the abutting contact.

[0014] In some embodiments, the abutting contact has a bottom surface that is coplanar with a top surface of the first conductive component and a top surface of the gate electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure.

[0016] Figures 1 to 4 FIG. 4 is a perspective view illustrating a semiconductor device structure at various manufacturing stages according to some embodiments.

[0017] FIG. 5A to FIG. 16A as well as FIG. 18A to FIG. 24A According to some embodiments, a cross-sectional view taken along the AA Figure 4 Cross-sectional side views of a semiconductor device structure at various manufacturing stages.

[0018] FIG. 5B to FIG. 16B as well as FIG. 18B to FIG. 24B According to some embodiments, a cross-sectional view taken along the BB Figure 4 Cross-sectional side views of a semiconductor device structure at various manufacturing stages.

[0019] FIG. 9C to FIG. 15C as well as FIG. 18C to FIG. 23C They are FIG. 9B to FIG. 15B as well as FIG. 18B to FIG. 23B A top view of a portion of a semiconductor device structure is shown.

[0020] Fig.12D FIG. 1 is an enlarged view of a portion of a semiconductor device structure showing the structural relationship of an L-shaped conductive component relative to surrounding film layers according to some embodiments.

[0021] FIG. 17A to FIG. 17I A layout diagram of a portion of a semiconductor device structure is shown according to some alternative embodiments.

[0022] Fig.25 A cross-sectional side view of a semiconductor device structure is shown according to some alternative embodiments.

[0023] Fig.26 A cross-sectional side view of a semiconductor device structure is shown according to some alternative embodiments.

[0024] The reference numerals are described as follows:

[0025] 100 / 200 / 300 / 400 / 500: Semiconductor device structure

[0026] 102: Base

[0027] 102N: N-type area

[0028] 102P: P-type area

[0029] 103N: N-well region

[0030] 103P: P well region

[0031] 104: First semiconductor layer

[0032] 106: Second semiconductor layer

[0033] 108a / 108b / 110a / 110b: Fins

[0034] 112: Insulation material

[0035] 117 / 317: Interconnection structure

[0036] 121: Shallow Trench Isolation Area

[0037] 128: Sacrificial Gate Stack

[0038] 130: Sacrificial gate dielectric layer

[0039] 132: Sacrificial gate electrode layer

[0040] 134: Mask structure

[0041] 140: Gate spacer

[0042] 141: Second contact etching stop layer

[0043] 143: Second interlayer dielectric layer

[0044] 145 / 171a / 171n: Etch stop layer

[0045] 146: Contact opening

[0046] 146a: First opening

[0047] 146b: Second opening

[0048] 148 / 348-1 / 348-2: Abutting contact opening

[0049] 149 / 349: Via contact opening

[0050] 152: Epitaxial source / drain components

[0051] 153 / 253a / 253b: L-shaped conductive part

[0052] 153a / 253-1 / 265-1 / 283-1: Part I

[0053] 153b / 253-2 / 265-2 / 283-2: Part 2

[0054] 153b-1: Segment 1

[0055] 153b-2: Segment 2

[0056] 153s: Sidewall

[0057] 153t / 167t / 172t / 179t / 180t: Top surface

[0058] 160: First contact etching stop layer

[0059] 162: First interlayer dielectric layer

[0060] 166: Gate dielectric layer

[0061] 167: Gate electrode layer

[0062] 168a / 168n: Intermetallic dielectric layer

[0063] 169a / 169n / 172: Conductive parts

[0064] 170 / 370: Silicide layer

[0065] 177 / 277a / 277b: Replacement gate structure

[0066] 178: The third interlayer dielectric layer

[0067] 179 / 279a / 279b / 379-1 / 379-2 / 479 / 579: abutment contact

[0068] 179b / 379-1b / 379-2b: Bottom surface

[0069] 180 / 380: Guide hole contact parts

[0070] 265a / 265b / 283a / 283b: T-shaped conductive part

[0071] 272 / 372: Conductive parts

[0072] 311: Patterned layer

[0073] 379: Final abutment contact

[0074] W1 / W2 / W3 / W4 / W5 / W6 / W7 / W8 / W9 / W10 / W11 / W12: Width DETAILED DESCRIPTION

[0075] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0076] Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "over", "above", "upper", "top", "higher" and the like, to facilitate the description of the relationship between one (or some) parts or components and another (or some) parts or components in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0077] Figures 1 to 26 FIG. 1 is a diagram illustrating a semiconductor device structure 100 at various stages of fabrication according to various embodiments of the present disclosure. It should be understood that additional embodiments of the method may be described in detail in the following. Figures 1 to 26 Additional steps are provided before, during, and after the processes shown, and some of the steps described below may be replaced or deleted. The order of the steps / processes may be interchanged.

[0078] Figures 1 to 4 FIG. 1 is a perspective view of a semiconductor device structure 100 at various manufacturing stages according to some embodiments. Figure 1 In the embodiment of the present invention, the first semiconductor layer 104 is formed on the substrate 102. The substrate can be a part of a chip in a wafer. In some embodiments, the substrate 102 is a bulk semiconductor substrate, such as a semiconductor wafer, for example, the substrate 102 is a silicon wafer. The substrate 102 may include silicon or another elemental semiconductor material (such as germanium). In some other embodiments, the substrate 102 includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable semiconductor material, or a combination of the foregoing. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate. The SOI substrate can be manufactured using a separation by implanted oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination of the foregoing.

[0079] The substrate 102 may be doped with P-type or N-type impurities. Figure 1As shown, the substrate 102 has a P-type region 102P and an N-type region 102N adjacent to the P-type region 102P, and the P-type region 102P and the N-type region 102N belong to a continuous substrate 102. In some embodiments of the present disclosure, the P-type region 102P is used to form a P-channel metal oxide semiconductor (PMOS) device thereon, and the N-type region 102N is used to form an N-channel metal oxide semiconductor (NMOS) device thereon. In some embodiments, the N-well region 103N and the P-well region 103P are formed in the substrate 102, such as Figure 1 As shown, for example, the N-well region 103N can be formed in the substrate 102 in the P-type region 102P, and the P-well region 103P can be formed in the substrate 102 in the N-type region 102N. The P-well region 103P and the N-well region 103N can be formed by any suitable technique, for example, by separate ion implantation processes in some embodiments. By using two different implantation mask layers (not shown), the P-well region 103P and the N-well region 103N can be formed sequentially in different ion implantation processes.

[0080] The first semiconductor layer 104 is deposited on the substrate 102. Figure 1 As shown. The first semiconductor layer 104 can be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor materials, or a combination thereof. In an exemplary embodiment, the first semiconductor layer 104 is made of silicon. The first semiconductor layer 104 can be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or any other suitable process.

[0081] exist Figure 2 In the embodiment of the present invention, a portion of the first semiconductor layer 104 disposed above the N-well region 103N is removed, and a second semiconductor layer 106 is formed above the N-well region 103N and adjacent to a portion of the first semiconductor layer 104 disposed above the P-well region 103P. A patterned mask layer (not shown) may be first formed on the portion of the first semiconductor layer 104 disposed above the P-well region 103P, and a portion of the first semiconductor layer 104 disposed above the N-well region 103N may be exposed. A removal process such as dry etching, wet etching, or a combination thereof may be performed to remove the portion of the first semiconductor layer 104 disposed above the N-well region 103N, and the N-well region 103N may be exposed. The removal process does not substantially affect the mask layer (not shown) formed on the portion of the first semiconductor layer 104 disposed above the P-well region 103P, which protects the portion of the first semiconductor layer 104 disposed above the P-well region 103P. Next, the second semiconductor layer 106 is formed on the exposed N-well region 103N. The second semiconductor layer 106 may be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor materials, or a combination thereof. In an exemplary embodiment, the second semiconductor layer 106 is made of silicon germanium. The second semiconductor layer 106 may be formed by the same process as the first semiconductor layer 104, for example, the second semiconductor layer 106 may be formed on the exposed N-well region 103N by an epitaxial growth process, and the epitaxial growth process does not form the second semiconductor layer 106 on a mask layer (not shown) disposed on the first semiconductor layer 104. In this way, the first semiconductor layer 104 is disposed above the P-well region 103P in the N-type region 102N, and the second semiconductor layer 106 is disposed above the N-well region 103N in the P-type region 102P.

[0082] Portions of the first semiconductor layer 104 may be used as channels in NMOS devices subsequently formed in the N-type region 102N, and portions of the second semiconductor layer 106 may be used as channels in PMOS devices subsequently formed in the P-type region 102P. In some embodiments, the NMOS device and the PMOS device are FinFETs. Although the embodiments described in the present disclosure are described in the context of FinFETs, some aspects of the present disclosure may be used in other processes and / or other devices, such as planar FETs, dual-gate FETs, tri-gate FETs, nanochannel FETs, fork-shaped FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, complementary FETs, negative capacitance FETs, and other suitable devices. Those skilled in the art will readily appreciate that other modifications that may be made are contemplated within the scope of the present disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method, for example, the structure can be patterned using one or more lithography processes (including double patterning or multiple patterning processes). Generally speaking, a double patterning or multiple patterning process combines a lithography process with a self-alignment process to create, for example, a pattern with a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0083] exist Figure 3 In the embodiment, a plurality of fins 108a, 108b, 110a, 110b are formed by a first semiconductor layer 104 and a second semiconductor layer 106, respectively, and a shallow trench isolation (STI) region 121 is formed. The fins 108a, 108b, 110a, 110b can be patterned by any suitable method, for example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern the fins 108a, 108b, 110a, 110b. In general, a double patterning or multi-patterning process combines a lithography process with a self-alignment process to create a pattern with a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer (not shown) is formed above a substrate and patterned using a lithography process. Spacers (not shown) are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the substrate and form the fins.

[0084] The fins 108a and 108b may each include a first semiconductor layer 104, and a portion of the first semiconductor layer 104 may be used as an NMOS channel. Each fin 108a and 108b may also include a P-well region 103P. Similarly, the fins 110a and 110b may each include a second semiconductor layer 106, and a portion of the second semiconductor layer 106 may be used as a PMOS channel. Each fin 110a and 110b may also include an N-well region 103N. A mask (not shown) may be formed on the first semiconductor layer 104 and the second semiconductor layer 106, and may remain on the fins 108a-b and 110a-b.

[0085] Once the fins 108a-b, 110a-b are formed, an insulating material 112 is formed between adjacent fins 108a-b, 110a-b. The insulating material 112 may be first formed between adjacent fins 108a-b, 110a-b and over the fins 108a-b, 110a-b, so that the fins 108a-b, 110a-b are embedded in the insulating material 112. A planarization process such as a chemical mechanical polishing or planarization (CMP) process may be performed to expose the tops of the fins 108a-b, 110a-b. In some embodiments, the planarization process exposes the tops of a mask (not shown) disposed over the fins 108a-b and 110a-b, and then recesses the insulating material 112 by removing portions of the insulating material 112 on both sides of each fin 108a-b, 110a-b. The insulating material 112 may be recessed by any suitable removal process, such as dry etching or wet etching, to selectively remove the insulating material 112 without substantially affecting the semiconductor material of the fins 108a-b, 110a-b. The insulating material 112 may include an oxygen-containing material, such as silicon oxide, carbon or nitrogen-doped oxide, fluorine-doped silicate glass (FSG); a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon carbon nitride (SiCN); a low dielectric constant (K) dielectric material (e.g., a material having a lower K value than silicon dioxide); or any suitable dielectric material. The insulating material 112 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). The insulating material 112 may be a shallow trench isolation (STI) region and is referred to as an STI region 121 in this disclosure.

[0086] In some alternative embodiments, instead of forming the first semiconductor layer 104 and the second semiconductor layer 106 above the substrate 102, the fins 108a-b, 110a-b can be formed by first forming an isolation region (e.g., STI region 121) on a bulk substrate (e.g., substrate 102). The formation of the STI region can include etching the bulk substrate to form a trench and filling the trench with a dielectric material to form the STI region, and the substrate portion between adjacent STI regions forms the fin. The top surface of the fin and the top surface of the STI region can be substantially flush with each other by a CMP process. After forming the STI region, at least the top portion of the fin is removed or substantially all of the fin is removed, thereby forming a recess between the STI regions. The bottom surface of the STI region can be flush with, higher than, or lower than the bottom surface of the STI region. Epitaxy is then performed to grow the first semiconductor layer and the second semiconductor layer (e.g., the first semiconductor layer 104 and the second semiconductor layer 106) individually in the recesses created by removing portions of the fins, thereby forming fins (e.g., fins 108a-b, 110a-b). CMP is then performed until the top surfaces of the fins are substantially coplanar with the top surfaces of the STI regions. In some embodiments, after the epitaxy and CMP, an implantation process is performed to define well regions (e.g., the P-well region 103P and the N-well region 103N) in the substrate. Alternatively, the fins are in-situ doped with impurities (e.g., dopants having P-type or N-type conductivity) during epitaxy. Thereafter, the STI regions are recessed to allow the fins of the first semiconductor layer and the second semiconductor layer (e.g., fins 108a-b, 110a-b) to be aligned with the top surfaces of the STI regions. Figure 3 A similar pattern is shown extending upward from the substrate to over the STI regions.

[0087] In some alternative embodiments, one of the fins 108a-b (e.g., fin 108a) in the N-type region 102N is formed from the second semiconductor layer 106, and the other fin 108b in the N-type region 102N is formed from the first semiconductor layer 104. In this case, the epitaxial source / drain (S / D) features 152 subsequently formed on the fins 108a and 108b in the N-type region 102N may be silicon (Si) or silicon phosphide (SiP); the epitaxial S / D features 152 subsequently formed on the fins 110a and 110b in the P-type region 102P may be silicon germanium (SiGe). In some alternative embodiments, the fins 108a-b and 110a-b are directly formed from a bulk substrate (e.g., substrate 102), which may be doped with P-type or N-type impurities to form well regions (e.g., P-well region 103P and N-well region 103N). In this case, the fins are formed of the same material as the substrate 102. In an exemplary embodiment, the fins and the substrate 102 are formed of silicon.

[0088] exist Figure 4In the embodiment of the present invention, one or more sacrificial gate stacks 128 are formed on a portion of the fins 108a-b, 110a-b. Each sacrificial gate stack 128 may include a sacrificial gate dielectric layer 130, a sacrificial gate electrode layer 132, and a mask structure 134. The sacrificial gate dielectric layer 130 may include one or more layers of dielectric materials, such as silicon dioxide (SiO2), silicon nitride (SiN), high-K dielectric materials and / or other suitable dielectric materials. In some embodiments, the sacrificial gate dielectric layer 130 may be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or other suitable processes. The sacrificial gate electrode layer 132 may include polysilicon. The mask structure 134 may include an oxygen-containing layer and a nitrogen-containing layer. In some embodiments, the sacrificial gate electrode layer 132 and the mask structure 134 are formed by various processes, such as film deposition, for example, CVD (including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD)), PVD, ALD, thermal oxidation, electron beam evaporation or other suitable deposition techniques or combinations thereof.

[0089] The sacrificial gate stack 128 can be formed by first depositing a blanket layer of a sacrificial gate dielectric layer 130, a sacrificial gate electrode layer 132, and a mask structure 134, followed by a patterning and etching process, for example, the patterning process includes a lithography process (e.g., yellow light lithography or electron beam lithography), which further includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations of the foregoing. In some embodiments, the etching process may include dry etching, wet etching, other etching methods and / or combinations of the foregoing. By patterning the sacrificial gate stack 128, the fins 108a-b, 110a-b are partially exposed on opposite sides of the sacrificial gate stack 128. Although Figure 4 Two sacrificial gate stacks 128 are depicted, but it will be appreciated that they are for illustration purposes only and any number of sacrificial gate stacks 128 may be formed.

[0090] FIG. 5A to FIG. 16A as well as FIG. 18A to FIG. 24A According to some embodiments, a cross-sectional view taken along the AA Figure 4Cross-sectional side views of a semiconductor device structure at various manufacturing stages. FIG. 5B to FIG. 16B as well as FIG. 18B to FIG. 24B According to some embodiments, a cross-sectional view taken along the BB Figure 4 The cross-sectional side view of the semiconductor device structure at various manufacturing stages. The cross-sectional view BB is located in the plane of the fin 110b along the X direction. The cross-sectional view AA is located in the plane perpendicular to the cross-sectional view BB and is located at the epitaxial S / D component 152 ( Fig. 6A )middle. FIG. 9C to FIG. 15C as well as FIG. 18C to FIG. 23C They are FIG. 9B to FIG. 15B as well as FIG. 18B to FIG. 23B A top view of a portion of a semiconductor device structure 100 is shown. FIG. 9B to FIG. 16B as well as FIG. 18B to FIG. 24B The figure shows a section taken along section BB. FIG. 9C to FIG. 15C as well as FIG. 18C to FIG. 23C Cross-sectional side view.

[0091] exist FIG. 5A to FIG. 5B , a gate spacer 140 is formed on the sacrificial gate structure 128 and the exposed portions of the first semiconductor layer 104 and the second semiconductor layer 106. The gate spacer 140 may be conformally deposited on the exposed surface of the semiconductor device structure 100. The conformal gate spacer 140 may be formed by ALD or any suitable process, and then an anisotropic etch is performed on the gate spacer 140 using, for example, reactive ion etching (RIE). During the anisotropic etching process, a majority of the gate spacer 140 is removed from horizontal surfaces, such as the top of the sacrificial gate structure 128 and the tops of the fins 108a-b, 110a-b, thereby leaving the gate spacer 140 on vertical surfaces, such as on opposite sidewalls of the sacrificial gate structure 128. The gate spacer 140 may partially remain on opposite sidewalls of the fins 108a-b, 110a-b, such as Figure 5A In some embodiments, the gate spacer 140 formed on the source / drain regions of the fins 108a-b, 110a-b is completely removed.

[0092] The gate spacer 140 can be made of a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), an air gap, and / or any combination of the foregoing. In some embodiments, the gate spacer 140 includes one or more layers of dielectric materials discussed herein.

[0093] exist FIG. 6A to FIG. 6BIn the embodiment, the first semiconductor layer 104 and the second semiconductor layer 106 of the fins 108a-b, 110a-b not covered by the sacrificial gate structure 128 and the gate spacer 140 are recessed and form epitaxial source / drain (S / D) features 152. For n-channel field effect transistors (NFETs), the epitaxial S / D features 152 may include one or more layers of silicon (Si), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), or III-V materials (indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), indium arsenide (InAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs)). In some embodiments, for n-type devices, the epitaxial S / D features 152 may be doped with n-type dopants, such as phosphorus (P), arsenic (As), etc. For p-channel field effect transistors (PFETs), the epitaxial S / D components 152 may include one or more layers of silicon (Si), silicon germanium (SiGe), silicon germanium boride (SiGeB), germanium (Ge), or a III-V material (indium antimonide (InSb), gallium antimonide (GaSb), indium gallium antimonide (InGaSb)). In some embodiments, the epitaxial S / D components 152 may be doped with a P-type dopant, such as boron (B). The epitaxial S / D components 152 may be grown vertically and horizontally to form facets that may correspond to the facets of the material used for the substrate 102. The epitaxial S / D components 152 may be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE).

[0094] In some embodiments, portions of the first semiconductor layer 104 on both sides of each sacrificial gate structure 128 are completely removed, and epitaxial S / D features 152 are formed on the P-well regions 103P of the fins 108a-b. The epitaxial S / D features 152 can be grown vertically and horizontally to form crystal planes that can correspond to crystal planes of the material used for the substrate 102. In some embodiments, the epitaxial S / D features 152 of the fins 108a-108b and 110a-110b are merged, such as Fig. 6A The epitaxial S / D features 152 may each have a top surface that is higher than the top surface of the first semiconductor layer 104, as shown in FIG. Figure 6B shown.

[0095] exist FIG. 7A to FIG. 7BIn the embodiment of the present invention, a first contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device structure 100. The first CESL 160 covers the sacrificial gate structure 128, the insulating material 112, and the sidewalls of the epitaxial S / D features 152. The first CESL 160 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) 162 is formed on the first CESL 160. The material for the first ILD 162 may include a compound containing silicon (Si), oxygen (O), carbon (C) and / or hydrogen (H), such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, silicon oxide or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials. The first ILD 162 may be deposited by a PECVD process or a FCVD process or other suitable deposition techniques. The first ILD 162 may have a thickness in a range of about 0 nm to 50 nm, such as about 10 nm to about 15 nm. In some embodiments, after forming the first ILD 162, the semiconductor device structure 100 may be thermally treated to anneal the first ILD 162. After forming the first ILD 162, a planarization process is performed to expose the sacrificial gate electrode layer 132. The planarization process may be any suitable process, such as a chemical mechanical polishing or planarization (CMP) process. The planarization process removes the first ILD 162 and a portion of the first CESL 160 disposed on the sacrificial gate structure 128. The planarization process may also remove the mask structure 134.

[0096] exist FIG. 8A to FIG. 8B In the embodiment, the mask structure 134 (if not removed during the previous CMP process), the sacrificial gate electrode layer 132 ( Figure 7B ), and the sacrificial gate dielectric layer 130 ( Figure 7B) is removed. The sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 may be removed by one or more etching processes, such as a dry etching process, a wet etching process, or a combination thereof. The one or more etching processes selectively remove the sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 without substantially affecting the gate spacer 140, the first CESL 160, and the first ILD 162. The removal of the sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 exposes the top portions of the first semiconductor layer 104 and the second semiconductor layer 106 in the channel region (at Fig. 8A Only the first semiconductor layer 104 can be seen in the figure).

[0097] exist 9A to 9C In the embodiment of the present invention, a replacement gate structure 177 is formed. The replacement gate structure 177 may include a gate dielectric layer 166 and a gate electrode layer 167 formed on the gate dielectric layer 166. The gate dielectric layer 166 may include one or more dielectric layers and may include the same material as the sacrificial gate dielectric layer 130.

[0098] In some embodiments, the gate dielectric layer 166 is a high-K dielectric material, such as a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, a metal oxynitride, a metal aluminate, a zirconium silicate, a zirconium aluminate, or any combination of the foregoing. For example, the gate dielectric layer 166 may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), The gate dielectric layer 166 may be a layer of a silicon oxide (e.g., an interfacial layer) and a layer of a high-K material. In some embodiments, the gate dielectric layer 166 may be a layer of a silicon oxide (e.g., an interfacial layer) and a layer of a high-K material. In some embodiments, the gate dielectric layer 166 may be deposited by one or more ALD processes or other suitable processes.

[0099] Depending on the application and / or conductivity type of the devices in the N-type region 102N and the P-type region 102P, the gate electrode layer 167 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), aluminum titanium (AlTi), aluminum titanium oxide (AlTiO), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaSiN), metal alloys, other suitable materials and / or any combination thereof. For the devices in the N-type region 102N, the gate electrode layer 167 may be aluminum titanium oxide (AlTiO), aluminum titanium carbide (AlTiC), aluminum titanium nitride (AlTiN), metal alloys, other suitable materials and / or any combination thereof. For the devices in the N-type region 102N, the gate electrode layer 167 may be aluminum titanium oxide (AlTiO), aluminum titanium carbide (AlTiC), aluminum titanium nitride (AlTiN), or any combination thereof. For the devices in the P-type region 102P, the gate electrode layer 167 may be aluminum titanium oxide (AlTiO), aluminum titanium carbide (AlTiC), aluminum titanium nitride (AlTiN), or any combination thereof. The gate electrode layer 167 may be formed by PVD, CVD, ALD, electroplating or other suitable methods.

[0100] exist FIG. 10A to FIG. 10C , a second contact etch stop layer (CESL) 141 and a second ILD 143 are sequentially formed over the semiconductor device structure 100. The second CESL 141 may be silicon nitride, silicon carbide, silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide, a low-k dielectric (e.g., carbon-doped oxide), an ultra-low-k dielectric (e.g., porous carbon-doped silicon dioxide), or a combination thereof, and may be deposited by CVD, PVD, ALD, a spin-on dielectric process, or a combination thereof. In one embodiment, the second CESL 141 is silicon nitride. The second ILD 143 may include the same material as the first ILD 162 and may be deposited in the same manner as the first ILD 162, as described above with respect to FIG. Fig. 7A as well as Figure 7B In one embodiment, the first ILD 162 is silicon oxide (SiO x In some embodiments, the second CESL 141 may have a thickness in a range of about 0 nm to about 20 nm, such as about 1 nm to about 5 nm, and the second ILD 143 may have a thickness in a range of about 0.1 nm to about 50 nm, such as about 20 nm.

[0101] exist FIG. 11A to FIG. 11CIn the embodiment of the present invention, the second ILD 143, the second CESL 141, the first ILD 162, and the portions of the first CESL 160 disposed on both sides of the replacement gate structure 177 are removed. Portions of the second ILD 143, the second CESL 141, the first ILD 162, and the first CESL 160 are removed to form a contact opening 146 exposing the epitaxial S / D feature 152. In some embodiments, the upper portion of the exposed epitaxial S / D feature 152 is also removed. The contact opening 146 may be formed using an etching process such as dry etching, wet etching, or a combination of the foregoing. The etching process uses an etchant to remove portions of the first ILD 162 and the second ILD 176, the first CESL 160, and the optional epitaxial S / D feature 152. In some embodiments, portions of the gate dielectric layer 166 at and / or adjacent to the L-shaped contact opening 146 may also be removed to expose portions of the gate electrode layer 167.

[0102] The sidewalls of the contact opening 146 may be vertical or inclined. In some embodiments, the contact opening 146 has a sidewall profile in which the size of the top of the contact opening 146 is larger than the size of the bottom of the contact opening 146. In some embodiments, the contact opening 146 may have different shapes in selected areas, for example, the contact opening 146 may be formed to have an extended shape / profile in areas where abutment contacts are to be formed or in areas where the source feature is not large enough and the drain feature size remains small, thereby expanding the contact window for subsequent S / D contacts. In some embodiments, the contact opening 146 is formed so that the contact opening 146 on the first side of the replacement gate structure 177 may have an L-shape, and the contact opening 146 on the second side of the replacement gate structure 177 may be rectangular or square. In an exemplary embodiment, the contact opening 146 between two adjacent replacement gate structures 177 has an L-shaped profile, such as Fig. 11C As shown. The L-shaped contact opening 146 allows the conductive material to be filled therein and form the S / D contact relative to the plan view of the semiconductor device structure. As will be discussed in more detail below, the S / D contact having the L-shaped profile increases the contact window of the epitaxial S / D component 152, and thus increases the contact between the S / D contact and the subsequent abutting contact (179, Fig. 15B ) surface contact area. Fig. 11C In one exemplary embodiment shown, the contact openings 146 between the replacement gate structures 177 have an L-shaped profile relative to a plan view of the semiconductor device structure 100 , and the contact openings 146 adjacent to the replacement gate structures 177 have a rectangular profile relative to a plan view of the semiconductor device structure 100 .

[0103] The contact opening 146 may be formed by a suitable lithography process. The mask used in the lithography process may have various predetermined patterns, such as an L-shaped pattern and a rectangular pattern. The contact openings 146 in different regions may be formed simultaneously or by separate lithography processes. During the lithography process, a patterned mask layer (not shown) may be first formed on the second ILD 143. A removal process such as dry etching, wet etching, or a combination thereof may be performed to remove portions of the second ILD 143, the second CESL 141, the first ILD 162, and the first CESL 160. The removal process may expose a portion of the epitaxial S / D feature 152, such as FIG. 11A to FIG. 11C According to the predetermined pattern in the mask, the removal process can also remove the gate spacer 140 and the gate dielectric layer 166 in the area where the L-shaped contact opening 146 is to be formed, thereby generating L-shaped contact openings, each of which has a first opening 146a with a width W1 and a second opening 146b with a width W2 ( Fig. 11C ). A ratio of the width W1 to the width W2 (W1:W2) may have a range of about 1.5:1 to about 3:1. The contact openings 146 of other regions may have a width W3 that is equal to, greater than, or less than the width W2.

[0104] exist FIG. 12A to FIG. 12CIn the embodiment of the present invention, the conductive component 172 is formed above the epitaxial S / D component 152 in the contact opening 146. The conductive component 172 filled in the L-shaped contact opening 146 forms an L-shaped conductive component 153. The L-shaped conductive component 153 and the conductive component 172 serve as metal contacts (i.e., S / D contacts) of the epitaxial S / D component 152. The L-shaped conductive component 153 and the conductive component 172 may include a conductive material, such as one or more of ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), titanium nitride (TiN), and tantalum nitride (TaN). The L-shaped conductive component 153 and the conductive component 172 may be formed by any suitable process, such as PVD, CVD, ALD, electrochemical plating or other suitable methods. The silicide layer 170 may be formed between the epitaxial S / D component 152 and the L-shaped conductive component 153 and the conductive component 172, respectively. The silicide layer 170 conductively couples the epitaxial S / D feature 152 to the L-shaped conductive feature 153 and the conductive feature 172, respectively. The silicide layer 170 is a metal or metal alloy silicide, and the metal may include a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof. Once the L-shaped conductive feature 153 and the conductive feature 172 are formed, a planarization process such as CMP is performed on the semiconductor device structure 100 until the top surface of the first ILD 162 is exposed. As a result, the top surface 153t of the L-shaped conductive feature 153, the top surface 172t of the conductive feature 172, the top surface 167t of the gate electrode layer 167, and the top surfaces of the gate dielectric layer 166, the gate spacer 140, the CESL 160, and the first ILD 162 are substantially coplanar.

[0105] Each L-shaped conductive component 153 has a first portion 153a with a width W4 and a second portion 153b with a width W5, wherein the width W5 is smaller than the width W4 ( Fig. 12C ). The first portion 153a is disposed toward the replacement gate structure 177 and closer to the replacement gate structure 177 than the second portion 153b. The ratio of the width W4 to the width W5 (W4:W5) may have a width of about 1.5:1 to about 3:1. The conductive feature 172 of other regions may have a width W6 that is equal to, greater than, or less than the width W5.

[0106] In some embodiments, a portion (eg, first portion 153a) of L-shaped conductive component 153 has sidewall 153s directly in contact with gate electrode layer 167. In some embodiments, a portion of L-shaped conductive component 153 is separated from gate electrode layer 167 by gate dielectric layer 166.

[0107] Fig.12DFIG. 1 is an enlarged view of a portion of the structure of the semiconductor device 100 according to some embodiments, showing the structural relationship of the L-shaped conductive component 153 relative to the surrounding film layers. Fig.12D As shown, a portion of the L-shaped conductive feature 153 is in contact with the silicide layer 170, the gate spacer 140, and the gate dielectric layer 166. In some embodiments, the gate spacer 140 is in contact with the L-shaped conductive feature 153, the gate dielectric layer 166, the second semiconductor layer 106, the epitaxial S / D feature 152, and the silicide layer 170. In some embodiments, a first section 153b-1 of a second portion 153b of the L-shaped conductive feature 153 is at a first height, and a second section 153b-2 of the second portion 153b of the L-shaped conductive feature 153 is at a second height lower than the first height. The second section 153b-2 is disposed between the silicide layer 170 and the gate dielectric layer 166 and is in contact with the silicide layer 170 and the gate dielectric layer 166. The top surface of the gate spacer 140 disposed under the L-shaped conductive feature 153 may be at the same or different height as the top surface of the epitaxial S / D feature 152.

[0108] exist FIG. 13A to FIG. 13C , an etch stop layer 145 and a third ILD 178 are sequentially formed over the semiconductor device structure 100. In some embodiments, the etch stop layer 145 is omitted. The etch stop layer 145 may be silicon nitride, silicon carbide, silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide, a low dielectric constant dielectric (such as carbon-doped oxide), an extremely low dielectric constant dielectric (such as porous carbon-doped silicon dioxide), or a combination thereof, and is deposited by CVD, PVD, ALD, a spin-on dielectric process, or the like, or a combination thereof. In one embodiment, the etch stop layer 145 is silicon nitride. The third ILD 178 may include the same material as the first ILD 162 and be deposited in the same manner as the first ILD 162, as described above with respect to FIG. Fig. 7A as well as Figure 7B In the case of using an etch stop layer 145, the etch stop layer 145 may have a thickness in a range of about 0 nm to about 30 nm, such as about 8 nm to about 15 nm. The third ILD 178 may have a thickness in a range of about 0.1 nm to about 80 nm, such as about 10 nm to about 30 nm.

[0109] exist FIG. 14A to FIG. 14C, portions of the third ILD 178 and the etch stop layer 145 (if any) disposed above the L-shaped conductive feature 153 and the conductive feature 172 are removed. Removing portions of the third ILD 178 and the etch stop layer 145 forms an abutment contact opening 148 exposing the L-shaped conductive feature 153 and the gate electrode layer 167. Removing portions of the third ILD 178 and the etch stop layer 145 also forms a via contact opening 149 exposing the conductive feature 172. A patterned layer (not shown) may first be formed on portions of the third ILD 178. The patterned layer has openings (e.g., via contact openings 149) at locations aligned with the epitaxial S / D features 152. The patterned layer also has openings (e.g., via contact openings 149) at locations where the abutment contacts (179, Fig. 16B ) has an opening (e.g., abutment contact opening 148). The abutment contact opening 148 exposes the top surface 153t of the L-shaped conductive contact 153 and the top surface 167t of the gate electrode layer 167. In some embodiments, the abutment contact opening 148 and the via contact opening 149 can be formed together or by separate lithography processes.

[0110] The patterned layer may be used as a mask to perform removal of the third ILD 178 and a portion of the etch stop layer 145 by one or more etching processes (e.g., wet etching, dry etching, or a combination thereof). In one embodiment, a dry etching process such as RIE or other suitable anisotropic etching processes is used to remove the third ILD 178 and a portion of the etch stop layer 145. In an exemplary embodiment, a dry etching process using a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source, or a glow discharge plasma (GDP) source driven by a radio frequency (RF) power generator or a microwave plasma source may be used. The dry etching process may use a plasma formed by a gas mixture containing one or more etchants, such as a bromide-based gas, a chlorine-based gas, a fluorine-based gas, and / or other suitable etching gases. Inert gas such as argon (Ar) may be provided with the etchant to increase the bombardment effect and thus enhance the etching rate of the third ILD 178 and the etch stop layer 145. When forming the abutment contact opening 148 and the via contact opening 149, any suitable process (eg, an ashing process) may be used to remove the patterned layer.

[0111] The sidewalls of the abutment contact opening 148 and the via contact opening 149 may be vertical or inclined. In some embodiments, the abutment contact opening 148 and the via contact opening 149 have a sidewall profile, wherein the size of the abutment contact opening 148 and the via contact opening 149 at the top is larger than the size at the bottom. When viewed from the top, the abutment contact opening 148 may be a circular, rectangular, square, or oval opening. In an exemplary embodiment, the via contact opening 149 is a square opening, and the abutment contact opening 148 is a rectangular opening. In any case, the size of the abutment contact opening 148 is wide enough so that subsequent conductive materials can be deposited in the abutment contact opening 148 without gap filling problems. In some embodiments, the abutment contact opening 148 has a width W7, and the via contact opening 149 has a width W8 that is less than the width W7. The ratio of the width W7 to the width W8 (W7:W8) may have a range of about 2:1 to about 6:1. Width W7 may be in the range of about 10 nanometers to about 120 nanometers, such as about 25 nanometers to about 50 nanometers, depending on the diameters of the L-shaped conductive feature 153 and the gate electrode layer 167. In some embodiments, the exposed top surface 153t of the L-shaped conductive contact 153 may have a width in the range of about 1 nanometer to about 80 nanometers, and the top surface 167t of the gate electrode layer 167 may have a width in the range of about 1 nanometer to about 80 nanometers.

[0112] exist FIG. 15A to FIG. 15C In the embodiment, the abutting contact 179 and the via contact part 180 are formed at the abutting contact opening 148 and the via contact opening 149, respectively. Fig. 14B ). Once the abutment contact 179 and the via contact feature 180 are formed, a planarization process such as CMP is performed on the semiconductor device structure 100 until the top surface of the third ILD 178 is exposed. The abutment contact 179 electrically connects the L-shaped conductive feature 153 (e.g., an S / D contact for the epitaxial S / D feature 152) to the gate electrode layer 167. The via contact feature 180 serves as a metal contact for connecting to the epitaxial S / D feature 152 through an S / D contact (e.g., conductive feature 172). The abutment contact 179 spans across two conductive regions of the semiconductor device structure 100, such as the source / drain region of the first transistor and the gate region of the second transistor. The abutment contact 179 adjoins two conductive regions and can significantly reduce the number of required contacts. The abutment contacts 179 may be used to establish electrical connections to die areas that require high device density, such as embedded static random access memory (SRAM) and dynamic random access memory (DRAM) component areas, thereby reducing die area and enhancing device reliability.

[0113] Each abutting contact 179 has a bottom surface 179b that falls on the top surface 153t of the L-shaped conductive component 153 and the top surface 167t of the gate electrode layer 167, respectively. The bottom surface 179b of the abutting contact 179, the top surface 153t of the L-shaped conductive component 153, and the top surface 167t of the gate electrode layer 167 are coplanar. Similarly, the top surface 179t of the abutting contact 179 is coplanar with the top surface 180t of the via contact component 180. Therefore, the abutting contact 179 is at the same height as the via contact component 180. The abutting contact 179 and the L-shaped conductive component 153 expand the contact surface area of ​​the S / D contact, which results in a reduction in the S / D contact resistance. Furthermore, since the top surface 153 t of the L-shaped conductive member 153 is coplanar with the top surface 167 t of the gate electrode layer 167 , the parasitic capacitance between the L-shaped conductive member 153 and the gate electrode layer 167 is reduced.

[0114] The abutment contact 179 and the via contact feature 180 may include the same material as the conductive feature 172, such as W, Co, Al, platinum (Pt), Ni, silver (Ag), Ru, Cu, Ti, Ta, TiN, TaN, ruthenium cobalt (RuCo), Ru alloy, Cu alloy, W alloy, Mo alloy, or any suitable low resistance (R) metal. In some embodiments, the abutment contact 179 and the via contact feature 180 include materials that are chemically different from each other. In some embodiments, a conductive barrier layer may be provided before forming the abutment contact 179. Thus, the conductive barrier layer contacts the abutment contact 179, the third ILD 178, the optional etch stop layer 145, the L-shaped contact feature 153, the gate dielectric layer 166, and the gate spacer 140. In this case, the barrier layer may include W, Mo, or other suitable materials listed for the abutment contact 179. The barrier layer may include a material that is chemically different from the abutment contact 179. The abutment contact 179 and the via contact 180 may be formed by any suitable process, such as PVD, CVD, ALD, electrochemical plating or other suitable methods. In some embodiments, the via contact 180 and the abutment contact 179 are deposited by different deposition techniques, for example, the via contact 180 may be deposited in a bottom-up manner (e.g., an ALD-based deposition process), and the abutment contact 179 may be deposited by a CVD-based deposition process.

[0115] exist FIG. 16A to FIG. 16BIn the embodiment of the present invention, an interconnect structure 117 is formed above the semiconductor device structure 100. In some embodiments, the interconnect structure 117 includes a plurality of intermetal dielectric (IMD) layers 168a-168n, a plurality of conductive features 169a-169n embedded in the plurality of IMD layers, and a plurality of etch stop layers 171a-171n disposed between ILD layers and IMD layers (e.g., the third ILD 178 and the first IMD layer 168a) and between IMD layers (e.g., the first IMD 168a and the second IMD layer (not shown)). The IMD layers, the conductive features, and the etch stop layers may be repeated until a desired number of IMD layers 168n (e.g., the topmost IMD layer in the interconnect structure 117), a desired number of etch stop layers 171n, and a desired number of conductive features 169n embedded in the IMD layers 168n (e.g., the topmost conductive feature in the interconnect structure 117) are achieved. Conductive features (e.g., conductive vias and conductive lines) may be formed using any suitable formation process (e.g., lithography with etching, damascene, dual damascene, etc.). In some embodiments, the step of forming the conductive features may include forming openings in the corresponding dielectric layers, depositing a conductive layer in the openings, and then performing a planarization process (e.g., a CMP process) to remove excess material where the conductive material overfills the openings. The conductive layer may be deposited by CVD, PVD, sputtering, electroplating, chemical plating, or other suitable deposition techniques.

[0116] The IMD layers 168a-n may include or be formed of any suitable dielectric material, such as silicon oxide, a low dielectric constant (low-k) material, or a combination thereof. The low-k material may include fluorinated silicate glass (FSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), polyimide, SiOxCyHz, or SiOxCy, where x, y, and z are integers or non-integers, and / or other low-k dielectric materials developed in the future. The IMD layers 168a-n may be deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or other suitable deposition techniques. The material of the etch stop layers 171a-n is selected so that the etch rate of the etch stop layers 171a-n is less than the etch rate of the IMD layers 168a-n. In some embodiments, the etch stop layers 171a-n may include the same material as the above-described etch stop layer 145. The conductive vias / lines (e.g., conductive features 169a-n) may include or be formed of any suitable conductive material, such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or a combination of the foregoing.

[0117] In some embodiments, one or more etch stop layers may be omitted. For example, the IMD layer 168a may be in direct contact with the third ILD 178, such as Fig. 16B This may be advantageous in some cases because the etch stop layer has a high dielectric constant and having less etch stop layer can reduce the overall capacitance of the device.

[0118] FIG. 17A to FIG. 17I FIG. 2 is a layout diagram of a portion of a semiconductor device structure 200 according to some alternative embodiments. The semiconductor device structure 200 is substantially the same as the semiconductor device structure 100 except for the proposed arrangement / configuration of the S / D contacts and the abutting contacts. Fig.17A, replacement gate structures 277a, 277b (collectively referred to as replacement gate structures 277) such as replacement gate structure 177 are arranged in parallel along the Y direction. L-shaped conductive components 253a, 253b (collectively referred to as L-shaped conductive components 253) such as L-shaped conductive components 153 are arranged on one side of the corresponding replacement gate structure 277. Each L-shaped conductive component 253 has a first portion 253-1 and a second portion 253-2 protruding from one end of the first portion 253-1. The second portion 253-2 of the L-shaped conductive component 253 is arranged in parallel with respect to the replacement gate structure 277. The first portion 253-1 extends toward the replacement gate structure 277 (e.g., replacement gate structure 277a) and has a square shape. The L-shaped conductive component 253a can be used as an S / D contact of the source / drain component of the first transistor, and the L-shaped conductive component 253b can be used as an S / D contact of the source / drain component of the second transistor. In an exemplary embodiment, the L-shaped conductive features 253a, 253b are symmetrically arranged. The conductive feature 272, such as the conductive feature 172, can be used as an S / D contact, serving as a source / drain feature of a transistor disposed between replacement gate structures 277. The abutment contacts 279a, 279b (collectively referred to as abutment contacts 279) are configured to electrically connect the L-shaped conductive feature 253 to the corresponding replacement gate structure 277, for example, the abutment contact 279a electrically connects the L-shaped conductive feature 253a to the replacement gate structure 277a through the first portion 253-1 of the L-shaped conductive feature 253a, and the abutment contact 279b electrically connects the L-shaped conductive feature 253b to the replacement gate structure 277b through the first portion 253-1 of the L-shaped conductive feature 253b.

[0119] exist Fig. 17B In the embodiment described, Fig.17A The embodiment of FIG. 2 is substantially the same except that the first portion 253 - 1 of the L-shaped conductive member 253 is rounded.

[0120] exist Fig. 17C In the embodiment described, the embodiment is similar to Fig.17A 2 , except that the L-shaped conductive component 253 is replaced by T-shaped conductive components 265a, 265b (collectively referred to as T-shaped conductive components 265). Each T-shaped conductive component 265 has a first portion 265-1 and a second portion 265-2 protruding from the middle of the first portion 265-1. Similarly, the abutment contact 279a electrically connects the T-shaped conductive component 265a to the replacement gate structure 277a through the first portion 265-1 of the T-shaped conductive component 265, and the abutment contact 279b electrically connects the T-shaped conductive component 265b to the replacement gate structure 277b through the first portion 265-1 of the T-shaped conductive component 265b.

[0121] exist Fig.17DIn the embodiment described, the embodiment is similar to Fig. 17C , except that the first portion 265 - 1 of the T-shaped conductive member 265 is a rounded shape.

[0122] exist Fig.17E In the embodiment described, the embodiment is similar to Fig.17A as well as Fig. 17C 1, except that different S / D feature profiles are used. Specifically, an L-shaped conductive feature (e.g., L-shaped conductive feature 253a) and a T-shaped conductive feature (e.g., T-shaped conductive feature 265b) are used as metal contacts (i.e., S / D contacts) of the epitaxial S / D feature 152. In this embodiment, the abutment contact 279a electrically connects the L-shaped conductive feature 253a to the replacement gate structure 277a through the first portion 253-1 of the L-shaped conductive feature 253a, and the abutment contact 279b electrically connects the T-shaped conductive feature 265b to the replacement gate structure 277b through the first portion 265-1 of the T-shaped conductive feature 265b.

[0123] exist Fig.17F In the embodiment described, the embodiment is similar to Fig.17E , except that the first portion 253 - 1 of the L-shaped conductive member 253 is a rounded shape.

[0124] exist Figure 17G In the embodiment described, the embodiment is similar to Fig.17D In this embodiment, the T-shaped conductive features 283a, 283b (collectively referred to as T-shaped conductive features 283) are used as metal contacts (i.e., S / D contacts) for the epitaxial S / D features 152. The T-shaped conductive features 283a, 283b are oriented in the same direction as the epitaxial S / D features 152. Fig.17D The T-shaped conductive components 265a, 265b shown are different. Each T-shaped conductive component 283a, 283b includes a first portion 283-1 and a second portion 283-2 protruding from the middle of the first portion 283-1. The second portion 283-2 of the T-shaped conductive component 283 is arranged in parallel with respect to the replacement gate structure 277. Specifically, the first portion 283-1 has a circular or elliptical profile. Similarly, the abutment contact 279a electrically connects the T-shaped conductive component 283a to the replacement gate structure 277a through the first portion 283-1 of the T-shaped conductive component 283a, and the abutment contact 279b electrically connects the T-shaped conductive component 283b to the replacement gate structure 277b through the first portion 283-1 of the T-shaped conductive component 283b.

[0125] exist Fig.17H In the embodiment described, the embodiment is similar to Fig. 17C as well as Fig.17DIn particular, the T-shaped conductive component (e.g., Fig. 17C The T-shaped conductive component 265a shown) and the T-shaped conductive component (eg, Fig.17D The T-shaped conductive feature 265b is shown as a metal contact (i.e., S / D contact) for the epitaxial S / D feature 152. In this embodiment, the abutment contact 279a electrically connects the T-shaped conductive feature 265a to the replacement gate structure 277a through the first portion 265-1 having a square shape, and the abutment contact 279b electrically connects the T-shaped conductive feature 265b to the replacement gate structure 277b through the first portion 265-1 having a circular shape.

[0126] exist Fig.17I In the embodiment described, the embodiment is similar to Figure 17G as well as Fig.17H The embodiment of the present invention is different in that a different S / D component profile is used. Specifically, a T-shaped conductive component (e.g., Figure 17G The T-shaped conductive component 283a shown) and the T-shaped conductive component (eg, Fig.17D The T-shaped conductive feature 265b shown is used as a metal contact (i.e., S / D contact) of the epitaxial S / D feature 152. In this embodiment, the abutment contact 279a electrically connects the T-shaped conductive feature 283a to the replacement gate structure 277a through the first portion 283-1 having a rounded shape, and the abutment contact 279b electrically connects the T-shaped conductive feature 265b to the replacement gate structure 277b through the first portion 265-1 also having a rounded shape. However, the directions of the T-shaped conductive features 283a, 265b are different from each other.

[0127] 18A to 18C arrive FIG. 24A to FIG. 24B FIG. 3 is a diagram illustrating a semiconductor device structure 300 at various stages of fabrication according to some embodiments. Fig. 15B The embodiment shown, in addition to using rectangular S / D contacts in the areas where abutment contacts are to be formed, is useful when a single patterning process is used to form abutment contacts with small gaps therebetween, which can be challenging for some lithography processes due to the formation of undesirable bridges between abutment contacts. 18A to 18CIn the embodiment of the present invention, after forming the second CESL 141 and the second ILD 143, portions of the second ILD 143, the second CESL 141, the first ILD 162, and the first CESL 160 disposed on both sides of the replacement gate structure 177 are removed. The removal of portions of the second ILD 143, the second CESL 141, the first ILD 162, and the first CESL 160 forms a contact opening 146 exposing the epitaxial S / D component 152. In some embodiments, the upper portion of the exposed epitaxial S / D component 152 is also removed. The contact opening 146 may be formed using an etching process such as dry etching, wet etching, or a combination of the foregoing. Likewise, the sidewalls of the contact opening 146 may be vertical or inclined. When viewed from the top, the contact opening 146 has a rectangular profile and may be formed at one time by any suitable lithography process.

[0128] exist FIG. 19A to FIG. 19C 146, the conductive feature 372 is formed over the epitaxial S / D feature 152 in the contact opening 146. The conductive feature 372 serves as an S / D contact for the epitaxial S / D feature 152. The conductive feature 372 may include the same material as the conductive feature 172. A silicide layer 370, such as a silicide layer 170, may be formed between the S / D epitaxial feature 152 and the conductive feature 372. Once the conductive feature 372 is formed, a planarization process, such as CMP, is performed on the semiconductor device structure 300 until the top surface of the first ILD 162 is exposed. As such, the conductive feature 372, the gate electrode layer 167, the gate dielectric layer 166, the gate spacer 140, the CESL 160, and the top surface of the first ILD 162 are substantially coplanar.

[0129] exist FIG. 20A to FIG. 20C In the embodiment, the etching stop layer 145 and the third ILD 178 are similar to those described above. FIG. 13A to FIG. 13C A similar manner as discussed above is sequentially formed over the semiconductor device structure 300. Thereafter, the third ILD 178 and the portion of the etch stop layer 145 disposed over the conductive feature 372 are removed. The removal of the third ILD 178 and the portion of the etch stop layer 145 forms a via contact opening 349 exposing the conductive feature 372. In the region where the abutting contact is to be formed, the removal of the third ILD 178 and the portion of the etch stop layer 145 forms a first half 348-1 of the abutting contact opening having a width W9 greater than the width W10 of the via contact opening 349. In some embodiments, the width W9 is about 50% to about 70% of the width W12 of the final abutting contact 379 ( Fig. 23B). The first half 348-1 of the abutment contact opening exposes the conductive feature 372, the first ILD 162, the CESL 160, and the gate spacer 140. In some embodiments, the first half 348-1 of the abutment contact opening exposes the conductive feature 372, the first ILD 162, the CESL 160, the gate spacer 140, and the gate electrode layer 167. The via contact opening 349 and the first half 348-1 of the abutment contact opening can be formed simultaneously using any suitable lithography process.

[0130] exist FIG. 21A to FIG. 21C 20B ). Once the first half of the abutment contact 379-1 and the via contact 380 are formed, a planarization process such as CMP is performed on the semiconductor device structure 300 until the top surface of the third ILD 178 is exposed. The first half of the abutment contact 379-1 and the via contact 380 may include the same material as the conductive feature 172. The first half of the abutment contact 379-1 and the via contact 380 may include a conductive material such as one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. In some embodiments, the first half of the abutment contact 379-1 and the via contact 380 include a material that is chemically different from the conductive feature 172.

[0131] exist FIG. 22A to FIG. 22C , a patterned layer 311 is formed on the semiconductor device structure 300. The patterned layer 311 has an opening at a location aligned with the replacement gate structure 177 and adjacent to the first half 379-1 of the abutment contact. An etching process is then performed using the patterned layer 311 as a mask to form a second half 348-2 of the abutment contact opening. The second half 348-2 of the abutment contact opening may have a width W11. The width W11 of the second half 348-2 of the abutment contact opening and the width W9 of the first half 348-1 of the abutment contact opening are substantially equal to the width W12 of the final abutment contact 379 ( Fig. 23B The width W11 may vary according to the width W9 of the first half of the abutment contact opening 348-1. In some embodiments, the width W11 is about 30% to about 50% of the width W12 of the final abutment contact 379 ( Fig. 23B). The second half 348-2 of the abutment contact opening exposes the top surfaces of the CESL 160, the gate spacer 140, the gate dielectric layer 166, and the gate electrode layer 167. In some embodiments, the second half 348-2 of the abutment contact opening exposes the top surfaces of the first ILD 162, the CESL 160, the gate spacer 140, the gate dielectric layer 166, and the gate electrode layer 167. The second half 348-2 of the abutment contact opening may be formed using any suitable lithography process.

[0132] The etching process may be RIE or other suitable anisotropic etching process. The etchant is selective so that it removes the third ILD 178 and a portion of the etch stop layer 145 without substantially removing the first half 379-1 of the abutment contact. When forming the second half 348-2 of the abutment contact opening, any suitable process (e.g., an ashing process) may be used to remove the patterned layer.

[0133] exist FIG. 23A to FIG. 23C , the second half 379-2 of the abutment contact is formed in the second half 348-2 of the abutment contact opening. Once the second half 379-2 of the abutment contact is formed, a planarization process such as CMP is performed on the semiconductor device structure 300 until the top surface of the third ILD 178 is exposed. The second half 379-2 of the abutment contact may include the same material as the conductive feature 372. The second half 379-2 of the abutment contact may include a conductive material such as one or more of W, Co, Al, Pt, Ni, Ag, Ru, Cu, Ti, Ta, TiN, TaN, RuCo, Ru alloy, Cu alloy, W alloy, Mo alloy, or any suitable low-R metal. In some embodiments, the first half 379-1 of the abutment contact and the second half 379-2 of the abutment contact include a material that is chemically different from the conductive feature 372. In some embodiments, the first half 379-1 of the abutment contact and the second half 379-2 of the abutment contact include materials that are chemically different from each other, such as Fig. 23B In some embodiments, the first half 379-1 of the abutting contact member and the second half 379-2 of the abutting contact member include the same material, such as Fig.25Alternative embodiment shown. In some exemplary embodiments, the first half 379-1 of the abutting contact comprises the same material as the conductive component 372, and the second half 379-2 of the abutting contact comprises a different material than the first half 379-1 of the abutting contact. In some exemplary embodiments, the first half 379-1 of the abutting contact comprises a different material than the conductive component 372, and the second half 379-2 of the abutting contact comprises a different material than the first half 379-1 of the abutting contact. In some exemplary embodiments, the first half 379-1 of the abutting contact comprises a different material than the conductive component 372, and the second half 379-2 of the abutting contact comprises the same material as the conductive component 372. In some embodiments, a conductive barrier layer may be provided prior to forming the abutting contact 379.

[0134] In any case, the abutment contact 379, which includes a first half 379-1 of the abutment contact and a second half 379-2 of the abutment contact, electrically connects the conductive component 372 (e.g., an S / D contact for the epitaxial S / D component 152) to the gate electrode layer 167. The via contact component 380 serves as a metal contact for connecting to the epitaxial S / D component 152 through the S / D contact (e.g., the conductive component 372). The abutment contact 379 spans across two conductive regions of the semiconductor device structure 300, such as the source / drain region of the first transistor and the gate region of the second transistor. The abutment contact 379 abuts the two conductive regions and can significantly reduce the number of contacts required.

[0135] The first half 379-1 of the abutment contact has a bottom surface 379-1b that rests on the top surfaces of the conductive feature 372, the CESL 160, the first ILD 162, the gate spacer 140, and the gate dielectric layer 166. The second half 379-2 of the abutment contact has a bottom surface 379-2b that rests on the top surfaces of the gate electrode layer 167, the gate dielectric layer 166, the gate spacer 140, the CESL 160, and optionally the first ILD 162. The bottom surfaces 379-1b, 379-2b of the abutment contact 379 are substantially coplanar with the top surfaces of the conductive feature 372, the CESL 160, the first ILD 162, the gate spacer 140, and the gate dielectric layer 166. Likewise, the via contact feature 380, the first half 379-1 of the abutment contact, and the top surfaces of the second half 379-2 of the abutment contact are substantially coplanar. Therefore, the abutment contact 379 is at the same height as the via contact 380. The abutment contact 379 enlarges the contact surface area of ​​the S / D contact, which in turn reduces the contact resistance of the transistor device. In addition, since the top surface of the conductive component 372 is coplanar with the top surface of the gate electrode layer 167, the parasitic capacitance between the conductive component 372 and the gate electrode layer 167 is reduced.

[0136] exist FIG. 24A to FIG. 24B 1, interconnect structure 317 is formed over semiconductor device structure 300. Interconnect structure 317 may include the same components as interconnect structure 117 and may be formed in the same manner as described above with reference to FIG. FIG. 16A to FIG. 16B Deposition is carried out in a similar manner as discussed above.

[0137] Fig.25 A cross-sectional side view of a semiconductor device structure 400 is shown according to some alternative embodiments. Fig.25 Examples and Fig. 24B The embodiment of the present invention is substantially the same, except that the abutment contact 479 is formed of a single material different from the conductive feature 372. The abutment contact 479 can be formed of the same material as the abutment contact 379 described above. The abutment contact 479 can include a material that is chemically different from the material of the via contact feature 380.

[0138] Fig.26 A cross-sectional side view of a semiconductor device structure 500 is shown according to some alternative embodiments. Fig.26 Examples and Fig. 24B The embodiment of the present invention is substantially the same except that the abutment contact 579 is formed of a single material different from the conductive member 372. The abutment contact 579 can be formed of the same material as the abutment contact 379 described above. The abutment contact 579 can include a material that is chemically the same as the material of the via contact member 380.

[0139] The present disclosure provides a semiconductor device structure with improved S / D contacts and abutment contacts. The S / D contacts and abutment contacts disposed between and in contact with the epitaxial S / D components have an L-shaped profile. The L-shaped S / D contacts and abutment contacts together increase the contact surface area between two conductive regions (e.g., source / drain regions and gate regions) of the semiconductor device structure. In this way, the S / D contact resistance of the semiconductor device structure is reduced. The abutment contact has the same height as the via contact, which is electrically connected to the epitaxial S / D component through the S / D contact. Specifically, the abutment contact has a bottom surface that is coplanar with the top surface of the L-shaped conductive component and the gate electrode, thereby reducing the parasitic capacitance between the S / D contact and the gate contact.

[0140] One embodiment is a semiconductor device structure, the structure comprising a first source / drain feature, a first interlayer dielectric layer disposed above the first source / drain feature, a first conductive feature extending through the first interlayer dielectric layer and in electrical contact with the first source / drain feature, wherein the first conductive feature has an L-shaped profile relative to a plan view of the semiconductor device structure. The structure also includes a gate electrode layer extending through the first interlayer dielectric layer and disposed adjacent to the first conductive feature, wherein a top surface of the first conductive feature is substantially coplanar with a top surface of the gate electrode layer.

[0141] Another embodiment is a semiconductor device structure, the structure including a first source / drain component disposed above a substrate, an abutment contact disposed above the first source / drain component. The abutment contact includes a first portion including a first material and a second portion including a second material. The structure also includes a first conductive component disposed between the first source / drain component and the first portion of the abutment contact, and a gate electrode layer disposed adjacent to the first conductive component and in contact with the second portion of the abutment contact.

[0142] Yet another embodiment is a method of manufacturing a semiconductor device structure, the method comprising providing a first source / drain component and a second source / drain component on opposite sides of a gate structure, forming a first interlayer dielectric layer over the first source / drain component and the second source / drain component, removing portions of the first interlayer dielectric layer to form a first contact opening and a second contact opening, wherein the first contact opening has an L-shaped profile and extends to expose portions of the first source / drain component and the gate structure, and the second contact opening extends to expose portions of the second source / drain component. The method further comprises filling the first contact opening and the second contact opening with a conductive material to form a first conductive component and a second conductive component, respectively, performing a planarization process to make a top surface of the gate structure, a top surface of the first conductive component, and a top surface of the second conductive component substantially coplanar. The method also includes forming a second interlayer dielectric layer above the first interlayer dielectric layer, removing multiple portions of the second interlayer dielectric layer to form abutment contact openings, the abutment contact openings exposing the first conductive component and multiple top surfaces of the gate structure, and filling the abutment contact openings with one or more conductive materials to form abutment contacts.

[0143] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: a first source / drain component; a first interlayer dielectric layer disposed above the first source / drain feature; a first conductive member extending through the first interlayer dielectric layer and in electrical contact with the first source / drain member, wherein the first conductive member has an L-shaped profile relative to a plan view of the semiconductor device structure; and a gate electrode layer extending through the first interlayer dielectric layer and disposed adjacent to the first conductive component, A top surface of the first conductive component and a top surface of the gate electrode layer are substantially coplanar.

2. The semiconductor device structure according to claim 1, wherein: Also includes: a second interlayer dielectric layer disposed above the first interlayer dielectric layer; and An abutting contact has a top surface and a bottom surface, the abutting contact extends through the second interlayer dielectric layer and contacts the top surface of the first conductive component and the top surface of the gate electrode layer.

3. The semiconductor device structure according to claim 2, wherein: The bottom surface of the abutting contact, the top surface of the first conductive component, and the top surface of the gate electrode layer are substantially coplanar.

4. The semiconductor device structure according to claim 1, wherein: The first conductive component includes a first portion having a first width and a second portion having a second width, wherein the second width is smaller than the first width.

5. The semiconductor device structure according to claim 4, wherein: The first portion is disposed closer to the gate electrode layer than the second portion.

6. The semiconductor device structure according to claim 4, wherein: The first portion of the first conductive component is in direct contact with the gate electrode layer.

7. The semiconductor device structure according to claim 4, wherein: Also includes: A gate dielectric layer is disposed between the first portion of the first conductive component and the gate electrode layer, and the gate dielectric layer is in direct contact with the first portion of the first conductive component and the gate electrode layer.

8. A semiconductor device structure, characterized in that: include: a first source / drain component disposed above a substrate; An abutting contact is disposed above the first source / drain component, the abutting contact comprising: a first part, comprising a first material; and a second part, comprising a second material; a first conductive component disposed between the first source / drain component and the first portion of the abutting contact; and A gate electrode layer is disposed adjacent to the first conductive component and contacts the second portion of the abutting contact.

9. The semiconductor device structure according to claim 8, wherein: Also includes: a second source / drain component; a via contact component disposed on the second source / drain component; as well as A second conductive component is disposed between the second source / drain component and the via contact component, wherein a top surface of the via contact component and a top surface of the abutting contact are substantially coplanar.

10. The semiconductor device structure according to claim 8 or 9, characterized in that: The abutting contact has a bottom surface that is coplanar with a top surface of the first conductive component and a top surface of the gate electrode layer.

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