Semiconductor die package

Abstract

The utility model provides a semiconductor tube core packaging piece. Some embodiments described herein provide an inductor device formed in a substrate of a semiconductor device, including an integrated circuit device. The inductor device may use one or more conductor layers included in the substrate. Further, the inductor device may be electrically coupled to the integrated circuit device. By forming an inductor device in a substrate of a semiconductor device, a circuit including the inductor device and an integrated circuit device can be formed within a single semiconductor device.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor die package. Background Art

[0002] Various semiconductor device packaging techniques may be used to incorporate one or more semiconductor dies into a semiconductor die package. In some cases, semiconductor dies may be stacked in a semiconductor die package to achieve a smaller horizontal or lateral footprint of the semiconductor die package and / or to increase the density of the semiconductor die package. Semiconductor device packaging techniques may be performed to integrate multiple semiconductor dies into a semiconductor die package, and the semiconductor device packaging techniques may include integrated fan-out (InFO), package-on-package (PoP), chip-on-wafer (CoW), wafer-on-wafer (WoW), and / or chip-on-wafer-on-substrate (CoWoS), among other examples. Utility Model Content

[0003] According to some embodiments of the present disclosure, a semiconductor die package includes a substrate region, the substrate region includes a first side and a second side opposite to the first side. The semiconductor die package includes an interconnect region, the interconnect region is above the first side of the substrate region and includes at least one metal layer. The semiconductor die package includes a redistribution region, the redistribution region is above the second side of the substrate region and includes at least one conductive layer. The semiconductor die package includes at least two through-hole structures, the two through-hole structures pass through the substrate region to connect the conductive layer in the redistribution region and at least one metal layer in the interconnect region, wherein the at least two through-hole structures, the conductive layer and the metal layer form an inductor.

[0004] According to some other embodiments of the present disclosure, a semiconductor die package includes a first semiconductor die, the first semiconductor die including a substrate region, an interconnection region above the substrate region, a via structure passing through the substrate region, and an inductor including a portion formed in the substrate region. The semiconductor die package includes a second semiconductor die bonded to the interconnection region of the first semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0007] Figure 2A and Figure 2B is a diagram of an example voltage regulator circuit including an inductor described herein;

[0008] FIG. 3A to FIG. 3D is a diagram of an example implementation of an example semiconductor die package described herein;

[0009] 4A to 4H is a diagram of an example implementation of forming a semiconductor die package described herein;

[0010] Figure 5A and Figure 5B is a diagram of an example implementation of an example semiconductor die package described herein;

[0011] FIG. 6A to FIG. 6D is a diagram of an example implementation of an example solenoid inductor structure described herein;

[0012] 7A to 7D is a diagram of an example implementation of a circuit including an example solenoid inductor structure described herein;

[0013] Figure 8 is a graph of an example transient response of a semiconductor die package including a solenoidal inductor structure described herein;

[0014] Fig. 9 This article describes Figure 1 diagrams of example elements of one or more devices;

[0015] Fig.10 is a flow chart of an example process associated with forming the semiconductor die packages described herein. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not restrictive. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first and second features are formed in a direct joint, and may also include an embodiment in which additional features may be formed between the second feature, so that the first and second features may not be in a direct joint. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] In some cases, the circuit includes a combination of devices. For example, the circuit may include a voltage regulator device and an inductor device. The voltage regulator device may be included as part of a semiconductor device, and the inductor device may be included as part of a discrete device that is different and separate from the semiconductor device. In this case, and due to the length of the electrical path between the inductor device and the voltage regulator device, the performance of the circuit (e.g., parasitic resistance and / or transient response) may not meet the threshold. Additionally or alternatively, the design characteristics of the circuit (e.g., space consumption due to the combination of the discrete device and the semiconductor device) may not meet the sizing threshold.

[0019] Some embodiments described herein provide an inductor device formed in a substrate of a semiconductor device, the semiconductor device including an integrated circuit device. The inductor device may use one or more conductor layers included in the substrate. In addition, the inductor device may be electrically coupled to the integrated circuit device. By forming the inductor device in the substrate of the semiconductor device, a circuit including the inductor device and the integrated circuit device may be formed within a single semiconductor device. Additionally or alternatively, the design characteristics of the circuit (e.g., space consumption due to the combination of a discrete device and a semiconductor device) may not meet the size setting threshold.

[0020] As such, the length of the electrical path between the inductor device and the integrated circuit device may be shortened relative to an implementation of the circuit using a discrete inductor device, thereby improving the performance of the circuit. Additionally or alternatively, including the inductor device within the semiconductor device may eliminate the need for a separate semiconductor die package (for the discrete inductor device) to reduce the amount of resources (semiconductor processing tools, raw materials, manpower and / or computing resources, among other examples) used to form the circuit.

[0021] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown, the example environment 100 may include a plurality of semiconductor processing tools (102 to 114) and a wafer / die transport tool 116. The plurality of semiconductor processing tools (102 to 114) may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a bonding tool 114, and / or other semiconductor processing tools. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among others.

[0022] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced chemical vapor deposition (PECVD) tool, a high-density plasma chemical vapor deposition (HDP-CVD) tool, a sub-atmospheric chemical vapor deposition (SACVD) tool, a low-pressure chemical vapor deposition (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form a layer and / or a region of a device by epitaxial growth. In some embodiments, the example environment 100 includes multiple types of deposition tools 102 .

[0023] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0024] The developing tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0025] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma assisted etching to etch one or more portions in the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0026] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing) to polish or planarize the surface of a semiconductor device. The planarization tool 110 may use abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and fixed in place by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and flatten any irregular topography of the semiconductor device to make the semiconductor device flat or planar.

[0027] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0028] The bonding tool 114 is a semiconductor processing tool capable of bonding two or more workpieces (e.g., two or more semiconductor substrates, two or more semiconductor devices, two or more semiconductor dies) together. For example, the bonding tool 114 may include a direct bonding tool. A direct bonding tool is a bonding tool configured to directly bond semiconductor dies together by copper to copper (or other direct metal) connection. As another example, the bonding tool 114 may include a eutectic bonding tool capable of forming a eutectic bond between two or more wafers. In these examples, the bonding tool 114 may heat two or more wafers to form a eutectic system between the materials of the two or more wafers.

[0029] The wafer / die transport 116 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and / or another type of device that is configured to transfer substrates and / or semiconductor devices between semiconductor processing tools (102 to 114), to transfer substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or to transport substrates and / or semiconductor devices to and from other locations such as wafer racks, storage rooms, and / or the like. In some embodiments, the wafer / die transport 116 can be a programmed device that is configured to travel a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer / die transports 116.

[0030] For example, the wafer / die transport vehicle 116 may be included in a cluster tool or another type of tool that includes multiple processing chambers; the wafer / die transport vehicle 116 may be configured to transfer substrates and / or semiconductor devices between multiple processing chambers, to transfer substrates and / or semiconductor devices between a processing chamber and a buffer, to transfer substrates and / or semiconductor devices between a processing chamber and a buffer, to transfer substrates and / or semiconductor devices between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or to transfer substrates and / or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), to name a few examples. In some embodiments, the wafer / die transport 116 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-clean process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport 116 is configured to transfer substrates and / or semiconductor devices between process chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the process chambers and / or between process operations in the deposition tool 102.

[0031] In some embodiments, one or more semiconductor processing tools (102 to 114) and / or wafer / die transport tools 116 may perform a series of semiconductor processing operations described herein. The series of semiconductor processing operations includes etching two or more first holes through the back side of a silicon substrate or semiconductor die to expose a conductive layer in an interconnect region of the semiconductor die. The series of semiconductor processing operations includes depositing a first conductive material in the two or more first holes to form two or more back-side through silicon via structures connected to the conductive layer. The series of semiconductor processing operations includes depositing one or more dielectric redistribution layers of a redistribution region on the back side of the silicon substrate. The series of semiconductor processing operations includes etching two or more second holes through the one or more dielectric redistribution layers to expose two or more back-side through silicon via structures. The series of semiconductor processing operations includes depositing a second conductive material that fills the two or more second holes and electrically couples the two or more back-side through silicon via structures to form an inductor.

[0032] Figure 1 The number and arrangement of devices shown are provided as one or more examples. Figure 1 There may be more devices, fewer devices, different devices, or devices arranged differently than shown. Figure 1 Two or more of the devices shown may be implemented in a single device, or Figure 1 The single device shown may be implemented as multiple distributed devices. Additionally or alternatively, one set of devices (eg, one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0033] Figure 2A and Figure 2B Included are implementations of an example voltage regulator circuit 200 that includes the inductor described herein. Figure 2A and Figure 2B May correspond to embodiments of voltage regulator circuits that may be included in semiconductor die packages described herein.

[0034] exist Figure 2A In the embodiment of the present invention, the voltage regulator circuit may include an example of a synchronous buck converter, which is a switch mode power converter. The voltage regulator circuit 200 may be used as a power supply circuit, a battery charging circuit, and / or another type of circuit in which direct current to direct current (DC:DC) conversion (e.g., buck conversion or boost conversion) may be provided by the voltage regulator circuit 200.

[0035] As shown in FIG. 2 , the voltage regulator circuit 200 may include an inductor 202 (e.g., an output inductor of the voltage regulator circuit 200 ), a capacitor 204 (e.g., an output capacitor of the voltage regulator circuit 200 ), a plurality of transistors (e.g., a high-side transistor 206 and a low-side transistor 208 ), and a pulse width modulation (PWM) circuit 210 , among other things.

[0036] Inductor 202 and capacitor 204 can be electrically connected in series as an inductor-capacitor (LC) filter of voltage regulator circuit 200. The LC filter can provide current charging and current discharging across a load at output terminal 212 (e.g., Vout) in a regulated manner. The load can be electrically connected in series to capacitor 204 at output terminal 212 and electrical ground terminal 214.

[0037] The high-side transistor 206 and the low-side transistor 208 can each include a bipolar transistor (BJT), a field effect transistor (FET), a metal oxide semiconductor FET (MOSFET) and / or another type of transistor. The high-side transistor 206 and the low-side transistor 208 can be electrically connected in series. The first source / drain terminal of the high-side transistor 206 can be electrically connected to the input terminal 216, and the input terminal 216 is connected to the voltage source. The second source / drain terminal of the high-side transistor 206 can be electrically connected to the first source / drain terminal of the low-side transistor 208 and the terminal of the inductor 202. The first source / drain terminal of the low-side transistor 208 can be electrically connected to the second source / drain terminal of the high-side transistor 206 and the terminal of the inductor 202. The second source / drain terminal of the low-side transistor 208 can be electrically connected to the electrical ground terminal 214.

[0038] The gate terminals of high-side transistor 206 and low-side transistor 208 may each be electrically connected to PWM circuit 210. PWM circuit 210 may include circuitry configured to synchronize switching operations of high-side transistor 206 and low-side transistor 208 to enable voltage regulator circuit 200 to provide a regulated output voltage to a load.

[0039] In operation, during the period when the high-side transistor 206 is turned on by the PWM circuit 210, current is provided to the load at the output terminal 212 through the high-side transistor 206. The low-side transistor 208 is turned off, which enables the LC filter of the voltage regulator circuit 200 to charge. When the PWM circuit 210 turns off the high-side transistor 206 and turns on the low-side transistor 208, the LC filter is discharged through the output terminal 212.

[0040] exist Figure 2B In the embodiment, the voltage regulator circuit includes a logic circuit 218 and a switch device 222. In some embodiments, the switch device 222 corresponds to a transistor device. Figure 2BAs shown, the voltage regulator circuit 200 includes a capacitor 204a and a capacitor 204b. In some embodiments, the capacitor 204a corresponds to a deep trench capacitor. Additionally or alternatively, in some embodiments, the capacitor 204b corresponds to a deep trench capacitor.

[0041] Figure 2B The voltage regulator circuit also includes an inductor 202. In some embodiments, and as shown in conjunction with FIG. Fig.10 As described in greater detail elsewhere herein, the inductor 202 can correspond to a solenoidal inductor structure. In some implementations, the inductor includes a magnetic core 224 .

[0042] As mentioned above, Figure 2A and Figure 2B Provided as examples. Other examples may differ from the Figure 2A and Figure 2B as described.

[0043] FIG. 3A to FIG. 3D is a diagram of an example implementation of an example semiconductor die package 300 described herein. The semiconductor die package 300 includes examples of a wafer-on-wafer (WoW) semiconductor die package, a chip-on-wafer (CoW) semiconductor die package, a die-to-die direct bonded semiconductor die package, or another semiconductor die package in which semiconductor dies are directly bonded and vertically arranged or stacked.

[0044] like Figure 3A As shown, semiconductor die package 300 includes a first semiconductor die 302 and a second semiconductor die 304. In some implementations, semiconductor die package 300 includes additional semiconductor dies. First semiconductor die 302 may include an inductor-capacitor (LC) semiconductor die, which is a semiconductor die including a combination of an inductor structure and a capacitor structure, the inductor structure and the capacitor structure corresponding to inductor 202 and capacitor 204 of voltage regulator circuit 200 included in semiconductor die package 300. Second semiconductor die 304 may include a logic semiconductor die, such as a system on chip (SoC) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, and / or an application specific integrated circuit (ASIC) chip, among other examples. Additionally or alternatively, first semiconductor die 302 may include a memory die, an input / output (I / O) die, a pixel sensor die, and / or another type of semiconductor die. The memory die may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a NAND die, a high bandwidth memory (HBM) die, and / or another type of memory die.

[0045] The first semiconductor die 302 and the second semiconductor die 304 can be connected together (e.g., directly bonded) at the bonding interface 306. In some embodiments, one or more layers can be included between the first semiconductor die 302 and the second semiconductor die 304 at the bonding interface 306, such as one or more passivation layers, one or more bonding films, and / or one or more layers of another type.

[0046] The first semiconductor die 302 may include a device region 308 (e.g., a substrate region) and an interconnect region 310 adjacent to and / or above the device region 308. In some embodiments, the first semiconductor die 302 may include an additional region. Similarly, the second semiconductor die 304 may include a device region 312 and an interconnect region 314 adjacent to and / or below the device region 312. In some embodiments, the second semiconductor die 304 may include an additional region. The first semiconductor die 302 and the second semiconductor die 304 may be combined at the interconnect region 310 and the interconnect region 314. The bonding interface 306 may be located at a first side of the interconnect region 314 facing the interconnect region 310 and corresponding to a first side of the second semiconductor die 304.

[0047] The device region 308 may be formed in or on a substrate 316. The substrate 316 may correspond to a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium substrate (Ge), a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0048] The device region 308 may include one or more other components of the voltage regulator circuit 200. For example, a trench capacitor structure 318 may be included in the device region 308 of the first semiconductor die 302. The trench capacitor structure 318 may correspond to the capacitor 204 of the LC filter of the voltage regulator circuit 200. Liners may be included between the trench capacitor structure 318 and the substrate in the device region 308 to prevent electron migration into the device region 308, to prevent metal diffusion into the device region 308, and / or to promote adhesion between the device region 308 and the trench capacitor structure 318.

[0049] The device region 312 may be formed in or on a substrate 320. The substrate 320 may correspond to a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium substrate (Ge), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0050] The device region 312 may include one or more integrated circuit devices 322 included in a semiconductor substrate of the device region 312. The integrated circuit devices 322 may include one or more semiconductor transistor structures (e.g., planar transistor structures, fin field effect transistor (FinFET) transistor structures, nanosheet transistor structures (e.g., gate-all-around (GAA) transistor structures), memory cells, pixel sensors, controller circuits, logic circuits, and / or other types of semiconductor devices. In some implementations, at least a subset of the integrated circuit devices 322 may be included in the voltage regulator circuit 200 of the semiconductor die package 300. For example, one integrated circuit device 322 may correspond to a high-side transistor 206 of the voltage regulator circuit 200, another integrated circuit device 322 may correspond to a low-side transistor 208 of the voltage regulator circuit 200, and one or more other integrated circuit devices 322 may correspond to a PWM circuit 210 of the voltage regulator circuit 200. The voltage regulator circuit 200 may be configured to provide voltage regulation to the other integrated circuit devices 322 of the second semiconductor die 304.

[0051] Interconnect region 310 and interconnect region 314 may be referred to as a back-end of line (BEOL) region. Interconnect region 310 may include one or more dielectric layers 324, which may include silicon nitride (SiNx), an oxide (e.g., silicon oxide (SiOx) and / or another oxide material), a low dielectric constant (low-k) dielectric material, and / or another type of dielectric material. In some embodiments, one or more etch stop layers (ESLs) may be included between layers of one or more dielectric layers 324. One or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and / or silicon oxide (SiOx), among other examples.

[0052] The interconnect region 310 may also include a metallization layer 326 and a metallization layer 328 in one or more dielectric layers 324. The trench capacitor structure 318 in the device region 308 may be electrically and / or physically connected to the metallization layer 326. The metallization layer 326 and the metallization layer 328 may include conductive lines, trenches, vias, pillars, interconnects, and / or another type of metallization layer.

[0053] The contacts 330 may be included in one or more dielectric layers 324 of the interconnect region 310. The contacts 330 may be electrically and / or physically connected to one or more metallization layers 328. The contacts 330 may include conductive terminals, conductive pads, conductive pillars, and / or another type of contacts. The metallization layers 326, the metallization layers 328, and the contacts 330 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more metal alloys, one or more conductive ceramics, and / or another type of conductive material.

[0054] The interconnect region 314 may include one or more dielectric layers 332, which may include silicon nitride (SiNx), an oxide (e.g., silicon oxide (SiOx) and / or another oxide material), a low dielectric constant (low-k) dielectric material, and / or another type of dielectric material. In some embodiments, one or more etch stop layers (ESLs) may be included between layers of the one or more dielectric layers 332. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and / or silicon oxide (SiOx), among other examples.

[0055] The interconnect region 314 may further include a metallization layer 334 in one or more dielectric layers 332. The metallization layer 334 may include a conductive line, a trench, a via, a pillar, an interconnect, and / or another type of metallization layer. In some implementations, the metallization layer 334 is connected to the integrated circuit device 322 in the device region 312.

[0056] The contacts 336 may be included in one or more dielectric layers 332 of the interconnect region 314. The contacts 336 may be electrically and / or physically connected to the one or more metallization layers 334.

[0057] The contact 336 may include a conductive terminal, a conductive pad, a conductive column, and / or another type of contact. The metallization layer 334 and the contact 336 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0058] In some embodiments, and as Figure 3AAs shown, contacts 336 and contacts 330 are combined (e.g., bonded) within bonding interface 306. In such implementations, contacts 336 and contacts 330 provide electrical connections between metallization layer 328 and metallization layer 334. In some embodiments, the bonding interface includes metal-to-metal and dielectric-to-dielectric bonding. In these embodiments, contacts 330 and contacts 336 and corresponding surfaces of one or more dielectric layers 332 and dielectric layer 334 can be bonded by a eutectic bonding process. In addition, in these embodiments, the bonding of contacts 330 and contacts 336 can correspond to metal-to-metal bonding.

[0059] like Figure 3A As further shown, semiconductor die package 300 may include a redistribution region 338. Redistribution region 338 may include a redistribution layer (RDL) structure and / or another type of redistribution region. Redistribution region 338 may be configured to fan out and / or route signals and I / Os of semiconductor die (302 and 304).

[0060] The redistribution region 338 may include one or more dielectric layers 340 and one or more metallization layers 342 disposed in the one or more dielectric layers 340. The one or more dielectric layers 340 may include silicon nitride (SiNx), an oxide (e.g., silicon oxide (SiOx) and / or another oxide material), a low dielectric constant (low-k) dielectric material, and / or another suitable dielectric material.

[0061] The one or more metallization layers 342 in the redistribution area 338 may include one or more of gold (Au) material, copper (Cu) material, silver (Ag) material, nickel (Ni) material, tin (Sn) material, and / or palladium (Pd) material, etc. The one or more metallization layers 342 in the redistribution area 338 may include metal lines, vias, interconnections, and / or another type of metallization layer.

[0062] An under bump metallization (UBM) layer 344 may be included on the top surface of the one or more dielectric layers 340 in the redistribution area 338. The UBM layer 344 may be electrically and / or physically connected to the one or more metallization layers 342 in the redistribution area 338. The UBM layer 344 may be contained in a recess in the top surface of the one or more dielectric layers 340. The UBM layer 344 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more metal alloys, one or more conductive ceramics, and / or another type of conductive material.

[0063] like Figure 3AAs further shown, the semiconductor die package 300 may include a conductive terminal 346. The conductive terminal 346 may be electrically and / or physically connected to the UBM layer 344. The UBM layer 344 may be included to facilitate adhesion to one or more metallization layers 342 in the redistribution area 338, and / or to provide increased structural rigidity to the conductive terminal 346 (e.g., by increasing the surface area to which the conductive terminal 346 is connected). The conductive terminal 346 may include a ball grid array (BGA) ball, a land grid array (LGA) pad, a pin grid array (PGA) pin, and / or other types of conductive terminals. The conductive terminal 346 may enable the semiconductor die package 300 to be mounted to a circuit board, a socket (e.g., an LGA socket), an interposer, or a redistribution area of ​​a semiconductor die package (e.g., a substrate CoWoS package, a chip on wafer on an integrated fan-out (InFO) package), and / or other types of mounting structures.

[0064] like Figure 3A As further shown in FIG. 1 , the semiconductor die package 300 may include one or more backside through silicon via (BTSV) structures 348 that pass through the device region 308. The one or more BTSV structures 348 may include vertically elongated conductive structures (e.g., conductive pillars, conductive vias) that electrically connect one or more metallization layers 326 in the interconnect region 310 of the first semiconductor die 302 to one or more metallization layers 342 in the redistribution region 338. The BTSV structures 348 may be referred to as through silicon via (TSV) structures because the BTSV structures 348 extend completely through the silicon substrate (e.g., the substrate 316 of the device region 308), as opposed to extending completely through a dielectric layer or an insulator layer. The one or more BTSV structures 348 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more metal alloys, one or more conductive ceramics, and / or another type of conductive material.

[0065] The magnetic core structure 350 may be between two or more interconnect structures (e.g., interconnect structures of the BTSV structure 348). The magnetic core structure 350 may include one or more magnetic materials, such as iron (Fe) material, cobalt (Co) material, nickel (Ni) material, cobalt-iron (CoFe) alloy material, nickel-cobalt (NiCo) alloy material, nickel-iron (NiFe) alloy material, nickel-cobalt-iron (NiCoFe) alloy material, one or more metals, one or more metal alloys, and / or another type of magnetic material.

[0066] In some implementations, one or more BTSV structures 348, portions of metallization layer 326, and portions of metallization layer 342 form a solenoidal inductor structure 352. Solenoid inductor structure 352 may correspond to inductor 202 of the LC filter of voltage regulator circuit 200.

[0067] As combined FIG. 4A to FIG. 8 As described in more detail elsewhere herein, current 354 can flow through solenoid inductor structure 352 to generate an inductance in a circuit (e.g., voltage regulator circuit 200). In some embodiments, and by way of example, the inductance performance of solenoid inductor structure 352 is included in a range of about 0.1 nanohenry (nH) to about 100 nH. If the inductance performance is less than about 0.1 nH, solenoid inductor structure 352 may be incompatible with the circuit of semiconductor die package 300 (e.g., voltage regulator circuit 200). If the inductance performance is greater than about 100 nH, solenoid inductor structure 352 may also be incompatible with the circuit of semiconductor die package 300. Additionally or alternatively, if the inductance performance is greater than about 100 nH, the size of solenoid inductor structure 352 may increase to consume space of semiconductor die package 300 and increase the cost of semiconductor die package 300. However, other values ​​and ranges of inductance properties are also within the scope of the present disclosure.

[0068] Figure 3B An example embodiment of a semiconductor die package 300 is shown in which a magnetic core structure 350 partially passes through a substrate 316. Figure 3B As shown, the top surface of the core structure 350 can be aligned with the top surface of the substrate 316. This configuration of the core structure 350 (e.g., the core structure 350 partially passes through the substrate 316, and the corresponding top surfaces are aligned) can be implemented to center the core structure 350 between the metallization layer 326 and the metallization layer 342 to improve the performance of the solenoidal inductor structure 352.

[0069] Figure 3C An example embodiment of a semiconductor die package 300 is shown in which a magnetic core structure 350 partially passes through a substrate 316. Figure 3C As shown, the bottom surface of the core structure 350 can be aligned with the bottom surface of the substrate 316. This configuration of the core structure 350 (e.g., the core structure 350 partially passes through the substrate 316, and the respective bottom surfaces are aligned) can be implemented to center the core structure 350 between the metallization layer 326 and the metallization layer 342, thereby improving the performance of the solenoidal inductor structure 352.

[0070] Figure 3D3 shows an example implementation of a semiconductor die package 300 in which a UBM layer 344 is distributed over multiple metallization layers within a redistribution region 338. FIG. 3A to FIG. 3C The UBM layer 344 is shown distributed across a single layer. Such distribution of the UBM layer 344 across multiple metallizations may reduce inductance within the semiconductor die package 300 .

[0071] like FIG. 3A to FIG. 3D As shown, a semiconductor die package (e.g., semiconductor die package 300) includes a substrate region (e.g., substrate 316), the substrate region including a first side and a second side opposite to the first side. The semiconductor die package includes an interconnect region (e.g., interconnect region 310) above the first side of the substrate region, the interconnect region including at least one metal layer (e.g., metallization layer 326). The semiconductor die package includes a redistribution region (e.g., redistribution region 338), the redistribution region is above the second side of the substrate region and includes at least one conductive layer (e.g., metallization layer 342). The semiconductor die package includes at least two through-hole structures (e.g., BTSV structure 348), the at least two through-hole structures pass through the substrate region to connect the conductive layer in the redistribution region and at least one metal layer in the interconnect region, wherein the at least two through-hole structures, the conductive layer, and the metal layer form an inductor (e.g., solenoid inductor structure 352).

[0072] Additionally or alternatively, a semiconductor die package (e.g., semiconductor die package 300) includes a first semiconductor die (e.g., first semiconductor die 302) including a base region (e.g., base 316), an interconnect region (e.g., interconnect region 310) above the base region, a through-via structure (e.g., one of BTSV structures 348) passing through the base region, and an inductor (e.g., solenoid inductor structure 352) including a portion formed in the base region. The semiconductor die package includes a second semiconductor die (e.g., second semiconductor die 304) bonded to the interconnect region of the first semiconductor die.

[0073] supply FIG. 3A to FIG. 3D The number and arrangement of the devices shown in the figure are provided as one or more examples. FIG. 3A to FIG. 3D There may be more devices, fewer devices, different devices, or differently arranged devices than those shown in . FIG. 3A to FIG. 3D Two or more of the devices shown may be implemented in a single device, or FIG. 3A to FIG. 3D The single device shown may be implemented as multiple distributed devices. Additionally or alternatively, FIG. 3A to FIG. 3D A set of devices (e.g., one or more devices) may perform the steps described as being performed by FIG. 3A to FIG. 3D One or more functions performed by another set of devices.

[0074] 4A to 4H is a diagram of an example implementation 400 of forming a semiconductor die package described herein. In some implementations, example implementation 400 includes an example process for forming first semiconductor die 302, second semiconductor die 304, or portions thereof. In some implementations, one or more of the semiconductor processing tools (102 to 114) and / or wafer / die transport tool 116 may perform one or more of the operations described in connection with example implementation 400. In some implementations, one or more of the operations described in connection with example implementation 400 may be performed by another semiconductor processing tool.

[0075] Steering Figure 4A , the trench capacitor structure 318 is formed as a portion of the device region 308. For example, one or more of the semiconductor processing tools (102-114) may perform a photolithography patterning operation, an etching operation, a deposition operation, a CMP operation, and / or another type of operation to form the trench capacitor structure 318 in the substrate 316.

[0076] like Figure 4B As shown, dielectric layer 324, metallization layer 326, metallization layer 328, and contact 330 are formed as part of interconnect region 310 (e.g., interconnect region 310 above the device region). For example, one or more of the semiconductor processing tools (102 to 114) can perform a photolithography patterning operation, an etching operation, a deposition operation, a CMP operation, and / or another type of operation to form dielectric layer 324, metallization layer 326, metallization layer 328, and contact 330 as part of interconnect region 310.

[0077] like Figure 4C As shown, a second semiconductor die 304 is formed and bonded to the first semiconductor die 302. For example, as part of forming the second semiconductor die 304, one or more of the semiconductor processing tools (102 to 114) can perform a photolithography patterning operation, an etching operation, a deposition operation, a CMP operation, and / or another type of operation to form a device region 312. Such operations can include forming an integrated circuit device 322 on or within a substrate 316. Additionally or alternatively, as part of forming the second semiconductor die 304, one or more of the semiconductor processing tools (102 to 114) can perform a photolithography patterning operation, an etching operation, a deposition operation, a CMP operation, and / or another type of operation to form an interconnect region 314. Such operations can include forming a dielectric layer 332, a metallization layer 334, and / or a contact 336. Furthermore, as Figure 4C As shown, the bonding tool 114 may bond the first semiconductor die 302 and the second semiconductor die 304 at a bonding interface 306 .

[0078] Steering Figure 4D , forming the cavity 402 in the first semiconductor die 302. For example, one or more of the one or more semiconductor processing tools (102-114) may perform a photolithography patterning operation, an etching operation, and / or another type of operation to form the cavity 402 in the device region 312.

[0079] like Figure 4E As shown, a magnetic layer 404 is formed on the first semiconductor die 302. For example, as part of forming the first semiconductor die 302, one or more of the semiconductor processing tools (102-114) may perform a deposition operation, a CMP operation, and / or another type of operation to form the magnetic layer 404 on the first semiconductor die 302. Forming the magnetic layer 404 on the first semiconductor die 302 may include filling the voids 402 in the device region 308.

[0080] Figure 4F The formation of the magnetic core structure 350 is shown. For example, one or more of the semiconductor processing tools (102-114) can perform an etching operation, a CMP operation, and / or another type of operation to remove a portion of the magnetic layer 404 on the surface of the first semiconductor die 302 (e.g., excluding other portions that fill the void 402) and form the magnetic core structure 350 in the device region 312.

[0081] like Figure 4G As shown, a BTSV structure 348 is formed through the device region 308 and into the interconnect region 310. For example, one or more of the semiconductor processing tools (102-114) may perform a photolithography patterning operation, an etching operation, a deposition operation, a CMP operation, and / or another type of operation as part of forming the BTSV structure 348. For example, as part of forming the BTSV structure 348, the etching tool 108 may etch two or more holes through the back side of the silicon substrate 316 to expose the metallization layer 326. Additionally or alternatively, the deposition tool 102 may deposit a conductive material in the two or more holes to form the BTSV structure 348 and connect the BTSV structure 348 to the metallization layer 326 and / or one or more of the metallization layers 328.

[0082] Steering Figure 4H, a redistribution region 338 is formed on the first semiconductor die 302. For example, one or more of the semiconductor processing tools (102 to 114) may perform a photolithography patterning operation, an etching operation, a deposition operation, a CMP operation, and / or another type of operation to form a dielectric layer 340, one or more metallization layers 342, a UBM layer 344, and a conductive terminal 346. For example, the deposition tool 102 may deposit one or more dielectric layers 340 on the back side of the substrate 316 and the etching tool 108 may etch two or more holes through the one or more dielectric layers 340 to expose the BTSV structure 348. In addition, the deposition tool 102 may deposit a metallization layer 342 that fills the two or more holes.

[0083] The example implementation 400 forms a solenoidal inductor structure 352 (e.g., a solenoidal inductor structure 352 including portions of metallization layer 326, metallization layer 342, and / or BTSV structure 348) as part of the semiconductor die package 300. In some implementations, the solenoidal inductor structure 352 is included in a circuit (e.g., voltage regulator circuit 200).

[0084] Relative to embodiments of the circuit using discrete inductor devices, the length of the electrical path between the solenoid inductor structure 352 and the integrated circuit device (e.g., integrated circuit device 322) can be reduced to improve the performance of the circuit. Additionally or alternatively, including the solenoid inductor structure 352 within the semiconductor die package 300 can eliminate the need for a separate semiconductor die package (for the discrete inductor device) to reduce the amount of resources (semiconductor processing tools, raw materials, manpower and / or computing resources, etc.) used to form the circuit.

[0085] As mentioned above, 4A to 4H Provided as examples. Other examples may differ from the 4A to 4H as described.

[0086] Figure 5A and Figure 5B is a diagram of an example implementation 500 of an example semiconductor die package described herein. The semiconductor die package may correspond to semiconductor die package 300 . Example implementation 500 includes an example of a shunt structure that may be included in solenoidal inductor structure 352 .

[0087] exist Figure 5A In FIG. 3 , semiconductor die package 300 includes a shunt structure 502 within device region 308. As shown, shunt structure 502 includes interconnect structures in two or more interconnect structures (eg, BTSV structure 348). Figure 5A, the shunt structure 502 may divert, divide, or redirect the current 354 within the solenoid inductor structure 352 to tune the solenoid inductor structure 352 and / or prevent surges within a circuit that includes the solenoid inductor structure 352 (eg, the voltage regulator circuit 200 ).

[0088] Steering Figure 5B , the semiconductor die package 300 further includes a shunt structure 504 within the interconnect region 310. As shown, the shunt structure 504 includes two or more conductive layers (e.g., portions of the metallization layer 326 and the metallization layer 328) within the interconnect region 310. Figure 5B , the shunt structure 504 may further divert, divide, or reposition the current 354 into the solenoid inductor structure 352 to tune the solenoid inductor structure 352 and / or prevent surges within a circuit including the solenoid inductor structure 352 (eg, the voltage regulator circuit 200 ).

[0089] As mentioned above, Figure 5A and Figure 5B Provided as examples. Other examples may differ from the Figure 5A and Figure 5B as described.

[0090] FIG. 6A to FIG. 6D is a diagram of an example implementation 600 of an example solenoid inductor structure described herein. FIG. 6A to FIG. 6D Schematically shown in FIG. 6 are directions X, Y, and Z. The solenoid inductor structure may correspond to the solenoid inductor structure 352 . Example implementation 600 includes examples of configurations and / or layouts of the solenoid inductor structure 352 .

[0091] like Fig. 6A As shown in the isometric view of , the solenoidal inductor structure 352 may include multiple segments formed by two or more of a portion of the metallization layer 326, a portion of the metallization layer 342, and a BTSV structure 348. Fig. 6A , the multiple segments may be arranged in approximately orthogonal angular order and centered about axis 602. Axis 602 may correspond to a substantially horizontal axis within a hierarchical structure (e.g., a hierarchical structure including interconnect region 310, device region 308, and redistribution region 338). Fig. 6A As shown, the solenoid inductor structure 352 can be formed into a nearly spiral shape extending along the axis 602. In addition, the solenoid inductor structure 352 can be selected as follows: Fig. 6A The multi-segment arrangement shown (eg, approximately a spiral structure) is used to increase the number of coils within solenoidal inductor structure 352 , thereby improving the inductance performance of solenoidal inductor structure 352 .

[0092] Steering Figure 6BIn the isometric view of FIG. 3 , the solenoidal inductor structure 352 may include multiple sections formed by two or more of a portion of the metallization layer 326 , a portion of the metallization layer 342 , and the BTSV structure 348 . Figure 6B , the upper and lower segments of the solenoidal inductor structure 352 (eg, portions of the metallization layer 326 and the metallization layer 342) are angled (eg, non-orthogonal) relative to the axis 602. Figure 6B As shown, the solenoid inductor structure 352 can be formed into a nearly spiral shape extending along the axis 602. In addition, the solenoid inductor structure 352 can be selected as follows: Figure 6B The illustrated multi-segment arrangement (eg, approximately a spiral-shaped solenoid inductor structure) is used to reduce the number of coils within the solenoid inductor structure 352 , thereby reducing the inductance performance of the solenoid inductor structure 352 .

[0093] like Figure 6C As shown in the top view of FIG. 3 , the solenoidal inductor structure 352 may include multiple segments formed by two or more of a portion of the metallization layer 326 , a portion of the metallization layer 342 , and the BTSV structure 348 . Figure 6C , the arrangement of the plurality of segments is centered about axis 604. Axis 604 may correspond to a substantially vertical axis passing through a layered structure (e.g., a layered structure including interconnect region 310, device region 308, and redistribution region 338). Figure 6C As shown, the solenoid inductor structure 352 can be in the shape of an approximately annular shape (e.g., an approximately annular structure) that is spread along the axis 604. In addition, when the availability of routing of lateral paths within the hierarchical structure is limited, a configuration such as Figure 6C Arrangement of multiple segments shown.

[0094] like Fig.6D As shown in the perspective view of FIG. 3 , the solenoidal inductor structure 352 includes a portion 352a and a portion 352b. Each of the portions 352a and 352b may include a plurality of segments formed by two or more of a portion of the metallization layer 326, a portion of the metallization layer 342, and a BTSV structure 348. Fig.6D In the embodiment, the arrangement of the multiple segments is centered around the axis 602. Fig.6D As shown, the solenoid inductor structure 352 may correspond to a back-coupled structure dispersed along the axis 602. Fig.6D In the solenoid inductor structure 352, the portion 352a (eg, the first portion) may be configured to conduct a current 354a (eg, the first current) along a first approximately spiral path in a first direction. Fig.6D In the solenoid inductor structure 352 of FIG. 3 , portion 352 b (eg, second portion) may be configured to conduct current 354 b (eg, second current) along a second approximately spiral path in a second direction opposite to the first direction. Fig.6D The arrangement of portion 352 a and portion 352 b including multiple segments (eg, a back-coupled solenoid inductor structure) is shown to increase the transient response of the solenoid inductor structure 352 .

[0095] As mentioned above, FIG. 6A to FIG. 6D Provided as examples. Other examples may differ from the FIG. 6A to FIG. 6D as described.

[0096] 7A to 7C is a diagram of an example implementation 700 of a circuit including an example solenoid inductor structure described herein. The solenoid inductor structure may correspond to the solenoid inductor structure 352 .

[0097] like Fig. 7A As shown, the semiconductor die package can receive input current 702 through conductive terminals 346. Fig. 7A In the embodiment of the present invention, a portion of the input current 702 can be routed to the trench capacitor structure 318. Additionally or alternatively, a portion of the input current 702 can be routed through the interconnect region 310, through the interconnect region 314, and to the device region 312 including the integrated circuit device 322. Fig. 7A As shown, integrated circuit device output current 704 may be routed from device region 312 , through interconnect region 314 , through interconnect region 310 , to solenoidal inductor structure 352 .

[0098] In some embodiments, and as Figure 7B As shown, semiconductor die package 300 may include switch element 706, wherein one or more elements of switch element 706 are within interconnect region 310. In this case, as shown in FIG. Figure 7B As shown, semiconductor die package 300 can receive input current 702 through conductive terminals 346. Figure 7B As shown, a portion of the input current 702 can be routed to the trench capacitor structure 318 and / or the switch element 706. Figure 7B As shown, inductor current 708 may be routed from switching element 706 to solenoid inductor structure 352 .

[0099] In some embodiments, and as Figure 7C As shown, semiconductor die package 300 may include multiple trench capacitor structures (eg, trench capacitor structure 318a includes a single trench capacitor and trench capacitor structure 318b includes a single trench capacitor). Figure 7C As shown, one or more components of the switching element 706 are within the interconnection region 310. In addition, as shown Figure 7CAs shown, semiconductor die package 300 may receive input current 702 through conductive terminal 346. A portion of input current 702 may pass through switching element 706. Figure 7C As shown, inductor current 708 may be routed from switching element 706 through solenoid inductor structure 352 to metallization layer 326 and trench capacitor structure 318 b.

[0100] In some embodiments, and as Fig.7D As shown, semiconductor die package 300 may include multiple trench capacitor structures (eg, trench capacitor structure 318a includes a single trench capacitor and trench capacitor structure 318b includes a single trench capacitor). Figure 7C on the contrary, Fig.7D The interconnect region of FIG. 3 does not include switch element 706. In this case, input current 702 and inductor current 708 may enter and exit other types of devices included in semiconductor die package 300 (integrated circuit device 322, among other examples), contacts 330, and / or contacts 336) using other conductive structures within the semiconductor die package (e.g., metallization layer 326, metallization layer 328, metallization layer 334).

[0101] As mentioned above, 7A to 7D Provided as examples. Other examples may differ from the 7A to 7D as described.

[0102] Figure 8 is a graph 800 of an example transient response of a semiconductor die package including a solenoidal inductor structure described herein. In some implementations, the semiconductor die package corresponds to semiconductor die package 300 and the solenoidal inductor structure corresponds to solenoidal inductor structure 352 .

[0103] Graph 800 includes an input voltage 802 (eg, a reference voltage in volts) and a response voltage 804 (eg, a transient response in volts). Graph 800 includes a time-based axis 806 and a voltage axis 808.

[0104] The first transient response 810 may correspond to a transient response of a device including a voltage regulator circuit (e.g., voltage regulator circuit 200) separate from an integrated circuit. For example, the device having the first transient response 810 may include a voltage regulator circuit (e.g., an inductor element and a capacitor element) and an integrated circuit (e.g., an integrated circuit device element) in a separate semiconductor die package mounted to a printed circuit board (PCB).

[0105] In contrast, second transient response 812 may correspond to a transient response of an apparatus including a voltage regulator circuit (e.g., voltage regulator circuit 200) and an integrated circuit, both included in the same semiconductor die package (e.g., semiconductor die package 300). The voltage regulator circuit may include a trench capacitor structure (e.g., trench capacitor structure 318) and a solenoid inductor structure (e.g., solenoid inductor structure 352).

[0106] like Figure 8 As shown, the second transient response 812 (eg, corresponding to the semiconductor die package 300 including the trench capacitance structure 318 and the solenoidal inductor structure 352 ) is suppressed (eg, improved) relative to the first transient response 810 .

[0107] As mentioned above, providing Figure 8 As an example. Other examples may differ from Figure 8 The content described.

[0108] Fig. 9 is a diagram of example elements of an apparatus 900 associated with forming an inductor embedded in a substrate of a semiconductor device. Apparatus 900 may correspond to one or more of semiconductor processing tools (102-114) and / or wafer / die transport tools 116. In some embodiments, one or more of semiconductor processing tools (102-114) and / or wafer / die transport tools 116 may include one or more apparatuses 900 and / or one or more elements of apparatus 900. Fig. 9 As shown, the apparatus 900 may include a bus 910 , a processor 920 , a memory 930 , an input component 940 , an output component 950 , and / or a communication component 960 .

[0109] The bus 910 may include one or more components that enable wired and / or wireless communication between components of the device 900. The bus 910 may include one or more components that enable wired and / or wireless communication between components of the device 900. Fig. 9 Two or more elements of are coupled together, for example, via operational coupling, communication coupling, electronic coupling and / or electrical coupling. For example, bus 910 may include electrical connections (e.g., wires, traces and / or leads) and / or wireless buses. Processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, an application specific integrated circuit and / or other types of processing elements. Processor 920 may be implemented with hardware, firmware or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors or processes that can be programmed to perform one or more operations described elsewhere herein.

[0110] The memory 930 may include volatile and / or non-volatile memory. For example, the memory 930 may include random access memory (RAM), read-only memory (ROM), a hard disk, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 930 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 930 may be a non-transitory computer-readable medium. The memory 930 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 900. In some embodiments, the memory 930 may include one or more memories such as coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 920) via the bus 910. The communicative coupling between the processor 920 and the memory 930 may enable the processor 920 to read and / or process information stored in the memory 930 and / or store information in the memory 930.

[0111] Input member 940 can enable device 900 to receive input, such as user input and / or sensor input. For example, input member 940 can include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, global positioning system sensor, accelerometer, gyroscope and / or actuator. Output member 950 can enable device 900 to provide output, such as via display, speaker and / or light emitting diode. Communication member 960 can enable device 900 to communicate with other devices via wired connection and / or wireless connection. For example, communication member 960 can include receiver, transmitter, transceiver, modem, network card and / or antenna.

[0112] The device 900 can perform one or more operations or processes described herein. For example, a non-transitory computer readable medium (e.g., memory 930) can store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 920. The processor 920 can execute the instruction set to perform one or more operations or processes described herein. In some embodiments, the execution of the instruction set by one or more processors 920 causes one or more processors 920 and / or the device 900 to perform one or more operations or processes described herein. In some embodiments, hardware circuits can be used instead of or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 920 can be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0113] Fig. 9 The number and arrangement of elements shown in are provided as examples. Apparatus 900 may include Fig. 9More elements, fewer elements, different elements, or differently arranged elements than shown in FIG. Additionally or alternatively, a group of elements (e.g., one or more elements) of device 900 may perform one or more functions described as being performed by another group of elements of device 900.

[0114] Fig.10 is a flow chart of an exemplary process 1000 associated with forming an inductor embedded in a substrate of a semiconductor device. In some embodiments, Fig.10 The one or more processing blocks are comprised of one or more semiconductor processing tools and / or wafer / die transport tools (e.g., one or more semiconductor processing tools (102 to 114) and / or wafer / die transport tool 116). Additionally or alternatively, Fig.10 One or more processing blocks may be executed by one or more elements of the device 900 , such as the processor 920 , the memory 930 , the input component 940 , the output component 950 , and / or the communication component 960 .

[0115] like Fig.10 As shown, process 1000 may include etching two or more first holes through a back side of a silicon substrate of a semiconductor die to expose a conductive layer in an interconnect region of the semiconductor die (block 1010). For example, one or more of the semiconductor processing tools (102 to 114) (e.g., etching tool 108) may etch two or more first holes through a silicon substrate (e.g., substrate 316) or a back side of a semiconductor die (e.g., semiconductor die 302) as described herein to expose a conductive layer (e.g., a conductive layer including metallization layer 326) in an interconnect region (e.g., interconnect region 310) of the semiconductor die.

[0116] like Fig.10 As further shown, process 1000 may include depositing a first conductive material in the two or more first holes to form two or more backside through silicon via structures connected to the conductive layer (block 1020). For example, one or more of the semiconductor processing tools (102-114) (e.g., deposition tool 102) may deposit a first conductive material in the two or more first holes to form two or more backside through silicon via structures (e.g., BTSV structures 348) connected to the conductive layer, as described herein.

[0117] like Fig.10As further shown in FIG. 1 , process 1000 may include depositing one or more dielectric redistribution layers of a redistribution region on a back side of the silicon substrate (block 1030). For example, one or more of the semiconductor processing tools (102-114) (e.g., deposition tool 102) may deposit one or more dielectric redistribution layers (e.g., dielectric layer 340) of a redistribution region (e.g., redistribution region 338) on a back side of the silicon substrate, as described herein.

[0118] like Fig.10 As further shown in FIG. 1 , process 1000 may include etching two or more second holes through the one or more dielectric redistribution layers to expose the two or more backside through silicon via structures (block 1040). For example, one or more of the semiconductor processing tools (102 to 114) may etch two or more second holes through the one or more dielectric redistribution layers to expose the two or more backside through silicon via structures, as described herein.

[0119] like Fig.10 As further shown, process 1000 may include depositing a second conductive material that fills the two or more second cavities and electrically couples the two or more back-side through silicon via structures to form an inductor (block 1050). For example, one or more of the semiconductor processing tools (102-114) may deposit a second conductive material (e.g., one or more metallization layers 342) that fills the two or more second cavities and electrically couples the two or more back-side through silicon via structures to form an inductor (e.g., solenoidal inductor structure 352), as described herein.

[0120] Process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0121] In a first embodiment, depositing a second conductive material that fills two or more second holes and electrically couples two or more back-side through silicon via structures to form an inductor includes electrically coupling a conductive layer and two or more back-side through silicon via structures to form a solenoidal inductor structure within a semiconductor die that spans an interconnect region, a silicon substrate, and a redistribution region of the semiconductor die.

[0122] In a second embodiment, alone or in combination with the first embodiment, the semiconductor die is a first semiconductor die and further comprising bonding the first semiconductor die to a second semiconductor die (eg, semiconductor die 304 ).

[0123] In a third embodiment, alone or in combination with one or more of the first and second embodiments, bonding the first semiconductor die to the second semiconductor die includes bonding surfaces of metal contacts of the first semiconductor die and the second semiconductor die (eg, contacts 330 and contacts 336 ).

[0124] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, bonding the first semiconductor die to the second semiconductor die includes bonding surfaces of dielectric layers of the first semiconductor die and the second semiconductor die (e.g., surfaces of one or more dielectric layers 324 and 332).

[0125] Although Fig.10 Example blocks of process 1000 are shown, but in some implementations, process 1000 includes Fig.10 1000. Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. Additionally or alternatively, two or more of the blocks or processes 1000 may be performed in parallel.

[0126] Some embodiments described herein provide an inductor device formed in a substrate of a semiconductor device, the semiconductor device including an integrated circuit device. The inductor device may use one or more conductor layers included in the substrate. In addition, the inductor device may be electrically coupled to the integrated circuit device. By forming the inductor device in the substrate of the semiconductor device, a circuit including the inductor device and the integrated circuit device may be formed within a single semiconductor device.

[0127] As a result, the length of the electrical path between the inductor device and the integrated circuit device can be shortened relative to an implementation of the circuit using a discrete inductor device, thereby improving the performance of the circuit. Additionally or alternatively, including the inductor device within the semiconductor device can eliminate the need for a separate semiconductor die package (for the discrete inductor device) to reduce the amount of resources (semiconductor processing tools, raw materials, manpower) and / or computing resources used to form the circuit, among other examples).

[0128] As described in more detail above, some embodiments described herein provide a semiconductor die package. The semiconductor die package includes a substrate region, the substrate region including a first side and a second side opposite to the first side. The semiconductor die package includes an interconnection region, the interconnection region is above the first side of the substrate region and includes at least one metal layer. The semiconductor die package includes a redistribution region, the redistribution region is above the second side of the substrate region and includes at least one conductive layer. The semiconductor die package includes at least two through-hole structures, the two through-hole structures pass through the substrate region to connect the conductive layer in the redistribution region and at least one metal layer in the interconnection region, wherein at least two through-hole structures, the conductive layer and the metal layer form an inductor. In some embodiments, the inductor includes an approximately spiral structure, and the approximately spiral structure is distributed along an approximately horizontal axis in the substrate region. In some embodiments, the inductor includes an approximately annular structure, and the approximately annular structure is centered on an approximately vertical axis in the substrate region. In some embodiments, the inductor includes a reverse coupling structure, the reverse coupling structure including: a first portion configured to conduct a first current along a first approximate spiral path in a first direction; and a second portion configured to conduct a second current along a second approximate spiral path in a second direction opposite to the first direction. In some embodiments, the inductor includes: a portion of a first conductive layer in an interconnection region; two or more interconnection structures in a substrate region; and a portion of a second conductive layer in a redistribution region. In some embodiments, the inductor also includes a core structure, the core structure being between the two or more interconnection structures in the substrate region. In some embodiments, the inductor also includes a shunt structure. In some embodiments, the shunt structure includes an interconnection structure of two or more interconnection structures in the substrate region. In some embodiments, the shunt structure includes a portion of two or more conductive layers in the substrate region.

[0129] As described in more detail above, some embodiments described herein provide a semiconductor die package. The semiconductor die package includes a first semiconductor die, the first semiconductor die including a substrate region, an interconnect region above the substrate region, a through-hole structure passing through the substrate region, and an inductor including a portion formed in the substrate region. The semiconductor die package includes a second semiconductor die bonded to the interconnect region of the first semiconductor die. In some embodiments, the first semiconductor die also includes: a trench capacitor structure; and a switching element, the switching element connecting the trench capacitor structure and the inductor. In some embodiments, the second semiconductor die includes a logic circuit. In some embodiments, the inductance performance of the inductor is included in the range of about 0.1 nanohenry to about 100 nanohenry. In some embodiments, the first semiconductor die also includes a redistribution region, and the inductor includes another portion within the redistribution region. In some embodiments, the through-hole structure is a first through-hole structure, and the inductor also includes a magnetic core structure, the magnetic core structure between the first through-hole structure and the second through-hole structure.

[0130] As described in more detail above, some embodiments described herein provide a method. The method includes etching two or more first holes through the back side of the silicon substrate of the semiconductor die to expose the conductive layer in the interconnection area of ​​the semiconductor die. The method includes depositing a first conductive material in the two or more first holes to form two or more back-side silicon through hole structures connected to the conductive layer. The method includes depositing one or more dielectric redistribution layers of the redistribution area on the back side of the silicon substrate. The method includes etching two or more second holes through the one or more dielectric redistribution layers to expose two or more back-side silicon through hole structures. The method includes depositing a second conductive material, the second conductive material fills the two or more second holes and electrically couples the two or more back-side silicon through hole structures to form an inductor. In some embodiments, depositing a second conductive material, the second conductive material fills the two or more second holes and electrically couples the two or more back-side silicon through hole structures to form an inductor includes: electrically coupling a conductive layer and two or more back-side silicon through hole structures to form a solenoid inductor structure across the interconnection area of ​​the semiconductor die, the silicon substrate, and the redistribution area in the semiconductor die. In some embodiments, the semiconductor die is a first semiconductor die and further comprises: bonding the first semiconductor die to a second semiconductor die. In some embodiments, bonding the first semiconductor die to the second semiconductor die comprises: bonding surfaces of metal contacts of the first semiconductor die and the second semiconductor die. In some embodiments, bonding the first semiconductor die to the second semiconductor die further comprises: bonding surfaces of dielectric layers of the first semiconductor die and the second semiconductor die.

[0131] As used herein, the term "and / or", when used in conjunction with multiple items, is intended to cover each of the multiple items individually as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A and not B", and "B and not A".

[0132] As used herein, "satisfies a threshold" may refer to greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0133] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor die package, characterized in that: include: a base region including a first side and a second side opposite to the first side; an interconnect region over the first side of the substrate region and comprising at least one metal layer; a redistribution region over the second side of the base region and comprising at least one conductive layer; as well as at least two through-hole structures passing through the base region and connecting the conductive layer in the redistribution region and the at least one metal layer in the interconnection region, The at least two through-hole structures, the conductive layer and the metal layer form an inductor.

2. The semiconductor die package according to claim 1, wherein: The inductor comprises: The spiral structure is distributed along the horizontal axis in the base region.

3. The semiconductor die package according to claim 1, wherein: The inductor comprises: An annular structure centered on a vertical axis within the base region.

4. The semiconductor die package according to claim 1, wherein: The inductor comprises: A reverse coupling structure comprising: a first portion configured to conduct a first current along a first spiral path in a first direction; and The second portion is configured to conduct a second current along a second spiral path in a second direction opposite to the first direction.

5. The semiconductor die package according to claim 1, wherein: The inductor comprises: a portion of the first conductive layer within the interconnect region; two or more interconnect structures within the substrate region; and A portion of the second conductive layer is within the redistribution region.

6. The semiconductor die package according to claim 5, wherein: The inductor further comprises: A magnetic core structure is disposed between the two or more interconnect structures in the base region.

7. A semiconductor die package, characterized in that: include: A first semiconductor die comprising: Basal region; an interconnection region above the substrate region; A through-hole structure passes through the base region; and an inductor including a portion formed in the substrate region; and A second semiconductor die is bonded to the interconnect region of the first semiconductor die.

8. The semiconductor die package according to claim 7, wherein: The first semiconductor die also includes: Trench capacitor structure; and A switch element connects the trench capacitor structure and the inductor.

9. The semiconductor die package according to claim 7, wherein: The second semiconductor die comprises: Logic circuit.

10. The semiconductor die package according to claim 7, wherein: The inductance performance of the inductor is included in the range of 0.1 nanohenry to 100 nanohenry.

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