Frequency abnormity protection circuit

Abstract

The utility model discloses a frequency abnormity protection circuit, comprising an AC rectification circuit used for carrying out rectification processing on an obtained voltage sampling signal to obtain a DC voltage signal; the square wave circuit is used for converting the direct-current voltage signal into a square wave signal; the pre-stage comparison circuit is used for gating and transmitting the square wave signal; the post-stage comparison circuit is used for differentiating the square wave signal, determining whether the signal frequency of the square wave signal exceeds a preset frequency range or not, and sending out a state signal for representing a signal frequency state; and the OR gate circuit is used for outputting a protection signal when determining that the state signal is abnormal. According to the utility model, the condition that the alternating current frequency is too low or too high can be detected through the post-stage comparison circuit, so that the problem that the switching power supply is damaged when the alternating current frequency is too low or too high can be effectively solved, and the switching power supply or other electronic equipment can be protected.

Description

Technical Field

[0001] The utility model belongs to the field of switching power supply power electronics, and in particular relates to a frequency anomaly protection circuit. Background Art

[0002] With the development of the power electronics industry, energy saving, high efficiency and high power density have become the inevitable trend of the development of switching power supplies. Abnormal power grid AC frequency often occurs in applications. Switching power supplies working under abnormal frequency power grids are prone to damage and even interfere with the quality of the power grid. Traditional analog circuits lack accurate and effective detection methods for abnormal power grid AC frequency detection. Utility Model Content

[0003] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a frequency anomaly protection circuit, thereby solving the problems of few existing solutions, complex circuits, inaccurate detection, etc.

[0004] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0005] The utility model provides a frequency anomaly protection circuit, the frequency anomaly protection circuit comprising:

[0006] An AC rectifier circuit is used to rectify the acquired voltage sampling signal to obtain a DC voltage signal;

[0007] A square wave circuit, used for converting the DC voltage signal into a square wave signal;

[0008] The front-stage comparison circuit is used to select and transmit the square wave signal;

[0009] A post-stage comparison circuit is used to differentiate the square wave signal, determine whether the signal frequency of the square wave signal exceeds a preset frequency range, and issue a status signal for characterizing the signal frequency state;

[0010] An OR gate circuit, used to output a protection signal when determining that the state signal is abnormal;

[0011] The output end of the AC rectifier circuit is connected to the input end of the OR gate circuit through the square wave circuit, the front-stage comparison circuit and the rear-stage comparison circuit in sequence.

[0012] Optionally, the pre-stage comparison circuit includes an upper frequency limit comparison branch and a lower frequency limit comparison branch, and the upper frequency limit comparison branch and the lower frequency limit comparison branch are interlocked so that only one of the upper frequency limit comparison branch or the lower frequency limit comparison branch is turned on at the same time.

[0013] Optionally, the upper frequency limit comparison branch includes a ninth resistor, a tenth resistor, a thirteenth resistor, a fifth diode and a first comparator;

[0014] The anode of the fifth diode is connected to the first output terminal of the square wave circuit, the cathode of the fifth diode is connected to the non-inverting input terminal of the first comparator, the inverting input terminal of the first comparator is connected to the voltage terminal through the ninth resistor, the inverting input terminal of the first comparator is also connected to the reference ground through the tenth resistor, and the output terminal of the first comparator is connected to the non-inverting input terminal of the first comparator through the thirteenth resistor;

[0015] The frequency lower limit comparison branch includes an eleventh resistor, a twelfth resistor, a fourteenth resistor, a sixth diode and a second comparator;

[0016] The anode of the sixth diode is connected to the second output terminal of the square wave circuit, the cathode of the sixth diode is connected to the non-inverting input terminal of the second comparator, the inverting input terminal of the second comparator is connected to the voltage terminal through the eleventh resistor, the inverting input terminal of the second comparator is also connected to the reference ground through the twelfth resistor, the output terminal of the second comparator is connected to the non-inverting input terminal of the second comparator through the fourteenth resistor, and the inverting input terminal of the first comparator is also connected to the inverting input terminal of the second comparator.

[0017] Optionally, the AC rectifier circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a second diode, a third diode, a fourth diode, a first capacitor and a second capacitor, the first end of the first resistor is connected to the L line, the second end of the first resistor is connected to the reference ground through the third resistor, the first capacitor is connected in parallel with the third resistor, the second end of the first resistor is respectively connected to the anode of the first diode and the cathode of the third diode, the first end of the second resistor is connected to the N line, the second end of the second resistor is connected to the reference ground through the fourth resistor, the second capacitor is connected in parallel with the fourth resistor, the second end of the second resistor is respectively connected to the anode of the second diode and the cathode of the fourth diode, the anode of the third diode and the anode of the fourth diode are both connected to the reference ground, and the cathode of the first diode and the cathode of the second diode are both connected to the input end of the square wave circuit.

[0018] Optionally, the square wave circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a twenty-first resistor, a first voltage regulator tube, a second voltage regulator tube, a first switch tube, a second switch tube and a third switch tube, the cathode of the first voltage regulator tube is connected to the output end of the AC rectifier circuit through the seventh resistor, the anode of the first voltage regulator tube is connected to the control end of the first switch tube, the first end of the first switch tube is connected to the voltage end through the twenty-first resistor, the cathode of the second voltage regulator tube is connected to the output end of the AC rectifier circuit through the eighth resistor, the anode of the second voltage regulator tube is connected to the control end of the second switch tube, the first end of the second switch tube is connected to the voltage end through the fifth resistor, the first end of the second switch tube is also connected to the control end of the third switch tube, the first end of the third switch tube is connected to the voltage end through the sixth resistor, the second ends of the first switch tube, the second ends of the second switch tube and the second end of the third switch tube are all connected to the reference ground, the first end of the first switch tube is connected to the first input end of the pre-stage comparison circuit, and the first end of the third switch tube is connected to the second input end of the pre-stage comparison circuit.

[0019] Optionally, the post-stage comparison circuit includes a seventh diode, an eighth diode, a fifteenth resistor, a sixteenth resistor, a third comparator, a fourth comparator, a third capacitor and a fourth capacitor;

[0020] The first end of the fifteenth resistor is connected to the first output end of the preceding comparison circuit and the cathode of the seventh diode respectively, the second end of the fifteenth resistor is connected to the non-inverting input end of the third comparator and the anode of the seventh diode respectively, the non-inverting input end of the third comparator is connected to the reference ground through the third capacitor, and the output end of the third comparator is connected to the first port of the output end of the OR gate circuit;

[0021] The first end of the sixteenth resistor is respectively connected to the second output terminal of the previous stage comparison circuit and the cathode of the eighth diode, the second end of the sixteenth resistor is respectively connected to the non-inverting input terminal of the fourth comparator and the anode of the eighth diode, the non-inverting input terminal of the fourth comparator is connected to the reference ground through the fourth capacitor, the output terminal of the fourth comparator is connected to the second port of the output terminal of the OR gate circuit, and the inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator are both connected to the reference voltage terminal.

[0022] Optionally, the OR gate circuit includes a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a ninth diode, a tenth diode, a fifth capacitor, a sixth capacitor and a fourth switch tube;

[0023] The anode of the ninth diode is connected to the first output terminal of the subsequent comparison circuit, the cathode of the ninth diode is connected to the control terminal of the fourth switch tube through the eighteenth resistor, the anode of the ninth diode is also connected to the control terminal of the fourth switch tube through the seventeenth resistor, and the control terminal of the fourth switch tube is connected to the reference ground through the fifth capacitor;

[0024] The anode of the tenth diode is connected to the second output terminal of the post-stage comparison circuit, the cathode of the tenth diode is connected to the first terminal of the fourth switch tube through the twentieth resistor, the anode of the tenth diode is also connected to the first terminal of the fourth switch tube through the nineteenth resistor, the first terminal of the fourth switch tube is connected to the reference ground through the sixth capacitor, and the second terminal of the fourth switch tube is connected to the reference ground.

[0025] Optionally, the first switch tube is an NPN transistor, the first end of the first switch tube is a collector, the second end of the first switch tube is an emitter, and the control end of the first switch tube is a base;

[0026] The second switch tube is an NPN transistor, the first end of the second switch tube is a collector, the second end of the second switch tube is an emitter, and the control end of the second switch tube is a base;

[0027] The third switch tube is an NPN transistor, the first end of the third switch tube is a collector, the second end of the third switch tube is an emitter, and the control end of the third switch tube is a base.

[0028] Compared with the prior art, the utility model has the following beneficial effects:

[0029] 1) The utility model is applied to the switching power supply in the case of unstable power grid quality. The latter comparison circuit can detect the situation that the AC frequency is too low or too high, thereby effectively solving the problem that the switching power supply is damaged when the AC frequency is too low or too high;

[0030] 2) Compared with the prior art, the utility model has fewer components and more accurate detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The utility model is a circuit principle diagram of a frequency anomaly protection circuit. DETAILED DESCRIPTION

[0032] The present invention / utility model and its beneficial effects will be further described in detail below in conjunction with specific implementation methods and drawings of the specification, but the specific implementation methods of the present invention / utility model are not limited thereto.

[0033] refer to Figure 1The utility model provides a frequency anomaly protection circuit, the frequency anomaly protection circuit comprising:

[0034] The AC rectifier circuit 1 is used to rectify the acquired voltage sampling signal to obtain a DC voltage signal;

[0035] A square wave circuit 2, used for converting a DC voltage signal into a square wave signal;

[0036] The front-stage comparison circuit 3 is used to select and transmit the square wave signal;

[0037] The post-stage comparison circuit 4 is used to differentiate the square wave signal, determine whether the signal frequency of the square wave signal exceeds a preset frequency range, and issue a status signal for characterizing the signal frequency state;

[0038] The OR gate circuit 5 is used to output a protection signal when determining that the status signal is abnormal;

[0039] The output end of the AC rectifier circuit 1 is connected to the input end of the OR gate circuit 5 through the square wave circuit 2, the front-stage comparison circuit 3 and the rear-stage comparison circuit 4 in sequence.

[0040] In this embodiment, it is mainly used to detect abnormal frequency of AC power in the power grid. It should be noted that the utility model converts the AC voltage sampling signal into a DC voltage signal, and then into a square wave signal with a signal frequency, and then through differentiation, in the post-stage comparison circuit 4, by voltage comparison, it is determined whether the signal frequency exceeds the preset frequency range. If the signal frequency exceeds the upper frequency limit or the signal frequency is lower than the lower frequency limit, the state signal is abnormal, and the gate circuit 5 will output a protection signal, indicating that circuit protection needs to be executed, effectively solving the problem of damage to the switching power supply when the AC frequency is too low or too high.

[0041] In one embodiment, the pre-stage comparison circuit 3 includes an upper frequency limit comparison branch 31 and a lower frequency limit comparison branch 32, and the upper frequency limit comparison branch 31 and the lower frequency limit comparison branch 32 are interlocked so that only one of the upper frequency limit comparison branch 31 or the lower frequency limit comparison branch 32 is turned on at the same time.

[0042] The upper frequency comparison branch 31 and the lower frequency comparison branch 32 are interlocked by increasing the reference voltage of the other branch, so that only one of the upper frequency comparison branch 31 or the lower frequency comparison branch 32 is turned on at the same time.

[0043] In one embodiment, the upper frequency limit comparison branch 31 includes a ninth resistor R9, a tenth resistor R10, a thirteenth resistor R13, a fifth diode D5 and a first comparator U1;

[0044] The anode of the fifth diode D5 is connected to the first output terminal of the square wave circuit 2, the cathode of the fifth diode D5 is connected to the non-inverting input terminal of the first comparator U1, the inverting input terminal of the first comparator U1 is connected to the voltage terminal through the ninth resistor R9, the inverting input terminal of the first comparator U1 is also connected to the reference ground through the tenth resistor R10, and the output terminal of the first comparator U1 is connected to the non-inverting input terminal of the first comparator U1 through the thirteenth resistor R13;

[0045] The frequency lower limit comparison branch 32 includes an eleventh resistor R11, a twelfth resistor R12, a fourteenth resistor R14, a sixth diode D6 and a second comparator U2;

[0046] The anode of the sixth diode D6 is connected to the second output terminal of the square wave circuit 2, the cathode of the sixth diode D6 is connected to the non-inverting input terminal of the second comparator U2, the inverting input terminal of the second comparator U2 is connected to the voltage terminal through the eleventh resistor R11, the inverting input terminal of the second comparator U2 is also connected to the reference ground through the twelfth resistor R12, the output terminal of the second comparator U2 is connected to the non-inverting input terminal of the second comparator U2 through the fourteenth resistor R14, and the inverting input terminal of the first comparator U1 is also connected to the inverting input terminal of the second comparator U2.

[0047] In one embodiment, the square wave circuit 2 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a twenty-first resistor R21, a first voltage regulator tube DZ1, a second voltage regulator tube ZD1, a first switch tube Q1, a second switch tube Q2 and a third switch tube Q3, the cathode of the first voltage regulator tube DZ1 is connected to the output end of the AC rectifier circuit through the seventh resistor R7, the anode of the first voltage regulator tube DZ1 is connected to the control end of the first switch tube Q1, the first end of the first switch tube Q1 is connected to the voltage end through the twenty-first resistor R21, and the cathode of the second voltage regulator tube ZD1 is connected to the AC rectifier circuit through the eighth resistor R8. The output end of the circuit, the anode of the second voltage regulator tube ZD1 is connected to the control end of the second switch tube Q2, the first end of the second switch tube Q2 is connected to the voltage end through the fifth resistor R5, the first end of the second switch tube Q2 is also connected to the control end of the third switch tube Q3, the first end of the third switch tube Q3 is connected to the voltage end through the sixth resistor R6, the second ends of the first switch tube Q1, the second ends of the second switch tube Q2 and the second ends of the third switch tube Q3 are all connected to the reference ground, the first end of the first switch tube Q1 is connected to the first input end of the front-stage comparison circuit 3, and the first end of the third switch tube Q3 is connected to the second input end of the front-stage comparison circuit 3.

[0048] Among them, the first switch tube Q1, the second switch tube Q2, and the third switch tube Q3 can be implemented by switching devices such as triodes and MOS tubes. In this embodiment, the first switch tube Q1 is an NPN triode, the first end of the first switch tube Q1 is the collector, the second end of the first switch tube Q1 is the emitter, and the control end of the first switch tube Q1 is the base; the second switch tube Q2 is an NPN triode, the first end of the second switch tube Q2 is the collector, the second end of the second switch tube Q2 is the emitter, and the control end of the second switch tube Q2 is the base; the third switch tube Q3 is an NPN triode, the first end of the third switch tube Q3 is the collector, the second end of the third switch tube Q3 is the emitter, and the control end of the third switch tube Q3 is the base.

[0049] In this embodiment, the square wave signal is selected by the first comparator U1 and the second comparator U2. In state 1 of the pre-stage comparison circuit 3, when the DC voltage after AC rectification is less than the voltage of the first voltage regulator tube DZ1 and the second voltage regulator tube ZD1, the seventh resistor R7 and the first voltage regulator tube DZ1 are connected one way. When the terminal voltage of the seventh resistor R7 is less than the voltage of the first voltage regulator tube DZ1, the first voltage regulator tube DZ1 is not conducting, and the voltage is then connected to the B pole of the first switch tube Q1. The first switch tube Q1 is in a non-conducting state, and the high-level voltage flows from the C pole of the first switch tube Q1 to the fifth diode D5 and then to the non-inverting input terminal of the first comparator U1. At this time, the non-inverting input terminal is high level, and the first comparator U1 outputs a high level. The fifth diode D5 is connected to the midpoint of the eleventh resistor R11 and the twelfth resistor R12. At this time, the reference voltage of the inverting input of the second comparator U2 becomes high, and the upper frequency limit comparison branch 31 and the lower frequency limit comparison branch 32 are interlocked by increasing the reference voltage of the other side branch. At this time, the non-inverting input of the second comparator U2 is low, so the output of the second comparator U2 is low.

[0050] In state 2 of the pre-stage comparison circuit 3, after the AC rectification, when the DC voltage after the AC rectification is greater than the voltage of the first voltage regulator tube DZ1 and the second voltage regulator tube ZD1, the eighth resistor R8 and the second voltage regulator tube ZD1 are connected all the way. At this time, the terminal voltage of the eighth resistor R8 is greater than the voltage of the second voltage regulator tube ZD1, and the second voltage regulator tube ZD1 is turned on. The voltage is then connected to the B pole of the second switch tube Q2, and the second switch tube Q2 is in the on state. The C pole of the second switch tube Q2 pulls down the B pole of the third switch tube Q3, and the third switch tube Q3 is not turned on. The second comparison circuit 3 is in the on state. The non-inverting input terminal of the comparator U2 is pulled high, at this time, the inverting input terminal of the second comparator U2 is low, and the second comparator U2 outputs a high level; the sixth diode D6 is connected to the midpoint of the eleventh resistor R11 and the twelfth resistor R12, at this time, the reference voltage of the inverting input of the first comparator U1 becomes high, and the upper frequency limit comparison branch 31 and the lower frequency limit comparison branch 32 form an interlock by increasing the reference voltage of the other side branch. At this time, the non-inverting input terminal of the first comparator U1 is low, so the output of the first comparator U1 is low.

[0051] In one embodiment, the AC rectifier circuit 1 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first capacitor C1 and a second capacitor C2, a first end of the first resistor R1 is connected to the L line, a second end of the first resistor R1 is connected to the reference ground through the third resistor R3, the first capacitor C1 is connected in parallel with the third resistor R3, a second end of the first resistor R1 is respectively connected to the anode of the first diode D1 and the cathode of the third diode D3, a first end of the second resistor R2 is connected to the N line, a second end of the second resistor R2 is connected to the reference ground through the fourth resistor R4, the second capacitor C2 is connected in parallel with the fourth resistor R4, a second end of the second resistor R2 is respectively connected to the anode of the second diode D2 and the cathode of the fourth diode D4, an anode of the third diode D3 and an anode of the fourth diode D4 are both connected to the reference ground, and a cathode of the first diode D1 and a cathode of the second diode D2 are both connected to the input end of the square wave circuit 2.

[0052] In this embodiment, the AC voltages L and N are divided by the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, and then connected to the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 for full-wave rectification to generate a low-voltage forward voltage for convenient back-end detection.

[0053] In addition to the AC rectifier circuit 1 used in the above embodiment, AC rectifier circuits 1 with other structures can also be used.

[0054] In one embodiment, the post-stage comparison circuit 4 includes a seventh diode D7, an eighth diode D8, a fifteenth resistor R15, a sixteenth resistor R16, a third comparator U3, a fourth comparator U4, a third capacitor C3 and a fourth capacitor C4;

[0055] The first end of the fifteenth resistor R15 is respectively connected to the first output terminal of the previous stage comparison circuit 3 and the cathode of the seventh diode D7, the second end of the fifteenth resistor R15 is respectively connected to the non-inverting input terminal of the third comparator U3 and the anode of the seventh diode D7, the non-inverting input terminal of the third comparator U3 is connected to the reference ground through the third capacitor C3, and the output terminal of the third comparator U3 is connected to the first port of the output terminal of the OR gate circuit 5.

[0056] The first end of the sixteenth resistor R16 is respectively connected to the second output terminal of the previous stage comparison circuit 3 and the cathode of the eighth diode D8, the second end of the sixteenth resistor R16 is respectively connected to the non-inverting input terminal of the fourth comparator U4 and the anode of the eighth diode D8, the non-inverting input terminal of the fourth comparator U4 is connected to the reference ground through the fourth capacitor C4, the output terminal of the fourth comparator U4 is connected to the second port of the output terminal of the OR gate circuit 5, and the inverting input terminal of the third comparator U3 and the inverting input terminal of the fourth comparator U4 are both connected to the reference voltage terminal.

[0057] Among them, the post-stage comparison circuit 4 differentiates the voltage of the square wave signal output by the pre-stage comparison circuit 3 through the fifteenth resistor R15 and the third capacitor C3 connected to the output end of the pre-stage comparison circuit 3, and the sixteenth resistor R16 and the fourth capacitor C4 connected to the output end of the pre-stage comparison circuit 3, so that the voltage is positively correlated with time, and then compares it with the reference voltage of the inverting input end of the third comparator U3 and the fourth comparator U4. The voltage comparison here is equivalent to frequency comparison, and the upper and lower frequency limits can be adjusted by the reference voltage. In this embodiment, the reference voltage is 2.5V, which is equivalent to the upper frequency limit of 63hz and the lower frequency limit of 43hz. If the signal frequency is less than 43hz or greater than 63hz, it is judged as abnormal, and the voltage is pulled down to enter protection.

[0058] In one embodiment, the OR gate circuit 5 includes a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a ninth diode D9, a tenth diode D10, a fifth capacitor C5, a sixth capacitor C6 and a fourth switch tube Q4;

[0059] The anode of the ninth diode D9 is connected to the first output terminal of the subsequent comparison circuit 4, the cathode of the ninth diode D9 is connected to the control terminal of the fourth switch tube Q4 through the eighteenth resistor R18, the anode of the ninth diode D9 is also connected to the control terminal of the fourth switch tube Q4 through the seventeenth resistor R17, and the control terminal of the fourth switch tube Q4 is connected to the reference ground through the fifth capacitor C5;

[0060] The anode of the tenth diode D10 is connected to the second output terminal of the post-stage comparison circuit 4, the cathode of the tenth diode D10 is connected to the first end of the fourth switch tube Q4 through the twentieth resistor R20, the anode of the tenth diode D10 is also connected to the first end of the fourth switch tube Q4 through the nineteenth resistor R19, the first end of the fourth switch tube Q4 is connected to the reference ground through the sixth capacitor C6, and the second end of the fourth switch tube Q4 is connected to the reference ground.

[0061] The OR gate circuit 5 can be implemented by using an OR gate circuit 5 of other circuit structures. In this embodiment, if either the first output terminal or the second output terminal of the subsequent comparison circuit 4 outputs a low level, the OR gate circuit 5 sends a protection signal.

[0062] The above are only preferred embodiments of the present invention. If more equivalent variations or substitutions are added on this basis, they should also fall within the protection scope of the patent. It should be pointed out that the above preferred embodiments should not be regarded as limitations on the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the spirit and scope of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. The embodiments will not be repeated here. The protection scope of the present invention should be based on the scope defined by the claims.

Claims

1. A frequency anomaly protection circuit, characterized in that: The frequency anomaly protection circuit comprises: An AC rectifier circuit is used to rectify the acquired voltage sampling signal to obtain a DC voltage signal; A square wave circuit, used for converting the DC voltage signal into a square wave signal; The front-stage comparison circuit is used to select and transmit the square wave signal; A post-stage comparison circuit is used to differentiate the square wave signal, determine whether the signal frequency of the square wave signal exceeds a preset frequency range, and issue a status signal for characterizing the signal frequency state; An OR gate circuit, used to output a protection signal when determining that the state signal is abnormal; The output end of the AC rectifier circuit is connected to the input end of the OR gate circuit through the square wave circuit, the front-stage comparison circuit and the rear-stage comparison circuit in sequence.

2. A frequency anomaly protection circuit according to claim 1, characterized in that: The front-stage comparison circuit includes an upper frequency limit comparison branch and a lower frequency limit comparison branch, and the upper frequency limit comparison branch and the lower frequency limit comparison branch are interlocked, so that only one of the upper frequency limit comparison branch or the lower frequency limit comparison branch is turned on at the same time.

3. A frequency anomaly protection circuit according to claim 2, characterized in that: The upper frequency limit comparison branch includes a ninth resistor, a tenth resistor, a thirteenth resistor, a fifth diode and a first comparator; The anode of the fifth diode is connected to the first output terminal of the square wave circuit, the cathode of the fifth diode is connected to the non-inverting input terminal of the first comparator, the inverting input terminal of the first comparator is connected to the voltage terminal through the ninth resistor, the inverting input terminal of the first comparator is also connected to the reference ground through the tenth resistor, and the output terminal of the first comparator is connected to the non-inverting input terminal of the first comparator through the thirteenth resistor; The frequency lower limit comparison branch includes an eleventh resistor, a twelfth resistor, a fourteenth resistor, a sixth diode and a second comparator; The anode of the sixth diode is connected to the second output terminal of the square wave circuit, the cathode of the sixth diode is connected to the non-inverting input terminal of the second comparator, the inverting input terminal of the second comparator is connected to the voltage terminal through the eleventh resistor, the inverting input terminal of the second comparator is also connected to the reference ground through the twelfth resistor, the output terminal of the second comparator is connected to the non-inverting input terminal of the second comparator through the fourteenth resistor, and the inverting input terminal of the first comparator is also connected to the inverting input terminal of the second comparator.

4. A frequency anomaly protection circuit according to claim 1, characterized in that: The AC rectifier circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a second diode, a third diode, a fourth diode, a first capacitor and a second capacitor. The first end of the first resistor is connected to the L line, the second end of the first resistor is connected to the reference ground through the third resistor, the first capacitor is connected in parallel with the third resistor, the second end of the first resistor is respectively connected to the anode of the first diode and the cathode of the third diode, the first end of the second resistor is connected to the N line, the second end of the second resistor is connected to the reference ground through the fourth resistor, the second capacitor is connected in parallel with the fourth resistor, the second end of the second resistor is respectively connected to the anode of the second diode and the cathode of the fourth diode, the anode of the third diode and the anode of the fourth diode are both connected to the reference ground, and the cathode of the first diode and the cathode of the second diode are both connected to the input end of the square wave circuit.

5. A frequency anomaly protection circuit according to claim 1, characterized in that: The square wave circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a twenty-first resistor, a first voltage regulator tube, a second voltage regulator tube, a first switch tube, a second switch tube and a third switch tube. The cathode of the first voltage regulator tube is connected to the output end of the AC rectifier circuit through the seventh resistor, the anode of the first voltage regulator tube is connected to the control end of the first switch tube, the first end of the first switch tube is connected to the voltage end through the twenty-first resistor, the cathode of the second voltage regulator tube is connected to the output end of the AC rectifier circuit through the eighth resistor, the anode of the second voltage regulator tube is connected to the control end of the second switch tube, the first end of the second switch tube is connected to the voltage end through the fifth resistor, the first end of the second switch tube is also connected to the control end of the third switch tube, the first end of the third switch tube is connected to the voltage end through the sixth resistor, the second ends of the first switch tube, the second ends of the second switch tube and the second ends of the third switch tube are all connected to the reference ground, the first end of the first switch tube is connected to the first input end of the pre-stage comparison circuit, and the first end of the third switch tube is connected to the second input end of the pre-stage comparison circuit.

6. A frequency anomaly protection circuit according to claim 1, characterized in that: The post-stage comparison circuit includes a seventh diode, an eighth diode, a fifteenth resistor, a sixteenth resistor, a third comparator, a fourth comparator, a third capacitor and a fourth capacitor; The first end of the fifteenth resistor is connected to the first output end of the preceding comparison circuit and the cathode of the seventh diode respectively, the second end of the fifteenth resistor is connected to the non-inverting input end of the third comparator and the anode of the seventh diode respectively, the non-inverting input end of the third comparator is connected to the reference ground through the third capacitor, and the output end of the third comparator is connected to the first port of the output end of the OR gate circuit; The first end of the sixteenth resistor is respectively connected to the second output terminal of the previous stage comparison circuit and the cathode of the eighth diode, the second end of the sixteenth resistor is respectively connected to the non-inverting input terminal of the fourth comparator and the anode of the eighth diode, the non-inverting input terminal of the fourth comparator is connected to the reference ground through the fourth capacitor, the output terminal of the fourth comparator is connected to the second port of the output terminal of the OR gate circuit, and the inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator are both connected to the reference voltage terminal.

7. A frequency anomaly protection circuit according to claim 1, characterized in that: The OR gate circuit includes a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a ninth diode, a tenth diode, a fifth capacitor, a sixth capacitor and a fourth switch tube; The anode of the ninth diode is connected to the first output terminal of the subsequent comparison circuit, the cathode of the ninth diode is connected to the control terminal of the fourth switch tube through the eighteenth resistor, the anode of the ninth diode is also connected to the control terminal of the fourth switch tube through the seventeenth resistor, and the control terminal of the fourth switch tube is connected to the reference ground through the fifth capacitor; The anode of the tenth diode is connected to the second output terminal of the post-stage comparison circuit, the cathode of the tenth diode is connected to the first terminal of the fourth switch tube through the twentieth resistor, the anode of the tenth diode is also connected to the first terminal of the fourth switch tube through the nineteenth resistor, the first terminal of the fourth switch tube is connected to the reference ground through the sixth capacitor, and the second terminal of the fourth switch tube is connected to the reference ground.

8. A frequency anomaly protection circuit according to claim 5, characterized in that: The first switch tube is an NPN transistor, the first end of the first switch tube is a collector, the second end of the first switch tube is an emitter, and the control end of the first switch tube is a base; The second switch tube is an NPN transistor, the first end of the second switch tube is a collector, the second end of the second switch tube is an emitter, and the control end of the second switch tube is a base; The third switch tube is an NPN transistor, the first end of the third switch tube is a collector, the second end of the third switch tube is an emitter, and the control end of the third switch tube is a base.

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