TYPE-C fast charging data line

Abstract

The utility model provides a TYPE-C fast charging data line. The TYPE-C fast charging data line comprises a protocol module, a DC-DC voltage reduction module, a PD protocol decoy module, an input interface module and an output interface module, the PD protocol decoy module is electrically connected with the protocol module and the input interface module respectively; one end of the DC-DC voltage reduction module is electrically connected with the protocol module, and the other end is electrically connected with the output interface module; the DC-DC voltage reduction module comprises a first DC-DC voltage reduction module and a second DC-DC voltage reduction module; the first DC-DC voltage reduction module and the second DC-DC voltage reduction module are electrically connected with the protocol module; the input interface module is electrically connected with the first DC-DC voltage reduction module and the second DC-DC voltage reduction module. The output interface module comprises a first output interface module and a second output interface module; the first output interface module is electrically connected with the protocol module and the first DC-DC voltage reduction module. The second output interface module is electrically connected with the protocol module and the second DC-DC voltage reduction module. The intelligent charging device is reasonable in structural design, can intelligently distribute output port power, and can adapt to different charging devices.

Description

Technical Field

[0001] The utility model relates to a charging data cable, in particular to a TYPE-C fast charging data cable. Background Art

[0002] At present, the charging power of most chargers on the market is much higher than the 15W, 20W, and 40W low-power chargers of the past. The maximum charging power of the PD3.1 fast charging protocol is 240W. The charger that follows has also released a PD3.1 single-port 140W fast charging. The conventional TYPE-C TO TYPE-C fast charging cable on the market can only charge a single electronic device. Although there are TYPE-C one-to-three data cables on the market (output 3 interfaces: TYPE-C, Micro-B, and Lightning), this data cable can charge 3 electronic devices at the same time. However, with the popularity of the TYPE-C interface, most electronic devices have been updated to the TYPE-C interface, and Micro-B has been slowly launched on the market. As for the Lightning interface, with the release of Apple's 15th generation, the interface also uses TYPE-C. With the release of new products, the Lightning interface has also been slowly launched on the market. Obviously, this TYPE-C one-to-three data cable is not practical, and there is only one TYPE-C interface. Summary of the invention

[0003] In view of the technical problems existing in the above-mentioned background technology, the utility model proposes a TYPE-C fast charging data cable, which has a reasonable structural design. It mainly communicates with the adapter through handshake via the TYPE-C port to obtain the power information of the adapter, and intelligently allocates the output port power according to the device inserted into the TYPE-C port at the output end, so it can adapt to different charging devices.

[0004] In order to solve the above technical problems, the utility model provides a TYPE-C fast charging data cable, including a protocol module, a DC-DC buck module, a PD protocol deception module, an input interface module and an output interface module; one end of the PD protocol deception module is electrically connected to the protocol module, and the other end is electrically connected to the input interface module; one end of the DC-DC buck module is electrically connected to the protocol module, and the other end is electrically connected to the output interface module; the DC-DC buck module includes a pair of first DC-DC buck modules and second DC-DC buck modules connected in series with each other; the first DC-DC buck module and the second DC -DC step-down modules are electrically connected to the protocol module; the input interface module is electrically connected to the first DC-DC step-down module and the second DC-DC step-down module respectively; the output interface module includes a first output interface module and a second output interface module; one end of the first output interface module is electrically connected to the protocol module, and the other end is electrically connected to the first DC-DC step-down module; one end of the second output interface module is electrically connected to the protocol module, and the other end is electrically connected to the second DC-DC step-down module; the DC-DC outputs of the first output interface module and the second output interface module adopt independent step-down control.

[0005] The TYPE-C fast charging data cable, wherein: the protocol module is composed of a protocol chip U5, resistors R9~R15, and capacitors C23~C25; the model of the protocol chip U5 is IP2738U, which is grounded through pins GND and EPAD; one end of the resistor R9 is electrically connected to pin FB B of the protocol chip U5, and the other end is electrically connected to the second DC-DC buck module; one end of the resistor R10 is electrically connected to pin CMPI_B of the protocol chip U5, and the other end is electrically connected to the capacitor C24 and is electrically connected to the other end of the resistor R9 through the capacitor C24; one end of the resistor R11 is electrically connected to pin GPIO2 of the protocol chip U5, and the other end is grounded; one end of the resistor R12 is electrically connected to pin FB of the protocol chip U5 A, and the other end is electrically connected to the first DC-DC step-down module; one end of the resistor R13 is electrically connected to the pin CMPI_A of the protocol chip U5, and the other end is electrically connected to the capacitor C25 and is electrically connected to the other end of the resistor R12 through the capacitor C25; one end of the resistor R14 is electrically connected to the pin VI NA of the protocol chip U5, and the other end is electrically connected to the first DC-DC step-down module; one end of the resistor 15 is electrically connected to the pin VI NB of the protocol chip U5, and the other end is electrically connected to the second DC-DC step-down module; one end of the capacitor C23 is grounded, and the other end is electrically connected to the pin VCC of the protocol chip U5.

[0006] The TYPE-C fast charging data cable, wherein: the resistance value of the resistor R9 is 1K, and the accuracy is 1%; the resistance value of the resistor R10 is 200K, and the accuracy is 1%; the resistance value of the resistor R11 is 10K, and the accuracy is 1%; the resistance value of the resistor R12 is 1K, and the accuracy is 1%; the resistance value of the resistor R13 is 200K, and the accuracy is 1%; the resistance values ​​of the resistor R14 and the resistor R15 are both 2R, and the accuracy is 1%; the capacitance value of the capacitor C23 is 2.2uF, and the voltage is 25V; the capacitance values ​​of the capacitor C24 and the capacitor C25 are both 3.3nF.

[0007] The TYPE-C fast charging data cable, wherein: the first DC-DC buck module consists of a first DC-DC buck chip U2, resistors R2-R5, capacitors C10-C16, an inductor L1 and field effect transistors Q1-Q2; the field effect transistors Q1-Q2 are all N-MOS field effect transistors; the model of the first DC-DC buck chip U2 is IP6550;

[0008] The first DC-DC buck chip U2 is grounded through pins DM, DP, EPAD and PGND, is electrically connected to the power supply VBUS_I N through pin VIN, is electrically connected to the power supply VDD through pin VCC, is electrically connected to the resistor R12 through pin FB and is electrically connected to pin FB_A of the protocol chip U5 through the resistor R12, is electrically connected to the resistor R14 through pin VOUT and is electrically connected to pin V1 of the protocol chip U5 through the resistor R14 NA; one end of the resistor R2 is grounded, and the other end is electrically connected to the pin EN of the first DC-DC buck chip U2; one end of the capacitor C10 is grounded, and the other end is electrically connected to the pin VCC of the first DC-DC buck chip U2; one end of the capacitor C11 is grounded, and the other end is electrically connected to the pin COMP of the first DC-DC buck chip U2; one end of the capacitor C12 is electrically connected to the pin HVCC of the first DC-DC buck chip U2, and the other end is electrically connected to the pin PGND of the first DC-DC buck chip U2; one end of the capacitor C13 is electrically connected to the pin BST of the first DC-DC buck chip U2, and the other end is electrically connected to the pin LX of the first DC-DC buck chip U2; one end of the capacitor C14 is grounded, and the other end is electrically connected to the resistor R4 and is electrically connected to the pin LX of the first DC-DC buck chip U2 through the resistor R4; the drain of the field effect tube Q1 is electrically connected to the pin VI of the first DC-DC buck chip U2 N, the source is electrically connected to the pin LX of the first DC-DC buck chip U2, the gate is electrically connected to the resistor R3 and is electrically connected to the pin HG of the first DC-DC buck chip U2 through the resistor R3; one end of the capacitor C15 is electrically connected to the drain of the field effect tube Q1, and the other end is grounded; the source of the field effect tube Q2 is grounded, the drain is electrically connected to the source of the field effect tube Q1, the gate is electrically connected to the resistor R5 and is electrically connected to the pin LG of the first DC-DC buck chip U2 through the resistor R5; one end of the inductor L1 is electrically connected to the electrical connection point between the drain of the field effect tube Q2 and the source of the field effect tube Q1, and the other end is electrically connected to the first output interface module; the capacitor C16 is a polar capacitor, the positive electrode of which is electrically connected to the resistor R14 and is electrically connected to the pin VI NA of the protocol chip U5 through the resistor R14, and the negative electrode is grounded;

[0009] The second DC-DC buck module is composed of a second DC-DC buck chip U3, resistors R16-R18, resistor R20, capacitors C35-C38, capacitors C26-C27, capacitor C30, inductor L2 and field effect transistors Q3-Q4; the capacitor C30 is a polar capacitor; the field effect transistors Q3-Q4 are all N-MOS field effect transistors; the model of the second DC-DC buck chip U3 is IP6550;

[0010] The second DC-DC buck chip U3 is grounded through pins DM, DP, EPAD and PGND, electrically connected to the power supply VBUS_I N through pin VIN, electrically connected to the power supply VDD through pin VCC, electrically connected to the resistor R9 through pin FB, and electrically connected to the pin FB of the protocol chip U5 through the resistor R9. B, electrically connected to the resistor R15 through the pin VOUT and electrically connected to the pin VI of the protocol chip U5 through the resistor R15 NB; one end of the resistor R18 is grounded, and the other end is electrically connected to the pin EN of the second DC-DC buck chip U3; one end of the capacitor C35 is grounded, and the other end is electrically connected to the pin VCC of the second DC-DC buck chip U3; one end of the capacitor C37 is grounded, and the other end is electrically connected to the pin COMP of the second DC-DC buck chip U3; one end of the capacitor C38 is electrically connected to the pin HVCC of the second DC-DC buck chip U3, and the other end is electrically connected to the pin PGND of the second DC-DC buck chip U3; one end of the capacitor C27 is electrically connected to the pin BST of the second DC-DC buck chip U3, and the other end is electrically connected to the pin LX of the second DC-DC buck chip U3; one end of the capacitor C36 is grounded, and the other end is electrically connected to the resistor R17 and electrically connected to the pin LX of the second DC-DC buck chip U3 through the resistor R17; the drain of the field effect transistor Q3 is electrically connected to the pin VI of the second DC-DC buck chip U3 N, the source is electrically connected to the pin LX of the second DC-DC buck chip U3, the gate is electrically connected to the resistor R16 and is electrically connected to the pin HG of the second DC-DC buck chip U3 through the resistor R16; one end of the capacitor C26 is electrically connected to the drain of the field effect transistor Q3, and the other end is grounded; the drain of the field effect transistor Q4 is electrically connected to the source of the field effect transistor Q3, the source is grounded, the gate is electrically connected to the resistor R20 and is electrically connected to the pin LG of the second DC-DC buck chip U3 through the resistor R20; one end of the inductor L2 is electrically connected to the electrical connection point between the drain of the field effect transistor Q4 and the source of the field effect transistor Q3, and the other end is electrically connected to the second output interface module; the capacitor C30 is a polar capacitor, the positive electrode of which is electrically connected to the resistor R15 and is electrically connected to the pin VI NB of the protocol chip U5 through the resistor R15, and the negative electrode is grounded.

[0011] The TYPE-C fast charging data cable, wherein: the resistance value of the resistor R2 is 51K, and the accuracy is 1%; the resistance values ​​of the resistor R3 and the resistor R5 are both 2.2R, and the accuracy is 1%; the resistance value of the resistor R4 is 2R, and the accuracy is 1%; the capacitance values ​​of the capacitors C10 and C12 are both 2.2uF, and the voltages are both 25V; the capacitance value of the capacitor C11 is 1nF, and the voltage is 50V; the capacitance value of the capacitor C13 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C14 is 1nF, and the voltage is 50V; the capacitance value of the capacitor C15 is 10uF, and the voltage is 35V; the capacitance value of the capacitor C16 is 100uF, and the voltage is 35V.

[0012] The TYPE-C fast charging data cable, wherein: the resistance value of the resistor R16 is 2.2R, and the accuracy is 1%; the resistance value of the resistor R17 is 2R, and the accuracy is 1%; the resistance value of the resistor R18 is 51K, and the accuracy is 1%; the resistance value of the resistor R20 is 2.2R, and the accuracy is 1%; the capacitance value of the capacitor C35 is 2.2uF, and the voltage is 25V; the capacitance values ​​of the capacitors C36 and C37 are both 1nF, and the voltage is 50V; the capacitance value of the capacitor C38 is 2.2uF, and the voltage is 25V; the capacitance value of the capacitor C26 is 10uF, and the voltage is 35V; the capacitance value of the capacitor C27 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C30 is 100uF, and the voltage is 35V.

[0013] The TYPE-C fast charging data cable, wherein: the first output interface module is composed of a first output interface TYPR-C1, capacitors C21-C22, and resistors R7-R8; the model of the first output interface TYPR-C1 is TYPR-C PAD, which is electrically connected to the other end of the inductor L1 through the pin VBUS, and is electrically connected to the pin DP of the protocol chip U5 through the pin D+ A, electrically connect the pin D- to the pin DM of the protocol chip U5 A, electrically connected to the pin CC1_A of the protocol chip U5 through the pin CC1, electrically connected to the resistor R8 through the pin GND and grounded through the resistor R8; one end of the capacitor C21 is grounded, and the other end is electrically connected to the pin VBUS of the first output interface TYPR-C1; one end of the resistor R6 is grounded, and the other end is electrically connected to the pin FB of the first DC-DC buck chip U2; one end of the resistor R7 is electrically connected to the pin VBUS of the first output interface TYPR-C1, and the other end is electrically connected to the pin FB of the first DC-DC buck chip U2; the capacitor C22 is connected in parallel to both ends of the resistor R7;

[0014] The second output interface module is composed of a second output interface TYPR-C2, capacitors C28-C29, resistors R19, and resistors R21-R22; the model of the second output interface TYPR-C2 is TYPR-C PAD, which is electrically connected to the other end of the inductor L2 through pin VBUS, electrically connected to pin DP_B of the protocol chip U5 through pin D+, electrically connected to pin DM_A of the protocol chip U5 through pin D-, electrically connected to pin CC1 A of the protocol chip U5 through pin CC1, electrically connected to the resistor 21 through pin GND and grounded through the resistor 21; one end of the capacitor C29 is grounded, and the other end is electrically connected to pin VBUS of the second output interface TYPR-C2; one end of the resistor R22 is grounded, and the other end is electrically connected to pin FB of the second DC-DC buck chip U3; one end of the resistor R19 is electrically connected to pin VBUS of the second output interface TYPR-C2, and the other end is electrically connected to pin FB of the second DC-DC buck chip U3; the capacitor C28 is connected in parallel to both ends of the resistor R19.

[0015] The TYPE-C fast charging data cable, wherein: the capacitance value of the capacitor C21 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C22 is 200PF, and the voltage is 25V; the resistance value of the resistor R6 is 20K, and the accuracy is 1%; the resistance value of the resistor R7 is 100K, and the accuracy is 1%; the resistance value of the resistor R8 is 5mR, and the accuracy is 1%.

[0016] The TYPE-C fast charging data cable, wherein: the capacitance value of the capacitor C28 is 200pF, and the voltage is 25V; the capacitance value of the capacitor C29 is 100nF, and the voltage is 25V; the resistance value of the resistor R19 is 100K, and the accuracy is 1%; the resistance value of the resistor R22 is 20K, and the accuracy is 1%; the resistance value of the resistor 21 is 5mR, and the accuracy is 1%.

[0017] The TYPE-C fast charging data cable, wherein: the PD protocol deception module is composed of a PD protocol deception chip U1 and capacitors C7 to C9; the model of the PD protocol deception chip U1 is IP2752, which is grounded through pins GND and EPAD, electrically connected to the power supply VBUS_I N through pin VBUS, electrically connected to the power supply VCC through pin VDD, electrically connected to pin GPIO3 of the protocol chip U5 through pin SCL, electrically connected to pin GPIO0 of the protocol chip U5 through pin SDA, and electrically connected to pin I NT-N is electrically connected to the pin GPIO1 of the protocol chip U5; one end of the capacitor C7 is grounded, and the other end is electrically connected to the pin VDD of the PD protocol deception chip U1; one end of the capacitor C8 is grounded, and the other end is electrically connected to the pin VBUS of the PD protocol deception chip U1; one end of the capacitor C9 is grounded, and the other end is electrically connected to the pin CC1 of the PD protocol deception chip U1; the capacitance value of the capacitor C7 is 1uF, and the voltage is 25V; the capacitance value of the capacitor C8 is 1uF, and the voltage is 25V; the capacitance value of the capacitor C9 is 330pF, and the voltage is 25V;

[0018] The input interface module consists of an input interface TYPE-C, a capacitor C2, and a capacitor C6; the capacitor C2 is a polar capacitor; the model of the input interface TYPE-C is TYPE-C_PAD, which is electrically connected to the pin VI N of the first DC-DC buck chip U2 and the pin VI N of the second DC-DC buck chip U3 through the pin VBUS, electrically connected to the pin CC1 of the PD protocol spoofing chip U1 through the pin CC, and grounded through the pin GND; the capacitor C2 is a polar capacitor, the positive pole of which is electrically connected to the pin VBUS of the input interface TYPE-C, and the negative pole is grounded; one end of the capacitor C6 is grounded, and the other end is electrically connected to the pin VBUS of the input interface TYPE-C; the capacitance value of the capacitor C2 is 100uF, and the voltage is 35V; the capacitance value of the capacitor C6 is 10uF, and the voltage is 35V.

[0019] By adopting the above technical solution, the utility model has the following beneficial effects:

[0020] The TYPE-C fast charging data cable of the utility model has a reasonable structural design. It mainly communicates with the adapter through handshake through the TYPE-C port to obtain the power information of the adapter. It intelligently allocates the output port power according to the device inserted into the TYPE-C port at the output end, and has been adapted to different charging devices. The utility model can be very conveniently used in multiple devices such as smartphones / notebooks / TWS charging warehouses / smart watches, etc.

[0021] This utility model TYPE-C fast charging data cable adopts 1C to 2C design, which can meet the fast charging needs of two electronic devices at the same time (computers, tablets, mobile phones, Switch and other devices). It is a cable product that supports single-port and dual-port fast charging, and can output a maximum of 100W PD2.0 / PD3.1 fast charging protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 This is the structural principle diagram of the TYPE-C fast charging data cable of the utility model;

[0024] Figure 2 This is a circuit diagram of the protocol module of the TYPE-C fast charging data cable of the utility model;

[0025] Figure 3 This is a circuit connection diagram of the first DC-DC buck module and the first output interface module of the TYPE-C fast charging data cable of the utility model;

[0026] Figure 4 This is a circuit connection diagram of the second DC-DC buck module and the second output interface module of the TYPE-C fast charging data cable of the utility model;

[0027] Figure 5 This is a circuit diagram of the PD protocol deception module of the TYPE-C fast charging data cable of the utility model;

[0028] Figure 6 This is a circuit diagram of the input interface module of the TYPE-C fast charging data cable of the utility model. DETAILED DESCRIPTION

[0029] The technical solution of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0030] The present invention will be further explained below in conjunction with specific implementation methods.

[0031] like Figure 1As shown, the TYPE-C fast charging data cable provided in this embodiment includes a protocol module 1, a pair of DC-DC step-down modules 2, a PD protocol spoofing module 3, an input interface module 4, a first output interface module 5 and a second output interface module 6.

[0032] The pair of DC-DC buck modules 2 are connected in series with each other and are both electrically connected to the protocol module 1. The pair of DC-DC buck modules 2 are respectively a first DC-DC buck module 21 and a second DC-DC buck module 22. One end of the PD protocol spoofing module 3 is electrically connected to the protocol module 1, and the other end is electrically connected to the input interface module 4; the input interface module 4 is also electrically connected to the serial connection point of the pair of DC-DC buck modules 2; one end of the first output interface module 5 is electrically connected to the protocol module 1, and the other end is electrically connected to one of the DC-DC buck modules 2; one end of the second output interface module 6 is electrically connected to the protocol module 1, and the other end is electrically connected to the other DC-DC buck module 2.

[0033] The DC-DC outputs of the first output interface module 5 and the second output interface module 6 adopt independent step-down control. Through the first output interface module 5 and the second output interface module 6, dual-port charging can be compatible with faster charging at low voltage while achieving dual-port charging. For example, the C1 device is 9V / 2A, the C2 device can be 5V / 3A, or 15V / 2A, etc., which are independent of each other.

[0034] like Figure 2As shown, the protocol module 1 is composed of a protocol chip U5, resistors R9-R15, and capacitors C23-C25. Among them, the model of the protocol chip U5 is IP2738U, which is grounded through pin GND and pin EPAD; one end of the resistor R9 is electrically connected to pin FB_B of the protocol chip U5, and the other end is electrically connected to the second DC-DC buck module 22; one end of the resistor R10 is electrically connected to pin CMPI B of the protocol chip U5, and the other end is electrically connected to capacitor C24 and electrically connected to the other end of the resistor R9 through capacitor C24; one end of the resistor R11 is electrically connected to pin GPIO2 of the protocol chip U5, and the other end is grounded; one end of the resistor R12 is electrically connected to pin FB_A of the protocol chip U5, and the other end is electrically connected to the first DC-DC buck module 21; one end of the resistor R13 is electrically connected to pin CMPI_A of the protocol chip U5, and the other end is electrically connected to capacitor C25 and electrically connected to the other end of the resistor R12 through capacitor C25; one end of the resistor R14 is electrically connected to pin VI of the protocol chip U5 NA, and the other end is electrically connected to the first DC-DC buck module 21; one end of the resistor 15 is electrically connected to the pin VI NB of the protocol chip U5, and the other end is electrically connected to the second DC-DC buck module 22; one end of the capacitor C23 is grounded, and the other end is electrically connected to the pin VCC of the protocol chip U5. Among them, the resistance value of the resistor R9 is 1K, and the accuracy is 1%; the resistance value of the resistor R10 is 200K, and the accuracy is 1%; the resistance value of the resistor R11 is 10K, and the accuracy is 1%; the resistance value of the resistor R12 is 1K, and the accuracy is 1%; the resistance value of the resistor R13 is 200K, and the accuracy is 1%; the resistance values ​​of the resistor R14 and the resistor R15 are both 2R, and the accuracy is 1%; the capacitance value of the capacitor C23 is 2.2uF, and the voltage is 25V; the capacitance values ​​of the capacitor C24 and the capacitor C25 are both 3.3nF.

[0035] like Figure 3 As shown, the first DC-DC buck module 21 is composed of a first DC-DC buck chip U2, resistors R2-R5, capacitors C10-C16, inductor L1 and field effect transistors Q1-Q2; the field effect transistors Q1-Q2 are all N-MOS field effect transistors; the model of the first DC-DC buck chip U2 is IP6550. Among them, the first DC-DC buck chip U2 is grounded through pins DM, DP, EPAD and PGND, is electrically connected to the input interface module 4 through pins VI N, is electrically connected to the power supply VDD through pin VCC, is electrically connected to the resistor R12 of the protocol module 1 through pin FB, and is electrically connected to the pin FB of the protocol chip U5 of the protocol module 1 through the resistor R12. A, electrically connected to the resistor R14 of the protocol module 1 through the pin VOUT and electrically connected to the pin VI of the protocol chip U5 through the resistor R14 NA; one end of the resistor R2 is grounded, and the other end is electrically connected to the pin EN of the first DC-DC buck chip U2; one end of the capacitor C10 is grounded, and the other end is electrically connected to the pin VCC of the first DC-DC buck chip U2; one end of the capacitor C11 is grounded, and the other end is electrically connected to the pin COMP of the first DC-DC buck chip U2; one end of the capacitor C12 is electrically connected to the pin HVCC of the first DC-DC buck chip U2, and the other end is electrically connected to the pin PGND of the first DC-DC buck chip U2; one end of the capacitor C13 is electrically connected to the pin BST of the first DC-DC buck chip U2, and the other end is electrically connected to the pin LX of the first DC-DC buck chip U2; one end of the capacitor C14 is grounded, and the other end is electrically connected to the resistor R4 and is electrically connected to the pin LX of the first DC-DC buck chip U2 through the resistor R4; the drain of the field effect tube Q1 is electrically connected to the pin VI of the first DC-DC buck chip U2 N, the source is electrically connected to the pin LX of the first DC-DC buck chip U2, the gate is electrically connected to the resistor R3 and is electrically connected to the pin HG of the first DC-DC buck chip U2 through the resistor R3; one end of the capacitor C15 is electrically connected to the drain of the field effect tube Q1, and the other end is grounded; the drain of the field effect tube Q2 is electrically connected to the source of the field effect tube Q1, the source is grounded, the gate is electrically connected to the resistor R5 and is electrically connected to the pin LG of the first DC-DC buck chip U2 through the resistor R5; one end of the inductor L1 is electrically connected to the electrical connection point between the drain of the field effect tube Q2 and the source of the field effect tube Q1, and the other end is electrically connected to the first output interface module 5; the capacitor C16 is a polar capacitor, the positive electrode of which is electrically connected to the resistor R14 of the protocol module 1 and is electrically connected to the pin VI NA of the protocol chip U5 through the resistor R14, and the negative electrode is grounded. Among them, the resistance value of the resistor R2 is 51K, and the accuracy is 1%; the resistance values ​​of the resistor R3 and the resistor R5 are both 2.2R, and the accuracy is 1%; the resistance value of the resistor R4 is 2R, and the accuracy is 1%; the capacitance values ​​of the capacitors C10 and C12 are both 2.2uF, and the voltages are both 25V; the capacitance value of the capacitor C11 is 1nF, and the voltage is 50V; the capacitance value of the capacitor C13 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C14 is 1nF, and the voltage is 50V; the capacitance value of the capacitor C15 is 10uF, and the voltage is 35V; the capacitance value of the capacitor C16 is 100uF, and the voltage is 35V.

[0036] like Figure 3 As shown, the first output interface module 5 is composed of a first output interface TYPR-C1, capacitors C21-C22, and resistors R7-R8. The model of the first output interface TYPR-C1 is TYPR-C PAD, which is electrically connected to the other end of the inductor L1 through the pin VBUS, and is electrically connected to the pin DP of the protocol chip U5 of the protocol module 1 through the pin D+ A, electrically connected to the pin DM_A of the protocol chip U5 of the protocol module 1 through the pin D-, electrically connected to the pin CC1_A of the protocol chip U5 of the protocol module 1 through the pin CC1, electrically connected to the resistor R8 through the pin GND and grounded through the resistor R8. One end of the capacitor C21 is grounded, and the other end is electrically connected to the pin VBUS of the first output interface TYPR-C1; one end of the resistor R6 is grounded, and the other end is electrically connected to the pin FB of the first DC-DC buck chip U2 of the first DC-DC buck module 21; one end of the resistor R7 is electrically connected to the pin VBUS of the first output interface TYPR-C1, and the other end is electrically connected to the pin FB of the first DC-DC buck chip U2 of the first DC-DC buck module 21; the capacitor C22 is connected in parallel to both ends of the resistor R7. Among them, the capacitance value of the capacitor C21 is 100nF and the voltage is 25V; the capacitance value of the capacitor C22 is 200PF and the voltage is 25V; the resistance value of the resistor R6 is 20K and the accuracy is 1%; the resistance value of the resistor R7 is 100K and the accuracy is 1%; the resistance value of the resistor R8 is 5mR and the accuracy is 1%.

[0037] like Figure 4As shown, the second DC-DC buck module 22 is composed of a second DC-DC buck chip U3, resistors R16-R18, resistor R20, capacitors C35-C38, capacitors C26-C27, capacitor C30, inductor L2 and field effect transistors Q3-Q4; the capacitor C30 is a polar capacitor; the field effect transistors Q3-Q4 are all N-MOS field effect transistors; the model of the second DC-DC buck chip U3 is IP6550. Among them, the second DC-DC buck chip U3 is grounded through pins DM, DP, EPAD and PGND, electrically connected to the input interface module 4 through pin VI N, electrically connected to the power supply VDD through pin VCC, electrically connected to the resistor R9 of the protocol module 1 through pin FB and electrically connected to the pin FB_B of the protocol chip U5 of the protocol module 1 through the resistor R9, electrically connected to the resistor R15 of the protocol module 1 through pin VOUT and electrically connected to the pin VI of the protocol chip U5 through the resistor R15. NB; one end of the resistor R18 is grounded, and the other end is electrically connected to the pin EN of the second DC-DC buck chip U3; one end of the capacitor C35 is grounded, and the other end is electrically connected to the pin VCC of the second DC-DC buck chip U3; one end of the capacitor C37 is grounded, and the other end is electrically connected to the pin COMP of the second DC-DC buck chip U3; one end of the capacitor C38 is electrically connected to the pin HVCC of the second DC-DC buck chip U3, and the other end is electrically connected to the pin PGND of the second DC-DC buck chip U3; one end of the capacitor C27 is electrically connected to the pin BST of the second DC-DC buck chip U3, and the other end is electrically connected to the pin LX of the second DC-DC buck chip U3; one end of the capacitor C36 is grounded, and the other end is electrically connected to the resistor R17 and is electrically connected to the pin LX of the second DC-DC buck chip U3 through the resistor R17; the drain of the field effect transistor Q3 is electrically connected to the pin VI of the second DC-DC buck chip U3 N, the source is electrically connected to the pin LX of the second DC-DC buck chip U3, the gate is electrically connected to the resistor R16 and is electrically connected to the pin HG of the second DC-DC buck chip U3 through the resistor R16; one end of the capacitor C26 is electrically connected to the drain of the field effect tube Q3, and the other end is grounded; the drain of the field effect tube Q4 is electrically connected to the source of the field effect tube Q3, the source is grounded, the gate is electrically connected to the resistor R20 and is electrically connected to the pin LG of the second DC-DC buck chip U3 through the resistor R20; one end of the inductor L2 is electrically connected to the electrical connection point between the drain of the field effect tube Q4 and the source of the field effect tube Q3, and the other end is electrically connected to the second output interface module 6; the capacitor C30 is a polar capacitor, the positive electrode of which is electrically connected to the resistor R15 of the protocol module 1 and is electrically connected to the pin VINB of the protocol chip U5 through the resistor R15, and the negative electrode is grounded.Among them, the resistance value of the resistor R16 is 2.2R, and the accuracy is 1%; the resistance value of the resistor R17 is 2R, and the accuracy is 1%; the resistance value of the resistor R18 is 51K, and the accuracy is 1%; the resistance value of the resistor R20 is 2.2R, and the accuracy is 1%; the capacitance value of the capacitor C35 is 2.2uF, and the voltage is 25V; the capacitance values ​​of the capacitors C36 and C37 are both 1nF, and the voltage is 50V; the capacitance value of the capacitor C38 is 2.2uF, and the voltage is 25V; the capacitance value of the capacitor C26 is 10uF, and the voltage is 35V; the capacitance value of the capacitor C27 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C30 is 100uF, and the voltage is 35V.

[0038] like Figure 4 As shown, the second output interface module 6 is composed of a second output interface TYPR-C2, capacitors C28-C29, resistors R19, and resistors R21-R22. The model of the second output interface TYPR-C2 is TYPR-C PAD, which is electrically connected to the other end of the inductor L2 through the pin VBUS, electrically connected to the pin DP_B of the protocol chip U5 of the protocol module 1 through the pin D+, electrically connected to the pin DM_A of the protocol chip U5 of the protocol module 1 through the pin D-, electrically connected to the pin CC1 A of the protocol chip U5 of the protocol module 1 through the pin CC1, and electrically connected to the resistor 21 through the pin GND and grounded through the resistor 21. One end of the capacitor C29 is grounded, and the other end is electrically connected to the pin VBUS of the second output interface TYPR-C2; one end of the resistor R22 is grounded, and the other end is electrically connected to the pin FB of the second DC-DC buck chip U3 of the second DC-DC buck module 22; one end of the resistor R19 is electrically connected to the pin VBUS of the second output interface TYPR-C2, and the other end is electrically connected to the pin FB of the second DC-DC buck chip U3 of the second DC-DC buck module 22; the capacitor C28 is connected in parallel to the two ends of the resistor R19. Among them, the capacitance value of the capacitor C28 is 200pF and the voltage is 25V; the capacitance value of the capacitor C29 is 100nF and the voltage is 25V; the resistance value of the resistor R19 is 100K and the accuracy is 1%; the resistance value of the resistor R22 is 20K and the accuracy is 1%; the resistance value of the resistor 21 is 5mR and the accuracy is 1%.

[0039] like Figure 5As shown, the PD protocol deception module 3 is composed of a PD protocol deception chip U1 and capacitors C7 to C9. The model of the PD protocol deception chip U1 is IP2752, which is grounded through pins GND and EPAD, electrically connected to the input interface module 4 through pin VBUS, electrically connected to the power supply VCC through pin VDD, electrically connected to pin GPIO3 of the protocol chip U5 of the protocol module 1 through pin SCL, electrically connected to pin GPIO0 of the protocol chip U5 of the protocol module 1 through pin SDA, and electrically connected to pin GPIO1 of the protocol chip U5 of the protocol module 1 through pin I NT-N; one end of the capacitor C7 is grounded, and the other end is electrically connected to pin VDD of the PD protocol deception chip U1; one end of the capacitor C8 is grounded, and the other end is electrically connected to pin VBUS of the PD protocol deception chip U1; one end of the capacitor C9 is grounded, and the other end is electrically connected to pin CC1 of the PD protocol deception chip U1. The capacitance value of the capacitor C7 is 1uF, and the voltage is 25V; the capacitance value of the capacitor C8 is 1uF, and the voltage is 25V; the capacitance value of the capacitor C9 is 330pF, and the voltage is 25V.

[0040] like Figure 6 As shown, the input interface module 4 is composed of an input interface TYPE-C, a capacitor C2, and a capacitor C6; the capacitor C2 is a polarized capacitor. PAD, which is electrically connected to the pin VI N of the first DC-DC buck chip U2 of the first DC-DC buck module 21 and the pin VI N of the second DC-DC buck chip U3 of the second DC-DC buck module 22 through the pin VBUS; the input interface TYPE-C is also electrically connected to the pin CC1 of the PD protocol deception chip U1 of the PD protocol deception module 3 through the pin CC, and is grounded through the pin GND; the capacitor C2 is a polar capacitor, the positive electrode of which is electrically connected to the pin VBUS of the input interface TYPE-C, and the negative electrode is grounded; one end of the capacitor C6 is grounded, and the other end is electrically connected to the pin VBUS of the input interface TYPE-C. The capacitance value of the capacitor C2 is 100uF, and the voltage is 35V; the capacitance value of the capacitor C6 is 10uF, and the voltage is 35V.

[0041] The utility model has a reasonable structural design. It mainly communicates with the adapter through handshake via the TYPE-C port to obtain the power information of the adapter. It intelligently distributes the output port power according to the device inserted into the TYPE-C port at the output end. It can be adapted to different charging devices and is very convenient to use in multiple devices such as smartphones / notebooks / TWS charging bins / smart watches, etc.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A TYPE-C fast charging data cable, comprising a protocol module (1), a DC-DC buck module (2), a PD protocol decoy module (3), an input interface module (4) and an output interface module; one end of the PD protocol decoy module (3) is electrically connected to the protocol module (1), and the other end is electrically connected to the input interface module (4); one end of the DC-DC buck module (2) is electrically connected to the protocol module (1), and the other end is electrically connected to the output interface module; characterized in that: The DC-DC step-down module (2) comprises a pair of a first DC-DC step-down module (21) and a second DC-DC step-down module (22) connected in series with each other; The first DC-DC step-down module (21) and the second DC-DC step-down module (22) are both electrically connected to the protocol module (1); the input interface module (4) is electrically connected to the first DC-DC step-down module (21) and the second DC-DC step-down module (22) respectively; The output interface module comprises a first output interface module (5) and a second output interface module (6); one end of the first output interface module (5) is electrically connected to the protocol module (1), and the other end is electrically connected to the first DC-DC step-down module (21); one end of the second output interface module (6) is electrically connected to the protocol module (1), and the other end is electrically connected to the second DC-DC step-down module (22); The DC-DC outputs of the first output interface module (5) and the second output interface module (6) adopt independent voltage reduction control.

2. The TYPE-C fast charging data cable according to claim 1, characterized in that: The protocol module (1) is composed of a protocol chip U5, resistors R9-R15, and capacitors C23-C25; The model of the protocol chip U5 is IP2738U, which is grounded through the pin GND and the pin EPAD; one end of the resistor R9 is electrically connected to the pin FB_B of the protocol chip U5, and the other end is electrically connected to the second DC-DC buck module (22); one end of the resistor R10 is electrically connected to the pin CMPI_B of the protocol chip U5, and the other end is electrically connected to the capacitor C24 and is electrically connected to the other end of the resistor R9 through the capacitor C24; one end of the resistor R11 is electrically connected to the pin GPIO2 of the protocol chip U5, and the other end is grounded; one end of the resistor R12 is electrically connected to the pin FB_A of the protocol chip U5, and the other end is electrically connected to the second DC-DC buck module (22); The first DC-DC step-down module (21) is connected; one end of the resistor R13 is electrically connected to the pin CMPI_A of the protocol chip U5, and the other end is electrically connected to the capacitor C25 and electrically connected to the other end of the resistor R12 through the capacitor C25; one end of the resistor R14 is electrically connected to the pin VINA of the protocol chip U5, and the other end is electrically connected to the first DC-DC step-down module (21); one end of the resistor 15 is electrically connected to the pin VINB of the protocol chip U5, and the other end is electrically connected to the second DC-DC step-down module (22); one end of the capacitor C23 is grounded, and the other end is electrically connected to the pin VCC of the protocol chip U5.

3. The TYPE-C fast charging data cable according to claim 2, characterized in that: The resistance value of the resistor R9 is 1K, and the accuracy is 1%; the resistance value of the resistor R10 is 200K, and the accuracy is 1%; the resistance value of the resistor R11 is 10K, and the accuracy is 1%; the resistance value of the resistor R12 is 1K, and the accuracy is 1%; the resistance value of the resistor R13 is 200K, and the accuracy is 1%; the resistance values ​​of the resistor R14 and the resistor R15 are both 2R, and the accuracy is both 1%; the capacitance value of the capacitor C23 is 2.2uF, and the voltage is 25V; the capacitance values ​​of the capacitor C24 and the capacitor C25 are both 3.3nF.

4. The TYPE-C fast charging data cable according to claim 2, characterized in that: The first DC-DC buck module (21) comprises a first DC-DC buck chip U2, resistors R2-R5, capacitors C10-C16, an inductor L1 and field effect transistors Q1-Q2; the field effect transistors Q1-Q2 are all N-MOS field effect transistors; the model of the first DC-DC buck chip U2 is IP6550; The first DC-DC buck chip U2 is grounded through pins DM, DP, EPAD and PGND, electrically connected to the power supply VBUS_IN through pin VIN, electrically connected to the power supply VDD through pin VCC, electrically connected to the resistor R12 through pin FB and electrically connected to the pin FB_A of the protocol chip U5 through the resistor R12, electrically connected to the resistor R14 through pin VOUT and electrically connected to the pin VINA of the protocol chip U5 through the resistor R14; one end of the resistor R2 is grounded, and the other end is electrically connected to the first DC-DC buck chip The first DC-DC buck chip U2 has a pin EN; one end of the capacitor C10 is grounded, and the other end is electrically connected to the pin VCC of the first DC-DC buck chip U2; one end of the capacitor C11 is grounded, and the other end is electrically connected to the pin COMP of the first DC-DC buck chip U2; one end of the capacitor C12 is electrically connected to the pin HVCC of the first DC-DC buck chip U2, and the other end is electrically connected to the pin PGND of the first DC-DC buck chip U2; one end of the capacitor C13 is electrically connected to the pin BST of the first DC-DC buck chip U2, and the other end is electrically connected to the pin BST of the first DC-DC buck chip U2. The pin LX of the DC-DC buck chip U2; one end of the capacitor C14 is grounded, and the other end is electrically connected to the resistor R4 and electrically connected to the pin LX of the first DC-DC buck chip U2 through the resistor R4; the drain of the field effect tube Q1 is electrically connected to the pin VIN of the first DC-DC buck chip U2, the source is electrically connected to the pin LX of the first DC-DC buck chip U2, the gate is electrically connected to the resistor R3 and is electrically connected to the pin HG of the first DC-DC buck chip U2 through the resistor R3; one end of the capacitor C15 is electrically connected to the drain of the field effect tube Q1 , and the other end is grounded; the source of the field effect tube Q2 is grounded, the drain is electrically connected to the source of the field effect tube Q1, the gate is electrically connected to the resistor R5 and is electrically connected to the pin LG of the first DC-DC buck chip U2 through the resistor R5; one end of the inductor L1 is electrically connected to the electrical connection point between the drain of the field effect tube Q2 and the source of the field effect tube Q1, and the other end is electrically connected to the first output interface module (5); the capacitor C16 is a polar capacitor, the positive electrode of which is electrically connected to the resistor R14 and is electrically connected to the pin VINA of the protocol chip U5 through the resistor R14, and the negative electrode is grounded; The second DC-DC buck module (22) is composed of a second DC-DC buck chip U3, resistors R16-R18, a resistor R20, capacitors C35-C38, capacitors C26-C27, a capacitor C30, an inductor L2 and field effect transistors Q3-Q4; the capacitor C30 is a polar capacitor; the field effect transistors Q3-Q4 are all N-MOS field effect transistors; the model of the second DC-DC buck chip U3 is IP6550; The second DC-DC buck chip U3 is grounded through pins DM, DP, EPAD and PGND, electrically connected to the power supply VBUS_IN through pin VIN, electrically connected to the power supply VDD through pin VCC, electrically connected to the resistor R9 through pin FB and electrically connected to pin FB_B of the protocol chip U5 through the resistor R9, electrically connected to the resistor R15 through pin VOUT and electrically connected to pin VINB of the protocol chip U5 through the resistor R15; one end of the resistor R18 is grounded, and the other end is electrically connected to the second DC-DC buck chip U3 One end of the capacitor C35 is grounded, and the other end is electrically connected to the pin VCC of the second DC-DC buck chip U3; one end of the capacitor C37 is grounded, and the other end is electrically connected to the pin COMP of the second DC-DC buck chip U3; one end of the capacitor C38 is electrically connected to the pin HVCC of the second DC-DC buck chip U3, and the other end is electrically connected to the pin PGND of the second DC-DC buck chip U3; one end of the capacitor C27 is electrically connected to the pin BST of the second DC-DC buck chip U3, and the other end is electrically connected to the pin BST of the second DC-DC buck chip U3 The pin LX of the second DC-DC buck chip U3 is connected to the pin LX of the second DC-DC buck chip U3; one end of the capacitor C36 is grounded, and the other end is electrically connected to the resistor R17 and electrically connected to the pin LX of the second DC-DC buck chip U3 through the resistor R17; the drain of the field effect tube Q3 is electrically connected to the pin VIN of the second DC-DC buck chip U3, the source is electrically connected to the pin LX of the second DC-DC buck chip U3, the gate is electrically connected to the resistor R16 and electrically connected to the pin HG of the second DC-DC buck chip U3 through the resistor R16; one end of the capacitor C26 is electrically connected to the drain of the field effect tube Q3, and the other end is electrically connected to the pin VIN of the second DC-DC buck chip U3, the source is electrically connected to the pin LX of the second DC-DC buck chip U3, the gate is electrically connected to the resistor R16 and electrically connected to the pin HG of the second DC-DC buck chip U3 through the resistor R16; One end is grounded; the drain of the field effect transistor Q4 is electrically connected to the source of the field effect transistor Q3, the source is grounded, and the gate is electrically connected to the resistor R20 and electrically connected to the pin LG of the second DC-DC buck chip U3 through the resistor R20; one end of the inductor L2 is electrically connected to the electrical connection point between the drain of the field effect transistor Q4 and the source of the field effect transistor Q3, and the other end is electrically connected to the second output interface module (6); the capacitor C30 is a polar capacitor, the positive electrode of which is electrically connected to the resistor R15 and electrically connected to the pin VINB of the protocol chip U5 through the resistor R15, and the negative electrode is grounded.

5. The TYPE-C fast charging data cable according to claim 4, characterized in that: The resistance value of the resistor R2 is 51K, and the accuracy is 1%; the resistance values ​​of the resistor R3 and the resistor R5 are both 2.2R, and the accuracy is 1%; the resistance value of the resistor R4 is 2R, and the accuracy is 1%; the capacitance values ​​of the capacitors C10 and C12 are both 2.2uF, and the voltages are both 25V; the capacitance value of the capacitor C11 is 1nF, and the voltage is 50V; the capacitance value of the capacitor C13 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C14 is 1nF, and the voltage is 50V; the capacitance value of the capacitor C15 is 10uF, and the voltage is 35V; the capacitance value of the capacitor C16 is 100uF, and the voltage is 35V.

6. The TYPE-C fast charging data cable according to claim 4, characterized in that: The resistance value of the resistor R16 is 2.2R, and the accuracy is 1%; the resistance value of the resistor R17 is 2R, and the accuracy is 1%; the resistance value of the resistor R18 is 51K, and the accuracy is 1%; the resistance value of the resistor R20 is 2.2R, and the accuracy is 1%; the capacitance value of the capacitor C35 is 2.2uF, and the voltage is 25V; the capacitance values ​​of the capacitors C36 and C37 are both 1nF, and the voltage is 50V; the capacitance value of the capacitor C38 is 2.2uF, and the voltage is 25V; the capacitance value of the capacitor C26 is 10uF, and the voltage is 35V; the capacitance value of the capacitor C27 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C30 is 100uF, and the voltage is 35V.

7. The TYPE-C fast charging data cable according to claim 4, characterized in that: The first output interface module (5) is composed of a first output interface TYPR-C1, capacitors C21-C22, and resistors R7-R8; the model of the first output interface TYPR-C1 is TYPR-C_PAD, which is electrically connected to the other end of the inductor L1 through the pin VBUS, electrically connected to the pin DP_A of the protocol chip U5 through the pin D+, electrically connected to the pin DM_A of the protocol chip U5 through the pin D-, electrically connected to the pin CC1_A of the protocol chip U5 through the pin CC1, and electrically connected to the resistor R8 through the pin GND and grounded through the resistor R8; one end of the capacitor C21 is grounded, and the other end is electrically connected to the pin VBUS of the first output interface TYPR-C1; one end of the resistor R6 is grounded, and the other end is electrically connected to the pin FB of the first DC-DC buck chip U2; one end of the resistor R7 is electrically connected to the pin VBUS of the first output interface TYPR-C1, and the other end is electrically connected to the pin FB of the first DC-DC buck chip U2; the capacitor C22 is connected in parallel to the two ends of the resistor R7; The second output interface module (6) is composed of a second output interface TYPR-C2, capacitors C28-C29, a resistor R19, and resistors R21-R22; the model of the second output interface TYPR-C2 is TYPR-CPAD, which is electrically connected to the other end of the inductor L2 through the pin VBUS, electrically connected to the pin DP_B of the protocol chip U5 through the pin D+, electrically connected to the pin DM_A of the protocol chip U5 through the pin D-, electrically connected to the pin CC1_A of the protocol chip U5 through the pin CC1, and electrically connected to the pin G ND is electrically connected to the resistor 21 and grounded through the resistor 21; one end of the capacitor C29 is grounded, and the other end is electrically connected to the pin VBUS of the second output interface TYPR-C2; one end of the resistor R22 is grounded, and the other end is electrically connected to the pin FB of the second DC-DC buck chip U3; one end of the resistor R19 is electrically connected to the pin VBUS of the second output interface TYPR-C2, and the other end is electrically connected to the pin FB of the second DC-DC buck chip U3; the capacitor C28 is connected in parallel to both ends of the resistor R19.

8. The TYPE-C fast charging data cable according to claim 7, characterized in that: The capacitance value of the capacitor C21 is 100nF, and the voltage is 25V; the capacitance value of the capacitor C22 is 200PF, and the voltage is 25V; the resistance value of the resistor R6 is 20K, and the accuracy is 1%; the resistance value of the resistor R7 is 100K, and the accuracy is 1%; the resistance value of the resistor R8 is 5mR, and the accuracy is 1%.

9. The TYPE-C fast charging data cable according to claim 7, characterized in that: The capacitance value of the capacitor C28 is 200pF, and the voltage is 25V; the capacitance value of the capacitor C29 is 100nF, and the voltage is 25V; the resistance value of the resistor R19 is 100K, and the accuracy is 1%; the resistance value of the resistor R22 is 20K, and the accuracy is 1%; the resistance value of the resistor 21 is 5mR, and the accuracy is 1%.

10. The TYPE-C fast charging data cable according to claim 4, characterized in that: The PD protocol deception module (3) is composed of a PD protocol deception chip U1 and capacitors C7 to C9; the model of the PD protocol deception chip U1 is IP2752, which is grounded through pins GND and EPAD, electrically connected to a power supply VBUS_IN through a pin VBUS, electrically connected to a power supply VCC through a pin VDD, electrically connected to a pin GPIO3 of the protocol chip U5 through a pin SCL, electrically connected to a pin GPIO0 of the protocol chip U5 through a pin SDA, and electrically connected to a pin INT-N of the protocol chip U5. Pin GPIO1; one end of the capacitor C7 is grounded, and the other end is electrically connected to the pin VDD of the PD protocol deception chip U1; one end of the capacitor C8 is grounded, and the other end is electrically connected to the pin VBUS of the PD protocol deception chip U1; one end of the capacitor C9 is grounded, and the other end is electrically connected to the pin CC1 of the PD protocol deception chip U1; the capacitance value of the capacitor C7 is 1uF, and the voltage is 25V; the capacitance value of the capacitor C8 is 1uF, and the voltage is 25V; the capacitance value of the capacitor C9 is 330pF, and the voltage is 25V; The input interface module (4) is composed of an input interface TYPE-C, a capacitor C2, and a capacitor C6; the capacitor C2 is a polar capacitor; the model of the input interface TYPE-C is TYPE-C_PAD, which is electrically connected to the pin VIN of the first DC-DC buck chip U2 and the pin VIN of the second DC-DC buck chip U3 through the pin VBUS, electrically connected to the pin CC1 of the PD protocol deception chip U1 through the pin CC, and grounded through the pin GND; the capacitor C2 is a polar capacitor, the positive electrode of which is electrically connected to the pin VBUS of the input interface TYPE-C, and the negative electrode is grounded; one end of the capacitor C6 is grounded, and the other end is electrically connected to the pin VBUS of the input interface TYPE-C; the capacitance value of the capacitor C2 is 100uF, and the voltage is 35V; the capacitance value of the capacitor C6 is 10uF, and the voltage is 35V.

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