Radio frequency switching power supply switching circuit, power supply management circuit and radio frequency chip

Abstract

The utility model relates to the technical field of radio frequency switching power supplies, and discloses a radio frequency switching power supply switching circuit, a power supply management circuit and a radio frequency chip, the radio frequency switching power supply switching circuit comprises a power supply detection unit and an output unit; the power supply detection unit comprises a resistor R1, a resistor R2, a resistor R3, an MOS tube MP1, a voltage drop unit and a signal processing unit; the output unit comprises a second signal processing unit, a first switch unit and a second switch unit; when in use, whether the power supply VIO and the power supply VLDO are connected or not is checked by arranging the power supply detection unit, and the on-off of the first switch unit and the second switch unit is controlled by a selection signal SEL and a control signal, so that the selective output of the power supply VIO and the power supply VLDO is realized, and the power supply switching circuit is compatible with single power supply input and dual power supply input.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency switching power supplies, and in particular to a radio frequency switching power supply switching circuit, a power management circuit and a radio frequency chip. Background Art

[0002] With the continuous development of technology, the demand for RF front-end devices such as power amplifiers, active antenna tuners, low noise amplifiers and antenna switches is increasing. For equipment manufacturers, controlling all RF front-end devices will be a huge challenge.

[0003] At present, the control routing of RF front-end terminal chips generally adopts MIPI bus control; at the same time, GPIO control routing also exists on some RF front-end terminal chips.

[0004] For GPIO control, it is powered by a separate power supply plus some control bit signal routing; the structure of its power management circuit is as follows Figure 2 As shown, the MIPI protocol demodulation module is used to input an enable signal EN to the RF switch module when the power supply VIO is input. The enable signal EN is used to determine whether the RF switch module can perform RF switch selection. In addition, the control signal VCTRL output by the MIPI protocol demodulation module is used to select the RF channel in the RF switch module for RF signal transmission.

[0005] For the MIPI bus control mode, in addition to the power supply VIO specified by the MIPI protocol, there is also a power supply VDD, that is, there are two current sources for power supply, which increases the resource pressure of the system board power routing;

[0006] In addition, the structure of the power management circuit corresponding to the MIPI bus control method is as follows Figure 1 As shown, the MIPI protocol demodulation module is used to input an enable signal EN to the RF switch module and the power supply module respectively when the power supply VIO is input, and the power supply module outputs a voltage VLDO when the power supply VDD and the enable signal EN are input;

[0007] Combination Figure 1 and Figure 2 The existing power management circuit cannot be compatible with single power supply VIO and dual power supply input at the same time, and cannot perform switching selection. Utility Model Content

[0008] In view of the shortcomings of the background technology, the utility model provides a radio frequency switch power switching circuit, a power management circuit and a radio frequency chip. The technical problem to be solved is that the power management circuit in the existing radio frequency chip can only meet single power input or dual power input, and is not compatible with these two solutions.

[0009] To solve the above technical problems, in a first aspect, the utility model provides the following technical solutions: a radio frequency switch power supply switching circuit, comprising a power supply detection unit and an output unit;

[0010] The power detection unit includes a resistor R1, a resistor R2, a resistor R3, a MOS tube MP1, a voltage drop unit and a signal processing unit. One end of the resistor R1 is electrically connected to the source of the MOS tube MP1 and is used to input the power supply VIO. The other end of the resistor R1 is electrically connected to one end of the resistor R2 and the gate of the MOS tube MP1 respectively, and is grounded through the voltage drop unit. The other end of the resistor R2 is used to input the power supply VLDO. The drain of the MOS tube MP1 is grounded through the resistor R3 and is electrically connected to the signal processing unit. The signal processing unit is used to perform two inversion processes on the input signal and output a selection signal SEL.

[0011] The output unit includes a second signal processing unit, a first switch unit, and a second switch unit. The input end of the first switch unit is used to input a power supply VIO, and the input end of the second switch unit is used to input a power supply VLDO. The output end of the first switch unit is electrically connected to the output end of the second switch unit. The selection signal SEL is input to the first switch unit to control the on and off of the first switch unit. The second signal processing unit is used to invert the selection signal SEL and input a control signal to the second switch unit. The control signal is used to control the on and off of the second switch unit.

[0012] In some implementation manner of the first aspect, the first switch unit is turned on when the selection signal SEL is at a high level, and is turned off when the selection signal SEL is at a low level.

[0013] In a certain implementation manner of the first aspect, the first switch unit includes a MOS transistor MN1, a MOS transistor MP2 and a resistor R4, the drain of the MOS transistor MP2 is the input end of the first switch unit, the source of the MOS transistor MP2 is the output end of the first switch unit, and is electrically connected to the gate of the MOS transistor MP2 and the drain of the MOS transistor MN1 respectively through the resistor R4, the selection signal SEL is input to the gate of the MOS transistor MN1, and the source of the MOS transistor MN1 is grounded.

[0014] In some implementation manner of the first aspect, the second switch unit is turned on when the control signal is at a high level, and is turned off when the control signal is at a low level.

[0015] In a certain implementation of the first aspect, the second switch unit includes a MOS transistor MN2, a MOS transistor MP3 and a resistor R5, the drain of the MOS transistor MP3 is the input end of the second switch unit, the source of the MOS transistor MP3 is the output end of the second switch unit, and is electrically connected to the gate of the MOS transistor MP3 and the drain of the MOS transistor MN2 respectively through the resistor R5, the control signal is input to the gate of the MOS transistor MN2, and the source of the MOS transistor MN2 is grounded.

[0016] In a certain implementation of the first aspect, the voltage drop unit includes four diodes connected in series in sequence, one end of the resistor R2 is electrically connected to the anode of the head-end diode, and the cathode of the terminal diode is grounded.

[0017] In a certain embodiment of the first aspect, the signal processing unit includes a first inverter and a second inverter, the input end of the first inverter is electrically connected to one end of the resistor R3, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter outputs the selection signal SEL.

[0018] In a certain implementation of the first aspect, the second signal processing unit includes a third inverter, the input end of the third inverter inputs the selection signal SEL, and the output end of the third inverter outputs the control signal.

[0019] In a second aspect, the utility model provides a power management circuit, including a MIPI protocol demodulation module, a power supply module and a radio frequency switch module, wherein the MIPI protocol demodulation module is used to input an enable signal EN to the power supply module and the radio frequency switch module respectively when a power supply VIO is input, and the MIPI protocol demodulation module is electrically connected to the radio frequency switch module, and inputs a radio frequency control signal VCTRL to the radio frequency switch module.

[0020] It also includes the above-mentioned RF switch power switching circuit, the power supply module is used to input power VLDO to the RF switch power switching circuit when the power supply VDD and the enable signal EN are input, and the output end of the first switch unit is electrically connected to the RF switch module to provide a voltage Vcon to the RF switch module.

[0021] In a third aspect, the utility model further provides a radio frequency chip, on which the above-mentioned power management circuit is provided.

[0022] Compared with the prior art, the utility model has the following beneficial effects: the utility model checks whether the power supply VIO and the power supply VLDO are connected by setting a power supply detection unit, and controls the on and off of the first switch unit and the second switch unit by selecting a signal SEL and a control signal, thereby realizing the selection output of the power supply VIO and the power supply VLDO, so that the utility model can be compatible with single power supply and dual power supply input;

[0023] In addition, the power supply VIO not only supplies power to the MIPI protocol-related digital circuit modules, but also supplies power to the analog controller circuit, thereby saving system routing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of an existing power management circuit with dual power input;

[0025] Figure 2 A schematic diagram of the structure of an existing power management circuit with a single power input;

[0026] Figure 3 It is a structural schematic diagram of the radio frequency switch power supply switching circuit of the utility model;

[0027] Figure 4 It is a structural schematic diagram of the power management circuit of the utility model. DETAILED DESCRIPTION

[0028] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0029] Embodiment 1

[0030] like Figure 3 As shown, this embodiment provides a radio frequency switch power switching circuit, including a power detection unit 10 and an output unit 11;

[0031] The power detection unit 10 includes a resistor R1, a resistor R2, a resistor R3, a MOS tube MP1, a voltage drop unit 100 and a signal processing unit 101. One end of the resistor R1 is electrically connected to the source of the MOS tube MP1 for inputting a power source VIO. The other end of the resistor R1 is electrically connected to one end of the resistor R2 and the gate of the MOS tube MP1 respectively, and is grounded through the voltage drop unit 100. The other end of the resistor R2 is used for inputting a power source VLDO. The drain of the MOS tube MP1 is grounded through the resistor R3 and is electrically connected to the signal processing unit 101. The signal processing unit 101 is used for performing two inversion processes on the input signal and outputting a selection signal SEL. In addition, the MOS tube MP1 is a PMOS tube.

[0032] The output unit 11 includes a second signal processing unit 112, a first switch unit 110 and a second switch unit 111. The input end of the first switch unit 110 is used to input a power supply VIO, and the input end of the second switch unit 111 is used to input a power supply VLDO. The output end of the first switch unit 110 is electrically connected to the output end of the second switch unit 111. The selection signal SEL is input to the first switch unit 110 to control the on and off of the first switch unit 110. The second signal processing unit 112 is used to invert the selection signal SEL and input a control signal to the second switch unit 111. The control signal is used to control the on and off of the second switch unit 111.

[0033] Specifically, in this embodiment, the first switch unit 110 is turned on when the selection signal SEL is at a high level, and is turned off when the selection signal SEL is at a low level.

[0034] More specifically, in Figure 3 In the embodiment, the first switch unit 110 includes a MOS transistor MN1, a MOS transistor MP2 and a resistor R4, the drain of the MOS transistor MP2 is the input end of the first switch unit 110, the source of the MOS transistor MP2 is the output end of the first switch unit 110, and is electrically connected to the gate of the MOS transistor MP2 and the drain of the MOS transistor MN1 through the resistor R4, the selection signal SEL is input to the gate of the MOS transistor MN1, and the source of the MOS transistor MN1 is grounded.

[0035] The MOS tube MN1 is an NMOS tube, and the MOS tube MP2 is a PMOS tube.

[0036] In actual use, when the selection signal SEL is at a high level, the MOS transistor MN1 is turned on, and the turned-on MOS transistor MN1 pulls down the gate potential of the MOS transistor MP2, so that when the drain of the MOS transistor MP2 is connected to the power supply VIO, the MOS transistor MP2 is turned on.

[0037] Specifically, in this embodiment, the second switch unit 111 is turned on when the control signal is at a high level, and is turned off when the control signal is at a low level.

[0038] More specifically, in Figure 3 In the embodiment, the second switch unit 111 includes a MOS transistor MN2, a MOS transistor MP3 and a resistor R5, the drain of the MOS transistor MP3 is the input end of the second switch unit 111, the source of the MOS transistor MP3 is the output end of the second switch unit 111, and is respectively electrically connected to the gate of the MOS transistor MP3 and the drain of the MOS transistor MN2 through the resistor R5, the control signal is input to the gate of the MOS transistor MN2, and the source of the MOS transistor MN2 is grounded.

[0039] The MOS tube MN2 is an NMOS tube, and the MOS tube MP3 is a PMOS tube.

[0040] In actual use, when the control signal is at a high level, the MOS tube MN2 is turned on, and the turned-on MOS tube MN2 pulls down the gate potential of the MOS tube MP3, so that when the drain of the MOS tube MP3 is connected to the power supply VLDO, the MOS tube MP3 is turned on.

[0041] Specifically, in this embodiment, the voltage drop unit 100 includes four diodes connected in series, namely diode D1, diode D2, diode D3 and diode D4, one end of the resistor R2 is electrically connected to the anode of the head diode D1, and the cathode of the terminal diode D4 is grounded.

[0042] In actual use, the voltage drop unit 100 is used to provide a fixed conduction voltage drop. When the gate voltage of the MOS tube MP1 is greater than the conduction voltage drop, the voltage drop unit 100 is turned on. In addition, the voltage drop of a common single diode is 0.7V, so the conduction voltage drop of the voltage drop unit 100 is 2.8V.

[0043] In some implementations, the number of diodes connected in series in the voltage drop unit 100 may be increased or decreased according to actual needs, thereby providing different conduction voltage drops.

[0044] Specifically, in this embodiment, the signal processing unit 101 includes a first inverter and a second inverter, the input end of the first inverter is electrically connected to one end of the resistor R3, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter outputs the selection signal SEL. In actual use, the drain signal of the MOS tube MP1 is inverted twice by the first inverter and the second inverter.

[0045] Specifically, in this embodiment, the second signal processing unit 112 includes a third inverter, an input terminal of the third inverter inputs the selection signal SEL, and an output terminal of the third inverter outputs the control signal.

[0046] In actual use, the switching circuit in this embodiment checks whether the power supply VIO and the power supply VLDO are connected by setting the power supply detection unit 10, and controls the on and off of the first switch unit 110 and the second switch unit 111 by selecting the signal SEL and the control signal, thereby realizing the selection output of the power supply VIO and the power supply VLDO, so that the utility model can be compatible with single power supply and dual power supply input.

[0047] Embodiment 2

[0048] like Figure 4As shown, this embodiment provides a power management circuit, including a MIPI protocol demodulation module 2, a power supply module 3 and a radio frequency switch module 4. The MIPI protocol demodulation module 2 is used to input an enable signal EN to the power supply module 3 and the radio frequency switch module 4 respectively when there is a power supply VIO input. The MIPI protocol demodulation module 2 is electrically connected to the radio frequency switch module 4, and inputs a radio frequency control signal VCTRL to the radio frequency switch module 4.

[0049] It also includes the RF switch power switching circuit 1 in the first embodiment, the power supply module 3 is used to input the power supply VLDO to the RF switch power switching circuit 1 when the power supply VDD and the enable signal EN are input, and the output end of the first switch unit 100 is electrically connected to the RF switch module 4, and is used to provide the voltage Vcon to the RF switch module 4.

[0050] In this embodiment, the voltage amplitude of the common power supply VIO is between 1.6V and 2V, and the voltage amplitude of the common power supply VDD is between 1.6V and 5V.

[0051] Figure 4 The working process of the circuit is as follows:

[0052] When the power supply VIO and the power supply VDD are not connected, the power supply VLDO is 0 and the voltage Vcon is also 0;

[0053] When the power source VIO is connected and the power source VDD is not connected, the power source VLDO is 0V, at this time, the MOS tube MP1 is turned on, the selection signal SEL is at a high level, the MOS tube MN1 and the MOS tube MP2 are both turned on, the first switch unit 110 is turned on, and the voltage Vcon is connected to the power source VIO; in addition, the control signal is at a low level, the MOS tube MN2 and the MOS tube MP3 are both turned off, and the second switch unit 111 is turned off;

[0054] When the power supply VIO is not connected and the power supply VDD is connected, the enable signal EN is at a level, the power supply VLDO is 0V, the voltage Vcon is also 0, and the RF switch module 4 is closed without power input;

[0055] When the power supply VIO and the power supply VDD are connected at the same time, the power supply VLDO outputs about 2.5V. Since the RF switch generally adopts the SOI process of 2.5V devices, the performance of the RF switch manufactured by the SOI process can only be reflected when the bias voltage is higher than a certain value. The voltage Vcon is connected to the power supply VLDO to power the RF switch module 4.

[0056] In combination with the above principle description, the power management circuit in this embodiment can realize the selective output of the power supply VIO and the power supply VLDO, so that the utility model can be compatible with single power supply and dual power supply input.

[0057] Embodiment 3

[0058] This embodiment further provides a radio frequency chip, on which the power management circuit in the second embodiment is provided.

[0059] The above is based on the enlightenment of this utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A radio frequency switching power supply switching circuit, characterized in that: It includes a power detection unit and an output unit; The power detection unit includes a resistor R1, a resistor R2, a resistor R3, a MOS tube MP1, a voltage drop unit and a signal processing unit. One end of the resistor R1 is electrically connected to the source of the MOS tube MP1 and is used to input the power supply VIO. The other end of the resistor R1 is electrically connected to one end of the resistor R2 and the gate of the MOS tube MP1 respectively, and is grounded through the voltage drop unit. The other end of the resistor R2 is used to input the power supply VLDO. The drain of the MOS tube MP1 is grounded through the resistor R3 and is electrically connected to the signal processing unit. The signal processing unit is used to perform two inversion processes on the input signal and output a selection signal SEL. The output unit includes a second signal processing unit, a first switch unit, and a second switch unit. The input end of the first switch unit is used to input a power supply VIO, and the input end of the second switch unit is used to input a power supply VLDO. The output end of the first switch unit is electrically connected to the output end of the second switch unit. The selection signal SEL is input to the first switch unit to control the on and off of the first switch unit. The second signal processing unit is used to invert the selection signal SEL and input a control signal to the second switch unit. The control signal is used to control the on and off of the second switch unit.

2. A radio frequency switching power supply switching circuit according to claim 1, characterized in that: The first switch unit is turned on when the selection signal SEL is at a high level, and is turned off when the selection signal SEL is at a low level.

3. A radio frequency switching power supply switching circuit according to claim 1 or 2, characterized in that: The first switch unit includes a MOS transistor MN1, a MOS transistor MP2 and a resistor R4. The drain of the MOS transistor MP2 is the input end of the first switch unit, and the source of the MOS transistor MP2 is the output end of the first switch unit. The drain of the MOS transistor MP2 is electrically connected to the gate of the MOS transistor MP2 and the drain of the MOS transistor MN1 through the resistor R4. The selection signal SEL is input to the gate of the MOS transistor MN1, and the source of the MOS transistor MN1 is grounded.

4. The radio frequency switching power supply switching circuit according to claim 1, characterized in that: The second switch unit is turned on when the control signal is at a high level, and is turned off when the control signal is at a low level.

5. A radio frequency switch power supply switching circuit according to claim 1 or 4, characterized in that: The second switch unit includes a MOS transistor MN2, a MOS transistor MP3 and a resistor R5, wherein the drain of the MOS transistor MP3 is the input end of the second switch unit, the source of the MOS transistor MP3 is the output end of the second switch unit, and is electrically connected to the gate of the MOS transistor MP3 and the drain of the MOS transistor MN2 respectively through the resistor R5, the control signal is input to the gate of the MOS transistor MN2, and the source of the MOS transistor MN2 is grounded.

6. The radio frequency switching power supply switching circuit according to claim 1, characterized in that: The voltage drop unit includes four diodes connected in series in sequence, one end of the resistor R2 is electrically connected to the anode of the first-end diode, and the cathode of the terminal diode is grounded.

7. The radio frequency switching power supply switching circuit according to claim 1, characterized in that: The signal processing unit includes a first inverter and a second inverter, the input end of the first inverter is electrically connected to one end of the resistor R3, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter outputs the selection signal SEL.

8. A radio frequency switch power supply switching circuit according to claim 1 or 7, characterized in that: The second signal processing unit includes a third inverter, an input terminal of the third inverter inputs the selection signal SEL, and an output terminal of the third inverter outputs the control signal.

9. A power management circuit, comprising a MIPI protocol demodulation module, a power supply module and a radio frequency switch module, wherein the MIPI protocol demodulation module is used to input an enable signal EN to the power supply module and the radio frequency switch module respectively when a power supply VIO is input, the MIPI protocol demodulation module is electrically connected to the radio frequency switch module, and inputs a radio frequency control signal VCTRL to the radio frequency switch module, characterized in that: It also includes the RF switch power switching circuit according to any one of claims 1 to 8, wherein the power supply module is used to input power VLDO to the RF switch power switching circuit when power VDD and enable signal EN are input, and the output end of the first switch unit is electrically connected to the RF switch module for providing voltage Vcon to the RF switch module.

10. A radio frequency chip, characterized in that: The radio frequency chip is provided with the power management circuit described in claim 9.

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