Power supply circuit
By designing a negative voltage power supply circuit combining PMOS, NMOS tubes, capacitors and diodes, the problem of large space, high cost and poor EMC characteristics in the prior art is solved, and an efficient, cheap and good EMC characteristics of negative voltage power supply output is achieved.
Patent Information
- Application Number
- CN202421268737.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-04
- Publication Date
- 2025-03-21
- Estimated Expiration
- 2034-06-04
AI Technical Summary
The negative voltage power supply in the existing new energy vehicle battery management module is generated by the isolation transformer, resulting in large space, high cost and poor EMC characteristics.
A negative voltage power supply circuit is designed, and the generation of a negative voltage power supply is achieved by controlling the clock signal by controlling the clock signal, including the first capacitor connecting the PMOS and NMOS drain terminals, the second capacitor connecting the drain terminal in parallel, the control clock connecting the gate terminal, and the combination of diode and capacitor to achieve stable output of the negative voltage power supply.
It realizes efficient and cheap negative voltage power output, reducing space usage and cost while improving EMC characteristics.
Smart Images
Figure CN222655042U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a negative voltage power supply circuit, and in particular to battery management in the field of new energy vehicles. A battery management module can obtain a cheap and efficient negative voltage power supply through the utility model. Background Art
[0002] For the battery management module of new energy vehicles, a negative voltage power supply is required internally for positive and negative current detection and various functional diagnosis. The current negative voltage power supply is mainly generated by an isolation transformer, which occupies a large space, is expensive, and has poor EMC characteristics. Utility Model Content
[0003] In order to overcome the above technical defects, the purpose of the utility model is to provide a negative voltage power supply circuit, comprising:
[0004] A first capacitor, wherein a first end is connected to a drain end of the PMOS tube and a drain end of the NMOS tube, and a source end of the PMOS tube is connected to a positive electrode of a positive voltage DC power supply; a second end of the first capacitor is connected to a positive electrode of the first diode and a negative electrode of the second diode;
[0005] The second capacitor is connected in parallel with the first capacitor, a first end of which is connected to the drain end of the PMOS tube and the drain end of the NMOS tube, a source end of the NMOS tube is connected to the ground end, and a second end of the second capacitor is connected to the positive electrode of the third diode and the negative electrode of the fourth diode;
[0006] A control clock connected to the gate terminal of the PMOS tube and the gate terminal of the NMOS tube, the control clock providing a first control signal of a low level and a second control signal of a high level;
[0007] The gate end of the PMOS tube and the gate end of the NMOS tube are used to receive a first control signal and a second control signal from a control clock.
[0008] The cathode of the first diode is grounded, the cathode of the second diode is connected to the first end of the third capacitor and the anode of the third diode; the cathode of the third diode is also connected to the anode of the fourth diode, and the second end of the third capacitor is grounded.
[0009] The anode of the fourth diode is connected to the output port of the power supply circuit and the first end of the fourth capacitor, and the second end of the fourth capacitor is grounded and connected to the source end of the PMOS tube.
[0010] The PMOS tube and the NMOS tube may be elements having a switch function.
[0011] The first diode, the second diode, the third diode and the fourth diode are silicon type diodes.
[0012] The first capacitor, the second capacitor, the third capacitor and the fourth capacitor are non-polar ceramic capacitors.
[0013] The control clock is a square wave signal with a duty cycle of 50%. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 A schematic diagram of an embodiment of a power supply circuit of the utility model
[0015] Reference numerals:
[0016] S1 is a square wave signal with a duty cycle of 50%, DC is a 5V positive DC power supply, T1 is a P-type MOS tube, T2 is an N-type MOS tube, C1, C2, C3, C4 are the first to fourth capacitors, and D1, D2, D3, D4 are the first to fourth diodes. DETAILED DESCRIPTION
[0017] The advantages of the present disclosure are further described below in conjunction with the accompanying drawings and specific embodiments.
[0018] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0019] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms "a", "the", and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0020] It should be understood that although the terms first, second, third, etc. may be used in the present disclosure to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0021] In the description of the present disclosure, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.
[0022] In the description of the present disclosure, unless otherwise specified and limited, it should be noted that the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal connection between two elements. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.
[0023] In the following description, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present disclosure, and have no specific meanings. Therefore, "module" and "component" can be used interchangeably.
[0024] See also Figure 1 In one embodiment of the present invention, the first end of C1 is connected to the drain end of T1 and the drain end of T2, the source end of T1 is connected to DC, and DC is a 5V positive voltage DC power supply; the second end of C1 is connected to the positive electrode of D1 and the negative electrode of D2; the negative electrode of D1 is grounded.
[0025] C2 is connected in parallel with C1, and the first end of C2 is also connected to the drain end of T1 and the drain end of T2 at the same time, the second end of C2 is connected to the positive electrode of D3 and the negative electrode of D4, and the drain end of T2 is connected to the ground end.
[0026] The gate ends of T1 and T2 are simultaneously connected to a control clock S1, and the gate ends of T1 and T2 are used to receive control signals. S1 is a square wave signal with a duty cycle of 50%, providing a first control signal and a second control signal, wherein the first control signal is a low level and the second control signal is a high level.
[0027] The positive electrode of D2 is connected to the first end of C3, the second end of C3 is grounded, the positive electrode of D2 is also connected to the negative electrode of D3, and the positive electrode of D3 is also connected to the negative electrode of D4.
[0028] The positive electrode of D4 is connected to the output end of the power supply circuit and the first end of C4, and the second end of C4 is connected to the source of T2 and the ground end.
[0029] The process of generating the negative voltage power supply in this embodiment is as follows:
[0030] 1) When S1 is at a low level, the first control signal is output, T1 is closed, T2 is disconnected, and C1 is charged. Since the voltage drop of D1 is 0.7V, the voltage at point A is 0.7V;
[0031] 2) When S1 is at a high level, the second control signal is output, T1 is disconnected, T2 is closed, and C1 is discharged. Since the voltage drop of D1 is 0.7V, the voltage at point A is 0.7-5=-4.3V;
[0032] Because the voltage drop of D1 is 0.7V, the voltage at point B is -4.3+0.7=-3.5V;
[0033] Because the voltage drop of D3 is 0.7V, the voltage at point C is -3.5+0.7=-2.8V; however, C2 discharges at this time, generating -5V at point C, which will be superimposed on the voltage generated by the discharge of C1, so the actual voltage at point C is -2.8+(-5)=-7.8V.
[0034] Since the voltage drop of D4 is 0.7V, the voltage at the output point D of the circuit is -7.8+0.7=-7.1V
[0035] 3) Repeat steps 1) and 2) to ensure that the output voltage is always -7.1V.
[0036] Among them, C3 stabilizes the negative voltage generated by C1, and C4 stabilizes the total negative pressure generated.
[0037] In this embodiment, D1-D4 are silicon diodes, which can be replaced by other diodes according to the actual requirements of the output voltage, and are not specifically limited here. C1-C4 are non-polar ceramic capacitors, which can be replaced by other capacitors, and are not specifically limited here.
[0038] It should be noted that, in the present embodiment, the description of the transistor (whether NMOS or PMOS) is specific to the “source end” or “drain end”, wherein the source end is the source of the transistor, and the drain end is the drain of the transistor, and the specific “source end” or “drain end” does not constitute a limitation on the present embodiment. The reason is that: since the transistor mentioned in the present embodiment is used for the function of a switch, the purpose is to turn on the circuit where the transistor is located, and therefore in other embodiments, the positions of the source end and the drain end of the transistor can be interchanged, and in some embodiments, the transistor can even be directly replaced by other devices with switching functions.
[0039] Those skilled in the art can make various changes in form and details according to the specific requirements of outputting different negative voltage values, such as increasing or decreasing D1-D4, and increasing or decreasing the capacitances C1 and C2, etc., to obtain the required negative voltage power supply.
[0040] It should be noted that the embodiments of the present application have better practicability and do not impose any form of limitation on the present application. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A power supply circuit, characterized in that: include: A first capacitor, wherein a first end is connected to a drain end of the PMOS tube and a drain end of the NMOS tube, and a source end of the PMOS tube is connected to a positive electrode of a positive voltage DC power supply; a second end of the first capacitor is connected to a positive electrode of the first diode and a negative electrode of the second diode; The second capacitor is connected in parallel with the first capacitor, a first end of which is connected to the drain end of the PMOS tube and the drain end of the NMOS tube, a source end of the NMOS tube is connected to the ground end, and a second end of the second capacitor is connected to the positive electrode of the third diode and the negative electrode of the fourth diode; A control clock connected to the gate terminal of the PMOS tube and the gate terminal of the NMOS tube, the control clock providing a first control signal of a low level and a second control signal of a high level; The gate end of the PMOS tube and the gate end of the NMOS tube are used to receive a first control signal and a second control signal from a control clock.
2. The power supply circuit according to claim 1, characterized in that The cathode of the first diode is grounded, the cathode of the second diode is connected to the first end of the third capacitor and the anode of the third diode; the cathode of the third diode is also connected to the anode of the fourth diode, and the second end of the third capacitor is grounded.
3. The power supply circuit according to claim 2, characterized in that: The anode of the fourth diode is connected to the output port of the power supply circuit and the first end of the fourth capacitor, and the second end of the fourth capacitor is grounded and connected to the source end of the PMOS tube.
4. The power supply circuit according to claim 1, characterized in that: The PMOS tube and the NMOS tube may be elements having a switch function.
5. The power supply circuit according to any one of claims 1 to 3, characterized in that: The first diode, the second diode, the third diode and the fourth diode are silicon type diodes.
6. The power supply circuit according to any one of claims 1 to 3, characterized in that: The first capacitor, the second capacitor, the third capacitor and the fourth capacitor are non-polar ceramic capacitors.
7. The power supply circuit according to claim 1, characterized in that: The control clock is a square wave signal with a duty cycle of 50%.