No-operational-amplifier zero-temperature-drift band-gap reference voltage generation circuit

Abstract

The utility model relates to the technical field of integrated circuits, in particular to an operational-amplifier-free zero-temperature-drift band-gap reference voltage generating circuit, a biasing circuit comprises a resistor R1, a resistor R2, a resistor R4, a resistor R5, a resistor R6, a PMOS tube MP1, a PMOS tube MP2, an NPN tube Q1 and an NPN tube Q2, and the band-gap voltage generating circuit comprises a resistor R3, a resistor R7, a resistor R8, a resistor R9, a PMOS tube MP3, an NPN tube Q3, an NPN tube Q4, an NPN tube Q5, an NPN tube Q6 and a capacitor C1. The zero-temperature-drift band-gap reference voltage source can output zero-temperature-drift band-gap reference voltage, has small vision, and has certain driving capacity.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to an operational amplifier-free zero temperature drift bandgap reference voltage generating circuit. Background Art

[0002] A reference voltage is usually required inside an integrated circuit, and this reference voltage does not change with temperature. There are two circuit modes for generating a bandgap reference voltage. One is a voltage-mode bandgap reference, which generates a bandgap voltage with zero temperature drift; the other is a current-mode bandgap reference, which generates a current with zero temperature drift. The zero temperature drift current flows to a zero temperature coefficient resistor to generate a zero temperature drift voltage. General reference voltage generation circuits all contain op amps. Due to the existence of the offset of the op amp, the variation of the reference voltage increases. Although the viriation of the reference voltage can be reduced by reducing the offset of the op amp, the area is inevitably increased. For a bandgap reference voltage circuit that does not contain an op amp, the matching of the circuit will be relatively poor, and for processes with large deviations, the viriation of the reference voltage will also be relatively large. Utility Model Content

[0003] The utility model provides an operational amplifier-free zero temperature drift bandgap reference voltage generating circuit, which has a small output reference voltage viriation and a certain driving capability.

[0004] In order to achieve the purpose of the utility model, the technical scheme adopted is: an op amp-free zero temperature drift bandgap reference voltage generating circuit, including a bias circuit and a bandgap voltage generating circuit, the bias circuit includes a resistor R1, a resistor R2, a resistor R4, a resistor R5, a resistor R6, a PMOS tube M P1 、PMOS tube M P2 , NPN tube Q1 and NPN tube Q2, the bandgap voltage generating circuit includes resistor R3, resistor R7, resistor R8, resistor R9, PMOS tube M P3 , NPN tube Q3, NPN tube Q4, NPN tube Q5, NPN tube Q6 and capacitor C1, the positive electrodes of resistors R1, R2 and R3 and the collector of NPN tube Q6 are connected to the power supply VDD, and the negative electrodes of resistors R1, R2 and R3 are connected to PMOS tube M P1 、PMOS tube M P2 And PMOS tube M P3 The source of PMOS tube M P1 、PMOS tube M P3 The gate and PMOS tube M P2 The gate and drain of the PMOS tube M are connected to the positive electrode of the resistor R5. P1The drain of is connected to one end of the resistor R4, the cathode of the resistor R4 is connected to the collector and base of the NPN tube Q1 and the base of the NPN tube Q2, the emitter of the NPN tube Q1 is grounded, the collector of the NPN tube Q2 is connected to the cathode of the resistor R5, the emitter of the NPN tube Q2 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, and the PMOS tube M P3 The drain of NPN tube Q3, the collector of NPN tube Q6 are connected to the positive electrode of capacitor C1, the base of NPN tube Q3 is connected to the negative electrode of capacitor C1, the negative electrode of resistor R8 and the collector of NPN tube Q5, the emitter of NPN tube Q3 is grounded, the emitter of NPN tube Q6 is connected to the positive electrodes of resistors R7 and R8, the negative electrode of resistor R7 is connected to the positive electrode of resistor R9 and the base of NPN tube Q4, the negative electrode of resistor R9 is connected to the collector of NPN tube Q4 and the base of NPN tube Q5, and the emitters of NPN tubes Q4 and Q5 are grounded.

[0005] As an optimization solution of the utility model, the collector of NPN tube Q5 is connected to the base of NPN tube Q3, the collector of NPN tube Q3 is connected to the base of NPN tube Q6, and NPN tube Q3, NPN tube Q6 and NPN tube Q5 form a feedback loop.

[0006] As an optimization solution of the present invention, the emitter area ratio of NPN tube Q1, NPN tube Q2, NPN tube Q3, NPN tube Q4 and NPN tube Q5 is 1:N:1:1:N. The general value of N is 8, 15, 24.

[0007] As an optimization solution of the utility model, the PMOS tube M P1 、PMOS tube M P2 Size and PMOS tube M P3 Same size.

[0008] As an optimization solution of the present invention, the resistance values ​​of the resistors R1 , R2 and R3 are equal, the resistance values ​​of the resistors R6 and R9 are equal, and the resistance values ​​of the resistors R7 and R8 are equal.

[0009] The utility model has positive effects: 1) Compared with the general bandgap reference circuit with operational amplifier, the circuit of the utility model can be combined with the formula of the reference voltage to obtain a smaller viation of the reference voltage. Since it is a circuit structure without operational amplifier, the layout area will be smaller; and since the circuit of the utility model has a feedback loop, the self-adjustment capability helps to improve the stability and accuracy of the reference voltage; compared with the general bandgap reference, since the voltage is output from the emitter of the NPN tube Q6, the output impedance seen from the output end is about 1 / Gm, Gm is the transconductance of Q6, and the output impedance is small, so the output reference voltage has a certain driving capability, and a certain voltage can be output to drive other circuits or components;

[0010] 2) The utility model realizes the generation of a zero temperature drift bandgap reference voltage in a circuit structure without an operational amplifier, does not introduce additional viriation, and is less affected by process deviations.

[0011] 3) The utility model adopts a more simplified and efficient circuit structure, reducing unnecessary components and complexity, thereby achieving a smaller circuit area;

[0012] 4) The utility model improves the stability and accuracy of the reference voltage by adjusting or improving the component parameters and connection mode in the circuit, thereby achieving a smaller reference voltage variation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The utility model is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0014] Figure 1 It is a circuit schematic diagram of the utility model;

[0015] Figure 2 This is the output waveform of the reference voltage changing with temperature under no-load condition;

[0016] Figure 3 It is the output waveform of the reference voltage changing with temperature under different loads. DETAILED DESCRIPTION

[0017] The specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0018] like Figure 1 As shown, the utility model discloses a zero temperature drift bandgap reference voltage generating circuit without an operational amplifier, including a bias circuit and a bandgap voltage generating circuit, wherein the bias circuit includes a resistor R1, a resistor R2, a resistor R4, a resistor R5, a resistor R6, a PMOS tube M P1 、PMOS tube M P2 , NPN tube Q1 and NPN tube Q2, the bandgap voltage generating circuit includes resistor R3, resistor R7, resistor R8, resistor R9, PMOS tube M P3 , NPN tube Q3, NPN tube Q4, NPN tube Q5, NPN tube Q6 and capacitor C1, the positive electrodes of resistors R1, R2 and R3 and the collector of NPN tube Q6 are connected to the power supply VDD, and the negative electrodes of resistors R1, R2 and R3 are connected to PMOS tube M P1 、PMOS tube M P2 And PMOS tube M P3 The source of PMOS tube M P1 、PMOS tube M P3 The gate and PMOS tube M P2The gate and drain of the PMOS tube M are connected to the positive electrode of the resistor R5. P1 The drain of is connected to one end of the resistor R4, the cathode of the resistor R4 is connected to the collector and base of the NPN tube Q1 and the base of the NPN tube Q2, the emitter of the NPN tube Q1 is grounded, the collector of the NPN tube Q2 is connected to the cathode of the resistor R5, the emitter of the NPN tube Q2 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, and the PMOS tube M P3 The drain of NPN tube Q3, the collector of NPN tube Q6 are connected to the positive electrode of capacitor C1, the base of NPN tube Q3 is connected to the negative electrode of capacitor C1, the negative electrode of resistor R8 and the collector of NPN tube Q5, the emitter of NPN tube Q3 is grounded, the emitter of NPN tube Q6 is connected to the positive electrodes of resistors R7 and R8, the negative electrode of resistor R7 is connected to the positive electrode of resistor R9 and the base of NPN tube Q4, the negative electrode of resistor R9 is connected to the collector of NPN tube Q4 and the base of NPN tube Q5, and the emitters of NPN tubes Q4 and Q5 are grounded.

[0019] The collector of NPN tube Q5 is connected to the base of NPN tube Q3, and the collector of NPN tube Q3 is connected to the base of NPN tube Q6. NPN tubes Q3, Q6 and Q5 form a feedback loop, whose function is that when the temperature changes, the bandgap voltage can have a very small temperature coefficient due to the existence of the feedback loop, thereby outputting a zero temperature drift bandgap voltage.

[0020] Example:

[0021] The resistance values ​​of resistors R1 and R2 are equal, and the PMOS tube M P1 、M P2 With the same size, due to the PMOS tube M P1 、PMOS tube M P2 The gate terminal is connected, so it flows through the PMOS tube M P1 、PMOS tube M P2 The source-drain current is equal, that is, the emitter current I of NPN tube Q1 and NPN tube Q2 e1 ,I e2 The emitter area ratio of NPN tube Q1 and NPN tube Q2 is 1:N, so the voltage difference between the base and emitter of NPN tube Q1 and NPN tube Q2 is ΔV BE Equal to V T lnN, and because the bases of NPN tubes Q1 and Q2 are connected, the voltage across resistor R6 is equal to ΔV BE voltage, so the current I e1 =I e2 =ΔV BE / R6=V T lnN / R6, the resistance of resistor R3 is equal to R2, and the PMOS tube M P3Size and M P1 、M P2 The same size, so I e3 =I e1 =I e2 , the emitter area ratio of NPN tubes Q1, Q2, Q3, Q4, and Q5 is 1:N:1:1:N, the resistance value of resistor R9 is equal to that of resistor R6, and the resistance values ​​of resistors R7 and R8 are also equal, so the base-emitter voltage V of NPN tube Q3 is be3 Equal to the base emitter voltage V of Q4 be4 , so I be4 =I be5 =V T lnN / R9, emitter voltage V of NPN tube Q6 BG =V be4 +V T lnN*R7 / R6,V be4 is a voltage with a negative temperature coefficient, and V T lnN*R7 / R6 is a voltage with a positive temperature coefficient. The superposition of the two produces a bandgap reference voltage V with zero temperature drift. BG .

[0022] from Figure 2 It can be concluded that when the circuit is in the no-load state, the temperature change has little effect on the reference voltage. Figure 3 It can be concluded that under different loads, the temperature changes in the range from -40° to 120°, the reference voltage changes within 0.003V, the change range is small, and the temperature change has little effect on the reference voltage.

[0023] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A zero temperature drift bandgap reference voltage generation circuit without an operational amplifier, characterized in that: The invention comprises a bias circuit and a bandgap voltage generating circuit, wherein the bias circuit comprises a resistor R1, a resistor R2, a resistor R4, a resistor R5, a resistor R6, a PMOS tube M P1 、PMOS tube M P2 , NPN tube Q1 and NPN tube Q2, the bandgap voltage generating circuit includes resistor R3, resistor R7, resistor R8, resistor R9, PMOS tube M P3 , NPN tube Q3, NPN tube Q4, NPN tube Q5, NPN tube Q6 and capacitor C1, the positive electrodes of resistors R1, R2 and R3 and the collector of NPN tube Q6 are connected to the power supply VDD, and the negative electrodes of resistors R1, R2 and R3 are connected to PMOS tube M P1 、PMOS tube M P2 And PMOS tube M P3 The source of PMOS tube M P1 、PMOS tube M P3 The gate and PMOS tube M P2 The gate and drain of the PMOS tube M are connected to the positive electrode of the resistor R5. P1 The drain of is connected to one end of the resistor R4, the cathode of the resistor R4 is connected to the collector and base of the NPN tube Q1 and the base of the NPN tube Q2, the emitter of the NPN tube Q1 is grounded, the collector of the NPN tube Q2 is connected to the cathode of the resistor R5, the emitter of the NPN tube Q2 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, and the PMOS tube M P3 The drain of NPN tube Q3, the collector of NPN tube Q6 are connected to the positive electrode of capacitor C1, the base of NPN tube Q3 is connected to the negative electrode of capacitor C1, the negative electrode of resistor R8 and the collector of NPN tube Q5, the emitter of NPN tube Q3 is grounded, the emitter of NPN tube Q6 is connected to the positive electrodes of resistors R7 and R8, the negative electrode of resistor R7 is connected to the positive electrode of resistor R9 and the base of NPN tube Q4, the negative electrode of resistor R9 is connected to the collector of NPN tube Q4 and the base of NPN tube Q5, and the emitters of NPN tubes Q4 and Q5 are grounded.

2. The zero temperature drift bandgap reference voltage generating circuit without an operational amplifier according to claim 1, characterized in that: The collector of NPN tube Q5 is connected to the base of NPN tube Q3, and the collector of NPN tube Q3 is connected to the base of NPN tube Q6. NPN tube Q3, NPN tube Q6 and NPN tube Q5 form a feedback loop.

3. The zero temperature drift bandgap reference voltage generating circuit without an operational amplifier according to claim 2, characterized in that: The emitter area ratio of NPN tube Q1, NPN tube Q2, NPN tube Q3, NPN tube Q4 and NPN tube Q5 is 1:N:1:1:N, and N is 8, 15 or 24.

4. The zero temperature drift bandgap reference voltage generating circuit without an operational amplifier according to claim 3, characterized in that: PMOS tube M P1 、PMOS tube M P2 Size and PMOS tube M P3 Same size.

5. The zero temperature drift bandgap reference voltage generating circuit without an operational amplifier according to claim 4, characterized in that: The resistance values ​​of the resistors R1 , R2 and R3 are equal, the resistance values ​​of the resistors R6 and R9 are equal, and the resistance values ​​of the resistors R7 and R8 are equal.

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