Semiconductor resistor structure

Abstract

Some embodiments described herein include techniques and apparatus for forming a semiconductor device including a semiconductor resistor structure. A semiconductor resistor structure (e.g., a low impedance thin film resistor structure) may include a resistive layer having an approximately rectangular shape (e.g., an aspect ratio of less than about 1). The semiconductor resistor structure includes a contact structure connected to the resistive layer, a conductive bus structure having an approximately rectangular shape connected to the contact structure, and an electrical terminal (e.g., a wiring pin) located at a center of or near an edge of the conductive bus structure. Some embodiments of the utility model are used for improving the distribution of current in the semiconductor resistor structure so as to reduce the resistance change in the semiconductor resistor structure.

Description

Technical Field

[0001] The embodiments of the utility model relate to an interconnection design, and in particular to an interconnection design of a thin film resistor. Background Art

[0002] Semiconductor-based integrated circuits may include a wide range of semiconductor devices. These semiconductor devices may include active semiconductor devices and / or passive semiconductor devices. Active semiconductor devices may include transistors and other semiconductor devices that operate using power. Passive semiconductor devices include inductors, capacitors, resistors, and / or other semiconductor devices that can operate without power. Resistors are widely used in many applications, such as resistor-capacitor (RC) circuits, power drivers, power amplifiers, and / or radio frequency (RF) applications, as well as other examples. Utility Model Content

[0003] The utility model proposes a semiconductor resistor structure to solve the problem in the prior art that the current distribution in the semiconductor resistor structure is uneven, which further reduces the performance of the semiconductor device including the semiconductor resistor structure. The semiconductor resistor structure includes a resistor layer. The semiconductor resistor structure includes a row of contact structures located at or near the edge of the resistor layer. The semiconductor resistor structure includes a conductive bus structure, the conductive bus structure includes a first edge region connected to the row of contact structures, a second edge region opposite to the first edge region, and an electrical terminal, wherein, in a top view of the semiconductor resistor structure, the electrical terminal is located at or near the approximate center axis of the row of contact structures and is located at or near the second edge region.

[0004] The purpose of an embodiment of the utility model is to propose another semiconductor resistor structure. The semiconductor resistor structure includes a resistor layer. The semiconductor resistor structure includes a first conductive bus structure above and along a first edge of the resistor layer, wherein, in a top view of the semiconductor resistor structure, the first conductive bus structure has a first length. The semiconductor resistor structure includes a first row of contact structures between the first conductive bus structures and along the first edge of the resistor layer, wherein the first row of contact structures electrically connects the first conductive bus structure to the first edge of the resistor layer. The semiconductor resistor structure includes a second conductive bus structure above and along a second edge of the resistor layer, wherein the second edge is opposite to the first edge, and in a top view of the semiconductor resistor structure, the second conductive bus structure has a second length. The semiconductor resistor structure includes a second row of contact structures between the second conductive bus structures and along the second edge of the resistor layer, wherein the second row of contact structures electrically connects the second conductive bus structure to the second edge of the resistor layer. In some embodiments, and in a top view of the semiconductor resistor structure, the distance between the second row of contact structures and the first row of contact structures is less than the first length of the first conductive bus structure or the second length of the second conductive bus structure.

[0005] The purpose of an embodiment of the utility model is to propose another semiconductor resistor structure. The semiconductor resistor structure includes a first thin film resistor structure, a second thin film resistor structure and a connection structure electrically connecting the second thin film resistor structure and the first thin film resistor structure in parallel. Each of the first thin film resistor structure and the second thin film resistor structure includes a resistor layer. Each of the first thin film resistor structure and the second thin film resistor structure includes a row of contact structures located at or near the edge of the resistor layer. Each of the first thin film resistor structure and the second thin film resistor structure includes a conductive bus structure, the conductive bus structure includes a first edge region connected to the row of contact structures, a second edge region opposite to the first edge region, and an electrical terminal, wherein, in the top view of each of the first thin film resistor structure and the second thin film resistor structure, the position of the electrical terminal is located at or near the approximate central axis of the row of contact structures and is located at or near the second edge region. Wherein, the connection structure is between the conductive bus structure of the first thin film resistor structure and the conductive bus structure of the second thin film resistor structure.

[0006] The semiconductor resistor structure described above can improve the distribution of current throughout the semiconductor resistor structure. The improved current distribution can reduce resistance variation within the semiconductor resistor structure, thereby improving the performance of a semiconductor device including the semiconductor resistor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0009] Figure 2 is a diagram of a portion of an example semiconductor device described herein;

[0010] Figure 3 is a diagram of an example implementation of a semiconductor resistor structure described herein;

[0011] Figure 4 is a diagram of an example implementation of a semiconductor resistor structure described herein;

[0012] FIG. 5A to FIG. 5J is a diagram of an example implementation of forming a semiconductor resistor structure described herein;

[0013] Figure 6 is a diagram of an example implementation of a semiconductor resistor structure described herein;

[0014] Figure 7 is a diagram of an example implementation of a semiconductor resistor structure described herein;

[0015] Figure 8 is a graph illustrating example performance associated with variations of example semiconductor resistor structures described herein;

[0016] Fig. 9 are diagrams of example elements of the apparatus described herein;

[0017] Fig.10 is a flow chart of an example process associated with forming a semiconductor device including a semiconductor resistor structure described herein.

[0018]

Explanation of symbols

[0019] 100: Environment

[0020] 102:Semiconductor processing tools / deposition tools

[0021] 104:Semiconductor processing tools / exposure tools

[0022] 106:Semiconductor processing tools / development tools

[0023] 108:Semiconductor processing tools / etching tools

[0024] 110:Semiconductor processing tools / planarization tools

[0025] 112:Semiconductor processing tools / electroplating tools

[0026] 114: Wafer / die transport tool

[0027] 200:Semiconductor devices

[0028] 202:Substrate

[0029] 204: Fin structure

[0030] 206,210,214,218,222,226,502: Dielectric layer

[0031] 208,212,216,220,224: Etch stop layer / ESL

[0032] 228: Epitaxial area

[0033] 230: Metal source or drain contact

[0034] 232: Gate

[0035] 234,236: Spacer

[0036] 238: Source or drain interconnect

[0037] 240: Gate Interconnect

[0038] 242: Gate contact

[0039] 244,246,252,254: Conductive structure

[0040] 248,250,266,268:Through hole

[0041] 260,260a,260b:Semiconductor resistor structure

[0042] 262:Resistance layer

[0043] 264a, 264b: Contact structure

[0044] 270, 270a, 270b, 272, 272a, 272b: Conductive bus structure

[0045] 274,274a,274b,276,276a,276b,702,704: Electrical terminals

[0046] 278: Covering

[0047] 300,400,500,600,700: Implementation

[0048] 302: Electric current

[0049] 504: Conductive layer

[0050] 506: Hard mask layer

[0051] 520,522,524,526: Depression

[0052] 528,530: Cavity

[0053] 602,604: Connection structure

[0054] 800: Schematic diagram

[0055] 802,804,806,808: Sample Performance / Examples

[0056] 810,812:Axle

[0057] 814: Benchmark

[0058] 816,818: Resistivity

[0059] 900: Device

[0060] 910: Bus

[0061] 920: Processor

[0062] 930: Memory

[0063] 940: Input element

[0064] 950: Output element

[0065] 960: Communication Components

[0066] 1000: Process

[0067] 1010,1020,1030,1040: Blocks

[0068] AA: Section

[0069] D1,D5: Length

[0070] D2: Distance

[0071] D3,D4: Width DETAILED DESCRIPTION

[0072] The following utility model provides many different embodiments or examples to implement different features of the provided subject matter. The specific examples of components and arrangements described below are to simplify the utility model. Of course, these are merely examples and are not intended to limit the utility model. For example, in the description, a first feature is formed above or on a second feature, which may include an embodiment in which the first feature and the second feature are formed in direct contact, which may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the utility model may repeat reference numbers and / or text in various examples. This repetition is for the purpose of simplicity and clarity, but is not itself used to specify the relationship between the various embodiments and / or architectures discussed.

[0073] Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to facilitate description of the relationship of one element or feature to another element or features as depicted in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be oriented in different ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0074] In some cases, a semiconductor resistor structure (e.g., a thin film resistor (TFR) structure) may be formed in a back end of line (BEOL) region of a semiconductor device. A resistive layer of the TFR structure may be formed in a dielectric layer of the back end of line (BEOL) region. A contact structure of the TFR structure may be formed above the resistive layer. In addition, a metal layer of the TFR structure may be formed above the contact structure, wherein electrical terminals (e.g., routing pins) for passing current through the TFR structure are located at end regions of the metallization layer.

[0075] For high impedance (e.g., greater than about 50 ohm impedance) TFR structures and for various applications, resistivity variations within the TFR structure generally do not substantially affect the performance of the semiconductor device. However, for low impedance (e.g., less than about 50 ohm impedance) TFR structures and for radio frequency (RF) applications, resistivity variations within the TFR structure may degrade the performance of the semiconductor device. Additionally or alternatively, if the length-to-width ratio of the low impedance TFR structure is less than about 1, the layout of the contact structure (in combination with the electrical terminals located at the end regions of the metallization layer) may result in non-uniform current distribution within the low impedance TFR structure and further degrade the performance of the semiconductor device.

[0076] Some embodiments described herein include techniques and apparatus for forming a semiconductor device including a semiconductor resistor structure. The semiconductor resistor structure (e.g., a low-impedance TFR structure) may include a resistive layer having an approximately rectangular shape (e.g., an aspect ratio of less than about 1). The semiconductor resistor structure includes a contact structure connected to the resistive layer, a conductive bus structure having an approximately rectangular shape connected to the contact structure, and an electrical terminal (e.g., a wiring pin) located at the center of an edge of the conductive bus structure or near an edge of the conductive bus structure.

[0077] The centrally located electrical terminal (combined with the approximately rectangular shape of the conductive bus structure) can improve the distribution of current throughout the semiconductor resistor structure relative to other semiconductor resistor structures that do not include a centrally located electrical terminal and / or have a conductive bus structure with an approximately rectangular shape. The improved current distribution can reduce resistance variation within the semiconductor resistor structure.

[0078] In this way, the performance of semiconductor devices including semiconductor resistor structures is improved. The improved performance of semiconductor devices can increase the manufacturing yield of semiconductor devices to a specific performance threshold, thereby reducing the amount of resources required to support the market, which consumes the total amount of semiconductor devices that meet the specific performance threshold (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources).

[0079] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown, the example environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transfer tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or other types of semiconductor processing tools. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among other examples.

[0080] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials on a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool to form layers and / or regions of a device by epitaxial growth. In some embodiments, the example environment 100 includes multiple types of deposition tools 102.

[0081] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme UV (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from the mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, the pattern may include patterns for forming one or more structures of a semiconductor device, the pattern may include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0082] The developing tool 106 is a semiconductor processing tool that is capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portion of the photoresist layer.

[0083] The etching tool 108 is a semiconductor processing tool that is capable of etching various materials of a substrate, a wafer, or a semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0084] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or a semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that polish or planarize a layer or surface of a deposited material or a plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing) to polish or planarize the surface of a semiconductor device. The planarization tool 110 may use abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planarized.

[0085] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or electroplating equipment for one or more other types of conductive materials, metals, and / or the like.

[0086] The wafer / die transporter 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and / or other types of devices, the above other types of devices are used to transfer substrates and / or semiconductor devices between semiconductor processing tools 102-112, the above other types of devices are used to transfer substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or the above other types of devices are used to transfer substrates and / or semiconductor devices to and from other locations, such as wafer racks, storage rooms, and / or the like. In some embodiments, the wafer / die transporter 114 can be a programmed device for traveling a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer / die transporters 114.

[0087] For example, the wafer / die transporter 114 may be included in a cluster tool or in other types of tools including multiple processing chambers, and the wafer / die transporter 114 may be used to transfer substrates and / or semiconductor devices between multiple processing chambers, to transfer substrates and / or semiconductor devices between a processing chamber and a buffer, to transfer substrates and / or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or to transfer substrates and / or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transporter 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, for oxidation and / or for other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport vehicle 114 is used to transfer substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) of the processing chambers and / or between processing operations in the deposition tool, as described herein.

[0088] In some embodiments, one or more semiconductor processing tools 102-112 and / or wafer / die transport tool 114 may perform a series of semiconductor processing operations to form the semiconductor resistor structure described herein. For example, the series of semiconductor processing operations may include: forming a row of contact structures along the length-wise edges of the approximately rectangular resistor layer, and forming a dielectric layer above the row of contact structures. The series of semiconductor processing operations include: forming a recess in the dielectric layer, the recess having a first side biased near the row of contact structures and a second side opposite to the first side and biased away from the row of contact structures, wherein the recess exposes the row of contact structures. The series of semiconductor processing operations include: forming a conductive bus structure in the recess, wherein the formed conductive bus structure electrically connects the conductive bus structure to the approximately rectangular resistor layer through the row of contact structures. In some embodiments, one or more semiconductor processing tools 102-112 and / or wafer / die transport tool 114 may perform a combination of Figure 2 , Figure 3 , Figure 4 , FIG. 5A to FIG. 5J , Figure 6 , Figure 7 , Figure 8 , and / or Fig. 9 , and other examples, one or more operations described.

[0089] Figure 1 The number and arrangement of devices shown in the figure are provided as one or more examples. In practice, there may be Figure 1 The devices shown may include additional devices, fewer devices, different devices, or differently arranged devices. Figure 1 Two or more of the devices shown in may be implemented in a single device, or, Figure 1 The single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (eg, one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0090] Figure 2 2 is a diagram of a portion of an example semiconductor device 200 described herein. The semiconductor device 200 includes an example of a semiconductor device, such as a semiconductor memory device (e.g., static random access memory (SRAM), dynamic random access memory (DRAM)), a semiconductor logic device, a processor, an input / output device, or other types of semiconductor devices including one or more transistors.

[0091] The semiconductor device 200 includes a substrate 202 (e.g., a silicon substrate) and one or more fin structures 204. The semiconductor device 200 also includes one or more stacked layers, including a dielectric layer 206, an etch stop layer (ESL) 208, a dielectric layer 210, an ESL 212, a dielectric layer 214, an ESL 216, a dielectric layer 218, an ESL 220, a dielectric layer 222, an ESL 224, and a dielectric layer 226, as well as other examples. The semiconductor device 200 includes the dielectric layers 206, 210, 214, 218, 222, and 226 to electrically isolate various structures of the semiconductor device 200. The dielectric layers 206, 210, 214, 218, 222, and 226 include silicon nitride (SiN x ), oxides (e.g., silicon oxide (SiO x) and / or other oxide materials), and / or other types of dielectric materials. ESL 208, 212, 216, 220, 224 includes a layer of material that allows various portions of semiconductor device 200 (or layers included therein) to be selectively etched or protected from etching to form one or more structures included in semiconductor device 200.

[0092] like Figure 2 As further shown, the semiconductor device 200 includes a plurality of epitaxial (epi) regions 228 that grow and / or are otherwise formed on and / or around portions of the fin structure 204. The epitaxial regions 228 are formed by epitaxial growth. In some embodiments, the epitaxial regions 228 are formed in recessed portions in the fin structure 204. The recessed portions may be formed by strained source drain (SSD) etching and / or other types of etching operations of the fin structure 204. The epitaxial regions 228 serve as source regions or drain regions of transistors included in the semiconductor device 200.

[0093] The epitaxial region 228 is electrically connected to a metal source or drain contact 230 of a transistor included in the semiconductor device 200. The metal source or drain contact 230 (MDs or CAs) includes cobalt (Co), ruthenium (Ru), and / or other conductive materials or other metal materials. The transistor also includes a gate 232 (metal gates, MGs), which is formed of polysilicon material, metal (e.g., tungsten (W) or other metals), and / or other types of conductive materials. The metal source or drain contact 230 and the gate 232 are electrically isolated by one or more sidewall spacers, and the one or more sidewall spacers include a spacer 234 on each side of the metal source or drain contact 230 and a spacer 236 on each side of the gate 232. The spacers 234 and 236 include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and / or other suitable materials. In some embodiments, the spacer 234 is omitted from the sidewalls of the metal source or drain contact 230.

[0094] like Figure 2As further shown, the metal source or drain contact 230 and the gate 232 are electrically connected to one or more types of interconnects. The above interconnects electrically connect the transistors of the semiconductor device 200 to each other and / or to other regions of the semiconductor device 200 and / or other elements of the semiconductor device 200. In some embodiments, the above interconnects electrically connect the transistors to the back end of line (BEOL) region of the semiconductor device 200.

[0095] The metal source or drain contact 230 is electrically connected to the source or drain interconnect 238 (e.g., source / drain vias or VDs). One or more gates 232 are electrically connected to the gate interconnect 240 (e.g., gate vias or VGs). The source or drain interconnect 238 and the gate interconnect 240 include conductive materials, such as tungsten, cobalt, ruthenium, copper, and / or other types of conductive materials. In some embodiments, the gate 232 is electrically connected to the gate interconnect 240 through a gate contact 242 (CB or MP) to reduce the contact resistance between the gate 232 and the gate interconnect 240. The gate contact 242 includes examples of tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) or gold (Au), as well as other conductive materials.

[0096] like Figure 2 As further shown, source or drain interconnect 238 and gate interconnect 240 are electrically connected to a plurality of conductive layers, each conductive layer including one or more metallization layers and / or vias. As an example, source or drain interconnect 238 and gate interconnect 240 may be electrically connected to an M0 metallization layer including conductive structures 244 and 246. The M0 metallization layer is electrically connected to a V0 via layer including vias 248 and 250. The V0 via layer is electrically connected to an M1 metallization including conductive structures 252 and 254. In some embodiments, the conductive layers of semiconductor device 200 include additional metallization layers and / or vias that connect semiconductor device 200 to a package. The back end of line (BEOL) region of semiconductor device 200 may refer to a region of semiconductor device 200 above ESL 208, including structures / layers 210-226 and 238-254.

[0097] like Figure 2As further shown, the semiconductor device 200 may include one or more devices and / or structures in a back end of line (BEOL) region of the semiconductor device 200. For example, the semiconductor device 200 may include one or more semiconductor resistor structures 260 in a back end of line (BEOL) region of the semiconductor device 200. The semiconductor resistor structure 260 may be included in one or more of the dielectric layers 210, 214, 218, 222, and / or 226 in the back end of line (BEOL) region of the semiconductor device 200. Therefore, the semiconductor resistor structure 260 may be referred to as a resistor structure or a thin film resistor (TFR) structure, among other examples.

[0098] The semiconductor resistor structure 260 includes a resistor layer 262. The resistor layer 262 may include one or more materials for providing resistance. In some embodiments, the resistor layer 262 includes a silicon chromium (SiCr) resistor material. Relative to other types of resistor materials (e.g., polysilicon resistor materials), the silicon chromium resistor material may provide a reduced temperature coefficient of resistance (TCR). Due to heat, the reduced temperature coefficient of resistance (TCR) may cause the resistance change of the semiconductor resistor structure 260 to be reduced relative to a semiconductor resistor structure including a polysilicon resistor material. In some embodiments, the thickness of the resistor layer 262 may be included in the range of about 50 angstroms to about 600 angstroms. However, other values ​​of this range are also within the scope of the present invention.

[0099] Semiconductor resistor structure 260 includes contact structures 264a and 264b above and / or on resistor layer 262. Contact structures 264a and 264b are electrically connected to resistor layer 262, and contact structures 264a and 264b provide input to resistor layer 262 and provide output from resistor layer 262. Therefore, contact structures 264a and 264b are used as terminals of semiconductor resistor structure 260. Contact structures 264a and 264b can each include one or more conductive materials, such as titanium nitride (TiN), ceramic materials, metal materials, metal alloys, and / or other conductive materials, and other examples. Contact structures 264a and 264b can be spaced apart by dielectric layer 222 so that contact structures 264a and 264b are electrically isolated to reduce the possibility of electrical short circuit between contact structures 264a and 264b. In some embodiments, the thickness of contact structures 264a and 264b is included in the range of about 650 angstroms to about 850 angstroms. However, other values ​​within this range are also within the scope of the present invention.

[0100] The contact structure 264a can be physically and / or electrically coupled to a row of vertical interconnect access structures (vias) 266 and / or other types of interconnect structures. In some embodiments, the contact structure 264a corresponds to a bus structure. Figure 2 As shown, a row of through holes 266 may be located on the lengthwise edge of the resistive layer 262 .

[0101] The contact structure 264b can be physically coupled and / or electrically coupled to a row of through holes 268 and / or other types of interconnect structures. In some embodiments, the contact structure 264b corresponds to a bus structure. Figure 2 As shown, a row of vias 268 may be located on opposing lengthwise edges of the resistive layer 262 .

[0102] The row of vias 266 may be physically coupled and / or electrically coupled to a conductive bus structure 270 and / or other types of metallization layers. The row of vias 268 may be physically coupled and / or electrically coupled to a conductive bus structure 272 and / or other types of metallization layers. The row of vias 266 and 268 and / or the conductive bus structures 270 and 272 may include materials similar to those included in one or more of the structures 238-254. The row of vias 266 and 268 may be included in the dielectric layer 222 and may extend into a portion of the contact structures 264a and 264b, respectively. The conductive bus structures 270 and 272 may be included in the dielectric layer 226 and may extend through the ESL 224. In some embodiments, the conductive bus structures 270 and 272 are top metal layers in the semiconductor device 200.

[0103] In some embodiments, Figure 2 As shown, the conductive bus structure 270 includes an electrical terminal 274. The electrical terminal 274 may be a protrusion extending from the conductive bus structure 270 and laterally away from the central region of the semiconductor resistor structure 260.

[0104] In addition, in some embodiments, Figure 2 As shown, the conductive bus structure 272 includes an electrical terminal 276. The electrical terminal 276 may be a protrusion extending from the conductive bus structure 272 and laterally away from a central region of the semiconductor resistor structure 260 (eg, a center of the resistor layer 262).

[0105] A capping layer 278 may be included above and / or on the contact structures 264a and 264b. The rows of vias 266 and 268 may extend through the capping layer 278. The capping layer 278 may include silicon nitride (Six N y ), silicon oxynitride (SiON), high dielectric constant (high-K) dielectric materials, and / or other suitable dielectric materials that can provide electrical isolation for the top surfaces of the contact structures 264a and 264b. During the manufacture / formation of the semiconductor resistor structure 260, the capping layer 278 can also be used as a hard mask layer to pattern the contact structures 264a and 264b. In some embodiments, the thickness of the capping layer 278 can be included in the range of about 300 angstroms to about 400 angstroms. However, other values ​​of this range are also within the scope of the present invention.

[0106] As mentioned above, providing Figure 2 As an example. Other examples may differ from Figure 2 as described.

[0107] Figure 3 is a diagram of an example implementation 300 of a semiconductor resistor structure (eg, semiconductor resistor structure 260 ) described herein. Figure 3 A top view of the semiconductor resistor structure 260 is illustrated. Figure 3 Further illustrations are given in the following figures (including Figure 4 and FIG. 5A to FIG. 5J ) is a reference section AA used in FIG. Section AA is located in a plane passing through the conductive bus structure 270, through the conductive bus structure 272, through the electrical terminal 274, and through the electrical terminal 276. Some structures / layers are shown in dashed lines to indicate that these structures / layers are located below one or more other structures / layers in the semiconductor resistor structure 260.

[0108] like Figure 3 As shown, a row of through holes 266 is located at or near the edge of the resistive layer 262. Figure 3 As shown, the edge region of the conductive bus structure 270 may be above (and / or connected to) the row of vias 266. Figure 3 As shown, the conductive bus structure 270 includes an opposite edge region, and the electrical terminal 274 is located at or near the opposite edge region. In some embodiments, the location of the electrical terminal 274 further corresponds to the approximate center axis of the row of through holes 266 (e.g., Figure 3 In some embodiments, the row of vias 266 electrically connects the conductive bus structure 270 to the resistive layer 262 through the contact structure 264 a and / or the cover layer 278 .

[0109] like Figure 3 As shown, a row of through holes 268 is located at or near opposite edges of the resistive layer 262. Figure 3 As shown, the edge region of the conductive bus structure 272 can be above (and / or connected to) the row of vias 268. Figure 3As shown, the conductive bus structure 272 includes opposite edge regions, and the electrical terminal 276 is located at or near the opposite edge regions. In some embodiments, the location of the electrical terminal 276 further corresponds to the approximate center axis of the row of through holes 266 (e.g., Figure 3 In some embodiments, the row of vias 268 electrically connects the conductive bus structure 272 to the resistive layer 262 through the contact structure 264 b and / or the capping layer 278 .

[0110] exist Figure 3 In FIG. 2 , the semiconductor resistor structure 260 includes an approximately rectangular shape. Figure 3 As shown, the resistive layer 262 includes an approximately rectangular shape.

[0111] For semiconductor resistor structures 260 and / or resistive layers 262 that include approximately rectangular shapes, the centralized location of electrical terminals 274 and 276 (combined with the rectangular shapes of conductive bus structures 270 and 272 ) may improve the uniformity of distribution of current 302 flowing through the entire semiconductor resistor structure 260 .

[0112] The improvement in the distribution of current 302 may improve the performance of an integrated circuit including semiconductor resistor structure 260. As an example, a digital-to-analog converter (DAC) circuit including other semiconductor resistor structures formed using other techniques (e.g., electrical terminals at the ends of a conductive bus structure) may experience a resistance change of up to about 10%, while a DAC circuit including semiconductor resistor structure 260 may experience a resistance change of less than about 5%. As another example, a radio frequency (RF) circuit including semiconductor resistor structure 260 may experience up to 85% less parasitic capacitance relative to other RF circuits including other semiconductor resistor structures.

[0113] In this manner, the performance of semiconductor devices including the semiconductor resistor structure 260 is improved. The improved performance of the semiconductor devices can increase the manufacturing yield of semiconductor devices to a specific performance threshold, thereby reducing the amount of resources required to support the market, which consumes the total amount of semiconductor devices that meet the specific performance threshold (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources).

[0114] In order to achieve performance thresholds for integrated circuit high frequency applications (e.g., an integrated circuit for an RF device requiring an impedance of less than about 50 ohms, or an impedance 260 of a semiconductor resistor structure less than 50 ohms), several dimensional characteristics may be applied to one or more structures of the semiconductor resistor structure 260. For example, the length D1 of the resistor layer 262 may be included in the range of about 0.6 microns to about 0.8 microns. If the length D1 is less than about 0.6 microns, or the length D1 is greater than about 0.8 microns, the impedance of the semiconductor resistor structure 260 may be greater than about 50 ohms. However, other values ​​and ranges of the length D1 are also within the scope of the present invention.

[0115] In addition, the distance D2 between the contact structures (e.g., contact structures 264a and 264b) connecting the conductive bus structures 270 and 272 and the resistive layer 262 may be included in the range of about 0.15 microns to about 0.45 microns. If the distance D2 is less than about 0.15 microns, or the distance D2 is greater than about 0.45 microns, the impedance of the semiconductor resistor structure 260 may be greater than about 50 ohms. However, other values ​​and ranges of the distance D2 are also within the scope of the present invention.

[0116] like Figure 3 As shown, the conductive bus structure 270 (and / or the conductive bus structure 272) may have a width D3 included in the range of about 0.3 microns to about 1.5 microns. If the width D3 is less than about 0.3 microns, "crowding" of the current 302 may occur, and the conductive bus structure 270 may not evenly distribute the current 302 throughout the semiconductor resistor structure 260 (for example, evenly distribute the current 302 in a row of through holes 266). If the width D3 is greater than about 1.5 microns, the size of the semiconductor device including the semiconductor resistor structure 260 may increase, thereby increasing the cost of the semiconductor device. In addition, if the width D3 is greater than about 1.5 microns, overlapping metal layers within the semiconductor device may cause the parasitic capacitance of the semiconductor resistor structure 260 to increase, thereby reducing the performance of the integrated circuit within the semiconductor device. However, other values ​​and ranges of width D3 are also within the scope of the present invention.

[0117] For a semiconductor resistor structure (e.g., a semiconductor resistor structure 260 including dimensional characteristics D1 and D2), the electrical terminal 274 (and / or the electrical terminal 276) may have a width D4 greater than approximately 0.3 microns and a length D5 greater than approximately 0.14 microns. If the width D4 of the electrical terminal 274 is less than approximately 0.3 microns, "crowding" of the current 302 may occur near the central area of ​​the conductive bus structure 270, and the current 302 may not be evenly distributed throughout the semiconductor resistor structure 260 (e.g., evenly distributing the current 302 in a row of through-holes 266). Additionally, or alternatively, if the length D5 of the electrical terminal 274 is less than approximately 0.14 microns, design rules that affect the manufacture of semiconductor devices (e.g., tolerance stacking within the semiconductor resistor structure 260) may be violated. However, other values ​​and ranges of width D4 and length D5 are also within the scope of the present invention.

[0118] As mentioned above, providing Figure 3 As an example. Other examples may differ from Figure 3 as described.

[0119] Figure 4 is a diagram of an example implementation 400 of a semiconductor resistor structure (eg, semiconductor resistor structure 260 ) described herein. Figure 4 Picture shows Figure 3 A cross-sectional view of the semiconductor resistor structure 260 is shown in section AA.

[0120] Semiconductor resistor structure 260 may be included in a portion of semiconductor device 200, such as a back-end of line (BEOL) region of semiconductor device 200. In some embodiments, semiconductor resistor structure 260 may be included in dielectric layer 222, which is included above and / or on ESL 220. ESL 224 is included above and / or on dielectric layer 222, and dielectric layer 226 is included above and / or on ESL 224.

[0121] Semiconductor resistor structure 260 may include resistor layer 262, contact structures 264a and 264b. Contact structure 264a is physically and / or electrically coupled to via 266, and via 266 is physically and / or electrically coupled to conductive bus structure 270. Contact structure 264b is physically and / or electrically coupled to via 268, and via 268 is physically and / or electrically coupled to conductive bus structure 272. Covering layer 278 may be included above and / or on contact structures 264a and 264b.

[0122] Figure 4 Shows the combination Figure 3Additional perspective views of the dimensions depicted include the distance D2 between the contact structures 264a and 264b, the width D3 of the conductive bus structure 270, and the length D5 of the electrical terminal 274.

[0123] As mentioned above, providing Figure 4 As an example. Other examples may differ from Figure 4 as described.

[0124] As combined Figures 2 to 4 As described elsewhere herein, a semiconductor resistor structure (e.g., semiconductor resistor structure 260) includes a resistive layer (e.g., resistive layer 262). The semiconductor resistor structure includes a row of contact structures (e.g., a row of through holes 266) located at or near the edge of the resistive layer. The semiconductor resistor structure includes a conductive bus structure (e.g., conductive bus structure 272), which includes a first edge region connected to the row of contact structures, a second edge region opposite to the first edge region, and an electrical terminal (e.g., electrical terminal 274), wherein, in a top view of the semiconductor resistor structure, the electrical terminal is located at or near the approximate center axis of the row of contact structures and at or near the second edge region.

[0125] Additionally or alternatively, the semiconductor resistor structure (e.g., semiconductor resistor structure 260) includes a resistive layer (e.g., resistive layer 262). The semiconductor resistor structure includes a first conductive bus structure (e.g., conductive bus structure 270) above and along a first edge of the resistive layer, wherein, in a top view of the semiconductor resistor structure, the first conductive bus structure has a first length (e.g., length D1). The semiconductor resistor structure includes a first row of contact structures (e.g., a row of through holes 266) between the first conductive bus structures and along the first edge of the resistive layer, wherein the first row of contact structures electrically connects the first conductive bus structure to the first edge of the resistive layer. The semiconductor resistor structure includes a second conductive bus structure (e.g., conductive bus structure 272) above and along a second edge of the resistive layer, wherein the second edge is opposite to the first edge, and wherein, in a top view of the semiconductor resistor structure, the second conductive bus structure has a second length (e.g., length D1). The semiconductor resistor structure includes a second row of contact structures (e.g., a row of vias 268) between the second conductive bus structures and along the second edge of the resistive layer, wherein the second row of contact structures electrically connects the second conductive bus structures to the second edge of the resistive layer. In some embodiments, and in a top view of the semiconductor resistor structure, a distance between the second row of contact structures and the first row of contact structures is less than a first width of the first conductive bus structures or a second width of the second conductive bus structures.

[0126] FIG. 5A to FIG. 5J is a diagram of an example implementation 500 for forming a semiconductor resistor structure described herein (e.g., semiconductor resistor structure 260). In some embodiments, one or more operations described in conjunction with example implementation 500 may be performed by one or more of semiconductor processing tools 102-112. In some embodiments, one or more operations described in conjunction with example implementation 500 may be performed by other semiconductor processing tools. In some embodiments, one or more operations described in conjunction with example implementation 500 may be performed after forming one or more other structures or layers of semiconductor device 200.

[0127] Steering Figure 5A , operations described in connection with example implementation 500 may be performed in a back-end-of-line (BEOL) region of semiconductor device 200. For example, a portion of dielectric layer 222 may be formed over and / or over ESL 220, dielectric layer 502 may be formed over and / or over a portion of dielectric layer 222, conductive layer 504 may be formed over and / or over dielectric layer 502, and / or hard mask layer 506 may be formed over and / or over conductive layer 504, among other examples.

[0128] The deposition tool 102 may use epitaxy technology, CVD technology, PVD technology, ALD technology, or a combination thereof. Figure 1 Other deposition techniques described, and / or in addition to the above combinations Figure 1 The ESL 220, portions of the dielectric layer 222, the dielectric layer 502, and / or the hard mask layer 506 may be deposited using deposition techniques other than those described above. The deposition tool 102 and / or the electroplating tool 112 may use CVD techniques, PVD techniques, ALD techniques, electroplating techniques, combinations thereof, or the like. Figure 1 Other deposition techniques described, and / or in addition to the above combinations Figure 1 Conductive layer 504 may be deposited using a deposition technique other than that described above. In some embodiments, planarization tool 110 may perform a CMP operation to planarize ESL 220, portions of dielectric layer 206, dielectric layer 502, conductive layer 504, and / or hard mask layer 506.

[0129] like Figure 5BAs shown, a portion of the dielectric layer 502 can be removed to form the resistive layer 262. In some embodiments, the pattern in the photoresist layer is used to remove a portion of the dielectric layer 502 to form the resistive layer 262. In these embodiments, the deposition tool 102 forms the photoresist layer over the hard mask layer 506. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches through the hard mask layer 506, etches through the conductive layer 504, and etches through the dielectric layer 502 to form the resistive layer 262. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or other etching techniques. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0130] In some embodiments, the etching tool 108 etches into a portion of the underlying dielectric layer 222 to ensure that the dielectric layer 502 is completely etched through. This is related to etching. The combination of the thickness of the resistive layer 262 and the overetch depth of the dielectric layer 222 may include a range of about 400 angstroms to about 600 angstroms. However, other values ​​of this range are also within the scope of the present invention.

[0131] like Figure 5C As shown, a portion of the hard mask layer 506 can be removed. The remaining portion of the hard mask layer 506 corresponds to the capping layer 278 of the semiconductor resistor structure 260. In some embodiments, the pattern in the photoresist layer is used to remove a portion of the hard mask layer 506 to form the capping layer 278. In these embodiments, the deposition tool 102 forms a photoresist layer over the hard mask layer 506. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches through the hard mask layer 506 to form the capping layer 278. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or other types of etching techniques. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0132] like Figure 5DAs shown, a portion of the conductive layer 504 is removed. The remaining portion of the conductive layer 504 corresponds to the contact structures 264a and 264b. The etching tool 108 can etch the conductive layer 504 to remove a portion of the conductive layer 504. The etching tool 108 can etch the conductive layer 504 based on the pattern in the hard mask layer 506 formed in the operation of removing a portion of the hard mask layer 506 to form the cap layer 278. In other words, the cap layer 278 is used as an etching pattern to etch the conductive layer 504 to form the contact structures 264a and 264b. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or other types of etching techniques.

[0133] like Figure 5E As shown, additional portions of dielectric layer 222 may be formed above, on, and / or around semiconductor resistor structure 260. Deposition tool 102 may use epitaxy techniques, CVD techniques, PVD techniques, ALD techniques, combinations thereof, or the like. Figure 1 Other deposition techniques described, and / or in addition to the above combinations Figure 1 The additional portion of dielectric layer 222 may be deposited using a deposition technique other than that described above. In some embodiments, planarization tool 110 may perform a CMP operation to planarize dielectric layer 222 after depositing the additional portion of dielectric layer 222 .

[0134] like Fig. 5F As shown, recesses 520 and 522 can be formed in dielectric layer 222, through cover layer 278, and into a portion of contact structures 264a and 264b, respectively. In these embodiments, deposition tool 102 forms a photoresist layer above dielectric layer 222. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. Etching tool 108 etches through dielectric layer 222, through cover layer 278, and into a portion of contact structures 264a and 264b to form recesses 520 and 522, respectively. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or other types of etching techniques. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0135] like Figure 5G As shown, recesses 520 and 522 may be filled with one or more conductive materials to form a row of through holes 266 and a row of through holes 268 in recesses 520 and 522, respectively. Deposition tool 102 and / or electroplating tool 112 may deposit using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Other deposition techniques described, and / or in addition to the above combinations Figure 1The row of vias 266 and the row of vias 268 may be deposited using a deposition technique other than that described herein. In some embodiments, the planarization tool 110 may perform a CMP operation to planarize the row of vias 266 and / or the row of vias 268.

[0136] like Figure 5H As shown, additional dielectric layers for the back-end of line (BEOL) region may be formed over semiconductor resistor structure 260. For example, ESL 224 may be formed over semiconductor resistor structure 260 and over and / or over dielectric layer 222. As another example, dielectric layer 226 may be formed over and / or over ESL 224. Deposition tool 102 may use epitaxy techniques, CVD techniques, PVD techniques, ALD techniques, or a combination thereof. Figure 1 Other deposition techniques described, and / or in addition to the above combinations Figure 1 The ESL 224 and / or the dielectric layer 226 may be deposited using a deposition technique other than those described above. In some embodiments, the planarization tool 110 may perform a CMP operation to planarize the ESL 224 and / or the dielectric layer 226 after depositing the ESL 224 and / or the dielectric layer 226 .

[0137] like Fig.5I As shown, recesses 524 and 526 can be formed through dielectric layer 226 and through ESL 224, respectively, to expose top surfaces of a row of vias 266 and a row of vias 268, respectively. In some embodiments, an edge (e.g., an inner edge) of recess 524 is biased towards the row of vias 266. In some embodiments, an edge (e.g., an inner edge) of recess 526 is biased towards the row of vias 268. Recesses 524 and 526 can also include cavities 528 and 530, respectively.

[0138] In these embodiments, deposition tool 102 forms a photoresist layer over dielectric layer 226. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to expose a pattern. Etching tool 108 etches through dielectric layer 226 and through ESL 224 to form recesses 520 and 522 and / or cavities 528 and 530. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or other etching techniques. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0139] like Figure 5JAs shown, recesses 524 and 526 may be filled with one or more conductive materials to form conductive bus structures 270 and 272 in recesses 524 and 526, respectively. Figure 5J As shown, cavities 528 and 530 may be simultaneously filled with one or more conductive materials to form electrical terminals 274 and 276, respectively. Deposition tool 102 and / or electroplating tool 112 may use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Other deposition techniques described, and / or in addition to the above combinations Figure 1 The conductive bus structures 270 and 272 and the electrical terminals 274 and 276 may be deposited using deposition techniques other than those described herein. In some embodiments, the planarization tool 110 may perform a CMP operation to planarize the conductive bus structures 270 and 272 and / or the electrical terminals 274 and 276.

[0140] As mentioned above, providing FIG. 5A to FIG. 5J As an example. Other examples may differ from FIG. 5A to FIG. 5J as described.

[0141] Figure 6 is a diagram of an example implementation 600 of a semiconductor resistor structure described herein. Figure 6 In the top view of FIG. 1 , the semiconductor resistor structure 260 a (eg, the first TFR) is electrically connected in parallel with the semiconductor resistor structure 260 b (eg, the second TFR). The combination of the electrically parallel semiconductor resistor structures 260 a and 260 b can form an ultra-low impedance semiconductor resistor structure.

[0142] Use combination Figures 5A-5J With the techniques described elsewhere herein, the conductive bus structure 270a of the first semiconductor resistor structure 260a can be formed simultaneously with the second conductive bus structure 270b of the second semiconductor resistor structure 260b. In other words, the conductive bus structures 270a and 270b (and / or the conductive bus structures 272a and 272b) can be formed on the same metal layer of the semiconductor device 200 using the same optical lithography, etching, and deposition operations. Alternatively, the conductive bus structures 270a and 270b (and / or the conductive bus structures 272a and 272b) can be formed on different metal layers of the semiconductor device using separate optical lithography, etching, and deposition operations. The conductive bus structures 270a and 270b can include conductive materials such as tungsten (W) materials, cobalt (Co materials), ruthenium (Ru) materials, titanium (Ti) materials, titanium nitride (TiN), tantalum (Ta) materials, tantalum nitride (TaN) materials, aluminum (Al) materials, copper (Cu) materials, or gold (Au) materials, or other examples of conductive materials.

[0143] like Figure 6As shown, the conductive bus structures 270a and 270b (eg, electrical terminals 274a and 274b) are connected via a connecting structure 602. Figure 6 As shown, the conductive bus structures 272a and 272b (e.g., electrical terminals 276a and 276b) are connected by a connection structure 604. The connection structures 602 and 604 may include a conductive material, such as a tungsten (W) material, a cobalt (Co) material, a ruthenium (Ru) material, a titanium (Ti) material, a titanium nitride (TiN) material, a tantalum (Ta) material, a tantalum nitride (TaN) material, an aluminum (Al) material, a copper (Cu) material, or a gold (Au) material, or other examples of conductive materials.

[0144] As mentioned above, providing Figure 6 As an example. Other examples may differ from Figure 6 as described.

[0145] Figure 7 is a diagram of an example implementation 700 of a semiconductor resistor structure (eg, semiconductor resistor structure 260) described herein. Figure 7 In the top view of FIG. 2 , the semiconductor resistor structure 260 includes an electrical terminal 702 as a part of the conductive bus structure 270. The electrical terminal 702 may correspond to a region located at or near an edge of the conductive bus structure 270 (eg, a land of a via structure).

[0146] Additionally, or alternatively, semiconductor resistor structure 260 includes an electrical terminal 704 as part of conductive bus structure 272. Electrical terminal 704 may correspond to a region at or near an edge of conductive bus structure 272 (eg, a land of a via structure).

[0147] In embodiments where protrusions (eg, electrical terminals 274 and / or 276 ) may be prohibited due to layout constraints of semiconductor resistor structure 260 , a configuration including electrical terminals 702 and / or 704 may be selected to distribute current throughout semiconductor resistor structure 260 .

[0148] In this manner, the performance of semiconductor devices including the semiconductor resistor structure 260 is improved. The improved performance of the semiconductor devices can increase the manufacturing yield of semiconductor devices to a specific performance threshold, thereby reducing the amount of resources required to support the market, which consumes the total amount of semiconductor devices that meet the specific performance threshold (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources).

[0149] As mentioned above, providing Figure 7 As an example. Other examples may differ from Figure 7 as described.

[0150] Figure 8 8 is a diagram 800 illustrating example performance (e.g., example performance 802-808) associated with variations of example semiconductor resistor structures described herein (e.g., variations of semiconductor resistor structure 260). The example performance illustrates variations in resistivity for different aspect ratios (e.g., length to width) of semiconductor resistor structure 260, which may correspond to combinations of Figure 3 Description of D2:D1.

[0151] In examples 802-808, axis 810 may illustrate an example width (e.g., width D3) of the conductive bus structure 270 in microns, and axis 812 may illustrate an example resistivity in ohms. Reference 814 may be a threshold value corresponding to the minimum manufacturable width of the conductive bus structure 270 (e.g., 0.3 microns).

[0152] In example 802, the width-to-length ratio D1:D2 is approximately 20:1. Resistivity 816 (e.g., solid filled data points) may correspond to a configuration of the semiconductor resistor structure 260 including an electrical terminal 274 centered near an edge of the conductive bus structure 270. Conversely, resistivity 818 (e.g., unfilled data points) may correspond to a configuration of the semiconductor resistor structure 260 having other electrical terminals (e.g., routing pins) located near the ends of the conductive bus structure 270. As shown in example 802, and for a width-to-length ratio of approximately 20:1, the change in resistivity 816 may be smaller relative to the change in resistivity 818.

[0153] In example 804, the width-to-length ratio D1:D2 is approximately 15:1. Resistivity 816 (e.g., solid filled data points) may correspond to a configuration of the semiconductor resistor structure 260 including an electrical terminal 274 centered near an edge of the conductive bus structure 270. Conversely, resistivity 818 (e.g., unfilled data points) may correspond to a configuration of the semiconductor resistor structure 260 having other electrical terminals located near the ends of the conductive bus structure 270. As shown in example 804, and for a width-to-length ratio of approximately 15:1, the change in resistivity 816 may be smaller relative to the change in resistivity 818.

[0154] In example 806, the width-to-length ratio D1:D2 is approximately 12:1. Resistivity 816 (e.g., solid filled data points) may correspond to a configuration of the semiconductor resistor structure 260 including an electrical terminal 274 centered near an edge of the conductive bus structure 270. Conversely, resistivity 818 (e.g., unfilled data points) may correspond to a configuration of the semiconductor resistor structure 260 having other electrical terminals located near the ends of the conductive bus structure 270. As shown in example 806, and for a width-to-length ratio of approximately 12:1, the change in resistivity 816 may be smaller relative to the change in resistivity 818.

[0155] In example 808, the width-to-length ratio D1:D2 is approximately 7:1. Resistivity 816 (e.g., solid filled data points) may correspond to a configuration of the semiconductor resistor structure 260 including an electrical terminal 274 centered near an edge of the conductive bus structure 270. Conversely, resistivity 818 (e.g., unfilled data points) may correspond to a configuration of the semiconductor resistor structure 260 having other electrical terminals located near the ends of the conductive bus structure 270. As shown in example 808, and for a width-to-length ratio of approximately 7:1, the change in resistivity 816 may be smaller relative to the change in resistivity 818.

[0156] As mentioned above, providing Figure 8 As an example. Other examples may differ from Figure 8 as described.

[0157] Fig. 9 900 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may include one or more of the apparatus 900 and / or one or more elements of the apparatus 900. Fig. 9 As shown, the device 900 may include a bus 910 , a processor 920 , a memory 930 , an input element 940 , an output element 950 , and / or a communication element 960 .

[0158] The bus 910 may include one or more components that enable wired and / or wireless communication between components of the device 900. The bus 910 may include one or more components that enable wired and / or wireless communication between components of the device 900. Fig. 9Two or more elements of are coupled together, for example, by operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 910 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or other types of processing elements. Processor 920 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0159] The memory 930 may include volatile and / or non-volatile memory. For example, the memory 930 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 930 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 930 may be a non-transitory computer-readable medium. The memory 930 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 900. In some embodiments, the memory 930 may include one or more memories, which are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 920), for example, via the bus 910. The communicative coupling between processor 920 and memory 930 may enable processor 920 to read and / or process information stored in memory 930 and / or store information in memory 930 .

[0160] Input element 940 can enable device 900 to receive input, such as user input and / or sensor input.For example, input element 940 may include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator.Output element 950 can enable device 900 to provide output, such as via display, speaker, and / or light emitting diode.Communication element 960 can enable device 900 to communicate with other devices via wired connection and / or wireless connection.For example, communication element 960 may include receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0161] The device 900 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 930) can store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 920. The processor 920 can execute the set of instructions to perform one or more operations or processes described herein. In some embodiments, the execution of the instruction set by one or more processors 920 causes one or more processors 920 and / or the device 900 to perform one or more operations or processes described herein. In some embodiments, hardwired circuits can be used instead of instructions or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 920 can be used to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuits and software.

[0162] Fig. 9 The number and arrangement of elements shown in are provided as examples. Apparatus 900 may include Fig. 9 The elements shown in the figure are additional elements, fewer elements, different elements, or differently arranged elements than those shown in the figure. Additionally or alternatively, a group of elements (e.g., one or more elements) of the device 900 can perform one or more functions described as being performed by another group of elements of the device 900.

[0163] Fig.10 1 is a flow chart of an example process 1000 associated with forming a semiconductor device (e.g., semiconductor device 200) including a semiconductor resistor structure (e.g., semiconductor resistor structure 260) described herein. In some embodiments, the process 1000 is performed by one or more semiconductor processing tools (e.g., one or more semiconductor processing tools 102-112). Fig.10 Additionally or alternatively, one or more components of the apparatus 900 may perform Fig.10One or more process blocks, the one or more elements mentioned above are, for example, a processor 920, a memory 930, an input element 940, an output element 950 and / or a communication element 960.

[0164] like Fig.10 As shown, process 1000 may include forming a row of contact structures along the lengthwise edges of a roughly rectangular resistive layer (block 1010). For example, one or more of semiconductor processing tools 102-112 may form a row of contact structures (e.g., a row of vias 266) along the lengthwise edges of a roughly rectangular resistive layer (e.g., resistive layer 262), as described herein.

[0165] like Fig.10 As further shown, process 1000 may include forming a dielectric layer over the row of contact structures (block 1020). For example, one or more of semiconductor processing tools 102-112 may form a dielectric layer (eg, dielectric layer 226) over the row of contact structures as described herein.

[0166] like Fig.10 As further shown, process 1000 may include forming a recess in the dielectric layer, the recess having a first side biased near the row of contact structures and a second side opposite the first side and biased away from the row of contact structures (block 1030). For example, one or more of semiconductor processing tools 102-112 may form a recess (e.g., recess 524) in the dielectric layer, the recess having a first side biased near the row of contact structures and a second side opposite the first side and biased away from the row of contact structures, as described herein. In some embodiments, the recess exposes the row of contact structures.

[0167] like Fig.10 As further shown, process 1000 may include forming a conductive bus structure in the recess (block 1040). For example, one or more of semiconductor processing tools 102-112 may form a conductive bus structure (e.g., conductive bus structure 270) in the recess, as described herein. In some embodiments, forming the conductive bus structure electrically connects the conductive bus structure to the approximately rectangular-shaped resistive layer through the row of contact structures.

[0168] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0169] In the first embodiment, forming the recess includes forming a substantially rectangular recess, wherein the first side is a lengthwise side of the substantially rectangular recess.

[0170] In a second embodiment, either alone or in combination with the first embodiment, forming the recess includes forming a cavity (e.g., cavity 528) extending laterally from an approximate midpoint of the second side and away from the first side, and wherein forming the conductive bus structure includes forming an electrical terminal (e.g., electrical terminal 274) in the cavity.

[0171] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming a conductive bus structure includes forming a first conductive bus structure (e.g., conductive bus structure 270a) for a first thin film resistor structure (e.g., semiconductor resistor structure 260a); also includes forming a second conductive bus structure (e.g., conductive bus structure 270b) for a second thin film resistor structure (e.g., semiconductor resistor structure 260b); and forming a connecting structure (e.g., conductive bus structure 270b) between the second conductive bus structure and the first conductive bus structure to electrically connect the second thin film resistor structure in parallel with the first thin film resistor structure.

[0172] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the first conductive bus structure and forming the second conductive bus structure together include performing a deposition operation to simultaneously form the first conductive bus structure and the second conductive bus structure.

[0173] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the deposition operation is a first deposition operation and forming the connection structure includes performing a second deposition operation as part of forming the connection structure.

[0174] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, forming a first conductive bus structure, forming a second conductive bus structure, and forming a connecting structure together include performing a deposition operation to simultaneously form the first conductive bus structure, the second conductive bus structure, and the connecting structure.

[0175] although Fig.10 Example blocks of process 1000 are shown, but in some implementations, process 1000 includes Fig.10 The blocks depicted in the process 1000 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in the process 1000. Additionally or alternatively, two or more of the blocks of the process 1000 may be performed in parallel.

[0176] Some embodiments described herein include techniques and devices for forming a semiconductor device including a semiconductor resistor structure. The semiconductor resistor structure (e.g., a low impedance TFR structure) may include a resistive layer having an approximately rectangular shape (e.g., an aspect ratio less than approximately 1). The semiconductor resistor structure includes a contact structure connected to the resistive layer, a conductive bus structure having an approximately rectangular shape connected to the contact structure, and an electrical terminal (e.g., a wiring pin) centered at or near an edge of the conductive bus structure.

[0177] The centrally located electrical terminal (combined with the approximately rectangular shape of the conductive bus structure) can improve the distribution of current throughout the semiconductor resistor structure relative to other semiconductor resistor structures that do not include a conductive bus structure having an approximately rectangular shape and / or a centrally located electrical terminal. This improved current distribution can reduce resistance variations within the semiconductor resistor structure.

[0178] In this way, the performance of semiconductor devices including semiconductor resistor structures is improved. The improved performance of semiconductor devices can increase the manufacturing yield of semiconductor devices to a specific performance threshold, thereby reducing the amount of resources required to support the market, which consumes the total amount of semiconductor devices that meet the specific performance threshold (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources).

[0179] As described in more detail above, some embodiments described herein provide a semiconductor resistor structure. The semiconductor resistor structure includes a resistor layer. The semiconductor resistor structure includes a row of contact structures located at or near the edge of the resistor layer. The semiconductor resistor structure includes a conductive bus structure, the conductive bus structure includes a first edge region connected to the row of contact structures, a second edge region opposite to the first edge region, and an electrical terminal, wherein, in a top view of the semiconductor resistor structure, the position of the electrical terminal is located at or near the approximate central axis of the row of contact structures and is located at or near the second edge region. In some embodiments, wherein the resistor layer includes an approximately rectangular shape. In some embodiments, wherein the electrical terminal is a protrusion, wherein the protrusion extends away from the second edge region of the conductive bus structure, and the protrusion extends away from a center of the resistor layer. In some embodiments, wherein the width of the protrusion is greater than about 0.3 microns and the length of the protrusion is greater than about 0.14 microns. In some embodiments, wherein the electrical terminal is an area in the second edge region connected to a vertical interconnection channel structure above the second edge region. In some embodiments, the width of the conductive bus structure is greater than the length of the conductive bus structure. In some embodiments, the length of the conductive bus structure is included in the range of about 0.3 microns to about 1.5 microns. In some embodiments, the conductive bus structure includes: tungsten material, copper material, titanium material, titanium nitride material, tantalum material, or tantalum nitride material.

[0180] As described in more detail above, some embodiments described herein provide a semiconductor resistor structure. The semiconductor resistor structure includes a resistor layer. The semiconductor resistor structure includes a first conductive bus structure above and along a first edge of the resistor layer, wherein, in a top view of the semiconductor resistor structure, the first conductive bus structure has a first length. The semiconductor resistor structure includes a first row of contact structures between the first conductive bus structures and along the first edge of the resistor layer, wherein the first row of contact structures electrically connects the first conductive bus structure to the first edge of the resistor layer. The semiconductor resistor structure includes a second conductive bus structure above and along a second edge of the resistor layer, wherein the second edge is opposite to the first edge, and in a top view of the semiconductor resistor structure, the second conductive bus structure has a second length. The semiconductor resistor structure includes a second row of contact structures between and along the second edge of the resistor layer, wherein the second row of contact structures electrically connects the second conductive bus structure to the second edge of the resistor layer. In some embodiments, and in a top view of the semiconductor resistor structure, the distance between the second row of contact structures and the first row of contact structures is less than the first length of the first conductive bus structure or the second length of the second conductive bus structure. In some embodiments, the semiconductor resistor structure further comprises: a third conductive bus structure connecting the first row of contact structures to the first edge of the resistive layer. In some embodiments, the semiconductor resistor structure further comprises: a third conductive bus structure connecting the second row of contact structures to the second edge of the resistive layer. In some embodiments, the impedance of the semiconductor resistor structure is less than about 50 ohms. In some embodiments, the resistance variation across the semiconductor resistor structure is less than about 15%.

[0181] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor resistor structure. The method includes forming a row of contact structures along the length direction edge of an approximately rectangular resistor layer. The method includes forming a dielectric layer above the row of contact structures. The method includes forming a recess in the dielectric layer, the recess having a first side biased near the row of contact structures and a second side opposite to the first side and biased away from the row of contact structures, wherein the recess exposes the row of contact structures. The method includes forming a conductive bus structure in the recess, wherein forming a conductive bus structure electrically connects the conductive bus structure to the approximately rectangular resistor layer through the row of contact structures. In some embodiments, wherein forming the recess includes: forming an approximately rectangular recess, wherein the first side is a length direction side of the approximately rectangular recess. In some embodiments, wherein forming the recess includes forming a cavity, wherein the cavity extends laterally from an approximate midpoint of the second side and away from the first side, wherein forming the conductive bus structure includes: forming an electrical terminal in the cavity. In some embodiments, forming the conductive bus structure includes: forming a first conductive bus structure for a first thin film resistor structure; forming a second conductive bus structure for a second thin film resistor structure; and forming a connection structure between the second conductive bus structure and the first conductive bus structure to electrically connect the second thin film resistor structure and the first thin film resistor structure in parallel. In some embodiments, forming the first conductive bus structure and forming the second conductive bus structure jointly include: performing a deposition operation to simultaneously form the first conductive bus structure and the second conductive bus structure. In some embodiments, the deposition operation is a first deposition operation, and forming the connection structure includes: performing a second deposition operation as part of forming the connection structure. In some embodiments, forming the first conductive bus structure, forming the second conductive bus structure, and forming the connection structure jointly include: performing a deposition operation, wherein the deposition operation simultaneously forms the first conductive bus structure, the second conductive bus structure, and the connection structure.

[0182] As described in more detail above, some embodiments described herein provide a semiconductor resistor structure. The semiconductor resistor structure includes a first thin film resistor structure, a second thin film resistor structure, and a connection structure electrically connecting the second thin film resistor structure and the first thin film resistor structure in parallel. Each of the first thin film resistor structure and the second thin film resistor structure includes a resistor layer. Each of the first thin film resistor structure and the second thin film resistor structure includes a row of contact structures located at or near the edge of the resistor layer. Each of the first thin film resistor structure and the second thin film resistor structure includes a conductive bus structure, the conductive bus structure includes a first edge region connected to the row of contact structures, a second edge region opposite to the first edge region, and an electrical terminal, wherein, in a top view of each of the first thin film resistor structure and the second thin film resistor structure, the position of the electrical terminal is located at or near the approximate central axis of the row of contact structures and is located at or near the second edge region. Wherein, the connection structure is between the conductive bus structure of the first thin film resistor structure and the conductive bus structure of the second thin film resistor structure.

[0183] As used herein, the term "and / or", when used in conjunction with multiple items, is intended to cover each of the multiple items individually as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A but not B", and "B but not A".

[0184] As used herein, "satisfies a threshold value" may refer to a numerical value that satisfies the following conditions, depending on the context: greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, etc.

[0185] The features of several embodiments are summarized above, so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same goals and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor resistor structure, characterized in that: include: a resistance layer; an array of contact structures located at or near an edge of the resistive layer; and A conductive bus structure, comprising: a first edge region connected to the row of contact structures; a second edge region, opposite to the first edge region; and an electrical terminal; Wherein, a position of the electrical terminal is located at or close to a central axis of the row of contact structures, and is located at or near the second edge region.

2. The semiconductor resistor structure according to claim 1, wherein: The resistance layer includes: A rectangular shape.

3. The semiconductor resistor structure according to claim 1, wherein: The impedance of the semiconductor resistor structure is less than 50 ohms.

4. A semiconductor resistor structure, characterized in that: include: a resistance layer; a first conductive bus structure above and along a first edge of the resistive layer; Wherein, the first conductive bus structure has a first length; a first row of contact structures between the first conductive bus structures and along the first edge of the resistive layer; wherein the first row of contact structures electrically connects the first conductive bus structure to the first edge of the resistor layer; a second conductive bus structure above and along a second edge of the resistive layer; wherein the second edge is opposite to the first edge; and Wherein, the second conductive bus structure has a second length; and a second row of contact structures between the second conductive bus structures and along the second edge of the resistive layer; wherein the second row of contact structures electrically connects the second conductive bus structure to the second edge of the resistor layer; and A distance between the second row of contact structures and the first row of contact structures is smaller than the first length of the first conductive bus structure or the second length of the second conductive bus structure.

5. The semiconductor resistor structure according to claim 4, characterized in that Also includes: A third conductive bus structure connects the first row of contact structures and the first edge of the resistor layer.

6. The semiconductor resistor structure according to claim 4, wherein: Also includes: A third conductive bus structure connects the second row of contact structures and the second edge of the resistor layer.

7. A semiconductor resistor structure, characterized in that: include: a first thin film resistor structure; a second thin film resistor structure; and a connection structure electrically connecting the second thin film resistor structure and the first thin film resistor structure in parallel; Each of the first thin film resistor structure and the second thin film resistor structure comprises: a resistance layer; an array of contact structures located at or near an edge of the resistive layer; and A conductive bus structure, comprising: a first edge region connected to the row of contact structures; a second edge region, opposite to the first edge region; and an electrical terminal; Wherein, a position of the electrical terminal is located at or close to a central axis of the row of contact structures, and is located at or close to the second edge region; The connection structure is between the conductive bus structure of the first thin film resistor structure and the conductive bus structure of the second thin film resistor structure.

8. The semiconductor resistor structure according to claim 7, characterized in that The electrical terminal is a protrusion, wherein the protrusion extends away from the second edge region of the conductive bus structure, and the protrusion extends away from a center of the resistance layer.

9. The semiconductor resistor structure according to claim 7, wherein: The electrical terminal is a region in the second edge region connected to a vertical interconnection channel structure above the second edge region.

10. The semiconductor resistor structure according to claim 7, wherein: The width of the conductive bus structure is greater than the length of the conductive bus structure.

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