Charge pump circuit, memory and electronic equipment

Abstract

The utility model discloses a charge pump circuit, a memory and an electronic device. The charge pump circuit comprises a voltage stabilizing module, a charge pump adjusting circuit, an NMOS tube and a charge pump module. The output end of the voltage stabilizing module is connected with the first voltage input end of the charge pump adjusting circuit, the output end of the charge pump adjusting circuit is connected with the grid electrode of the NMOS tube, and the source electrode of the NMOS tube is connected with the input end of the charge pump module. The input end of the voltage stabilizing module, the second voltage input end of the charge pump adjusting circuit and the drain electrode of the NMOS tube are respectively connected with the power supply module. By arranging the charge pump adjusting circuit, the working efficiency of the charge pump module can be improved, the output voltage ripple of the charge pump module can be relatively small, and the stability of voltage output is improved; and meanwhile, the stable second output voltage is generated by utilizing the NMOS tube, and a decoupling capacitor does not need to be additionally arranged, so that the miniaturization of the whole structure is facilitated, and the occupied space is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of charge pumps, and in particular to a charge pump circuit, a memory and an electronic device. Background Art

[0002] With the development of semiconductor technology, based on the design requirements of low power consumption and low cost, the power supply voltage of memory is usually relatively low. However, in order to realize the reading and writing of stored information, the programming voltage and erase voltage that are much higher than the power supply voltage are usually required. Therefore, charge pumps are widely used in memory to obtain higher read voltage, programming voltage and erase voltage through lower power supply voltage.

[0003] In the prior art, a charge pump is usually directly connected to a power module to obtain a power supply voltage, or a low dropout linear regulator (LDO) is connected in series to generate a low voltage as an input voltage of the charge pump.

[0004] However, the wide variation range of the power supply voltage makes the driving capability of the charge pump vary widely, resulting in large output voltage ripple of the charge pump and unstable output voltage; while the output voltage VDD generated by the LDO is too low, and too many levels are required to generate high voltage based on the output voltage VDD of the LDO (for example, from 1.2V to 10V), resulting in low efficiency and high power consumption of the charge pump, and the need to add additional larger decoupling capacitors, resulting in excessive circuit area.

[0005] Based on this, a new charge pump circuit is urgently needed to achieve charge pump regulation with fast voltage boost, small ripple and stable output voltage. Utility Model Content

[0006] In view of the above problems, the present invention is proposed to provide a charge pump circuit, a memory and an electronic device that overcome the above problems or at least partially solve the above problems.

[0007] According to the first aspect of the embodiment of the utility model, a charge pump circuit is provided, which is connected to a power supply module, and the charge pump circuit includes: a voltage stabilizing module, a charge pump regulating circuit, an NMOS tube and a charge pump module; the output end of the voltage stabilizing module is connected to the first voltage input end of the charge pump regulating circuit, the output end of the charge pump regulating circuit is connected to the gate of the NMOS tube, and the source of the NMOS tube is connected to the input end of the charge pump module; the input end of the voltage stabilizing module, the second voltage input end of the charge pump regulating circuit and the drain of the NMOS tube are respectively connected to the power supply module.

[0008] According to a second aspect of the embodiments of the present utility model, a memory is provided, comprising the above-mentioned charge pump circuit.

[0009] According to a third aspect of the embodiments of the present utility model, there is provided an electronic device, including: a processor and the above-mentioned memory.

[0010] The technical solution provided in the embodiment of the utility model has at least the following technical effects or advantages:

[0011] The charge pump circuit, memory and electronic device described in the embodiment of the utility model, the charge pump circuit can improve the working efficiency of the charge pump module and reduce the output voltage ripple of the charge pump module by setting the charge pump regulation circuit and using the power supply voltage VCC as its input voltage and the first output voltage VDD as the boost voltage of the clock of the charge pump regulation circuit, thereby improving the stability of the voltage output; at the same time, the NMOS tube is used to generate a stable second output voltage VCP, and no additional decoupling capacitor is required, which is conducive to the miniaturization of the overall structure and reduces space occupancy; and the charge pump module uses the second output voltage VCP as the input voltage and the boost voltage of the clock, and the boost efficiency is high.

[0012] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 This is a schematic diagram of the principle structure of the charge pump circuit of the utility model;

[0015] Figure 2 This is a reference circuit diagram of the charge pump regulation circuit of the utility model.

[0016] Description of reference numerals:

[0017] 1. Voltage regulator module; 2. Charge pump regulation circuit; 3. NMOS tube; 4. Charge pump module; 5. Power module; 6. Switch module. DETAILED DESCRIPTION

[0018] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0019] In order to enable those skilled in the art to better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. The drawings show preferred embodiments of the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0020] Unless otherwise specified, various raw materials, instruments and equipment used in the present invention can be purchased from the market or prepared by existing methods.

[0021] See also Figure 1 As shown, Figure 1 It is a schematic diagram of the principle structure of a charge pump circuit provided in an embodiment of the utility model. The charge pump circuit is connected to a power supply module 5, the output end of the power supply module 5 is connected to the input end of the charge pump circuit, and the power supply module 5 is used to provide a power supply voltage VCC for the charge pump circuit.

[0022] The charge pump circuit includes a voltage stabilizing module 1, a charge pump regulating circuit 2, an NMOS tube 3 and a charge pump module 4; the output end of the voltage stabilizing module 1 is connected to the first voltage input end of the charge pump regulating circuit 2, the output end of the charge pump regulating circuit 2 is connected to the gate of the NMOS tube 3, and the source of the NMOS tube 3 is connected to the input end of the charge pump module 4; the input end of the voltage stabilizing module 1, the second voltage input end of the charge pump regulating circuit 2 and the drain of the NMOS tube 3 are respectively connected to the power supply module 5.

[0023] The input end of the voltage stabilizing module 1 receives the power supply voltage VCC output by the power supply module 5, and the output end of the voltage stabilizing module 1 outputs a first output voltage VDD; the first voltage input end of the charge pump regulating circuit 2 receives the first output voltage VDD output by the voltage stabilizing module 1, the second voltage input end of the charge pump regulating circuit 2 receives the power supply voltage VCC output by the power supply module 5, and the output end of the charge pump regulating circuit 2 outputs a clamping voltage Vclamp; the gate of the NMOS tube 3 receives the clamping voltage Vclamp output by the charge pump regulating circuit 2, the drain of the NMOS tube 3 receives the power supply voltage VCC output by the power supply module 5, and the source of the NMOS tube 3 outputs a second output voltage VCP; the input end of the charge pump module 4 receives the second output voltage VCP output by the NMOS tube 3, and the output end of the charge pump module 4 outputs an operating voltage Vpos, and the operating voltage Vpos is a stable operating voltage of a storage unit in a memory.

[0024] In the embodiment of the utility model, the voltage stabilizing module 1 is a low-dropout linear regulator (LDO), which is used to convert the power supply voltage VCC (high voltage) output by the power supply module 5 into a first output voltage VDD (low voltage).

[0025] See also Figure 2 As shown, Figure 2 This is a reference circuit diagram of the charge pump regulation circuit 2 of the utility model. The charge pump regulation circuit 2 uses the high-voltage power supply voltage VCC as the input voltage, and uses the low-voltage first output voltage VDD output by the voltage regulator module 1 as the boost voltage of the clock of the charge pump regulation circuit 2, and finally outputs a clamping voltage Vclamp.

[0026] Specifically, the charge pump regulation circuit 2 includes n groups of sub-regulation units (i.e., n stages, each stage being a group of sub-regulation units) connected in series, the input end of the first group of sub-regulation units is connected to the output end of the power supply module, and the input end of each group of sub-regulation units except the first group of sub-regulation units is connected to the output end of the sub-regulation unit of the previous stage, the nth group of sub-regulation units is connected to the gate of the NMOS tube 3, and outputs the clamping voltage Vclamp, and n is a positive integer.

[0027] In the embodiment of the utility model, the structures of the n groups of sub-regulation units connected in series in the charge pump regulation circuit 2 are the same. It can be understood that the input end of the second group of sub-regulation units is connected to the output end of the first group of sub-regulation units, and the input end of the third group of sub-regulation units is connected to the output end of the second group of sub-regulation units.

[0028] The sub-regulation unit includes a diode (i.e. Figure 2One of D1 to Dn in the figure, the specifications of D1 to Dn are the same) and a decoupling capacitor (i.e. Figure 2 One of C1~Cn in the figure, and the specifications of C1~Cn are the same), wherein the positive electrode of the diode is the input end of the sub-regulation unit, the negative electrode of the diode and one end of the decoupling capacitor are connected in series and grounded, and the end in series of the negative electrode of the diode and the decoupling capacitor is the output end of the sub-regulation unit, and the other end of the decoupling capacitor is connected to the output end of the voltage stabilizing module 1; due to the problem of parasitic capacitance, in the embodiment of the utility model, one end of the parasitic capacitor is connected to the negative electrode of the diode and one end in series of the decoupling capacitor, and the other end of the parasitic capacitor is grounded, thereby reducing the influence of parasitic capacitance.

[0029] The first voltage input terminal includes a first clock voltage terminal and a second clock voltage terminal, and the first clock voltage terminal and the second clock voltage terminal are connected to the output terminal of the voltage stabilizing module 1; when the nth group is an odd number, each corresponding group of the sub-regulation units is connected to the first clock voltage terminal (CLKa); when the nth group is an even number, each corresponding group of the sub-regulation units is connected to the second clock voltage terminal (CLKb); that is, the clock voltage CLKa / CLKb of the charge pump regulation circuit 2 is equal to the first output voltage VDD, then each time the clock voltage flips, the amount of charge transmitted is small, so that the voltage ripple of the final output clamping voltage VClamp is small, thereby improving the stability of the voltage output.

[0030] In the embodiment of the utility model, since the size of the clamping voltage Vclamp output by the charge pump regulation circuit 2 is proportional to the number of levels set by the sub-regulation unit, that is, the larger the number n of levels set by the sub-regulation unit, the larger the output clamping voltage Vclamp, based on this, the embodiment of the utility model can determine the number n of levels set by the sub-regulation unit based on the clamping voltage Vclamp actually required.

[0031] Specifically, before determining the level n set by the sub-regulation unit, a voltage-level table can be obtained first, and the voltage-level table represents the correspondence between the voltage group (the first output voltage VDD and the actually required clamping voltage Vclamp) and the level n set by the sub-regulation unit; the voltage-level table can be obtained through multiple repeated tests before the memory is shipped; after obtaining the voltage size of the first output voltage VDD actually output by the voltage stabilizing module 1, the level n is determined by looking up the table according to the first output voltage VDD and the actually required clamping voltage Vclamp, and then the number of the connected sub-regulation units is determined according to the level n; since the voltage range corresponding to the first output voltage VDD actually output by the voltage stabilizing module 1 is very large, that is, there is uncertainty, therefore, the first output voltage VDD output each time may be slightly different, and the level n set by the sub-regulation unit is controlled by the first output voltage VDD and the actually required clamping voltage Vclamp, so that the charge pump regulation circuit 2 can stably boost the first output voltage VDD actually output by the voltage stabilizing module 1 to the clamping voltage Vclamp.

[0032] It can be known from the connection method between the aforementioned first clock voltage terminal and the second clock voltage terminal and the corresponding sub-regulation units that when n is an odd number and an even number respectively, the number of sub-regulation units correspondingly connected to the first clock voltage terminal and the second clock voltage terminal is not the same, that is, in the embodiment of the utility model, the number of the sub-regulation units finally connected can also be determined by determining the level n, so as to achieve the purpose of controlling the size of the output clamping voltage Vclamp.

[0033] Of course, the connection method of the charge pump regulation circuit 2 is not limited to the above-mentioned embodiment. As long as the charge pump regulation circuit 2 outputs a clamping voltage when the voltage stabilizing module 1 provides the first output voltage to the charge pump regulation circuit 2, it can be selected based on actual application requirements. Other connection forms can be adopted between the n groups of sub-regulation units, or each group of sub-regulation units can also adopt other structures or connection methods, which are also within the scope of the concept of the present invention.

[0034] A switch module 6 is further provided between the charge pump circuit and the power module 5 , and the switch module 6 is respectively connected to the output end of the power module 5 and the input end of the charge pump circuit, and is used to control the on or off of the output of the power module 5 .

[0035] Compared with the prior art, the charge pump circuit described in the embodiment of the utility model has the following advantages:

[0036] 1. By setting the charge pump regulating circuit 2, and using the power supply voltage VCC as its input voltage, and the first output voltage VDD as the boost voltage of the clock of the charge pump regulating circuit 2, the working efficiency of the charge pump module 4 can be improved, and the output voltage ripple of the charge pump module 4 can be reduced, thereby improving the stability of the voltage output;

[0037] 2. The NMOS tube 3 is used to generate a stable second output voltage VCP, and no additional decoupling capacitor is required, which is conducive to the miniaturization of the overall structure and reduces space occupation;

[0038] 3. The charge pump module 4 uses the second output voltage VCP as the input voltage and the boost voltage of the clock, and has high boost efficiency;

[0039] 4. The charge pump regulation circuit 2 is composed of n groups of sub-regulation units connected in series, and the larger the number of stages n of the sub-regulation units, the larger the output clamping voltage Vclamp. The embodiment of the utility model can determine the number of stages n of the sub-regulation units based on the actual required clamping voltage Vclamp, which is highly flexible and has good applicability even for the power supply voltage VCC with a wide voltage supply range.

[0040] The charge pump circuit described in the embodiment of the utility model can be used in a memory to provide voltage to the storage units in the memory. The memory may also include structures such as an erase control unit and a decoding circuit; the memory is used to store non-volatile software programs, non-volatile computer executable programs and modules.

[0041] The preferred embodiments of the utility model are as described above, but the utility model is not limited to the above embodiments. For example, the charge pump circuit is not limited to being set as one group, but can also be two groups, three groups or more. The number of charge pump circuit settings is determined based on the storage units in the memory. For example, an independently partitioned storage unit corresponds to a group of charge pump circuits, and each group of charge pump circuits supplies power to an independently partitioned storage unit. Of course, it should be noted that in the embodiments of the utility model, in order to save circuit area, only one group of charge pump circuits is set in the utility model. According to the above description of the utility model, when there are more than two independently partitioned storage units, it is understandable to ordinary technicians in the field to set a corresponding number of multiple groups of charge pump circuits, which will not be elaborated here.

[0042] In an embodiment of the utility model, when there are multiple groups of charge pump circuits, the switch module 6 can be the switch control end of all the charge pump circuits. In other implementations, a switch module 6 can also be configured separately for each group of charge pump circuits. It can be determined according to actual needs, and the utility model has no restrictions on this.

[0043] In addition, the present invention is not limited to using the switch module 6 to control whether the output end of each group of the power supply modules 5 is connected to the input end of the charge pump circuit. Other switch structures can also be used as long as the on and off control functions can be achieved. This is understandable to technicians in this field and will not be elaborated here.

[0044] The memory may be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc.; the memory may also include a combination of the above types of memory.

[0045] On the basis of the above embodiments, the utility model also provides an electronic device, the electronic device includes a processor and the memory described in any of the above embodiments, the processor is used to execute the non-transient software program, non-transient computer executable program and module stored in the memory; the processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components and other chips, or a combination of the above chips.

[0046] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0047] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various utility model aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: the claimed utility model requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims, the utility model aspects are less than all the features of the previously disclosed single embodiment. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0048] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A charge pump circuit, connected to a power module, characterized in that: The charge pump circuit includes: a voltage stabilizing module, a charge pump regulating circuit, an NMOS tube and a charge pump module; the output end of the voltage stabilizing module is connected to the first voltage input end of the charge pump regulating circuit, the output end of the charge pump regulating circuit is connected to the gate of the NMOS tube, and the source of the NMOS tube is connected to the input end of the charge pump module; the input end of the voltage stabilizing module, the second voltage input end of the charge pump regulating circuit and the drain of the NMOS tube are respectively connected to the power supply module.

2. The charge pump circuit according to claim 1, characterized in that: The charge pump regulation circuit includes n groups of sub-regulation units connected in series at multiple stages, the input end of the first group of sub-regulation units is connected to the power supply module, the input end of each group of sub-regulation units except the first group of sub-regulation units is connected to the output end of the sub-regulation unit of the previous stage, the nth group of sub-regulation units is connected to the gate of the NMOS tube, and n is a positive integer.

3. The charge pump circuit according to claim 2, characterized in that: The n groups of sub-regulation units in the charge pump regulation circuit have the same structure.

4. The charge pump circuit according to claim 3, characterized in that: The sub-regulation unit includes a diode and a decoupling capacitor, wherein the anode of the diode is the input end of the sub-regulation unit, the cathode of the diode and one end of the decoupling capacitor are connected in common and grounded, and the cathode of the diode and one end of the decoupling capacitor are connected in common as the output end of the sub-regulation unit, and the other end of the decoupling capacitor is connected to the output end of the voltage stabilization module.

5. The charge pump circuit according to any one of claims 2 to 4, characterized in that: The first voltage input terminal includes a first clock voltage terminal and a second clock voltage terminal, and the first clock voltage terminal and the second clock voltage terminal are connected to the output terminal of the voltage stabilizing module; when the nth group is an odd number, each corresponding group of the sub-regulation units is connected to the first clock voltage terminal; when the nth group is an even number, each corresponding group of the sub-regulation units is connected to the second clock voltage terminal.

6. The charge pump circuit according to claim 1, characterized in that: A switch module is further provided between the charge pump circuit and the power module, and the switch module is respectively connected to the output end of the power module and the input end of the charge pump circuit.

7. A memory, characterized in that: The charge pump circuit comprises the charge pump circuit according to any one of claims 1 to 6.

8. An electronic device, characterized in that: include: A processor and the memory as claimed in claim 7.

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