Semiconductor device

Abstract

The semiconductor device provided by the utility model comprises a substrate, a channel layer, a barrier layer and a gate structure. The channel layer is arranged on the substrate, and the channel layer comprises a nitride semiconductor material. The barrier layer is arranged on the side, away from the substrate, of the channel layer, the barrier layer comprises a nitride semiconductor material, and the energy gap of the barrier layer is larger than that of the channel layer. The gate structure comprises a cap layer, a gate and an etching insertion layer, the cap layer comprises a nitride semiconductor material and is arranged on one side, far away from the channel layer, of the barrier layer, the gate is arranged on one side, far away from the barrier layer, of the cap layer, and the etching insertion layer is arranged between the gate and the cap layer. Wherein the grid electrode comprises a first side wall, and a first chamfer is arranged at the position, adjacent to the etching insertion layer, of the first side wall; the etching insertion layer comprises a second side wall, and the second side wall is provided with a second chamfer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor device. Background Technology

[0002] Components containing direct bandgap semiconductors, such as semiconductor components containing III-V materials or III-V compounds (category: III-V compounds), can operate or function under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies).

[0003] Semiconductor components may include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), high-electron-mobility transistors (HEMTs), and modulation-doped FETs (MODFETs). Utility Model Content

[0004] According to one aspect of the embodiments of this application, a semiconductor device is provided, the semiconductor device comprising:

[0005] Substrate;

[0006] A channel layer is disposed on the substrate, and the channel layer comprises a nitride semiconductor material;

[0007] A barrier layer is disposed on the side of the channel layer away from the substrate, the barrier layer comprising a nitride semiconductor material, and the band gap of the barrier layer being larger than the band gap of the channel layer.

[0008] A gate structure, the gate structure including a cap layer, a gate and an etch insertion layer, the cap layer including a nitride semiconductor material and disposed on the side of the barrier layer away from the channel layer, the gate being disposed on the side of the cap layer away from the barrier layer, and the etch insertion layer being disposed between the gate and the cap layer;

[0009] The gate includes a first sidewall, which has a first chamfer at the location adjacent to the etch insertion layer; the etch insertion layer includes a second sidewall, which has a second chamfer.

[0010] In some embodiments, the width of the first chamfer gradually decreases as it approaches the cap layer.

[0011] In some embodiments, the first sidewall includes a vertically arranged first sub-sidewall and an inclined second sub-sidewall, with the first chamfer disposed on the second sub-sidewall.

[0012] In some embodiments, the width of the second chamfer gradually increases as it approaches the cap layer.

[0013] In some embodiments, the etched insertion layer comprises a nitride.

[0014] In some embodiments, the etched insertion layer comprises aluminum nitride.

[0015] In some embodiments, the cap layer comprises a p-type dopant.

[0016] In some embodiments, the cap layer comprises p-type gallium nitride.

[0017] In some embodiments, the channel layer comprises the compound In a Al b Ga (1-a-b) N, where a+b≦1;

[0018] Alternatively, the channel layer comprises the compound Al a Ga (1-a) N, where a≦1.

[0019] In some embodiments, the barrier layer comprises the compound In a Al b Ga (1-a-b) N, where a+b≦1;

[0020] Alternatively, the barrier layer may comprise the compound Al. a Ga (1-a) N, where a≦1.

[0021] In some embodiments, the channel layer is made of gallium nitride, and the barrier layer is made of aluminum gallium nitride.

[0022] In some embodiments, the semiconductor device further includes a buffer layer disposed between the substrate and the channel layer, the buffer layer comprising a III-V compound.

[0023] In some embodiments, the material of the buffer layer includes AlN, AlGaN, InAlGaN, GaAs, AlAs, ZnO, or combinations thereof.

[0024] In some embodiments, the semiconductor device further includes a nucleation layer disposed between the substrate and the channel layer. Attached Figure Description

[0025] Figure 1 This is a cross-sectional schematic diagram of an existing semiconductor device;

[0026] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in an exemplary embodiment of this application;

[0027] Figures 3 to 9 This is a cross-sectional schematic diagram of various stages of a method for manufacturing a semiconductor device provided in an exemplary embodiment of this application. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0029] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0030] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0031] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or placing a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed or placed in direct contact, and may also include embodiments in which additional features may be formed and placed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0032] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0033] This disclosure provides a semiconductor device, the semiconductor device comprising:

[0034] Substrate;

[0035] A channel layer is disposed on the substrate, and the channel layer comprises a nitride semiconductor material;

[0036] A barrier layer is disposed on the side of the channel layer away from the substrate, the barrier layer comprising a nitride semiconductor material, and the band gap of the barrier layer being larger than the band gap of the channel layer.

[0037] A gate structure, the gate structure including a cap layer, a gate and an etch insertion layer, the cap layer including a nitride semiconductor material and disposed on the side of the barrier layer away from the channel layer, the gate being disposed on the side of the cap layer away from the barrier layer, and the etch insertion layer being disposed between the gate and the cap layer;

[0038] The gate includes a first sidewall, which has a first chamfer at the location adjacent to the etch insertion layer; the etch insertion layer includes a second sidewall, which has a second chamfer.

[0039] By setting an etch insertion layer between the cap layer and the gate, and setting a first chamfer on the first sidewall of the gate adjacent to the etch insertion layer, and setting a second chamfer on the second sidewall of the etch insertion layer, the electric field curvature peak at the edge is reduced, the electric field distribution is optimized, and the gate reliability is improved.

[0040] The semiconductor devices disclosed herein can be used in, but are not limited to, HEMT devices, particularly in low-voltage HEMT devices, high-voltage HEMT devices, and radio frequency (RF) HEMT devices.

[0041] Figure 1 This is a cross-sectional schematic diagram of an existing semiconductor device. The semiconductor device has a channel layer, a barrier layer, a P-type GaN cap layer, and a gate electrode sequentially formed on a substrate. The gate electrode and the P-type GaN cap layer form a Schottky junction. The angle between the gate electrode sidewall and the upper surface of the P-type GaN cap layer is close to 90°, resulting in a concentrated electric field at the gate electrode. Under long-term gate electrode stress, high electric field-induced gate characteristic degradation occurs. Therefore, electric field optimization techniques are typically introduced to reduce the peak electric field on the Schottky junction sidewall and improve the gate electrode reliability of the device.

[0042] Figure 2 This is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may include a substrate 20, a buffer layer 30, a first nitride semiconductor layer 40, a second nitride semiconductor layer 50, and a gate structure 90. The gate structure 90 may include a cap layer 60, an etched insertion layer 70, and a gate 80.

[0043] Substrate 20 may comprise, but is not limited to, silicon (Si), doped silicon (SiC), silicon carbide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. Substrate 20 may comprise, but is not limited to, sapphire, silicon on insulator (SOI), or other suitable materials. In some embodiments, substrate 20 may also include doped regions (not shown), such as p-wells, n-wells, etc.

[0044] A nucleation layer (not shown) may be disposed between substrate 20 and buffer layer 30. The nucleation layer may form an interface with substrate 20. The nucleation layer is configured to provide a top surface for growing group III nitride material thereon. In other words, the nucleation layer forms a suitable template to transition from the lattice of the substrate to a template more suitable for the growth of group III nitride material. The nucleation layer provides a transition to accommodate mismatch / difference (e.g., epitaxial formation) between substrate 20 and the group III nitride layer to be formed on its top surface. Mismatch / difference may involve different lattice constants or coefficients of thermal expansion. Mismatch / difference may result in dislocations in the formed layer, thereby reducing the yield rate. Exemplary materials for the nucleation layer may include, but are not limited to, aluminum nitride (AlN) or any alloy thereof. Aluminum nitride may be, for example, but not limited to, doped n-type, p-type, or intrinsic. The material of the nucleation layer may be selected to eliminate mismatch / difference. For example, to accommodate mismatch / difference caused by a first element in the layer to be formed on the nucleation layer, the nucleation layer is formed to include the first element.

[0045] The buffer layer 30 can be disposed on the nucleation layer or directly on the substrate 20. The buffer layer 30 can form an interface with the nucleation layer. The buffer layer 30 has a bottom surface in contact with the nucleation layer. This interface is formed by the bottom surface of the buffer layer 30 and the top surface of the nucleation layer. The buffer layer 30 has a top surface opposite the bottom surface. The buffer layer 30 is configured to reduce lattice mismatch and thermal mismatch between the underlying layer and the layer to be formed on the buffer layer 30 (e.g., epitaxially formed thereon), thereby solidifying defects caused by mismatch / difference.

[0046] Buffer layer 30 may include III-V compounds. III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrides, or combinations thereof. Therefore, exemplary materials of buffer layer 30 may further include (e.g., but not limited to) AlN, AlGaN, InAlGaN, GaAs, AlAs, ZnO, or combinations thereof. In some embodiments, buffer layer 30 may include two group III elements, and the nucleation layer may have only one group III element. For example, the nucleation layer may include a compound containing aluminum but not gallium (e.g., AlN), and buffer layer 30 may include a III-V compound containing aluminum and gallium (e.g., AlGaN).

[0047] A first nitride semiconductor layer 40 (also referred to as channel layer 40) may be disposed on the buffer layer 30. The first nitride semiconductor layer 40 may comprise a III-V group material layer. The first nitride semiconductor layer 40 may comprise, but is not limited to, group III nitrides, such as the compound In. a Al b Ga (1-a-b) N, where a+b≦1. The group III nitrides further comprise, but are not limited to, for example, the compound Al. a Ga (1-a)N, where a≦1. The first nitride semiconductor layer 40 may comprise a gallium nitride (GaN) layer. The bandgap of GaN is approximately 3.4 eV. The thickness of the first nitride semiconductor layer 40 may range from, but is not limited to, approximately 0.5 μm to approximately 10 μm.

[0048] A second nitride semiconductor layer 50 (also referred to as a barrier layer 50) may be disposed on the first nitride semiconductor layer 40. The second nitride semiconductor layer 50 may comprise a III-V group material layer. The second nitride semiconductor layer 50 may comprise, but is not limited to, group III nitrides, such as the compound In. a Al b Ga (1-a-b) N, where a+b≦1. The group III nitrides may further include, but are not limited to, compounds such as Al. a Ga (1-a) N, where a≦1. The bandgap of the second nitride semiconductor layer 50 can be greater than the bandgap of the first nitride semiconductor layer 40. The second nitride semiconductor layer 50 may comprise an aluminum gallium nitride (AlGaN) layer. The bandgap of AlGaN is approximately 4.0 eV. The thickness of the second nitride semiconductor layer 50 can range from, but is not limited to, approximately 10 nm to approximately 100 nm.

[0049] A heterojunction is formed between the second nitride semiconductor layer 50 and the first nitride semiconductor layer 40. Because the band gap of the second nitride semiconductor layer 50 is larger than that of the first nitride semiconductor layer 40, free charges transfer from the second nitride semiconductor layer 50 to the first nitride semiconductor layer 40, causing polarization at the heterojunction interface. As a result, electrons overflow from the wide-bandgap second nitride semiconductor layer 50, leaving only positive charges (donor ions). These space charges generate an electrostatic potential, causing band bending and forming a two-dimensional potential well at the heterojunction interface. This two-dimensional potential well confines the polarization-induced electrons within it. These electrons can move in two dimensions within the potential well along a plane parallel to the interface between the second nitride semiconductor layer 50 and the first nitride semiconductor layer 40, thereby accumulating charge at the interface between the second nitride semiconductor layer 50 and the first nitride semiconductor layer 40, forming a two-dimensional electron gas (2DEG). 2DEGs can have very high electron mobility. In some embodiments, a second nitride semiconductor layer 50, having a larger bandgap than the first nitride semiconductor layer 40, can serve as a barrier layer in the semiconductor device 100. In some embodiments, a first nitride semiconductor layer 40, having a smaller bandgap than the second nitride semiconductor layer 50, can provide a channel for charge carriers, serving as a channel layer in the semiconductor device 100.

[0050] Due to severe alloy disorder scattering at the interface between the second nitride semiconductor layer 50 and the first nitride semiconductor layer 40, the electron mobility of the actual semiconductor device 100 is relatively low. To improve electron mobility, in some embodiments, an intercalation layer can be provided between the second nitride semiconductor layer 50 and the first nitride semiconductor layer 40. The intercalation layer may comprise a group III-V material layer. The intercalation layer may comprise, but is not limited to, group III nitrides, such as aluminum nitride (AlN). The thickness of the intercalation layer may range from, but is not limited to, about 0.5 μm to about 10 μm.

[0051] The cap layer 60 may be disposed on the second nitride semiconductor layer 50. The cap layer 60 may be in direct contact with the second nitride semiconductor layer 50. The cap layer 60 may be doped with impurities. The cap layer 60 may contain a p-type dopant. Upon careful consideration, the cap layer 60 may contain a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V group layers. The p-type dopant may contain magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).

[0052] The cap layer 60 can be configured to control the concentration of 2DEG in the first nitride semiconductor layer 40. The cap layer 60 can be used to deplete the 2DEG directly beneath it.

[0053] Gate 80 may be disposed on cap layer 60. Gate 80 may comprise gate material. Gate metal may comprise titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and their compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)), or other suitable materials.

[0054] An etch insertion layer 70 may be disposed between the gate 80 and the cap layer 60. The cap layer 60 may be separated from the gate 80 by the etch insertion layer 70. The etch insertion layer 70 may be disposed on the cap layer 60. The gate 80 may be disposed on the etch insertion layer 70. The gate 80 may contact the etch insertion layer 70. The gate 80 may cover the etch insertion layer 70. In some embodiments, the etch insertion layer 70 comprises a nitride. In some embodiments, the etch insertion layer 70 comprises aluminum nitride.

[0055] The gate 80 may include a first sidewall 84, which has a first chamfer 845 adjacent to the etched insertion layer 70. In some embodiments, the width of the first chamfer 845 gradually decreases as it approaches the cap layer 60. In some embodiments, the first sidewall 84 includes a vertically arranged first sub-sidewall 842 and an inclined second sub-sidewall 844, with the first chamfer 845 disposed on the second sub-sidewall 844.

[0056] The etched insertion layer 70 may include a second sidewall 74, which has a second chamfer 745. In some embodiments, the width of the second chamfer 745 gradually increases as it approaches the cap layer 60.

[0057] In the aforementioned semiconductor device 100, by providing an etched insertion layer 70 between the cap layer 60 and the gate 80, and by providing a first chamfer 845 on the first sidewall 84 of the gate 80 adjacent to the etched insertion layer 70, and a second chamfer 745 on the second sidewall 74 of the etched insertion layer 70, the electric field curvature peak at the edge of the Schottky junction sidewall is reduced, the electric field distribution is optimized, and the gate reliability is improved.

[0058] Figures 3 to 9 Various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated.

[0059] refer to Figure 3 A substrate 20 is provided. A nucleation layer (not shown), a buffer layer 30, a first nitride semiconductor layer 40, a second nitride semiconductor layer 50, and a cap material layer 61 can be formed on the substrate 20. The nucleation layer, buffer layer 30, first nitride semiconductor layer 40, second nitride semiconductor layer 50, and cap material layer 61 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD), epitaxial growth, or other suitable deposition steps.

[0060] Substrate 20 may comprise, but is not limited to, silicon (Si), doped silicon (SiC), silicon carbide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. Substrate 20 may comprise, but is not limited to, sapphire, silicon on insulator (SOI), or other suitable materials. In some embodiments, substrate 20 may also include doped regions (not shown), such as p-wells, n-wells, etc.

[0061] A nucleation layer may be formed on substrate 20. The nucleation layer may form an interface with substrate 20. The nucleation layer is configured to provide a top surface for growing a group III nitride material thereon. In other words, the nucleation layer forms a suitable template to transition from the lattice of the substrate to a template more suitable for the growth of the group III nitride material. The nucleation layer provides a transition to accommodate mismatch / difference (e.g., epitaxial formation) between substrate 20 and the group III nitride layer to be formed on its top surface. Mismatch / difference may involve different lattice constants or coefficients of thermal expansion. Mismatch / difference may result in dislocations in the formed layer, thereby reducing the yield rate. Exemplary materials for the nucleation layer may include, but are not limited to, aluminum nitride (AlN) or any alloy thereof. Aluminum nitride may be, for example, but not limited to, doped n-type, p-type, or intrinsic. The material of the nucleation layer may be selected to eliminate mismatch / difference. For example, to accommodate mismatch / difference caused by a first element in the layer to be formed on the nucleation layer, the nucleation layer is formed to include the first element.

[0062] A buffer layer 30 may be formed on the nucleation layer. The buffer layer 30 may form an interface with the nucleation layer. The buffer layer 30 has a bottom surface in contact with the nucleation layer. This interface is formed by the bottom surface of the buffer layer 30 and the top surface of the nucleation layer. The buffer layer 30 has a top surface opposite the bottom surface. The buffer layer 30 is configured to reduce lattice and thermal mismatches between the underlying layer and the layer to be formed on the buffer layer 30 (e.g., epitaxially formed thereon), thereby solidifying defects caused by mismatch / difference.

[0063] Buffer layer 30 may include III-V compounds. III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrides, or combinations thereof. Therefore, exemplary materials of buffer layer 30 may further include (e.g., but not limited to) AlN, AlGaN, InAlGaN, GaAs, AlAs, ZnO, or combinations thereof. In some embodiments, buffer layer 30 may include two group III elements, and the nucleation layer may have only one group III element. For example, the nucleation layer may include a compound containing aluminum but not gallium (e.g., AlN), and buffer layer 30 may include a III-V compound containing aluminum and gallium (e.g., AlGaN).

[0064] A first nitride semiconductor layer 40 (also referred to as channel layer 40) may be formed on the buffer layer 30. The first nitride semiconductor layer 40 may comprise a III-V group material layer. The first nitride semiconductor layer 40 may comprise, but is not limited to, group III nitrides, such as the compound In. a Al b Ga (1-a-b) N, where a+b≦1. The group III nitrides further comprise, but are not limited to, for example, the compound Al. a Ga (1-a)N, where a≦1. The first nitride semiconductor layer 40 may comprise a gallium nitride (GaN) layer. The bandgap of GaN is approximately 3.4 eV. The thickness of the first nitride semiconductor layer 40 may range from, but is not limited to, approximately 0.5 μm to approximately 10 μm.

[0065] A second nitride semiconductor layer 50 (also referred to as a barrier layer 50) may be formed on the first nitride semiconductor layer 40. The second nitride semiconductor layer 50 may comprise a III-V group material layer. The second nitride semiconductor layer 50 may comprise, but is not limited to, group III nitrides, such as the compound In. a Al b Ga (1-a-b) N, where a+b≦1. The group III nitrides may further include, but are not limited to, compounds such as Al. a Ga (1-a) N, where a≦1. The bandgap of the second nitride semiconductor layer 50 can be greater than the bandgap of the first nitride semiconductor layer 40. The second nitride semiconductor layer 50 may comprise an aluminum gallium nitride (AlGaN) layer. The bandgap of AlGaN is approximately 4.0 eV. The thickness of the second nitride semiconductor layer 50 can range from, but is not limited to, approximately 10 nm to approximately 100 nm.

[0066] The cap material layer 61 can be formed on the second nitride semiconductor layer 50. The cap material layer 61 can be in direct contact with the second nitride semiconductor layer 50. The cap material layer 61 can be doped with impurities. The cap material layer 61 can contain p-type dopants. The cap material layer 61 can contain a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V group layers. The p-type dopants can contain magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).

[0067] refer to Figure 4 An etched insert material layer 71 can be formed on the cap material layer 61. In some embodiments, the etched insert material layer 71 can be formed by atomic layer deposition (ALD). In some embodiments, the etched insert material layer 71 comprises a nitride. In some embodiments, the etched insert material layer 71 comprises aluminum nitride.

[0068] Reference Figure 5A gate material layer 81 can be formed on the etched insertion material layer 71. The gate material layer 81 may contain a gate material. The gate material may contain titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and their compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)), or other suitable materials.

[0069] Reference Figure 6 A mask pattern PR can be formed on the gate material layer 81. In some embodiments, the mask pattern PR can be a photoresist pattern.

[0070] Reference Figure 7 The gate material layer 81 and the insertion material layer 71 are etched using a mask pattern PR to remove the areas of the gate material layer 81 and the insertion material layer 71 that are not covered by the mask pattern PR, thereby forming the gate material layer 82 and the insertion material layer 72.

[0071] Reference Figure 8 Remove the mask pattern PR and form a protective layer 87 on both sides and above the gate material layer 82 and the etched insert material layer 72.

[0072] Reference Figure 9 as well as Figure 2 The protective layer 87 is used for etching. The etching can include dry etching and wet etching. Dry etching can remove a portion of the cap material layer 61 to form a cap layer 60. Wet etching can remove the protective layer 87, a portion of the gate material layer 82, and a portion of the etched insertion material layer 72 to form a gate 80 with a first chamfer 845 and an etched insertion layer 70 with a second chamfer 745.

[0073] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” are used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 80 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0074] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm when located along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0075] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; A channel layer, the channel layer is disposed on the substrate, and the channel layer comprises a nitride semiconductor material; A barrier layer, the barrier layer being disposed on a side of the channel layer away from the substrate, the barrier layer comprising a nitride semiconductor material, and having an energy gap greater than an energy gap of the channel layer; A gate structure, the gate structure comprising a cap layer, a gate and an etched insertion layer, the cap layer comprising a nitride semiconductor material and arranged on a side of the barrier layer away from the channel layer, the gate being arranged on a side of the cap layer away from the barrier layer, and the etched insertion layer being arranged between the gate and the cap layer; The gate includes a first side wall, and a first chamfer is arranged at the first side wall adjacent to the etched insertion layer; the etched insertion layer includes a second side wall, and a second chamfer is arranged at the second side wall.

2. The semiconductor device according to claim 1, wherein: As the first chamfer gradually approaches the cap layer, the width of the first chamfer gradually decreases.

3. The semiconductor device according to claim 1, wherein: The first side wall includes a vertically arranged first sub-side wall and an inclinedly arranged second sub-side wall, and the first chamfer is arranged on the second sub-side wall.

4. The semiconductor device according to claim 1, wherein: As the second chamfer gradually approaches the cap layer, the width of the second chamfer gradually increases.

5. The semiconductor device according to claim 1, wherein: The etching insertion layer includes nitride.

6. The semiconductor device according to claim 1, wherein: The etching insertion layer includes aluminum nitride.

7. The semiconductor device according to claim 1, wherein: The cap layer includes p-type gallium nitride.

8. The semiconductor device according to claim 1, wherein: The channel layer includes a compound In a Al b Ga (1-a-b) N, where a+b≦1; Alternatively, the channel layer includes compound Al a Ga (1-a) N, where a≦1.

9. The semiconductor device according to claim 1, wherein: The barrier layer includes a compound In a Al b Ga (1-a-b) N, where a+b≦1; Alternatively, the barrier layer comprises a compound Al a Ga (1-a) N, where a≦1.

10. The semiconductor device according to claim 1, wherein: The material of the channel layer includes gallium nitride, and the material of the barrier layer includes aluminum gallium nitride.

11. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a buffer layer disposed between the substrate and the channel layer, the buffer layer including a III-V compound.

12. The semiconductor device according to claim 11, characterized in that The material of the buffer layer is one of AlN, AlGaN, InAlGaN, GaAs, AlAs, and ZnO.

13. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a nucleation layer disposed between the substrate and the channel layer.

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