Semiconductor device

Abstract

The utility model provides a semiconductor device which comprises a substrate, a grid electrode located on the substrate, a drain end and a substrate leading-out end which are located on the same side edge of the grid electrode, a shallow trench isolation structure formed in the substrate between the drain end and the substrate leading-out end, and an auxiliary grid electrode formed on the shallow trench isolation structure. The auxiliary grid electrode is electrically connected with the drain terminal. According to the utility model, the auxiliary grid electrode is arranged and is electrically connected with the drain terminal, when voltage is applied to the drain terminal of the device, the same voltage is applied to the auxiliary grid electrode electrically connected with the drain terminal at the same time, and the auxiliary grid electrode can adjust the electric field distribution of the junction region of the drain drift region and the substrate drift region according to the magnitude of the applied voltage; concentration of an electric field at the corner of the shallow trench isolation structure is reduced, so that the source-drain breakdown voltage of the device is effectively improved. Meanwhile, only the auxiliary grid electrode is added and electrically connected with the drain terminal, other process conditions do not need to be changed, and other performance indexes of the device cannot be affected.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor manufacturing, in particular to a semiconductor device. Background Art

[0002] Taking NMOS as an example, HV devices have single-finger structures and multi-finger structures. WAT (Wafer Acceptance Test) test data shows that the source-drain breakdown voltage (BVds) of the multi-finger structure of the same device is about 5V higher than that of the single-finger structure.

[0003] The industry usually adjusts the source-drain breakdown voltage of the device by changing the IMP (ion implantation) conditions. Taking NMOS as an example, the source-drain breakdown voltage of NMOS is generally adjusted by increasing the concentration of the N drift region and reducing the width of the depletion region. However, when changing the IMP conditions, other performance indicators of the device (such as reliability, electrical parameters, etc.) will also be affected. Utility Model Content

[0004] The utility model aims to provide a semiconductor device, which can improve the source-drain breakdown voltage of the device without affecting other performance indicators of the device.

[0005] In order to solve the above technical problems, the utility model provides a semiconductor device, comprising: a substrate, a gate located on the substrate, a drain terminal and a substrate lead terminal located on the same side of the gate, a shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead terminal, an auxiliary gate is formed on the shallow trench isolation structure, and the auxiliary gate is electrically connected to the drain terminal.

[0006] Optionally, the auxiliary gate is electrically connected to the drain terminal through a metal wire.

[0007] Optionally, the width of the auxiliary gate is less than half of the width of the shallow trench isolation structure.

[0008] Optionally, a distance between the auxiliary gate and the drain terminal is equal to a distance between the auxiliary gate and the substrate lead terminal.

[0009] Optionally, a drain drift region surrounding the drain end and a substrate drift region surrounding the substrate lead-out end are formed in the substrate, and the auxiliary gate covers a portion of the drain drift region and a portion of the substrate drift region.

[0010] Optionally, a source terminal is further provided on the other side of the gate, and a source drift region surrounding the source terminal is formed in the substrate.

[0011] Optionally, the substrate lead-out end is in a ring shape, surrounding the gate, the auxiliary gate, the drain drift region and the source drift region.

[0012] Optionally, a gate dielectric layer is formed between the gate and the substrate.

[0013] Optionally, an auxiliary gate dielectric layer is formed between the auxiliary gate and the substrate.

[0014] Optionally, the auxiliary gate has the same thickness as the gate, and the auxiliary gate dielectric layer has the same thickness as the gate dielectric layer.

[0015] Compared with the prior art, in the semiconductor device provided by the utility model, an auxiliary gate is arranged on the shallow trench isolation structure between the drain terminal and the substrate lead-out terminal, and the auxiliary gate is electrically connected to the drain terminal. When a voltage is applied to the drain terminal of the device, the auxiliary gate electrically connected thereto is simultaneously applied with the same voltage. The existence of the auxiliary gate can adjust the electric field distribution in the junction area of ​​the drain drift region and the substrate drift region according to the magnitude of the applied voltage, reduce the concentration of the electric field at the corner of the shallow trench isolation structure, and thus effectively improve the source-drain breakdown voltage of the device. At the same time, the utility model only adds an auxiliary gate and electrically connects it to the drain terminal, and does not need to change other process conditions, and will not affect other performance indicators of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0017] Figure 1 is a cross-sectional view of a semiconductor device in the prior art.

[0018] Figure 2 It is a cross-sectional view of a semiconductor device provided by an embodiment of the utility model.

[0019] Figure 3 It is a top view of a semiconductor device provided by an embodiment of the utility model.

[0020] Figure 4 It is a schematic diagram of the drain terminal electric field strength when different drain terminal voltages are applied to the device structure provided by the utility model.

[0021] Description of reference numerals:

[0022] 10-substrate; 11-gate; 12-shallow trench isolation structure; 13-auxiliary gate; 14-drain terminal; 15-substrate lead terminal; 16-drain drift region; 17-substrate drift region; 18-source terminal; 19-source drift region; 20, 21, 22, 23-shallow trench isolation structure; 24-gate dielectric layer; 25-auxiliary gate dielectric layer; 26-well region. DETAILED DESCRIPTION

[0023] Figure 1 is a cross-sectional view of a semiconductor device in the prior art. Figure 1 As shown, the semiconductor device includes a substrate 10, a gate 11 located on the substrate 10, a source terminal 18, a drain terminal 14 and a substrate lead-out terminal 15 located on both sides of the gate 11. A source drift region 19, a drain drift region 16 and a substrate drift region 17 are also formed in the substrate 10. A plurality of shallow trench isolation structures are also formed in the substrate 10.

[0024] TCAD (Technology Computer Aided Design, a semiconductor process simulation and device simulation tool) simulation found that the reduction in the source-drain breakdown voltage of the single-finger structure is caused by the uneven electric field distribution in the junction area between the drain drift region 16 and the substrate drift region 17 and the electric field concentration at the corner of the shallow trench isolation structure 12.

[0025] Inspired by the multi-finger structure of high-voltage devices, the inventors designed a new device structure to improve the electromagnetic distribution in the junction area between the drain drift region and the substrate drift region, thereby improving the source-drain breakdown voltage of the device.

[0026] After further research, the utility model provides a semiconductor device, including: a substrate, a gate located on the substrate, a drain terminal and a substrate lead terminal located on the same side of the gate, a shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead terminal, an auxiliary gate is formed on the shallow trench isolation structure, and the auxiliary gate is electrically connected to the drain terminal.

[0027] The semiconductor device provided by the utility model has an auxiliary gate arranged on the shallow trench isolation structure between the drain terminal and the substrate lead-out terminal, the auxiliary gate being electrically connected to the drain terminal, and when a voltage is applied to the drain terminal of the device, the auxiliary gate electrically connected thereto is simultaneously applied with the same voltage, and the existence of the auxiliary gate can adjust the electric field distribution in the junction area of ​​the drain drift region and the substrate drift region according to the magnitude of the applied voltage, and reduce the concentration of the electric field at the corner of the shallow trench isolation structure, thereby effectively improving the source-drain breakdown voltage of the device. At the same time, the utility model only adds an auxiliary gate and electrically connects it to the drain terminal, and does not need to change other process conditions, and will not affect other performance indicators of the device.

[0028] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0029] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0030] Figure 2 is a cross-sectional view of a semiconductor device provided by an embodiment of the utility model, Figure 3 is a top view of a semiconductor device provided by an embodiment of the utility model, Figure 2 yes Figure 3 Cross-section in the horizontal direction. Please refer to Figure 2 and Figure 3 As shown, the semiconductor device provided by the embodiment of the utility model includes: a substrate 10, a gate 11 located on the substrate 10, a drain terminal 14 (D) and a substrate lead terminal 15 (B) located on the same side of the gate 11, a shallow trench isolation structure 12 is formed in the substrate 10 between the drain terminal 14 and the substrate lead terminal 15, an auxiliary gate 13 is formed on the shallow trench isolation structure 12, and the auxiliary gate 13 is electrically connected to the drain terminal 14.

[0031] In the utility model, an auxiliary gate 13 is arranged on the shallow trench isolation structure 12 between the drain terminal 14 and the substrate lead-out terminal 15, and the auxiliary gate 13 is electrically connected to the drain terminal 14. When a voltage is applied to the device drain terminal 14, the same voltage is applied to the auxiliary gate 13 electrically connected thereto at the same time. The existence of the auxiliary gate 13 can adjust the electric field distribution in the junction area of ​​the drain drift region and the substrate drift region according to the magnitude of the applied voltage. As the voltage applied to the drain terminal 14 increases, the electric field strength at the corner of the shallow trench isolation structure 12 decreases, and the maximum electric field is transferred from the corner of the shallow trench isolation structure 12 to the bottom of the auxiliary gate 13, thereby effectively improving the source-drain breakdown voltage of the device.

[0032] In an embodiment of the present invention, the auxiliary gate 13 is electrically connected to the drain terminal 14 through a metal wire.

[0033] In one embodiment of the present invention, the width of the auxiliary gate 13 is less than half of the width of the shallow trench isolation structure 12, wherein the width of the auxiliary gate 13 and the width of the shallow trench isolation structure 12 are Figure 2 and Figure 3 The width of the shallow trench isolation structure 12 is the width of the cross section in the horizontal direction. Figure 2 Of course, the width of the auxiliary gate 13 is not limited thereto.

[0034] In one embodiment of the present invention, the distance between the auxiliary gate 13 and the drain terminal 14 is equal to the distance between the auxiliary gate 13 and the substrate lead terminal 15, that is, the auxiliary gate 13 is located between the drain terminal 14 and the substrate lead terminal 15. Figure 2 As shown, the drain terminal 14 and the substrate lead-out terminal 15 refer to an area in the substrate 10 connected to the outside world, the size of the auxiliary gate 13 from the drain terminal 14 can be the size of the distance between the center of the auxiliary gate 13 and the center of the drain terminal 14, and the size of the auxiliary gate 13 from the substrate lead-out terminal 15 can be the size of the distance between the center of the auxiliary gate 13 and the center of the substrate lead-out terminal 15.

[0035] In one embodiment of the utility model, a drain drift region 16 surrounding the drain terminal 14 and a substrate drift region 17 surrounding the substrate lead-out terminal 15 are formed in the substrate 10, and the auxiliary gate 13 covers a portion of the drain drift region 16 and a portion of the substrate drift region 17, that is, the auxiliary gate 13 spans the drain drift region 16 and the substrate drift region 17.

[0036] A source terminal 18 (S) and a source drift region 19 surrounding the source terminal 18 are further disposed on the other side of the gate 11 .

[0037] Please refer to Figure 2As shown, a plurality of shallow trench isolation structures are formed in the substrate 10 for isolating different regions, for example, the shallow trench isolation structure 20 isolates the source terminal 18 from the substrate lead terminal 15, the shallow trench isolation structure 21 isolates the channel region (not shown) from the source terminal 18, the shallow trench isolation structure 22 isolates the channel region from the drain terminal 14, and the shallow trench isolation structure 23 isolates the substrate lead terminal 15 from the remaining regions not shown in the figure.

[0038] Please refer to Figure 2 As shown, a well region 26 is also formed in the substrate 10 , and the source drift region 19 , the drain drift region 16 and the substrate drift region 17 are all located above the well region 26 .

[0039] In one embodiment of the utility model, a gate dielectric layer 24 is formed between the gate 11 and the substrate 10, and an auxiliary gate dielectric layer 25 is also formed between the auxiliary gate 13 and the substrate 10. The gate dielectric layer 24 and the auxiliary gate dielectric layer 25 can be formed by the same process step, and the gate 11 and the auxiliary gate 13 can also be formed by the same process step, so there is no need to add an additional mask. The material of the auxiliary gate 13 is the same as that of the gate 11, and the thickness of the auxiliary gate 13 is also the same as that of the gate 11. Similarly, the material of the auxiliary gate dielectric layer 25 is the same as that of the gate dielectric layer 24, and the thickness of the auxiliary gate dielectric layer 25 is also the same as that of the gate dielectric layer 24. Exemplarily, the material of the auxiliary gate 13 is polysilicon, the material of the auxiliary gate dielectric layer 25 is silicon oxide, and the thickness of the auxiliary gate 13 and the auxiliary gate dielectric layer 25 can be determined according to the thickness of the gate 11 and the gate dielectric layer 24.

[0040] Of course, the gate dielectric layer 24 and the auxiliary gate dielectric layer 25 may also be formed in different process steps, and the gate 11 and the auxiliary gate 13 may also be formed in different process steps, which is not limited in the present invention. Therefore, the material and thickness of the auxiliary gate 13 may be different from those of the gate 11, and the material and thickness of the auxiliary gate dielectric layer 25 may also be different from those of the gate dielectric layer 24.

[0041] In another embodiment of the present invention, the auxiliary gate 13 may be formed only on the shallow trench isolation structure 12 without forming the auxiliary gate dielectric layer 25 .

[0042] The utility model only adds an auxiliary gate 13 and electrically connects it to the drain terminal 14, and does not need to change other process conditions or other process steps, and does not affect other performance indicators of the device, and does not introduce additional costs. In addition, when the device in the utility model is working, the auxiliary gate 13 needs to be connected to the drain terminal 14, and no additional post-process flow is added.

[0043] Taking NMOS as an example, the well region 26 is a P well, that is, HVPW, the source drift region 19 and the drain drift region 16 are N drift regions, the substrate drift region 17 is a P drift region, the source terminal 18 and the drain terminal 14 are n + , the substrate lead end 15 is p + .

[0044] Taking a high-voltage device with a size of 55.55um / 2.78um as an example, voltage is applied to the existing device structure (i.e., no auxiliary gate is added) and the device structure provided by the present invention (adding an auxiliary gate) for TCAD simulation. In the case where no auxiliary gate is added, the electric field at the corner of the shallow trench isolation structure 12 between the drain terminal 14 and the substrate lead-out terminal 15 near the drain terminal 14 reaches a peak value, which is easy to cause breakdown. In the case of adding an auxiliary gate in the present invention, an auxiliary gate 13 is formed on the shallow trench isolation structure 12 between the drain terminal 14 and the substrate lead-out terminal 15, and the auxiliary gate 13 is electrically connected to the drain terminal 14, and the peak electric field at the corner of the shallow trench isolation structure 12 near the drain terminal 14 is significantly improved, that is, the electric field strength at the corner is reduced, thereby effectively improving the source-drain breakdown voltage of the device.

[0045] Different drain terminal voltages are applied to the device structure provided by the utility model, wherein the drain terminal voltages applied are 0V, 10V, 30V, 50V, 70V and 80V respectively. It can be seen from the simulation diagram that the electric field at the corner of the shallow trench isolation structure is improved after adding an auxiliary gate and applying a voltage at the drain terminal, and the peak field strength is effectively reduced, so the source-drain breakdown voltage is significantly improved. And as the voltage applied at the drain terminal increases, the more obvious the improvement of the electric field at the corner of the shallow trench isolation structure, the lower the peak electric field. However, the voltage applied at the drain terminal cannot be increased all the time. After exceeding a certain value (for example, 70V or 80V), a larger electric field distribution appears below the shallow trench isolation structure, which will cause the source-drain breakdown voltage to drop sharply.

[0046] Figure 4 It is a schematic diagram of the drain terminal electric field strength when different drain terminal voltages are applied to the device structure provided by the utility model. Figure 4 In the figure, the horizontal axis represents the device position and the vertical axis represents the electric field strength. Figure 4As shown, the region where the horizontal coordinate is between about 3 and 3.6 is the corner of the shallow trench isolation structure 12 close to the drain terminal D, and the region where the horizontal coordinate is between about 3.8 and 4.6 is the center of the shallow trench isolation structure 12. Figure 4 It can be seen that as the voltage applied to the drain terminal increases, the electric field strength at the corner of the shallow trench isolation structure 12 close to the drain terminal D decreases continuously, while the electric field strength at the center of the shallow trench isolation structure 12 increases continuously.

[0047] Table 1

[0048] Voltage applied to drain terminal (V) Source-drain breakdown voltage(V) 0 35.6 5 36.7 10 37.7 15 38.6 20 39.4 25 40.1 30 40.9 35 41.5 40 42.05 45 42.6 50 43.05 55 43.5 60 43.8 65 44.1 70 43.4 75 33.1 80 22.6

[0049] Table 1 shows the source-drain breakdown voltage of the device when different drain voltages are applied. It can be seen from Table 1 that when the applied drain voltage exceeds 65V, the source-drain breakdown voltage will decrease.

[0050] Since the working voltage of the device is below 32V, a voltage higher than 65V will not be applied to the drain terminal 14. Therefore, the auxiliary gate is electrically connected to the drain terminal of the device. When a voltage is applied to the drain terminal 14 of the device, the auxiliary gate 13 electrically connected thereto is simultaneously applied with the same voltage. The existence of the auxiliary gate 13 can adjust the electric field distribution of the junction area of ​​the drain drift region 16 and the substrate drift region 17 with the magnitude of the applied voltage. As the voltage applied to the drain terminal 14 increases, the electric field strength at the corner of the shallow trench isolation structure 12 decreases, and the maximum electric field is transferred from the corner of the shallow trench isolation structure 12 to the bottom of the auxiliary gate 13, thereby effectively improving the source-drain breakdown voltage of the device. And for HV devices with a size of 55.55um / 2.78um, when the voltage applied to the drain terminal is in the range of 0 to 65V, the source-drain breakdown voltage increases with the increase of the drain terminal voltage.

[0051] In summary, in the semiconductor device provided by the utility model, an auxiliary gate is arranged on the shallow trench isolation structure between the drain terminal and the substrate lead-out terminal, and the auxiliary gate is electrically connected to the drain terminal. When a voltage is applied to the drain terminal of the device, the auxiliary gate electrically connected thereto is simultaneously applied with the same voltage. The existence of the auxiliary gate can adjust the electric field distribution in the junction area of ​​the drain drift region and the substrate drift region according to the magnitude of the applied voltage, reduce the concentration of the electric field at the corner of the shallow trench isolation structure, and thus effectively improve the source-drain breakdown voltage of the device. At the same time, the utility model only adds an auxiliary gate and electrically connects it to the drain terminal, and does not need to change other process conditions, and will not affect other performance indicators of the device.

[0052] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A semiconductor device, characterized in that: include: A substrate, a gate located on the substrate, a drain terminal and a substrate lead terminal located on the same side of the gate, a shallow trench isolation structure is formed in the substrate between the drain terminal and the substrate lead terminal, an auxiliary gate is formed on the shallow trench isolation structure, and the auxiliary gate is electrically connected to the drain terminal.

2. The semiconductor device according to claim 1, wherein: The auxiliary gate is electrically connected to the drain terminal through a metal wire.

3. The semiconductor device according to claim 1, wherein: The width of the auxiliary gate is less than half of the width of the shallow trench isolation structure.

4. The semiconductor device according to claim 1, wherein: The distance between the auxiliary gate and the drain terminal is equal to the distance between the auxiliary gate and the substrate lead terminal.

5. The semiconductor device according to claim 4, characterized in that A drain drift region surrounding the drain end and a substrate drift region surrounding the substrate lead-out end are formed in the substrate, and the auxiliary gate covers a portion of the drain drift region and a portion of the substrate drift region.

6. The semiconductor device according to claim 5, characterized in that A source terminal is also arranged on the other side of the gate, and a source drift region surrounding the source terminal is formed in the substrate.

7. The semiconductor device according to claim 6, characterized in that The substrate lead-out terminal is in a ring shape, surrounding the gate, the auxiliary gate, the drain drift region and the source drift region.

8. The semiconductor device according to claim 1, wherein: A gate dielectric layer is formed between the gate and the substrate.

9. The semiconductor device according to claim 8, characterized in that An auxiliary gate dielectric layer is formed between the auxiliary gate and the substrate.

10. The semiconductor device according to claim 9, characterized in that The auxiliary gate has the same thickness as the gate, and the auxiliary gate dielectric layer has the same thickness as the gate dielectric layer.

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