Integrated circuit

Abstract

The utility model provides an integrated circuit. An integrated circuit includes a first type of active region structure and a second type of active region structure extending in a first direction and a first terminal conductor and a second terminal conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in the first metal layer and a first power line and a second power line in the second metal layer. The integrated circuit further includes a first via connection directly connected between the first power stub and the first terminal conductor; a second via connector directly connected between the second power stub and the second terminal conductor; a third through-hole connector directly connected between the first power stub and the first power line; and a fourth through-hole connector directly connected between the second power stub and the second power line.

Description

Technical Field

[0001] The utility model relates to an integrated circuit. Background Art

[0002] The recent trend of integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. The miniaturization process has also resulted in more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize and verify standard cell layout designs for integrated circuits while ensuring that standard cell layout design and manufacturing specifications are met. Utility Model Content

[0003] The utility model provides an integrated circuit. The integrated circuit comprises: a first type active region structure and a second type active region structure, extending in a first direction; a first isolation region and a second isolation region, located in the first type active region structure; a third isolation region and a fourth isolation region, located in the second type active region structure, wherein the third isolation region in the second type active region structure is vertically aligned with the first isolation region in the first type active region structure along the second direction and delineates a first vertical cell boundary of a circuit cell, and wherein the fourth isolation region in the second type active region structure is vertically aligned with the second isolation region in the first type active region structure along the second direction and delineates a second vertical cell boundary of the circuit cell; a first power stub and a second power stub, located in a first metal layer overlying a first interlayer dielectric, the first interlayer dielectric covering the first type active region structure and the second type active region structure; a first through-hole connector, directly connected between the first power stub and the first source terminal of the first transistor located in the circuit cell; a second through-hole connector, directly connected between the second power stub and the second source terminal of the second transistor located in the circuit cell; and a first power line and a second power line, located in a second metal layer overlying a second interlayer dielectric, the second interlayer dielectric covering the first power stub and the second power stub in the first metal layer, wherein the first power line is connected to the first power stub, and the second power line is connected to the second power stub, and wherein the first power line is configured to receive a first power supply voltage, and the second power line is configured to receive a second power supply voltage different from the first power supply voltage.

[0004] The utility model discloses an integrated circuit. The integrated circuit comprises: a first type active region structure and a second type active region structure extending in a first direction; a plurality of dummy gate conductors extending in a second direction perpendicular to the first direction, wherein each of the first type active region structure and the second type active region structure has a plurality of isolation regions at a plurality of intersections where the plurality of dummy gate conductors intersect with the first type active region structure or the second type active region structure, and wherein a first dummy gate conductor among the plurality of dummy gate conductors is aligned with a first vertical cell boundary of a circuit cell, and a second dummy gate conductor among the plurality of dummy gate conductors is aligned with a second vertical cell boundary of the circuit cell; a plurality of gate conductors extending in the second direction, each of the plurality of gate conductors intersecting with one or both of the first type active region structure and the second type active region structure, wherein each of the plurality of gate conductors is located between two adjacent dummy gate conductors among the plurality of dummy gate conductors at an equal pitch distance; a first power stub and a second power stub; A power stub extending in the second direction in a first metal layer overlying a first interlayer dielectric, the first interlayer dielectric covering the first type active region structure and the second type active region structure; a first through-hole connector directly connected between the first power stub and a first source terminal of a first transistor located in the circuit cell; a second through-hole connector directly connected between the second power stub and a second source terminal of a second transistor located in the circuit cell; and a first power line and a second power line extending in the first direction in a second metal layer overlying a second interlayer dielectric, the second interlayer dielectric covering the first power stub and the second power stub in the first metal layer, wherein the first power line is connected to the first power stub and the second power line is connected to the second power stub, and wherein the first power line is configured to receive a first power supply voltage and the second power line is configured to receive a second power supply voltage different from the first power supply voltage.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1C is a layout diagram of a circuit cell according to some embodiments.

[0007] Figure 1D to Figure 1G is a cross-sectional view of a circuit cell according to some embodiments.

[0008] FIG. 2A to FIG. 2C is a layout diagram of a circuit cell according to some embodiments.

[0009] Figure 2D to Figure 2G is a cross-sectional view of a circuit cell according to some embodiments.

[0010] FIG. 3A to FIG. 3C is a layout diagram of a circuit cell according to some embodiments.

[0011] FIG. 4A to FIG. 4C is a layout diagram of a circuit cell according to some embodiments.

[0012] FIG. 5A to FIG. 5C is a layout diagram of a circuit cell according to some embodiments.

[0013] FIG. 5D to FIG. 5H is a cross-sectional view of a circuit cell according to some embodiments.

[0014] FIG. 6A to FIG. 6C is a layout diagram of a circuit cell according to some embodiments.

[0015] FIG. 6D to FIG. 6H is a cross-sectional view of a circuit cell according to some embodiments.

[0016] FIG. 7A to FIG. 7C is a layout diagram of a circuit cell according to some embodiments.

[0017] FIG. 8A to FIG. 8C is a layout diagram of a circuit cell according to some embodiments.

[0018] 9A to 9C is a layout diagram of a circuit cell according to some embodiments.

[0019] Fig.10 is a flow chart of a method of fabricating an integrated circuit having a power stub according to some embodiments.

[0020] Fig.11 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0021] Fig.12 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated with the IC manufacturing system according to some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components, values, operations, materials, arrangements or similar elements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements or similar elements. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed by itself.

[0023] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0024] In some embodiments, an integrated circuit has a circuit cell. The circuit cell includes a power stub located in a first metal layer (e.g., metal layer M0) overlying an interlayer dielectric, the interlayer dielectric covering a gate conductor of a transistor. The integrated circuit also includes a power line located in a second metal layer (e.g., metal layer M1). A power supply voltage is applied to the circuit cell via the power line and the power stub. In some embodiments, when the power stub extends in a direction perpendicular to the gate conductor, the length of the power stub is less than the width of the circuit cell. In some embodiments, when the power stub extends in a direction parallel to the gate conductor, the length of the power stub is less than the height of the circuit cell. In some embodiments, a circuit cell implemented using a power stub in the first metal layer has a smaller cell height than some alternative embodiments in which a power rail located in the first metal layer extends across a plurality of circuit cells located in a row.

[0025] Figure 1A and Figure 2A2 is a layout diagram of circuit cells 100A and 200A each implemented using an inverter according to some embodiments. Figure 1B and Figure 2B 2 is a layout diagram of circuit cells 100B and 200B each implemented using a NAND gate according to some embodiments. Figure 1C and Figure 2C 2 are layout diagrams of circuit cells 100C and 200C each implemented using an AND-OR-Inverter gate (ie, an AOI gate) according to some embodiments.

[0026] exist Figure 1A and Figure 2A In the embodiment, each of the circuit cells 100A and 200A includes a P-type metal-oxide semiconductor (PMOS) active region structure 50p and an N-type metal-oxide semiconductor (NMOS) active region structure 50n extending in the X direction. Each of the circuit cells 100A and 200A includes a gate conductor gT extending in the Y direction. Each of the circuit cells 100A and 200A also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cells. The gate conductor gT is separated from each of the dummy gate conductors g101 and g109 by a pitch distance of one contact pitch (“Contacted Poly Pitch, CPP”). Here, the Y direction is perpendicular to the X direction. The gate conductor gT intersects the PMOS active region structure 50p at the channel region of the PMOS transistor Tp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor Tn.

[0027] In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more fin structures, and thus, each of the PMOS transistor Tp and the NMOS transistor Tn is a fin field effect transistor (FinFET). In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more nanosheets, and thus, each of the PMOS transistor Tp and the NMOS transistor Tn is a nanosheet transistor. In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more nanowires, and thus, each of the PMOS transistor Tp and the NMOS transistor Tn is a nanowire transistor.

[0028] Each of the circuit cells 100A and 200A also includes terminal conductors (e.g., sTp, sTn, and dTpn) intersecting the PMOS active region structure 50p or the NMOS active region structure 50n at the respective source regions or drain regions of the transistor. The source terminal sTp of the PMOS transistor Tp is configured to receive the upper limit power supply voltage VDD, and the source terminal sTn of the NMOS transistor Tn is configured to receive the lower limit power supply voltage VSS. The terminal conductor dTpn connects the drain terminal dTp of the PMOS transistor Tp and the drain terminal dTn of the NMOS transistor Tn. The gate terminal of the PMOS transistor Tp and the gate terminal of the NMOS transistor Tn are conductively connected together via the gate conductor gT. The gate conductor gT is configured to carry the input signal "I" of the inverter, and the terminal conductor dTpn is configured to carry the output signal "Z" of the inverter.

[0029] exist Figure 1A In , circuit cell 100A includes horizontal conducting lines 122A, 124A, 126A, and 128A extending in the X direction in a first metal layer (e.g., metal layer M0). Circuit cell 100A also includes vertical conducting lines 174A1, 174A2, 176A1, and 176A2 extending in the Y direction in a second metal layer (e.g., metal layer M1). Each of the vertical conducting lines is aligned with a vertical routing track. Two adjacent vertical routing tracks are separated by a pitch distance of one CPP. In Figure 1D to Figure 1G 2 shows a cross-sectional view of the circuit cell 100A.

[0030] Figure 1D According to some embodiments, the circuit cell 100A is along Figure 1A A cross-sectional view of the cutting plane AA' shown in FIG. Figure 1E According to some embodiments, the circuit cell 100A is along Figure 1A A cross-sectional view of the cutting plane BB' shown in FIG. Figure 1F According to some embodiments, the circuit cell 100A is along Figure 1A Cross-sectional view of the cutting plane CC' shown in . Figure 1G According to some embodiments, the circuit cell 100A is along Figure 1A Cross-sectional view of the cutting plane DD' shown in .

[0031] like Figure 1D to Figure 1GAs shown in FIG, horizontal conductive lines 122A, 124A, 126A, and 128A are fabricated in a first metal layer (e.g., metal layer M0) overlying a first interlayer dielectric ILD0, wherein the first interlayer dielectric ILD0 covers a PMOS active region structure 50p, an NMOS active region structure 50n, a gate conductor gT, and various terminal conductors. Vertical conductive lines 174A1, 174A2, 176A1, and 176A2 are fabricated in a second metal layer (e.g., metal layer M1) overlying a second interlayer dielectric ILD1, wherein the second interlayer dielectric ILD1 covers the horizontal conductive lines in the first metal layer.

[0032] In addition, the gate conductor gT is connected to the vertical conductive line 176A2 via the horizontal conductive line 126A, and the vertical conductive line 176A2 is configured as the input pin of the inverter in the circuit cell 100A. The terminal conductor dTp is connected to the vertical conductive line 176A1 via the horizontal conductive line 122A, and the vertical conductive line 176A1 is configured as the output pin of the inverter in the circuit cell 100A.

[0033] exist Figure 1A and Figure 1D to Figure 1G , the source terminal sTp of the PMOS transistor Tp is directly connected to the horizontal conductive line 124A through the through-hole connection VD, and the horizontal conductive line 124A is directly connected to the vertical conductive line 174A1 through the through-hole connection V0. The vertical conductive line 174A1 is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is directly connected to the horizontal conductive line 128A through the through-hole connection VD, and the horizontal conductive line 128A is directly connected to the vertical conductive line 174A2 through the through-hole connection V0. The vertical conductive line 174A2 is configured to receive the lower limit power supply voltage VSS.

[0034] exist Figure 1A and Figure 1D to Figure 1G , each of the horizontal conductive lines 124A and 128A acts as a power stub, and each of the vertical conductive lines 174A1 and 174A2 acts as a power line. In some embodiments, when the power stub extends in the X direction, the length of the power stub is less than the width of the circuit cell, and the power stub is defined between the dummy gate conductor g101 and the dummy gate conductor g109. Here, the width of the circuit cell 100A is the pitch distance between the dummy gate conductor g101 and the dummy gate conductor g109. In some embodiments, when the power line extends in the Y direction, the length of the power stub is less than the height of the circuit cell. In some alternative embodiments, when the power line extends in the Y direction, the length of the power stub is greater than or equal to the height of the circuit cell.

[0035] exist Figure 2AIn FIG. 1 , circuit cell 200A includes horizontal conductive lines 222A1, 222A2, 226A, and 228A extending in the X direction in a first metal layer (e.g., metal layer M0). Circuit cell 200A also includes vertical conductive lines 274A1, 274A2, 275A, and 276A extending in the Y direction in a second metal layer (e.g., metal layer M1). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times the CPP. In FIG. Figure 2D to Figure 2G A cross-sectional view of the circuit cell 200A is shown in FIG.

[0036] Figure 2D According to some embodiments, the circuit cell 200A is along Figure 2A A cross-sectional view of the cutting plane AA' shown in FIG. Figure 2E According to some embodiments, the circuit cell 200A is along Figure 2A A cross-sectional view of the cutting plane BB' shown in FIG. Figure 2F According to some embodiments, the circuit cell 200A is along Figure 2A Cross-sectional view of the cutting plane CC' shown in . Figure 2G According to some embodiments, the circuit cell 200A is along Figure 2A Cross-sectional view of the cutting plane DD' shown in .

[0037] like Figure 2D to Figure 2G As shown in FIG. 1 , horizontal conductive lines 222A, 226A, and 228A are fabricated in a first metal layer (e.g., metal layer M0) overlying a first interlayer dielectric ILD0, wherein the first interlayer dielectric ILD0 covers a PMOS active region structure 50p, an NMOS active region structure 50n, a gate conductor gT, and various terminal conductors. Vertical conductive lines 274A1, 274A2, 275A, and 276A are fabricated in a second metal layer (e.g., metal layer M1) overlying a second interlayer dielectric ILD1, wherein the second interlayer dielectric ILD1 covers the horizontal conductive lines in the first metal layer.

[0038] exist Figure 2A and Figure 2D to Figure 2G In , the source terminal sTp of the PMOS transistor Tp is directly connected to the horizontal conductive line 222A1 through the through-hole connection VD, and the horizontal conductive line 222A1 is directly connected to the vertical conductive line 274A1 through the through-hole connection V0. The vertical conductive line 274A1 is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is directly connected to the horizontal conductive line 228A through the through-hole connection VD, and the horizontal conductive line 228A is directly connected to the vertical conductive line 274A2 through the through-hole connection V0. The vertical conductive line 274A2 is configured to receive the lower limit power supply voltage VSS. In Figure 2A and Figure 2D to Figure 2G In FIG. 5 , each of the horizontal conductive lines 222A1 and 228A acts as a power stub, and each of the vertical conductive lines 274A1 and 274A2 acts as a power line.

[0039] In addition, Figure 2A and Figure 2D to Figure 2G In the embodiment, the gate conductor gT is connected to the vertical conductive line 275A via the horizontal conductive line 226A, and the vertical conductive line 275A is configured as the input pin of the inverter in the circuit cell 200A. The terminal conductor dTp is connected to the vertical conductive line 276A via the horizontal conductive line 222A2, and the vertical conductive line 276A is configured as the output pin of the inverter in the circuit cell 200A.

[0040] exist Figure 1A and Figure 2A In the embodiment, each of the circuit cell 100A and the circuit cell 200A is located between a first vertical cell boundary aligned with the dummy gate conductor g101 and a second vertical cell boundary aligned with the dummy gate conductor g109. Figure 1D to Figure 1G and Figure 2D to Figure 2G In the example, the boundary isolation region i101p under the dummy gate conductor g101 and the boundary isolation region i101n under the dummy gate conductor g109 in the NMOS active region structure 50n delineate a first vertical cell boundary extending in the Y direction. The boundary isolation region i109p under the dummy gate conductor g101 and the boundary isolation region i109n under the dummy gate conductor g109 delineate a second vertical cell boundary extending in the Y direction. The boundary isolation region i101p and the boundary isolation region i109p in the PMOS active region structure 50p isolate the source region and the drain region of the PMOS transistor Tp from the source region and the drain region of other PMOS transistors in the adjacent circuit cells. The boundary isolation region i101n and the boundary isolation region i109n in the NMOS active region structure 50n isolate the source region and the drain region of the NMOS transistor Tn from the source region and the drain region of other NMOS transistors in the adjacent circuit cells.

[0041] In some other embodiments, the circuit cell is implemented as an inverted gate. Figure 1B and Figure 2B, each of the circuit cells 100B and 200B includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. Each of the circuit cells 100B and 200B includes gate conductors gA and gB extending in the Y direction. Each of the circuit cells 100B and 200B also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cells. The gate conductor gA intersects the PMOS active region structure 50p at the channel region of the PMOS transistor TAp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor TAn. The gate conductor gB intersects the PMOS active region structure 50p at the channel region of the PMOS transistor TBp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor TBn.

[0042] Each of the circuit cells 100B and 200B also includes terminal conductors (e.g., dAp, ssABp, dBp, sAn, and dBn) intersecting the PMOS active region structure 50p or the NMOS active region structure 50n at the respective source regions or drain regions of the transistors. The joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is configured to receive the upper limit power supply voltage VDD, and the source terminal sAn of the NMOS transistor TAn is configured to receive the lower limit power supply voltage VSS. The drain terminal dAp of the PMOS transistor TAp and the drain terminal dBp of the PMOS transistor TBp are conductively connected together via a horizontal conductive line. The drain terminal dBp of the PMOS transistor TBp and the drain terminal dBn of the NMOS transistor TBn are conductively connected together via a terminal conductor dBpn. The source terminal of the NMOS transistor TBn and the drain terminal of the NMOS transistor TAn are joined together in the NMOS active region structure 50n.

[0043] exist Figure 1BIn , the circuit cell 100B includes horizontal conductive lines 122B, 124B and 128B extending in the X direction in a first metal layer (e.g., metal layer M0). The circuit cell 100B also includes vertical conductive lines 175B1, 175B2 and 178B extending in the Y direction in a second metal layer (e.g., metal layer M1). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of one times CPP. The joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is connected to the vertical conductive line 175B1 via the horizontal conductive line 124B, and the vertical conductive line 175B1 is configured to receive an upper limit power supply voltage VDD. The source terminal sAn of the NMOS transistor TAn is connected to the vertical conductive line 175B2 via the horizontal conductive line 128B, and the vertical conductive line 175B2 is configured to receive a lower limit power supply voltage VSS. In Figure 1B In FIG. 1 , each of the horizontal conductive lines 124B and 128B acts as a power stub, and each of the vertical conductive lines 175B1 and 175B2 acts as a power line.

[0044] In addition, Figure 1B , the drain terminal dAp of the PMOS transistor TAp and the drain terminal dBp of the PMOS transistor TBp are conductively connected together via a horizontal conductive line 122B, and the horizontal conductive line 122B is connected to a vertical conductive line 178B, which is configured as an output pin of the anti-AND gate in the circuit cell 100B.

[0045] exist Figure 2B In , circuit cell 200B includes horizontal conductive lines 222B, 224B and 228B extending in the X direction in a first metal layer (e.g., metal layer M0). Circuit cell 200B also includes vertical conductive lines 272B, 274B, 275B, 276B and 278B extending in the Y direction in a second metal layer (e.g., metal layer M1). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times CPP. The joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is connected to the vertical conductive line 275B via the horizontal conductive line 224B, and the vertical conductive line 275B is configured to receive an upper limit power supply voltage VDD. The source terminal sAn of the NMOS transistor TAn is connected to the vertical conductive line 272B via the horizontal conductive line 228B, and the vertical conductive line 272B is configured to receive a lower limit power supply voltage VSS. In Figure 1B In FIG. 1 , each of the horizontal conductive lines 224B and 228B acts as a power stub, and each of the vertical conductive lines 275B and 272B acts as a power line.

[0046] In addition, Figure 1B , the drain terminal dAp of the PMOS transistor TAp and the drain terminal dBp of the PMOS transistor TBp are conductively connected together via a horizontal conductive line 222B, and the horizontal conductive line 222B is connected to a vertical conductive line 278B, which is configured as an output pin of the anti-AND gate in the circuit cell 200B. The gate conductors gA and gB are respectively connected to vertical conductive lines 274B and 276B, which are configured as input pins of the anti-AND gate in the circuit cell 200B.

[0047] In some other embodiments, the circuit cell is implemented as an AOI gate. Figure 1C , the circuit cell 100C includes PMOS active region structures 52p and 54p extending in the X direction and includes NMOS active region structures 52n and 54n extending in the X direction. The circuit cell 100C includes gate conductors gA1, gA2, gB1, and gB2 extending in the Y direction. The circuit cell 100C also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cell. The gate conductors gA1 and gA2 intersect the PMOS active region structure 54p at the channel regions of the PMOS transistors TA1p and TA2p, respectively. The gate conductors gA1 and gA2 also intersect the NMOS active region structure 54n at the channel regions of the NMOS transistors TA1n and TA2n, respectively. The gate conductors gB1 and gB2 intersect the PMOS active region structure 52p at the channel regions of the PMOS transistors TB1p and TB2p, respectively. The gate conductors gB1 and gB2 also intersect the NMOS active region structure 52n at the channel regions of the NMOS transistors TB1n and TB2n, respectively.

[0048] exist Figure 1CIn the embodiment, the circuit cell 100C includes terminal conductors (e.g., sB2p, sB1p, dA2p, dsBAp, and dA1pn) intersecting one of the PMOS active region structures 52p or 54p at each source region or drain region of the PMOS transistor. The circuit cell 100C includes terminal conductors (e.g., sB2n, dB1n, sA2n, and dA1pn) intersecting one of the NMOS active region structures 52n or 54n at each source region or drain region of the NMOS transistor. The circuit cell 100C includes horizontal conductive lines 121C1, 122C, 124C, 126C, and 129C extending in the X direction in a first metal layer (e.g., metal layer M0). The circuit cell 100C includes vertical conductive lines 174C1, 175C1, 175C2, and 176C2 extending in the Y direction in the second metal layer (eg, metal layer M1). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of one CPP.

[0049] exist Figure 1C , each of the source terminal sB1p of the PMOS transistor TB1p and the source terminal sB2p of the PMOS transistor TB2p is configured to receive the upper limit power supply voltage VDD. Each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is configured to receive the lower limit power supply voltage VSS. The gate conductors gA1, gA2, gB1 and gB2 are correspondingly configured to receive the input signal "A1", the input signal "A2", the input signal "B1" and the input signal "B2" of the AOI gate in the circuit cell 100C. The vertical conductive line 175C1 is configured to carry the output signal "ZN" of the AOI gate.

[0050] exist Figure 1C, the source terminal sB1p of the PMOS transistor TB1p and the source terminal sB2p of the PMOS transistor TB2p are connected to the vertical conductive line 176C2 via the horizontal conductive line 124C, and the vertical conductive line 176C2 is configured to receive the upper limit power supply voltage VDD. The drain terminals of the PMOS transistors TB1p and TB2p are connected to the source terminals of the PMOS transistors TA1p and TA2p by the joint terminal dsBAp. The drain terminal dA2p of the PMOS transistor TA2p is connected to the drain terminal of the PMOS transistor TA1p via the horizontal conductive line 126C, and the drain terminal of the PMOS transistor TA1p is connected to the drain terminal of the NMOS transistor TA1n via the joint terminal dA1pn. The source terminal of the NMOS transistor TB1n and the drain terminal of the NMOS transistor TB2n are joined together in the NMOS active region structure 54n. The source terminal sA2n of the NMOS transistor TA2n is connected to the vertical conductive line 175C2 via the horizontal conductive line 129C, and the vertical conductive line 175C2 is configured to receive the lower limit power supply voltage VSS.

[0051] exist Figure 1C , the horizontal conductive line 126C is also connected to the horizontal conductive line 122C via the vertical conductive line 175C1, and the horizontal conductive line 122C is connected to the drain terminal dB1n of the NMOS transistor TB1n. The source terminal of the NMOS transistor TB1n and the drain terminal of the NMOS transistor TB2n are joined together in the NMOS active region structure 52n. The source terminal sB2n of the NMOS transistor TB2n is connected to the vertical conductive line 174C1 via the horizontal conductive line 121C1, and the vertical conductive line 174C1 is configured to receive the lower limit power supply voltage VSS.

[0052] exist Figure 1C In the embodiment, each of the horizontal conductive lines 124C, 129C and 121C1 acts as a power stub, and each of the vertical conductive lines 176C2, 175C2 and 174C1 acts as a power line. In some embodiments, when the power stub extends in the X direction, the length of the power stub is less than the width of the circuit cell, and the power stub is defined between the dummy gate conductor g101 and the dummy gate conductor g109.

[0053] In some other embodiments, the circuit cell is implemented as an AOI gate. Figure 2C, the circuit cell 200C includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. The circuit cell 200C includes gate conductors gA1, gA2, gB1, and gB2 extending in the Y direction. The circuit cell 200C also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cell. The gate conductors gA1, gA2, gB1, and gB2 intersect the PMOS active region structure 50p at the channel regions of the PMOS transistors TA1p, TA2p, TB1p, and TB2p, respectively. The gate conductors gA1, gA2, gB1, and gB2 intersect the NMOS active region structure 50n at the channel regions of the NMOS transistors TA1n, TA2n, TB1n, and TB2n, respectively.

[0054] exist Figure 2C , the circuit cell 200C includes terminal conductors (e.g., dB2p, ssB12p, dsB1A1p, ddA12p, sA2p) intersecting the PMOS active region structure 50p at each source region or drain region of the PMOS transistor. The circuit cell 200C includes terminal conductors (e.g., sB2n, ddB1A1n, and sA2n) intersecting the NMOS active region structure 50n at each source region or drain region of the NMOS transistor. The circuit cell 200C includes horizontal conductive lines 222C, 224C1, 224C2, 228C1, 228C2, and 228C3 extending in the X direction in a first metal layer (e.g., metal layer M0). The circuit cell 200C includes vertical conductive lines 271C to 276C and 278C to 279C extending in the Y direction in a second metal layer (e.g., metal layer M1). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times the CPP.

[0055] exist Figure 2C , a joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is configured to receive an upper power supply voltage VDD. Each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is configured to receive a lower power supply voltage VSS. The gate conductors gA1, gA2, gB1, and gB2 are correspondingly configured to receive an input signal "A1", an input signal "A2", an input signal "B1", and an input signal "B2" of the AOI gate in the circuit cell 200C. The vertical conductive line 275C1 is configured to carry an output signal "ZN" of the AOI gate.

[0056] exist Figure 2C, a joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is connected to the vertical conductive line 273C via the horizontal conductive line 224C1, and the vertical conductive line 273C is configured to receive the upper limit power supply voltage VDD. The drain terminal dB2p of the PMOS transistor TB2p and the drain terminal of the PMOS transistor TB1p (at the joint terminal dsB1A1p) are conductively connected together via the horizontal conductive line 222C. The source terminal sA2p of the PMOS transistor TA2p and the source terminal of the PMOS transistor TA1p (at the joint terminal dsB1A1p) are also conductively connected together via the horizontal conductive line 222C. The joint drain terminal ddA12p of the PMOS transistor TA1p and the PMOS transistor TA2p is conductively connected to the vertical conductive line 275C via the horizontal conductive line 224C2. The vertical conductive line 275C is further connected to the joint drain terminal ddA1B1n of the NMOS transistor TB1n and the NMOS transistor TA1n via the horizontal conductive line 228C2. The source terminal of the NMOS transistor TB1n and the drain terminal of the NMOS transistor TB2n are joined together in the NMOS active region structure 50n. The source terminal of the NMOS transistor TA1n and the drain terminal of the NMOS transistor TA2n are joined together in the NMOS active region structure 50n.

[0057] The source terminal sB2n of the NMOS transistor TB2n is connected to the vertical conductive line 271C via the horizontal conductive line 228C1, and the vertical conductive line 271C is configured to receive the lower limit power supply voltage VSS. The source terminal sA2n of the NMOS transistor TA2n is connected to the vertical conductive line 279C via the horizontal conductive line 228C3, and the vertical conductive line 279C is configured to receive the lower limit power supply voltage VSS.

[0058] exist Figure 2C , each of the horizontal conductive lines 224C1, 228C1, and 228C3 acts as a power stub, and each of the vertical conductive lines 273C, 271C, and 279C acts as a power line. In some embodiments, when the power stub extends in the X direction, the length of the power stub is less than the width of the circuit cell, and the power stub is defined between the dummy gate conductor g101 and the dummy gate conductor g109.

[0059] In by Figures 1A to 1C The layout diagram shown and FIG. 2A to FIG. 2C The layout diagram shown specifies an integrated circuit in which each of the horizontal conductive lines is aligned with one of the horizontal wiring traces, and there are four horizontal wiring traces per unit cell height. For example, Figure 1A to Figure 1B The circuit cells and FIG. 2A to FIG. 2BEach of the circuit cells in is a single height cell, and there are four horizontal routing traces that can be used to position horizontal conductive lines. Figure 1C The circuit cells and Figure 2C Each of the circuit cells in is a double-height cell, and there are eight horizontal routing traces that can be used to position horizontal conductive lines.

[0060] In some alternative designs of integrated circuits, the number of horizontal wiring traces per unit cell height is reduced. FIG. 3A to FIG. 3C The layout diagram shown and FIG. 4A to FIG. 4C The layout diagram shown specifies an integrated circuit in which each of the horizontal conductive lines is still aligned with one of the horizontal wiring traces, but the number of horizontal wiring traces per unit cell height is reduced to three. FIG. 3A to FIG. 3B The circuit cells and FIG. 4A to FIG. 4B Each of the circuit cells in is a single height cell, and there are three horizontal routing traces that can be used to position horizontal conductive lines. Figure 3C The circuit cells and Figure 4C Each of the circuit cells in is a double-height cell, and there are six horizontal routing traces that can be used to position horizontal conductive lines.

[0061] Figure 3A and Figure 4A is a layout diagram of circuit cells 300A and 400A each implemented using an inverter according to some embodiments. Figure 3B and Figure 4B is a layout diagram of circuit cells 300B and 400B each implemented using an inverted AND gate according to some embodiments. Figure 3C and Figure 4C is a layout diagram of circuit cells 300C and 400C each implemented using an AND-OR-inverter gate (ie, AOI gate) according to some embodiments.

[0062] Figure 3A The circuit cell 300A shown is self-contained by changing the geometric positions of the horizontal conductive lines in the first metal layer and the geometric positions of the vertical conductive lines in the second metal layer. Figure 1A The circuit cell 100A shown is modified. Although the geometric position is changed, each of the power supply voltages (such as VDD and VSS) is still applied to the source terminal of the transistor via the horizontal conductive line in the first metal layer and the vertical conductive line in the second metal layer. Figure 3AIn the circuit cell 300A shown, the source terminal sTp of the PMOS transistor Tp is conductively connected to the horizontal conductive line 124A, the horizontal conductive line 124A is conductively connected to the vertical conductive line 174A1, and the vertical conductive line 174A1 is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is conductively connected to the horizontal conductive line 128A, the horizontal conductive line 128A is conductively connected to the vertical conductive line 174A2, and the vertical conductive line 174A2 is configured to receive the lower limit power supply voltage VSS.

[0063] Figure 4A The circuit cell 400A shown is self-contained by changing the geometric positions of the horizontal conductive lines in the first metal layer and the geometric positions of the vertical conductive lines in the second metal layer. Figure 2A The circuit cell 200A shown is modified. Although the geometric position is changed, each of the power supply voltages (such as VDD and VSS) is still applied to the source terminal of the transistor via the horizontal conductive line in the first metal layer and the vertical conductive line in the second metal layer. Figure 4A In the circuit cell 400A shown, the source terminal sTp of the PMOS transistor Tp is conductively connected to the horizontal conductive line 222A1, the horizontal conductive line 222A1 is conductively connected to the vertical conductive line 274A1, and the vertical conductive line 274A1 is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is conductively connected to the horizontal conductive line 228A, the horizontal conductive line 228A is conductively connected to the vertical conductive line 274A2, and the vertical conductive line 274A2 is configured to receive the lower limit power supply voltage VSS.

[0064] Figure 3B The circuit cell 300B shown is self-contained by changing the geometric positions of the horizontal conductive lines in the first metal layer and the geometric positions of the vertical conductive lines in the second metal layer. Figure 1B The circuit cell 100B shown is modified. Although the geometric position is changed, each of the power supply voltages (such as VDD and VSS) is still applied to the source terminal of the transistor via the horizontal conductive line in the first metal layer and the vertical conductive line in the second metal layer. Figure 3B In the circuit cell 300B shown, the joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is connected to the vertical conductive line 175B1 via the horizontal conductive line 124B, and the vertical conductive line 175B1 is configured to receive the upper limit power supply voltage VDD. The source terminal sAn of the NMOS transistor TAn is connected to the vertical conductive line 175B2 via the horizontal conductive line 128B, and the vertical conductive line 175B2 is configured to receive the lower limit power supply voltage VSS.

[0065] Figure 4B The circuit cell 400B shown is self-contained by changing the geometric positions of the horizontal conductive lines in the first metal layer and the geometric positions of the vertical conductive lines in the second metal layer. Figure 2B The circuit cell 200B shown is modified. Although the geometric position is changed, each of the power supply voltages (such as VDD and VSS) is still applied to the source terminal of the transistor via the horizontal conductive line in the first metal layer and the vertical conductive line in the second metal layer. Figure 4B In the circuit cell 400B shown, the joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is connected to the vertical conductive line 275B via the horizontal conductive line 224B, and the vertical conductive line 275B is configured to receive the upper limit power supply voltage VDD. The source terminal sAn of the NMOS transistor TAn is connected to the vertical conductive line 272B via the horizontal conductive line 228B, and the vertical conductive line 272B is configured to receive the lower limit power supply voltage VSS.

[0066] Figure 3C The circuit cell 300C shown is self-contained by changing the geometric positions of the horizontal conductive lines in the first metal layer and the geometric positions of the vertical conductive lines in the second metal layer. Figure 1C The circuit cell 100C shown is modified. Although the geometric position is changed, each of the power supply voltages (such as VDD and VSS) is still applied to the source terminal of the transistor via the horizontal conductive line in the first metal layer and the vertical conductive line in the second metal layer. Figure 3C In the circuit cell 300C shown, the source terminal sB1p of the PMOS transistor TB1p and the source terminal sB2p of the PMOS transistor TB2p are connected to the vertical conductive line 176C2 via the horizontal conductive line 124C, and the vertical conductive line 176C2 is configured to receive the upper limit power supply voltage VDD. The source terminal sA2n of the NMOS transistor TA2n is connected to the vertical conductive line 175C2 via the horizontal conductive line 129C, and the vertical conductive line 175C2 is configured to receive the lower limit power supply voltage VSS. The source terminal sB2n of the NMOS transistor TB2n is connected to the vertical conductive line 174C1 via the horizontal conductive line 121C1, and the vertical conductive line 174C1 is configured to receive the lower limit power supply voltage VSS.

[0067] Figure 4C The circuit cell 400C shown is self-contained by changing the geometric positions of the horizontal conductive lines in the first metal layer and the geometric positions of the vertical conductive lines in the second metal layer. Figure 2C The circuit cell 200C shown is modified. Although the geometric position is changed, each of the power supply voltages (such as VDD and VSS) is still applied to the source terminal of the transistor via the horizontal conductive line in the first metal layer and the vertical conductive line in the second metal layer. Figure 4CIn the circuit cell 400C shown, the joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is connected to the vertical conductive line 273C via the horizontal conductive line 224C1, and the vertical conductive line 273C is configured to receive the upper power supply voltage VDD. The source terminal sB2n of the NMOS transistor TB2n is connected to the vertical conductive line 271C via the horizontal conductive line 228C1, and the vertical conductive line 271C is configured to receive the lower power supply voltage VSS. The source terminal sA2n of the NMOS transistor TA2n is connected to the vertical conductive line 279C via the horizontal conductive line 228C3, and the vertical conductive line 279C is configured to receive the lower power supply voltage VSS.

[0068] Figure 5A and Fig. 6A is a layout diagram of circuit cells 500A and 600A each implemented using an inverter according to some embodiments. Figure 5B and Figure 6B is a layout diagram of circuit cells 500B and 600B each implemented using an inverted AND gate according to some embodiments. Figure 5C and Figure 6C is a layout diagram of circuit cells 500C and 600C each implemented using an AND-OR-inverter gate (ie, AOI gate) according to some embodiments.

[0069] exist Figure 5A and Fig. 6A , each of the circuit cells 500A and 600A includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. Each of the circuit cells 500A and 600A includes a gate conductor gT extending in the Y direction. Each of the circuit cells 500A and 600A also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cells. The gate conductor gT intersects the PMOS active region structure 50p at the channel region of the PMOS transistor Tp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor Tn.

[0070] Each of the circuit cells 500A and 600A also includes terminal conductors (e.g., sTp, sTn, and dTpn) intersecting the PMOS active region structure 50p or the NMOS active region structure 50n at the respective source regions or drain regions of the transistors. The source terminal sTp of the PMOS transistor Tp is configured to receive the upper limit power supply voltage VDD, and the source terminal sTn of the NMOS transistor Tn is configured to receive the lower limit power supply voltage VSS. The terminal conductor dTpn connects the drain terminal dTp of the PMOS transistor Tp and the drain terminal dTn of the NMOS transistor Tn. The gate terminal of the PMOS transistor Tp and the gate terminal of the NMOS transistor Tn are conductively connected together via the gate conductor gT. The gate conductor gT is configured to carry the input signal "I" of the inverter, and the terminal conductor dTpn is configured to carry the output signal "Z" of the inverter.

[0071] exist Figure 5A In FIG. 5 , circuit cell 500A includes vertical conductive lines 524A1, 524A2, 526A1, and 526A2 extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of one CPP. Circuit cell 500A also includes power rails 571 and 579 and horizontal conductive lines 572A and 578A extending in the X direction in a second metal layer (e.g., metal layer M1). In FIG. FIG. 5D to FIG. 5H A cross-sectional view of the circuit cell 500A is shown in FIG.

[0072] Figure 5D According to some embodiments, the circuit cell 500A is along Figure 5A Cross-sectional view of the cutting plane PP' shown in . Figure 5E According to some embodiments, the circuit cell 500A is along Figure 5A A cross-sectional view of the cutting plane AA' shown in FIG. Fig. 5F According to some embodiments, the circuit cell 500A is along Figure 5A Cross-sectional view of the cutting plane CC' shown in . Figure 5G According to some embodiments, the circuit cell 500A is along Figure 5A Cross-sectional view of the cutting plane DD' shown in . Figure 5H According to some embodiments, the circuit cell 500A is along Figure 5A A cross-sectional view of the cutting plane QQ' shown in FIG.

[0073] like FIG. 5D to FIG. 5HAs shown in FIG. 1 , vertical conductive lines 524A1, 524A2, 526A1, and 526A2 are fabricated in a first metal layer (e.g., metal layer M0) overlying a first interlayer dielectric ILD0, wherein the first interlayer dielectric ILD0 covers a PMOS active region structure 50p, an NMOS active region structure 50n, a gate conductor gT, and various terminal conductors. Horizontal conductive lines 572A and 578A are fabricated in a second metal layer (e.g., metal layer M1) overlying a second interlayer dielectric ILD1, wherein the second interlayer dielectric ILD1 covers the vertical conductive lines in the first metal layer.

[0074] In addition, the gate conductor gT is connected to the vertical conductive line 526A2 via the conductor 5MPg2, and the vertical conductive line 526A2 is connected to the horizontal conductive line 578A, and the horizontal conductive line 578A is configured as the input pin of the inverter in the circuit cell 500A. The terminal conductor dTp is connected to the horizontal conductive line 572A via the vertical conductive line 526A1, and the horizontal conductive line 572A is configured as the output pin of the inverter in the circuit cell 500A.

[0075] exist Figure 5A and FIG. 5D to FIG. 5H , the source terminal sTp of the PMOS transistor Tp is directly connected to the vertical conductive line 524A1 through a via connection VD, and the vertical conductive line 524A1 is directly connected to the power rail 571 through a via connection V0. The power rail 571 is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is directly connected to the vertical conductive line 524A2 through a via connection VD, and the vertical conductive line 524A2 is directly connected to the power rail 579 through a via connection V0. The power rail 579 is configured to receive the lower limit power supply voltage VSS. Each of the power rails 571 and the power rails 579 extends along the X direction and crosses a plurality of circuit cells (not shown in the figure) located in the same cell column as the circuit cell 500A.

[0076] exist Figure 5A and FIG. 5D to FIG. 5H In FIG. 5 , each of the vertical conductive lines 524A1 and 524A2 acts as a power stub, and each of the power rails 571 and 579 acts as a power line of the circuit cell 500A. Figure 5A In some embodiments shown in , a power stub extending in the Y direction extends across a power rail (e.g., 571 or 579) at a horizontal cell boundary of a circuit cell. Figure 5A In some embodiments shown in , the power stub extends in the Y direction and crosses the power rail (e.g., 571 or 579) at the horizontal cell boundary of the circuit cell. In some embodiments, when the power stub extends in the Y direction, the length of the power stub is less than the height of the circuit cell. Figure 5A In the embodiment shown in , each of the power rails 571 and 579 is aligned with one of the horizontal cell boundaries of the circuit cell. In some alternative embodiments, at least one power line is aligned with a horizontal routing trace located between two horizontal cell boundaries of the circuit cell.

[0077] exist Fig. 6A In FIG. 6 , circuit cell 600A includes vertical conductive lines 624A1, 624A2, 626A1, and 625A extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times the CPP. Circuit cell 600A also includes power rails 671 and 679 and horizontal conductive lines 672A and 676A extending in the X direction in a second metal layer (e.g., metal layer M1). In FIG. FIG. 6D to FIG. 6H A cross-sectional view of the circuit cell 600A is shown in FIG.

[0078] Fig.6D According to some embodiments, the circuit cell 600A is along Fig. 6A Cross-sectional view of the cutting plane PP' shown in . Fig. 6E According to some embodiments, the circuit cell 600A is along Fig. 6A A cross-sectional view of the cutting plane AA' shown in FIG. Fig. 6F According to some embodiments, the circuit cell 600A is along Fig. 6A Cross-sectional view of the cutting plane CC' shown in . Figure 6G According to some embodiments, the circuit cell 600A is along Fig. 6A Cross-sectional view of the cutting plane DD' shown in . Figure 6H According to some embodiments, the circuit cell 600A is along Fig. 6A A cross-sectional view of the cutting plane QQ' shown in FIG.

[0079] like FIG. 6D to FIG. 6H As shown in FIG. 1 , vertical conductive lines 624A1, 624A2, 626A1, and 625A are fabricated in a first metal layer (e.g., metal layer M0) overlying a first interlayer dielectric ILD0, wherein the first interlayer dielectric ILD0 covers a PMOS active region structure 50p, an NMOS active region structure 50n, a gate conductor gT, and various terminal conductors. Horizontal conductive lines 672A and 676A are fabricated in a second metal layer (e.g., metal layer M1) overlying a second interlayer dielectric ILD1, wherein the second interlayer dielectric ILD1 covers the vertical conductive lines in the first metal layer.

[0080] In addition, the gate conductor gT is connected to the vertical conductive line 625A via the through-hole connection VG, and the vertical conductive line 625A is connected to the horizontal conductive line 676A, and the horizontal conductive line 676A is configured as the input pin of the inverter in the circuit cell 600A. The terminal conductor dTp is connected to the horizontal conductive line 672A via the vertical conductive line 626A1, and the horizontal conductive line 672A is configured as the output pin of the inverter in the circuit cell 600A.

[0081] exist Fig. 6A and FIG. 6D to FIG. 6H , the source terminal sTp of the PMOS transistor Tp is directly connected to the vertical conductive line 624A1 through a via connection VD, and the vertical conductive line 624A1 is directly connected to the power rail 671 through a via connection V0. The power rail 671 is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is directly connected to the vertical conductive line 624A2 through a via connection VD, and the vertical conductive line 624A2 is directly connected to the power rail 679 through a via connection V0. The power rail 679 is configured to receive the lower limit power supply voltage VSS. Each of the power rails 671 and the power rails 679 extends along the X direction and crosses a plurality of circuit cells (not shown in the figure) located in the same cell column as the circuit cell 600A.

[0082] exist Fig. 6A and FIG. 6D to FIG. 6H In FIG. 6A , each of the vertical conductive lines 624A1 and 624A2 acts as a power stub, and each of the power rails 671 and 679 acts as a power line of the circuit cell 600A. Fig. 6A In some embodiments shown in , the power stub extends in the Y direction and crosses the power rail (e.g., 671 or 679) at a horizontal cell boundary of the circuit cell. Fig. 6A In some embodiments shown in , a power stub extending in the Y direction extends across a power rail (e.g., 671 or 679) at a horizontal cell boundary of a circuit cell. In some embodiments, when the power stub extends in the Y direction, the length of the power stub is less than the height of the circuit cell. Fig. 6A In the embodiment shown in , each of the power rails 671 and 679 is aligned with one of the horizontal cell boundaries of the circuit cell. In some alternative embodiments, at least one power line is aligned with a horizontal routing trace located between two horizontal cell boundaries of the circuit cell.

[0083] In some other embodiments, the circuit cell is implemented as an inverted gate. Figure 5B and Figure 6B, each of the circuit cells 500B and 600B includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. Each of the circuit cells 500B and 600B includes gate conductors gA and gB extending in the Y direction. Each of the circuit cells 500B and 600B also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cells. The gate conductor gA intersects the PMOS active region structure 50p at the channel region of the PMOS transistor TAp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor TAn. The gate conductor gB intersects the PMOS active region structure 50p at the channel region of the PMOS transistor TBp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor TBn.

[0084] Each of the circuit cells 500B and 600B also includes terminal conductors (e.g., dAp, ssABp, dBp, sAn, and dBn) intersecting the PMOS active region structure 50p or the NMOS active region structure 50n at the respective source regions or drain regions of the transistors. The joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is configured to receive the upper limit power supply voltage VDD, and the source terminal sAn of the NMOS transistor TAn is configured to receive the lower limit power supply voltage VSS. The drain terminal dAp of the PMOS transistor TAp and the drain terminal dBp of the PMOS transistor TBp are connected via horizontal conductive lines (e.g., Figure 5B 572B or Figure 6B The drain terminal dBp of the PMOS transistor TBp and the drain terminal dBn of the NMOS transistor TBn are conductively connected together via the terminal conductor dBpn. The source terminal of the NMOS transistor TBn and the drain terminal of the NMOS transistor TAn are joined together in the NMOS active region structure 50n.

[0085] exist Figure 5B, the circuit cell 500B includes vertical conductive lines 522B1, 522B2, 525B1 and 528B1 extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of one CPP. The circuit cell 500B also includes power rails 571 and 579 and a horizontal conductive line 572B extending in the X direction in a second metal layer (e.g., metal layer M1). The joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is connected to the vertical conductive line 525B1, and the vertical conductive line 525B1 is connected to the power rail 571. The power rail 571 is configured to receive an upper limit power supply voltage VDD. The source terminal sAn of the NMOS transistor TAn is connected to the vertical conductive line 522B2, and the vertical conductive line 522B2 is connected to the power rail 579. The power rail 579 is configured to receive the lower supply voltage VSS. Figure 5B In FIG. 5 , each of the vertical conductive lines 525B1 and 525B2 acts as a power stub, and each of the power rails 571 and 579 acts as a power line of the circuit cell 500B.

[0086] In addition, Figure 5B , the drain terminal dAp of the PMOS transistor TAp is connected to the vertical conductive line 522B1, and the drain terminal dBp of the PMOS transistor TBp is connected to the vertical conductive line 528B1, and the vertical conductive line 522B1 and the vertical conductive line 528B1 are conductively connected together via the horizontal conductive line 572B. The horizontal conductive line 572B is configured as the output pin of the NAND gate in the circuit cell 500B.

[0087] exist Figure 6B , the circuit cell 600B includes vertical conductive lines 622B1, 622B2, 625B1 and 628B1 extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times CPP. The circuit cell 600B also includes power rails 671 and 679 and a horizontal conductive line 672B extending in the X direction in a second metal layer (e.g., metal layer M1). The joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is connected to the vertical conductive line 625B1, and the vertical conductive line 625B1 is connected to the power rail 671. The power rail 671 is configured to receive an upper limit power supply voltage VDD. The source terminal sAn of the NMOS transistor TAn is connected to the vertical conductive line 622B2, and the vertical conductive line 622B2 is connected to the power rail 679. The power rail 679 is configured to receive the lower supply voltage VSS. Figure 6BIn FIG. 6 , each of the vertical conductive lines 625B1 and 625B2 acts as a power stub, and each of the power rails 671 and 679 acts as a power line of the circuit cell 600B.

[0088] In addition, Figure 6B , the drain terminal dAp of the PMOS transistor TAp is connected to the vertical conductive line 622B1, and the drain terminal dBp of the PMOS transistor TBp is connected to the vertical conductive line 628B1, and the vertical conductive line 622B1 and the vertical conductive line 628B1 are conductively connected together via the horizontal conductive line 672B. The horizontal conductive line 672B is configured as the output pin of the NAND gate in the circuit cell 600B.

[0089] In some other embodiments, the circuit cell is implemented as an AOI gate. Figure 5C and Figure 6C , each of the circuit cells 500C and 600C includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. Each of the circuit cells 500C and 600C includes gate conductors gA1, gA2, gB1, and gB2 extending in the Y direction. Each of the circuit cells 500C and 600C also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cells. The gate conductors gA1, gA2, gB1, and gB2 intersect the PMOS active region structure 50p at the channel regions of the PMOS transistors TA1p, TA2p, TB1p, and TB2p, respectively. The gate conductors gA1, gA2, gB1, and gB2 intersect the NMOS active region structure 50n at the channel regions of the NMOS transistors TA1n, TA2n, TB1n, and TB2n, respectively.

[0090] exist Figure 5C and Figure 6C In the embodiment, each of the circuit cells 500C and 600C includes a terminal conductor (e.g., dB2p, ssB12p, dsB1A1p, ddA12p, sA2p) intersecting the PMOS active region structure 50p at each source region or drain region of the PMOS transistor. Each of the circuit cells 500C and 600C includes a terminal conductor (e.g., sB2n, ddB1A1n, and sA2n) intersecting the NMOS active region structure 50n at each source region or drain region of the NMOS transistor.

[0091] exist Figure 5C and Figure 6C, a joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is configured to receive an upper power supply voltage VDD. Each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is configured to receive a lower power supply voltage VSS. The gate conductors gA1, gA2, gB1, and gB2 are correspondingly configured to receive an input signal "A1", an input signal "A2", an input signal "B1", and an input signal "B2" of the AOI gate. One of the terminal conductors (i.e., ddA12p) is configured to carry an output signal "ZN" of the AOI gate.

[0092] exist Figure 5C , circuit cell 500C includes vertical conductive lines 521C1, 521C3, 523C1, 525C1, 527C, 529C1, and 529C3 extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of one CPP. Circuit cell 500C includes horizontal conductive lines 572C and 578C extending in the X direction in a second metal layer (e.g., metal layer M1).

[0093] exist Figure 5C, a joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is connected to a vertical conductive line 523C1, and the vertical conductive line 523C1 is connected to a power rail 571 configured to receive an upper limit power supply voltage VDD. A drain terminal dB2p of the PMOS transistor TB2p and a drain terminal of the PMOS transistor TB1p (at a joint terminal dsB1A1p) are conductively connected to a horizontal conductive line 572C via one of corresponding vertical conductive lines 521C1 and 525C1. A source terminal sA2p of the PMOS transistor TA2p and a source terminal of the PMOS transistor TA1p (at a joint terminal dsB1A1p) are also conductively connected to the horizontal conductive line 572C via one of corresponding vertical conductive lines 525C1 and 529C1. The joint drain terminal ddA12p of the PMOS transistor TA1p and the PMOS transistor TA2p is conductively connected to the vertical conductive line 527C, and the vertical conductive line 527C is connected to the horizontal conductive line 578C. The horizontal conductive line 578C is further connected to the joint drain terminal ddA1B1n of the NMOS transistor TB1n and the NMOS transistor TA1n via the vertical conductive line 525C3. The source terminal of the NMOS transistor TB1n and the drain terminal of the NMOS transistor TB2n are joined together in the NMOS active region structure 50n. The source terminal of the NMOS transistor TA1n and the drain terminal of the NMOS transistor TA2n are joined together in the NMOS active region structure 50n.

[0094] Each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is connected to the power rail 579 via vertical conductive lines 521C3 and 529C3, respectively, and the power rail 579 is configured to receive the lower limit power supply voltage VSS. Figure 5C In FIG. 5 , each of the vertical conductive lines 523C1 , 521C3 , and 529C3 acts as a power stub, and each of the power rails 571 and 579 acts as a power line of the circuit cell 500C.

[0095] exist Figure 6C, circuit cell 600C includes vertical conductive lines 621C1, 621C3, 623C1, 625C1, 627C, 629C1, and 629C3 extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times CPP. Circuit cell 600C includes horizontal conductive lines 672C and 678C extending in the X direction in a second metal layer (e.g., metal layer M1). Circuit cell 600C also includes vertical conductive lines 622C, 624C, 626C, and 628C extending in the Y direction in the first metal layer and aligned with gate conductors gB1, gB2, gA1, and gA2, respectively.

[0096] exist Figure 6C , a joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is connected to a vertical conductive line 623C1, and the vertical conductive line 623C1 is connected to a power rail 671 configured to receive an upper limit power supply voltage VDD. A drain terminal dB2p of the PMOS transistor TB2p and a drain terminal of the PMOS transistor TB1p (at a joint terminal dsB1A1p) are conductively connected to a horizontal conductive line 672C via one of corresponding vertical conductive lines 621C1 and 625C1. A source terminal sA2p of the PMOS transistor TA2p and a source terminal of the PMOS transistor TA1p (at a joint terminal dsB1A1p) are also conductively connected to the horizontal conductive line 672C via one of corresponding vertical conductive lines 625C1 and 629C1. The joint drain terminal ddA12p of the PMOS transistor TA1p and the PMOS transistor TA2p is conductively connected to the vertical conductive line 627C, and the vertical conductive line 627C is connected to the horizontal conductive line 678C. The horizontal conductive line 678C is further connected to the joint drain terminal ddA1B1n of the NMOS transistor TB1n and the NMOS transistor TA1n via the vertical conductive line 625C3. The source terminal of the NMOS transistor TB1n and the drain terminal of the NMOS transistor TB2n are joined together in the NMOS active region structure 50n. The source terminal of the NMOS transistor TA1n and the drain terminal of the NMOS transistor TA2n are joined together in the NMOS active region structure 50n.

[0097] Each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is connected to the power rail 679 via vertical conductive lines 621C3 and 629C3, respectively, and the power rail 679 is configured to receive the lower limit power supply voltage VSS. Figure 6CIn FIG. 6 , each of the vertical conductive lines 623C1 , 621C3 , and 629C3 acts as a power stub, and each of the power rails 671 and 679 acts as a power line of the circuit cell 600C.

[0098] In by FIG. 5A to FIG. 5C The layout diagram shown and FIG. 6A to FIG. 6C In the integrated circuit specified by the layout diagram shown, each of the horizontal conductive lines is aligned with one of the horizontal wiring traces in the second metal layer, and FIG. 5A to FIG. 5C The circuit cells shown and FIG. 6A to FIG. 6C There are four horizontal routing traces in each of the circuit cells shown. Figure 6C , horizontal conductive line 672C occupies the first horizontal wiring trace, horizontal conductive lines connected to gate conductors gB1 and gA1 occupy the second horizontal wiring trace, horizontal conductive lines connected to gate conductors gB2 and gA2 occupy the third horizontal wiring trace, and horizontal conductive line 678C occupies the first horizontal wiring trace and the fourth horizontal wiring trace.

[0099] In some alternative designs of integrated circuits, the number of horizontal wiring traces per unit cell height is reduced. FIG. 7A to FIG. 7C The layout diagram shown and FIG. 8A to FIG. 8C The illustrated layout diagram specifies an integrated circuit in which each of the horizontal conductive lines is still aligned with one of the horizontal wiring traces, but the number of horizontal wiring traces per unit cell height is reduced to three.

[0100] Fig. 7A and Fig. 8A is a layout diagram of circuit cells 700A and 800A each implemented using an inverter according to some embodiments. Figure 7B and Figure 8B is a layout diagram of circuit cells 700B and 800B each implemented using an inverted AND gate according to some embodiments. Figure 7C and Figure 8C is a layout diagram of circuit cells 700C and 800C each implemented using an AND-OR-inverter gate (ie, AOI gate), according to some embodiments.

[0101] FIG. 7A to FIG. 7C The circuit cells and FIG. 8A to FIG. 8C The circuit cells in the FIG. 5A to FIG. 5C The circuit cells and FIG. 6A to FIG. 6C The modification includes changing the geometric position of some horizontal conductive lines in the second metal layer. Despite the change in geometric position, each of the power supply voltages (e.g., VDD and VSS) is still applied to the source terminal of the transistor via the vertical conductive lines in the first metal layer on the power rail.

[0102] exist Fig. 7AIn the circuit cell 700A shown, the source terminal sTp of the PMOS transistor Tp is conductively connected to the power rail 571 via the vertical conductive line 524A1, and the source terminal nTp of the NMOS transistor Tn is conductively connected to the power rail 579 via the vertical conductive line 524A2. Fig. 8A In the illustrated circuit cell 800A, the source terminal sTp of the PMOS transistor Tp is conductively connected to the power rail 671 via the vertical conductive line 624A1 , and the source terminal nTp of the NMOS transistor Tn is conductively connected to the power rail 679 via the vertical conductive line 624A2 .

[0103] exist Figure 7B In the circuit cell 700B shown, the joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is conductively connected to the power rail 571 via the vertical conductive line 525B1, and the source terminal sAn of the NMOS transistor TAn is conductively connected to the power rail 579 via the vertical conductive line 522B2. Figure 8B In the circuit cell 800B shown, the joint source terminal ssABp of the PMOS transistor TAp and the PMOS transistor TBp is conductively connected to the power rail 671 via the vertical conductive line 625B1, and the source terminal sAn of the NMOS transistor TAn is conductively connected to the power rail 679 via the vertical conductive line 622B2.

[0104] exist Figure 7C In the circuit cell 700C shown, the joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is conductively connected to the power rail 571 via the vertical conductive line 523C1, and each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is connected to the power rail 579 via the vertical conductive lines 521C3 and 529C3, respectively. Figure 8C In the circuit cell 800C shown, the joint source terminal ssB12p of the PMOS transistor TB1p and the PMOS transistor TB2p is conductively connected to the power rail 671 via the vertical conductive line 623C1, and each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is connected to the power rail 679 via the vertical conductive lines 621C3 and 629C3, respectively.

[0105] Fig. 9A is a layout diagram of a circuit cell 900A implemented using inverters according to some embodiments. Fig. 9B is a layout diagram of a circuit cell 900B implemented using an inverted AND gate according to some embodiments. Fig. 9C is a layout diagram of a circuit cell 900C implemented using an AOI gate according to some embodiments.

[0106] exist Fig. 9A , the circuit cell 900A includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. The circuit cell 900A includes a gate conductor gT extending in the Y direction and dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cell. The gate conductor gT intersects the PMOS active region structure 50p at the channel region of the PMOS transistor Tp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor Tn.

[0107] The source terminal sTp of the PMOS transistor Tp is configured to receive the upper limit power supply voltage VDD, and the source terminal sTn of the NMOS transistor Tn is configured to receive the lower limit power supply voltage VSS. The terminal conductor dTpn connects the drain terminal dTp of the PMOS transistor Tp and the drain terminal dTn of the NMOS transistor Tn. The gate terminal of the PMOS transistor Tp and the gate terminal of the NMOS transistor Tn are conductively connected together via the gate conductor gT. The gate conductor gT is configured to carry the input signal "I" of the inverter, and the terminal conductor dTpn is configured to carry the output signal "Z" of the inverter.

[0108] exist Fig. 9A , circuit cell 900A includes vertical conductive lines 924A1, 924A2, 926A1, and 925A extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times the CPP. Circuit cell 900A also includes power rails 951A and 959A in the Y direction in the first metal layer. Circuit cell 900A further includes horizontal conductive lines 972A, 974A, 976A, and 978A extending in the X direction in a second metal layer (e.g., metal layer M1).

[0109] exist Fig. 9A, the source terminal sTp of the PMOS transistor Tp is directly connected to the vertical conductive line 924A1 through the via connection VD, and the vertical conductive line 924A1 is directly connected to the horizontal conductive line 972A through the via connection V0. The horizontal conductive line 972A is further connected to the power rail 951A through the via connection V0, and the power rail 951A is configured to receive the upper limit power supply voltage VDD. The source terminal sTn of the NMOS transistor Tn is directly connected to the vertical conductive line 924A2 through the via connection VD, and the vertical conductive line 924A2 is directly connected to the horizontal conductive line 978A through the via connection V0. The horizontal conductive line 978A is further connected to the power rail 959A through the via connection V0, and the power rail 959A is configured to receive the lower limit power supply voltage VSS. Each of the power rails 951A and 959A extends along the Y direction and crosses multiple columns of circuit cells (not shown in the figure).

[0110] exist Fig. 9A In the embodiment of the present invention, each of the vertical conductive lines 924A1 and 924A2 acts as a power stub, and each of the horizontal conductive lines 972A and 978A acts as a power line of the circuit cell 900A. In some embodiments, when the power stub extends in the Y direction, the length of the power stub is less than the height of the circuit cell.

[0111] In some other embodiments, the circuit cell is implemented as an inverted gate. Fig. 9B , the circuit cell 900B includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. The circuit cell 900B includes gate conductors gA and gB extending in the Y direction. The circuit cell 900B also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cell. The gate conductor gA intersects the PMOS active region structure 50p at the channel region of the PMOS transistor TAp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor TAn. The gate conductor gB intersects the PMOS active region structure 50p at the channel region of the PMOS transistor TBp and intersects the NMOS active region structure 50n at the channel region of the NMOS transistor TBn. The circuit cell 900B also includes terminal conductors (eg, dAp, sAp, sBp, dBp, sAn, and dBn) intersecting the PMOS active region structure 50p or the NMOS active region structure 50n at respective source regions or drain regions of the transistor.

[0112] exist Fig. 9B, the circuit cell 900B includes a dummy gate conductor g105 extending in the Y direction. The dummy gate conductor g105 is spaced apart from each of the gate conductors gA and gB by a pitch distance of one contact pitch ("CPP"). The dummy gate conductor g105 is spaced apart from each of the dummy gate conductors g101 and g109 by a pitch distance of two CPP. An isolation region located under the dummy gate conductor g105 in the PMOS active region structure 50p isolates the drain terminal dAp of the PMOS transistor TAp from the source terminal sBp of the PMOS transistor TBp. An isolation region located under the dummy gate conductor g105 in the NMOS active region structure 50n isolates the drain terminal dAn of the NMOS transistor TAn from the source terminal sBn of the NMOS transistor TBn.

[0113] exist Fig. 9B , circuit cell 900B includes vertical conductive lines 922B1, 922B2, 924B1, 926B1, and 928B1 extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times the CPP. Circuit cell 900B also includes power rails 951B, 955B, and 959B extending in the Y direction in the first metal layer. Circuit cell 900B further includes horizontal conductive lines 972B, 974B, 976B1, 976B2, 978B1, and 978B2 extending in the X direction in a second metal layer (e.g., metal layer M1).

[0114] Each of the source terminal sAp of the PMOS transistor TAp and the source terminal sBp of the PMOS transistor TBp is conductively connected to the horizontal conductive line 972B via the corresponding vertical conductive lines 922B1 and 926B1. The horizontal conductive line 972B is connected to the vertical power rail 955B configured to receive the upper limit supply voltage VDD.

[0115] Each of the drain terminal dAp of the PMOS transistor TAp and the drain terminal dBp of the PMOS transistor TBp is conductively connected to the horizontal conductive line 974B via corresponding vertical conductive lines 924B1 and 928B1. The drain terminal dBp of the PMOS transistor TBp is also connected to the drain terminal dBn of the NMOS transistor TBn via a terminal conductor dBpn. The source terminal sBn of the NMOS transistor TBn and the drain terminal dAn of the NMOS transistor TAn are conductively connected together via a horizontal conductive line 978B2.

[0116] The source terminal sAn of the NMOS transistor TAn is conductively connected to the horizontal conductive line 978B1 via the vertical conductive line 922B2. The horizontal conductive line 978B1 is connected to the vertical power rail 951B configured to receive the upper limit supply voltage VDD.

[0117] Each of the horizontal conductive lines 976B1 and 976B2 is conductively connected to one of the gate conductors gA and gB via a corresponding vertical conductive line. The horizontal conductive lines 976B1 and 976B2 are configured as input pins of the NAND gate in the circuit cell 900B. The horizontal conductive line 974B is configured as an output pin of the NAND gate in the circuit cell 900B.

[0118] In some other embodiments, the circuit cell is implemented as an AOI gate. Fig. 9C , the circuit cell 900C includes a PMOS active region structure 50p and an NMOS active region structure 50n extending in the X direction. The circuit cell 900C includes gate conductors gA1, gA2, gB1, and gB2 extending in the Y direction. The circuit cell 900C also includes dummy gate conductors g101 and g109 located at the vertical cell boundaries of the circuit cell. The gate conductors gA1, gA2, gB1, and gB2 intersect the PMOS active region structure 50p at the channel regions of the PMOS transistors TA1p, TA2p, TB1p, and TB2p, respectively. The gate conductors gA1, gA2, gB1, and gB2 intersect the NMOS active region structure 50n at the channel regions of the NMOS transistors TA1n, TA2n, TB1n, and TB2n, respectively.

[0119] exist Fig. 9C , the circuit cell 900C includes dummy gate conductors g103, g105, and g107 extending in the Y direction. Each of the dummy gate conductors is separated from an adjacent gate conductor by a pitch distance of one contact pitch ("CPP"). Two adjacent dummy gate conductors are separated from each other by a pitch distance of two CPP. Each of the PMOS active region structure 50p and the NMOS active region structure 50n has an isolation region at the intersection where the dummy gate conductor intersects the PMOS active region structure 50p or the NMOS active region structure 50n.

[0120] exist Fig. 9C In the embodiment, the circuit cell 900C includes terminal conductors (e.g., dA2p, sA2p, sA1p, dA1p, dB1p, sB1p, dB2p, and sB2p) intersecting the PMOS active region structure 50p at respective source regions or drain regions of the PMOS transistor. The circuit cell 900C includes terminal conductors (e.g., sA2n, dA2n, sA1n, dA1n, dB1n, sB1n, dB2n, and sB2n).

[0121] exist Fig. 9C , the source terminal sB1p of the PMOS transistor TB1p and the source terminal sB2p of the PMOS transistor TB2p are configured to receive the upper limit power supply voltage VDD. Each of the source terminal sB2n of the NMOS transistor TB2n and the source terminal sA2n of the NMOS transistor TA2n is configured to receive the lower limit power supply voltage VSS. The gate conductors gA1, gA2, gB1 and gB2 are respectively configured to receive the input signal "A1", the input signal "A2", the input signal "B1" and the input signal "B2" of the AOI gate. One of the terminal conductors (i.e., ddA12p) is configured to carry the output signal "ZN" of the AOI gate.

[0122] exist Fig. 9C , circuit cell 900C includes vertical power rails 951C, 953C, 953C1, 955C, 957C, and 959C extending in the Y direction in a first metal layer (e.g., metal layer M0). Each of the vertical conductive lines is aligned with a vertical wiring trace. Two adjacent vertical wiring traces are separated by a pitch distance of 0.5 times CPP. Circuit cell 900C also includes horizontal conductive lines 972C, 974C1, 974C2, 976C1, 976C2, 976C3, 976C4, 978C1, 978C2, 978C3, 978C4, and 978C5 extending in the X direction in a second metal layer (e.g., metal layer M1).

[0123] Each of the source terminals sB1p and sB2p of PMOS transistor TB1p is conductively connected to horizontal conductive line 974C2 in the second metal layer via a corresponding vertical conductive line in the first metal layer. Horizontal conductive line 974C2 is further connected to vertical power rail 957C configured to receive upper limit supply voltage VDD.

[0124] Each of the drain terminal dB1p of the PMOS transistor TB1p and the drain terminal dB2p of the PMOS transistor TB2p is conductively connected to the horizontal conductive line 972C in the second metal layer via a corresponding vertical conductive line in the first metal layer. Each of the source terminal sA2p of the PMOS transistor TA2p and the source terminal sA1p of the PMOS transistor TA1p is also conductively connected to the horizontal conductive line 972C via one of the corresponding vertical conductive lines 925C1 and 929C1. Each of the drain terminal dA1p of the PMOS transistor TA1p and the drain terminal dA2p of the PMOS transistor TA2p is conductively connected to the horizontal conductive line 974C1 in the second metal layer via a corresponding vertical conductive line in the first metal layer. The drain terminal dA1p of the PMOS transistor TA1p is further connected to the drain terminal dA1n of the NMOS transistor TA1n by a terminal connector ddA1pn. Each of the drain terminal dA1n of the NMOS transistor TA1n and the drain terminal dB1n of the NMOS transistor TB1n is conductively connected to the horizontal conductive line 978C3 in the second metal layer via a corresponding vertical conductive line in the first metal layer.

[0125] Each of the source terminal dA1n of the NMOS transistor TA1n and the drain terminal dA2n of the NMOS transistor TA2n is conductively connected to the horizontal conductive line 978C2 in the second metal layer via the corresponding vertical conductive line in the first metal layer. The source terminal sA2n of the NMOS transistor TA2n is conductively connected to the horizontal conductive line 978C1 in the second metal layer via the corresponding vertical conductive line in the first metal layer. The horizontal conductive line 978C1 is further connected to the vertical power rail 951C configured to receive the lower limit power supply voltage VSS.

[0126] Each of the source terminal dB1n of the NMOS transistor TB1n and the drain terminal dB2n of the NMOS transistor TB2n is conductively connected to the horizontal conductive line 978C4 in the second metal layer via a corresponding vertical conductive line in the first metal layer. The source terminal sB2n of the NMOS transistor TB2n is conductively connected to the horizontal conductive line 978C4 in the second metal layer via a corresponding vertical conductive line in the first metal layer. The horizontal conductive line 978C4 is further connected to the vertical power rail 959C configured to receive the lower limit power supply voltage VSS.

[0127] Each of the horizontal conductive lines 974C1, 974C2, 974C3, and 974C4 is connected to one of the gate conductors gA2, gA1, gB1, and gB2, respectively, via a vertical conductive line in the first metal layer. The horizontal conductive lines 974C1, 974C2, 974C3, and 974C4 are configured as input pins of the AOI gate in the circuit cell 900C. The horizontal conductive line 974C1 is configured as an output pin of the AOI gate in the circuit cell 900C.

[0128] Fig.10 is a flow chart of a method 1000 of fabricating an integrated circuit having a power stub, according to some embodiments. Fig.10 The sequence of operations of method 1000 shown in FIG. 1 is for illustrative purposes only; the operations of method 1000 may be performed in the same manner as described above. Fig.10 It should be understood that the sequence shown in FIG. Fig.10 Additional operations may be performed before, during, and / or after the method 1000 depicted in the drawings, and some other processes may only be briefly described herein.

[0129] In operation 1010 of method 1000, a first type active region structure and a second type active region structure extending in the X direction are fabricated. In some embodiments, the first type active region structure is a p-type active region structure, and the second type active region structure is an n-type active region structure. In some embodiments, the first type active region structure is an n-type active region structure, and the second type active region structure is a p-type active region structure. Figure 1D to Figure 1G and FIG. 5D to FIG. 5H In the illustrated exemplary embodiment, a p-type active region semiconductor structure 50 p and an n-type active region semiconductor structure 50 n are fabricated.

[0130] In operation 1020 of method 1000, an isolation region is formed in the first type active region structure and the second type active region structure. Figure 1D to Figure 1G and FIG. 5D to FIG. 5H In the illustrated exemplary embodiment, isolation regions i101p and i109p are formed in the p-type active region semiconductor structure 50p, and isolation regions i101n and i109n are formed in the n-type active region semiconductor structure 50n.

[0131] In operation 1030 of method 1000, a terminal conductor extending in the Y direction is formed. Figure 1D to Figure 1G and FIG. 5D to FIG. 5H In the exemplary embodiment shown, terminal conductors sTp, sTn and dTpn are made. The terminal conductor sTp is the source terminal of the PMOS transistor Tp, and the terminal conductor sTn is the source terminal of the NMOS transistor Tn.

[0132] In operation 1040 of method 1000, a first interlayer dielectric is deposited, and the first interlayer dielectric covers the first type active region structure and the second type active region structure. Figure 1D to Figure 1G and FIG. 5D to FIG. 5H In the exemplary embodiment shown, a first interlayer dielectric ILD0 is deposited to cover the PMOS active region structure 50p and the NMOS active region structure 50n.

[0133] In operation 1050 of method 1000, a first power stub and a second power stub are formed in a first metal layer overlying a first interlayer dielectric. Figure 1D to Figure 1G In the exemplary embodiment shown, each of the horizontal conductive lines 124A and 128A overlying the first interlayer dielectric ILDO is formed as a power stub. FIG. 5D to FIG. 5H In the illustrated exemplary embodiment, each of the vertical conductive lines 524A1 and 524A2 overlying the first interlayer dielectric ILDO is fabricated as a power stub.

[0134] In operation 1060 of method 1000, a second interlayer dielectric is deposited, and the second interlayer dielectric covers the first power stub and the second power stub. Figure 1D to Figure 1G and FIG. 5D to FIG. 5H In the illustrated exemplary embodiment, a second interlayer dielectric ILD1 is deposited.

[0135] In operation 1070 of method 1000, a first power line and a second power line are formed in a second metal layer overlying the second interlayer dielectric. Figure 1D to Figure 1G In the exemplary embodiment shown, each of the vertical conductive lines 174A1 and 174A2 overlying the second interlayer dielectric ILD1 is formed as a power line. FIG. 5D to FIG. 5H In the illustrated exemplary embodiment, each of the power rails 571 and 579 overlying the second interlayer dielectric ILD1 is fabricated as a power line.

[0136] Fig.11 is a block diagram of an electronic design automation (EDA) system 1100 according to some embodiments.

[0137] In some embodiments, the EDA system 1100 includes an automatic placement and routing (APR) system. According to some embodiments, the method described herein for designing a layout diagram representing a wiring routing arrangement according to one or more embodiments may be implemented, for example, using the EDA system 1100.

[0138] In some embodiments, the EDA system 1100 is a general-purpose computing device including a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. The storage medium 1104 is encoded with (i.e., stores) computer program code 1106 (i.e., an executable instruction set) and other elements. The execution of the instructions 1106 by the hardware processor 1102 (at least in part) represents an EDA tool that implements part or all of the method described herein according to one or more embodiments (hereinafter referred to as the proposed process and / or method).

[0139] The processor 1102 is electrically coupled to the computer-readable storage medium 1104 via the bus 1108. The processor 1102 is also electrically coupled to an input / output (I / O) interface 1110 via the bus 1108. A network interface 1112 is also electrically connected to the processor 1102 via the bus 1108. The network interface 1112 is connected to a network 1114 so that the processor 1102 and the computer-readable storage medium 1104 can be connected to external components via the network 1114. The processor 1102 is configured to execute a computer program code 1106 encoded in the computer-readable storage medium 1104 so that the system 1100 can be used to implement part or all of the proposed process and / or method. In one or more embodiments, the processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0140] In one or more embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1104 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0141] In one or more embodiments, the storage medium 1104 stores computer program code 1106 configured to enable the system 1100 (where such implementation (at least in part) represents an EDA tool) to implement part or all of the proposed process and / or method. In one or more embodiments, the storage medium 1104 also stores information that facilitates the implementation of part or all of the proposed process and / or method. In one or more embodiments, the storage medium 1104 stores a standard cell library 1107 including such standard cells disclosed herein. In one or more embodiments, the storage medium 1104 stores one or more layout drawings 1109 corresponding to one or more layouts disclosed herein.

[0142] The EDA system 1100 includes an I / O interface 1110. The I / O interface 1110 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1110 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for communicating information and commands to the processor 1102.

[0143] The EDA system 1100 also includes a network interface 1112 coupled to the processor 1102. The network interface 1112 enables the system 1100 to communicate with a network 1114 to which one or more other computer systems are connected. The network interface 1112 includes a wireless network interface such as BLUETOOTH, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the proposed process and / or method is implemented in two or more systems 1100.

[0144] The system 1100 is configured to receive information via an I / O interface 1110. The information received via the I / O interface 1110 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters processed by the processor 1102. The information is transmitted to the processor 1102 via a bus 1108. The EDA system 1100 is configured to receive information related to a user interface (UI) via the I / O interface 1110. The information is stored in a computer-readable storage medium 1104 as a UI 1142.

[0145] In some embodiments, part or all of the proposed process and / or method is implemented in the form of a stand-alone software application executed by a processor. In some embodiments, part or all of the proposed process and / or method is implemented in the form of a software application that is part of an additional software application. In some embodiments, part or all of the proposed process and / or method is implemented in the form of a plug-in to a software application. In some embodiments, at least one of the proposed process and / or method is implemented in the form of a software application that is part of an EDA tool. In some embodiments, part or all of the proposed process and / or method is implemented in the form of a software application used by the EDA system 1100. In some embodiments, a tool (e.g., a software application available from Cadence Design Systems, Inc.) is used to implement the proposed process and / or method. or another suitable layout generation tool) to generate a layout diagram including standard cells.

[0146] In some embodiments, the process is implemented in the functional form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or storage units, such as one or more of an optical disk (e.g., DVD), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., ROM, RAM), a memory card, and the like.

[0147] Fig.12 is a block diagram of an integrated circuit (IC) manufacturing system 1200 and an IC manufacturing process associated with the IC manufacturing system 1200 according to some embodiments. In some embodiments, the manufacturing system 1200 is used to fabricate at least one of the following based on the layout diagram: (A) one or more semiconductor masks or (B) at least one component located in a layer of a semiconductor integrated circuit.

[0148] exist Fig.12In the present invention, the IC manufacturing system 1200 includes entities such as a design house 1220, a mask house 1230, and an IC manufacturer / fab 1250, which interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 1260. The entities in the system 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired communication channels and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, a single larger company owns two or more of the design house 1220, the mask house 1230, and the IC foundry 1250. In some embodiments, two or more of the design facility 1220, the mask facility 1230, and the IC foundry 1250 are co-located in a common facility and use common resources.

[0149] The design organization (or design team) 1220 generates an IC design layout 1222. The IC design layout 1222 includes various geometric patterns designed for the IC device 1260. The geometric patterns correspond to the patterns of the metal layers, oxide layers, or semiconductor layers that constitute the various components of the IC device 1260 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1222 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) (such as an active region, a gate electrode, a source and a drain, a metal wire or a through hole for interconnecting the layers, and an opening for a bonding pad) and various material layers disposed on the semiconductor substrate. The design organization 1220 implements an appropriate design program to form the IC design layout 1222. The design program includes one or more of a logic design, a physical design, or a placement and routing operation. The IC design layout 1222 is presented in the form of one or more data files having information of the geometric patterns. For example, the IC design layout 1222 can be expressed in a GDSII file format or a DFII file format.

[0150] The mask mechanism 1230 includes data preparation 1232 and mask production 1244. The mask mechanism 1230 uses the IC design layout 1222 to produce one or more masks 1245 for producing various layers of the IC device 1260 according to the IC design layout 1222. The mask mechanism 1230 performs mask data preparation 1232, translating the IC design layout 1222 into a representative data file (RDF) during the mask data preparation 1232. The mask data preparation 1232 provides the RDF for the mask production 1244. The mask production 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 1245 or a semiconductor wafer 1253). The mask data preparation 1232 manipulates the design layout 1222 to comply with the specific characteristics of the mask writer and / or the requirements of the IC foundry 1250. exist Fig.12 , mask data preparation 1232 and mask production 1244 are shown as separate elements. In some embodiments, mask data preparation 1232 and mask production 1244 may be collectively referred to as mask data preparation.

[0151] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, crosstalk, other process effects, and the like). OPC adjusts the IC design layout 1222. In some embodiments, mask data preparation 1232 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0152] In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC) that checks the IC design layout 1222 that has been processed in OPC using a set of mask generation rules containing certain geometric constraints and / or connectivity constraints to ensure that sufficient margins are in place to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for the effects of photolithography during mask fabrication 1244, which may cancel a portion of the modifications performed by OPC to satisfy the mask generation rules.

[0153] In some embodiments, mask data preparation 1232 includes lithography process checking (LPC), which simulates the process to be performed by IC foundry 1250 to fabricate IC device 1260. LPC simulates such process based on IC design layout 1222 to generate simulated manufactured device, such as IC device 1260. Process parameters in LPC simulation may include parameters associated with various processes of IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of manufacturing process. LPC takes into account various factors such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated manufactured device has been generated by LPC, if the shape similarity of the simulated device is not sufficient to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 1222.

[0154] It should be understood that the above description of mask data preparation 1232 has been simplified for the purpose of clarity. In some embodiments, data preparation 1232 includes additional features, such as modifying the logic operation (LOP) of IC design layout 1222 according to manufacturing rules. In addition, the processes applied to IC design layout 1222 during data preparation 1232 can be performed in a variety of different orders.

[0155] After the mask data preparation 1232 and during the mask fabrication 1244, a mask 1245 or a group of masks 1245 is fabricated based on the modified IC design layout 1222. In some embodiments, the mask fabrication 1244 includes performing one or more lithographic exposures based on the IC design layout 1222. In some embodiments, an electron-beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on the mask (photomask or stencil) 1245 based on the modified IC design layout 1222. The mask 1245 can be formed by various techniques. In some embodiments, the mask 1245 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of the mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, the mask 1245 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1245, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by the mask fabrication 1244 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1253, in an etching process to form various etched regions in the semiconductor wafer 1253, and / or in other suitable processes.

[0156] IC foundry 1250 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC foundry 1250 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line, BEOL) manufacturing for interconnects and packaging of IC products, and a third manufacturing facility may provide other services for the foundry.

[0157] IC foundry 1250 includes fabrication tools 1252 configured to perform various fabrication operations on semiconductor wafer 1253, thereby fabricating IC device 1260 based on a mask (e.g., mask 1245). In various embodiments, fabrication tools 1252 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a chemical vapor deposition (CVD) chamber or a low-pressure CVD (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0158] IC foundry 1250 uses mask 1245 made by mask mechanism 1230 to make IC device 1260. Therefore, IC foundry 1250 at least indirectly uses IC design layout 1222 to make IC device 1260. In some embodiments, IC foundry 1250 uses mask 1245 to make semiconductor wafer 1253 to form IC device 1260. In some embodiments, IC fabrication includes performing one or more lithography exposures based at least indirectly on IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other appropriate substrate with material layers formed thereon. Semiconductor wafer 1253 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and similar features (formed at subsequent manufacturing steps).

[0159] The present disclosure relates to an integrated circuit. The integrated circuit includes: a first type active region structure and a second type active region structure extending in a first direction; a first isolation region and a second isolation region located in the first type active region structure; and a third isolation region and a fourth isolation region located in the second type active region structure. The third isolation region in the second type active region structure is vertically aligned with the first isolation region in the first type active region structure along the second direction and delineates a first vertical cell boundary of a circuit cell. The fourth isolation region in the second type active region structure is vertically aligned with the second isolation region in the first type active region structure along the second direction and delineates a second vertical cell boundary of the circuit cell. The integrated circuit also includes a first power stub and a second power stub, the first power stub and the second power stub are located in a first metal layer overlying a first interlayer dielectric, the first interlayer dielectric covering the first type active region structure and the second type active region structure. The integrated circuit still includes: a first through-hole connector, directly connected between the first power stub and the first source terminal of the first transistor in the circuit cell; and a second through-hole connector, directly connected between the second power stub and the second source terminal of the second transistor in the circuit cell. The integrated circuit further includes a first power line and a second power line, the first power line and the second power line are located in a second metal layer overlying a second interlayer dielectric, and the second interlayer dielectric covers the first power stub and the second power stub in the first metal layer. The first power line is connected to the first power stub, and the second power line is connected to the second power stub. The first power line is configured to receive a first power supply voltage, and the second power line is configured to receive a second power supply voltage different from the first power supply voltage.

[0160] In a related embodiment, the integrated circuit further includes: a first terminal conductor, extending in the second direction and intersecting the first type active region structure at a first source region located between the first isolation region and the second isolation region, wherein the second direction is perpendicular to the first direction, wherein the first terminal conductor is the first source terminal of the first transistor; a second terminal conductor, extending in the second direction and intersecting the second type active region structure at a second source region located between the third isolation region and the fourth isolation region, wherein the second terminal conductor is the second source terminal of the second transistor; and the first through-hole connector, directly connected between the first power stub and the first terminal conductor.

[0161] In a related embodiment, the integrated circuit further includes: a third through-hole connector directly connected between the first power stub and the first power line; and a fourth through-hole connector directly connected between the second power stub and the second power line.

[0162] In a related embodiment, the integrated circuit, wherein each of the first power stub and the second power stub extends in the first direction, and wherein each of the first power line and the second power line extends in the second direction.

[0163] In a related embodiment, each of the first power stub and the second power stub is defined between the first vertical cell boundary and the second vertical cell boundary.

[0164] In a related embodiment, the integrated circuit further includes: a horizontal conductive line extending in the first direction in the first metal layer and aligned with a horizontal wiring trace, wherein the first power stub or the second power stub is aligned with the horizontal wiring trace for positioning the horizontal conductive line.

[0165] In a related embodiment, the integrated circuit further includes: a vertical conductive line extending in the second direction in the second metal layer and aligned with a vertical wiring trace, wherein the first power line or the second power line is aligned with the vertical wiring trace for positioning the vertical conductive line.

[0166] In a related embodiment, wherein each of the first power stub and the second power stub extends in the second direction, and wherein each of the first power line and the second power line extends in the first direction.

[0167] In a related embodiment, the integrated circuit further includes: a vertical conductive line extending in the second direction in the second metal layer and aligned with a vertical wiring trace, wherein the first power stub or the second power stub is aligned with the vertical wiring trace for positioning the vertical conductive line.

[0168] In a related embodiment, each of the first power line and the second power line is defined between the first vertical cell boundary and the second vertical cell boundary.

[0169] In a related embodiment, at least one of the first power line or the second power line crosses both the first vertical cell boundary and the second vertical cell boundary.

[0170] Another aspect of the present disclosure is also related to an integrated circuit. The integrated circuit includes: a first type active area structure and a second type active area structure extending in a first direction; a plurality of dummy gate conductors extending in a second direction perpendicular to the first direction; and a plurality of gate conductors extending in the second direction. Each of the first type active area structure and the second type active area structure has a plurality of isolation regions at a plurality of intersections where the plurality of dummy gate conductors intersect with the first type active area structure or the second type active area structure. The first dummy gate conductor is aligned with a first vertical cell boundary of a circuit cell, and the second dummy gate conductor is aligned with a second vertical cell boundary of the circuit cell. Each of the plurality of gate conductors intersects with one or both of the first type active area structure and the second type active area structure. Each of the plurality of gate conductors is located between two adjacent dummy gate conductors at an equal pitch distance. The integrated circuit also includes a first power stub and a second power stub, the first power stub and the second power stub extending in the second direction in a first metal layer overlying a first interlayer dielectric, the first interlayer dielectric covering the first type active region structure and the second type active region structure. The integrated circuit still includes: a first through-hole connector directly connected between the first power stub and a first source terminal of a first transistor in the circuit cell; and a second through-hole connector directly connected between the second power stub and a second source terminal of a second transistor in the circuit cell. The integrated circuit further includes a first power line and a second power line, the first power line and the second power line extending in the first direction in a second metal layer overlying a second interlayer dielectric, the second interlayer dielectric covering the first power stub and the second power stub in the first metal layer. The first power line is connected to the first power stub, and the second power line is connected to the second power stub. The first power line is configured to receive a first power supply voltage, and the second power line is configured to receive a second power supply voltage different from the first power supply voltage.

[0171] In a related embodiment, the integrated circuit further includes: a first terminal conductor, extending in the second direction and intersecting with the first type active region structure at a first source region, the first source region being the source terminal of the first type transistor located in the circuit cell, wherein the first terminal conductor is the first source terminal of the first transistor; a second terminal conductor, extending in the second direction and intersecting with the second type active region structure at a second source region, the second source region being the source terminal of the second type transistor located in the circuit cell, wherein the second terminal conductor is the second source terminal of the second transistor.

[0172] In a related embodiment, the integrated circuit further includes: a third through-hole connector directly connected between the first power stub and the first power line.

[0173] In a related embodiment, a pitch distance from a gate conductor among the plurality of gate conductors to an adjacent dummy gate conductor among the plurality of dummy gate conductors is one contact pitch.

[0174] In a related embodiment, a pitch distance between two adjacent dummy gate conductors is twice a contact pitch.

[0175] In a related embodiment, the plurality of dummy gate conductors includes a third dummy gate conductor, the third dummy gate conductor being spaced apart from the first dummy gate conductor by a pitch distance that is one contact pitch.

[0176] In a related embodiment, the integrated circuit further comprises: a first power rail extending in the first metal layer in the second direction and aligned with the first dummy gate conductor at the first vertical cell boundary, wherein the first power rail is connected to the first power line.

[0177] In a related embodiment, the integrated circuit further comprises: a second power rail extending in the first metal layer in the second direction and aligned with the second dummy gate conductor at the second vertical cell boundary, wherein the second power rail is connected to the second power line.

[0178] Another aspect of the present disclosure is related to a method for manufacturing an integrated circuit. The method includes: manufacturing a first type active region structure and a second type active region structure extending in a first direction; forming a first isolation region and a second isolation region in the first type active region structure; and forming a third isolation region and a fourth isolation region in the second type active region structure. The third isolation region in the second type active region structure is vertically aligned with the first isolation region in the first type active region structure along the second direction and delineates a first vertical cell boundary of a circuit cell. The fourth isolation region in the second type active region structure is vertically aligned with the second isolation region in the first type active region structure along the second direction and delineates a second vertical cell boundary of the circuit cell. The method also includes manufacturing a first power stub and a second power stub in a first metal layer overlying a first interlayer dielectric, the first interlayer dielectric covering the first type active region structure and the second type active region structure. The method still includes: connecting the first power stub to a first source region located between the first isolation region and the second isolation region; and connecting the second power stub to a second source region located between the third isolation region and the fourth isolation region. The method further includes forming a first power line and a second power line in a second metal layer overlying a second interlayer dielectric, the second interlayer dielectric covering the first power stub and the second power stub in the first metal layer. The first power line is configured to receive a first power supply voltage, and the second power line is configured to receive a second power supply voltage different from the first power supply voltage. The method further includes connecting the first power stub to the first power line and connecting the second power stub to the second power line.

[0179] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, comprising: The first type active region structure and the second type active region structure extend in a first direction; A first isolation region and a second isolation region are located in the first type active region structure; A third isolation region and a fourth isolation region are located in the second type active region structure, wherein the third isolation region in the second type active region structure is vertically aligned with the first isolation region in the first type active region structure along a second direction and defines a first vertical cell boundary of a circuit cell, and wherein the fourth isolation region in the second type active region structure is vertically aligned with the second isolation region in the first type active region structure along the second direction and defines a second vertical cell boundary of the circuit cell; A first power stub and a second power stub are located in a first metal layer overlying a first interlayer dielectric, wherein the first interlayer dielectric covers the first type active region structure and the second type active region structure; a first through-hole connector directly connected between the first power stub and a first source terminal of a first transistor in the circuit cell; a second through-hole connector directly connected between the second power stub and a second source terminal of a second transistor in the circuit cell; and A first power line and a second power line are located in a second metal layer overlying a second interlayer dielectric, the second interlayer dielectric covering the first power stub and the second power stub in the first metal layer, wherein the first power line is connected to the first power stub, and the second power line is connected to the second power stub, and wherein the first power line is configured to receive a first power supply voltage, and the second power line is configured to receive a second power supply voltage different from the first power supply voltage.

2. The integrated circuit according to claim 1, further comprising: a first terminal conductor extending in the second direction and intersecting the first type active region structure at a first source region between the first isolation region and the second isolation region, wherein the second direction is perpendicular to the first direction, wherein the first terminal conductor is the first source terminal of the first transistor; a second terminal conductor extending in the second direction and intersecting the second type active region structure at a second source region between the third isolation region and the fourth isolation region, wherein the second terminal conductor is the second source terminal of the second transistor; and The first through-hole connector is directly connected between the first power stub and the first terminal conductor.

3. The integrated circuit according to claim 2, further comprising: a third through-hole connector, directly connected between the first power stub and the first power line; as well as The fourth through-hole connector is directly connected between the second power stub and the second power line. 4 . The integrated circuit of claim 1 , wherein each of the first power stub and the second power stub extends in the first direction, and wherein each of the first power line and the second power line extends in the second direction. 5 . The integrated circuit of claim 4 , wherein each of the first power stub and the second power stub is defined between the first vertical cell boundary and the second vertical cell boundary.

6. The integrated circuit of claim 4, further comprising: A horizontal conductive line extends in the first direction in the first metal layer and is aligned with a horizontal wiring trace, wherein the first power stub or the second power stub is aligned with the horizontal wiring trace that positions the horizontal conductive line.

7. The integrated circuit of claim 4, further comprising: A vertical conductive line extends in the second direction in the second metal layer and is aligned with a vertical wiring trace, wherein the first power line or the second power line is aligned with the vertical wiring trace that positions the vertical conductive line.

8. The integrated circuit of claim 1, wherein each of the first power stub and the second power stub extends in the second direction, and wherein each of the first power line and the second power line extends in the first direction.

9. An integrated circuit comprising: The first type active region structure and the second type active region structure extend in a first direction; a plurality of dummy gate conductors extending in a second direction perpendicular to the first direction, wherein each of the first type active region structure and the second type active region structure has a plurality of isolation regions at a plurality of intersections where the plurality of dummy gate conductors intersect with the first type active region structure or the second type active region structure, and wherein a first dummy gate conductor of the plurality of dummy gate conductors is aligned with a first vertical cell boundary of a circuit cell, and a second dummy gate conductor of the plurality of dummy gate conductors is aligned with a second vertical cell boundary of the circuit cell; a plurality of gate conductors extending in the second direction, each of the plurality of gate conductors intersecting one or both of the first type active region structure and the second type active region structure, wherein each of the plurality of gate conductors is located between two adjacent dummy gate conductors of the plurality of dummy gate conductors at an equal pitch distance; A first power stub and a second power stub extending in the second direction in a first metal layer overlying a first interlayer dielectric, the first interlayer dielectric covering the first type active region structure and the second type active region structure; a first through-hole connector directly connected between the first power stub and a first source terminal of a first transistor in the circuit cell; a second through-hole connector directly connected between the second power stub and a second source terminal of a second transistor in the circuit cell; as well as A first power line and a second power line extend in the first direction in a second metal layer overlying a second interlayer dielectric, the second interlayer dielectric covering the first power stub and the second power stub in the first metal layer, wherein the first power line is connected to the first power stub, and the second power line is connected to the second power stub, and wherein the first power line is configured to receive a first power supply voltage, and the second power line is configured to receive a second power supply voltage different from the first power supply voltage.

10. The integrated circuit of claim 9, wherein a pitch distance from a gate conductor of the plurality of gate conductors to an adjacent dummy gate conductor of the plurality of dummy gate conductors is one contact pitch.

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