Electrocardiogram monitoring chip system-in-package structure

Abstract

The utility model discloses a system-level packaging structure of an electrocardiogram monitoring chip, and belongs to the technical field of semiconductor packaging. According to the scheme, all modules of the ECG product are integrated together through the SiP technology. Specifically, the MCU main control module is arranged in the middle of the left side of the substrate, the AFE module, the RF antenna module and the crystal oscillator module are arranged on the right side, the lower side and the upper side of the MCU main control module respectively, and the VDD power module and the AVDD power module are arranged on the upper side and the lower side of the AFE module respectively, so that connecting lines between the modules are shortest, and the layout is symmetrical and compact. And meanwhile, aiming at the chip type capacitance resistance device, the packaging area of the chip type device is reduced by reducing the size of the bonding pad and optimizing the windowing design of the solder mask. Compared with a traditional PCB design mode, according to the scheme, the packaging size and the internal signal path are remarkably shortened, signal loss is greatly reduced, high performance and high stability of signal transmission are ensured, and the overall power consumption of a product is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a system-level packaging structure of an electrocardiogram monitoring chip. Background Art

[0002] With the rapid development of portable applications and wearable medical electronic technology, the demand for product function expansion and structural integration is increasing year by year. Currently, wearable ECG (electrocardiogram) medical products on the market generally adopt a separate architecture design of MCU processing chip and AFE chip, that is, each single chip is connected to other components through traditional PCB (Printed Circuit Board) or FPC (Flexible Printed Circuit) technology to build a system. The limitation of this separate design is that it often leads to a relatively large product size, which in turn leads to higher power consumption and relatively poor portability.

[0003] In response to the market demand for thin, light and flexible wearable medical products, there is currently no solution on the market that successfully integrates MCU and AFE modules into SiP (System in Package) to form a mature product. How to successfully integrate the diversified functional components including the main control module, AFE processing module, Bluetooth RF module and power module, etc., to ensure that the functions of the product are stable and reliable, and on this basis, to improve the overall performance and reduce power consumption, is a challenge that the industry urgently needs to overcome. Utility Model Content

[0004] The technical problem to be solved by the utility model is: in view of the above-mentioned defects of the prior art, a system-level packaged electrocardiogram monitoring chip is provided to improve the portability of wearable ECG medical products.

[0005] To achieve the above object, the utility model provides a system-level packaging structure of an electrocardiogram monitoring chip, the structure comprising:

[0006] A substrate, comprising a front side and a back side arranged opposite to each other, wherein the front side is provided with solder pads electrically connected to each module, and the back side is provided with a solder ball array;

[0007] The MCU main control module is arranged in the middle of the left side of the front side of the substrate, and the MCU main control module includes an MCU chip;

[0008] An AFE module is arranged on the right side of the MCU main control module, and the AFE module includes an AFE chip;

[0009] The RF antenna module is arranged below the MCU main control module;

[0010] A crystal oscillator module is arranged above the MCU main control module;

[0011] A VDD power supply module is arranged above the AFE module, and the VDD power supply module provides digital power for each module;

[0012] An AVDD power supply module is arranged below the AFE module, and the AVDD power supply module provides analog power for each module;

[0013] The MCU main control module and the AFE module both include a plurality of chip capacitor and resistor components;

[0014] A pad group for electrically connecting chip capacitor and resistor components is arranged on the front side of the substrate, each chip capacitor and resistor component package corresponds to a pad group, each pad group includes two pads, and the size of the pads is smaller than the size of the pads of the corresponding chip capacitor and resistor component on the PCB board; interconnected solder resist layer openings are arranged in the pads in each pad group and in the bridging areas between the pads.

[0015] Preferably, a prohibited wiring area is arranged between two pads of each pad group of the chip capacitor and resistor device package.

[0016] Preferably, the MCU chip is packaged in a wafer-level chip packaging manner and is connected to the pad on the front side of the substrate via a BGA solder joint.

[0017] Preferably, the front side of the AFE chip is connected to the pad on the front side of the substrate via a bonding wire, and the back side is connected to the pad with a window on the front side of the substrate via a heat dissipation adhesive.

[0018] Preferably, a ground via is provided at a position on the substrate corresponding to the AFE chip.

[0019] Preferably, the interconnection line between the RF antenna module and the MCU chip is set to a non-bending line with uniform width, and adopts a ground-wrapped design.

[0020] Preferably, the crystal oscillator module includes a crystal oscillator and two filter capacitors, the two filter capacitors are arranged close to the crystal oscillator pins to maintain a shorter signal loop, and the entire crystal oscillator module adopts a ground-enclosed design.

[0021] Preferably, the substrate adopts a 6-layer stacked board structure, the first layer from the front to the back of the substrate is provided with pads for various devices, the second layer is a digital signal and analog signal ground layer, the third and fourth layers are signal routing layers, the fifth layer is a digital power supply and analog power supply layer, and the sixth layer is provided with a solder ball array.

[0022] The utility model proposes a system-level packaging structure for an ECG monitoring chip, which integrates various modules of ECG products through SiP technology. Specifically, the MCU main control module is arranged in the middle of the left side of the substrate, the AFE module, the RF antenna module, and the crystal oscillator module are arranged on the right side, below, and above the MCU main control module, respectively, and the VDD power supply module and the AVDD power supply module are arranged on the upper and lower sides of the AFE module, respectively, so that the connection between each module is the shortest, the layout is symmetrical and compact, and the pad size is reduced for chip capacitors and resistors, and the solder mask window design is optimized. Compared with the traditional PCB design method, this solution significantly shortens the package size and internal signal path, thereby greatly reducing signal loss, ensuring high performance and high stability of signal transmission, and reducing the overall power consumption of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0024] Figure 1 It is a plan view of the internal layout structure design of the SiP package of the ECG product provided by the embodiment of the utility model.

[0025] Figure 2 It is a side view of the internal layout structure design of the SiP package of the ECG product provided by the embodiment of the utility model.

[0026] Figure 3 It is a top view of the traditional PCB board chip capacitor and resistor device package pad design.

[0027] Figure 4 It is a schematic diagram of the key structural shapes of the traditional PCB chip capacitor and resistor device packaging pad design.

[0028] Figure 5 It is a cross-sectional schematic diagram of the traditional PCB chip capacitor and resistor device package pad design.

[0029] Figure 6 It is a top plan view of the chip capacitor and resistor device package pad design provided by an embodiment of the utility model.

[0030] Figure 7 It is a schematic diagram of the key structural shape of the chip capacitor and resistor device package pad design provided by the embodiment of the utility model.

[0031] Figure 8 It is a schematic cross-sectional view of the chip capacitor and resistor device package pad design provided by an embodiment of the utility model.

[0032] In the attached figure:

[0033] 10: substrate; 11: solder ball array;

[0034] 20: MCU main control module; 21: MCU chip; 211: MCU chip BGA solder joint;

[0035] 30: AFE module; 31: AFE chip; 32: AFE chip bonding wire; 33: heat dissipation glue;

[0036] 40: RF antenna module;

[0037] 50: crystal oscillator module;

[0038] 60: VDD power supply module;

[0039] 70: AVDD power supply module;

[0040] 80: Chip capacitor and resistor device; 81: Pad; 82: Solder mask layer; 83: Solder mask layer window; 84: No wiring area;

[0041] 90: SiP packaging plastic packaging; 91: packaging outline;

[0042] L: Package outline length; W: Package outline width; A: Horizontal outer margin of two pads (length of two pads plus pad spacing); B: Width of a single pad; C: Length of a single pad; E: Vertical solder mask window length; F: Vertical solder mask window width; D: Horizontal solder mask window length; G: Horizontal solder mask window width; H: Length of bottom edge of keep-out area; J: Height of middle part of keep-out area; K: Total height of keep-out area. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0044] The general idea of ​​the utility model is to integrate the various modules of ECG products through SiP technology. Specifically, the MCU main control module is set in the middle of the left side of the substrate, the AFE module, the RF antenna module, and the crystal oscillator module are respectively set on the right side, below, and above the MCU main control module, and the VDD power supply module and the AVDD power supply module are respectively set on the upper and lower sides of the AFE module, so that the connection between the modules is the shortest, the layout is symmetrical and compact, and the pad size is reduced for chip capacitors and resistors, and the solder mask window design is optimized.

[0045] The following is a further detailed description of the embodiments of the utility model in conjunction with the accompanying drawings of the specification. It should be understood that the embodiments described herein are only used to illustrate and explain the utility model, and are not used to limit the utility model.

[0046] The utility model is suitable for system-level packaging of electrocardiogram monitoring products. The system-level packaging chip provided by the utility model can be applied to medical products that require continuous electrocardiogram monitoring, including portable electrocardiogram monitors and dynamic electrocardiogram recorders.

[0047] like Figure 1-2 As shown, the embodiment of the utility model provides a system-level packaging structure of an electrocardiogram monitoring chip, including:

[0048] The substrate 10 comprises a front side and a back side which are arranged opposite to each other, wherein the front side is provided with solder pads which are electrically connected to each module, and the back side is provided with a solder ball array 11;

[0049] The MCU main control module 20 is arranged at the middle of the left side of the front side of the substrate 10, and the MCU main control module 20 includes an MCU chip 21;

[0050] An AFE module 30 is arranged on the right side of the MCU main control module 20, and the AFE module 30 includes an AFE chip 31;

[0051] The RF antenna module 40 is arranged below the MCU main control module 20;

[0052] A crystal oscillator module 50 is arranged above the MCU main control module 20;

[0053] A VDD power supply module 60 is disposed above the AFE module 30, and the VDD power supply module 60 provides digital power for each module;

[0054] An AVDD power supply module 70 is disposed below the AFE module 30 and provides analog power to each module;

[0055] The MCU main control module 20 and the AFE module 30 both include a plurality of chip capacitor and resistor devices 80. Chip devices refer to a type of electronic components designed for surface mount technology, which are characterized by being able to be directly mounted on the surface of a printed circuit board rather than being inserted into a through hole of the circuit board. The widespread use of chip devices has greatly promoted the miniaturization, lightweight and integrated development of electronic equipment. In the embodiment of the utility model, in order to meet the requirements of miniaturization, lightweight and integration, corresponding chip capacitor and resistor devices are selected for the capacitors and resistors in each module, such as the capacitor and resistor devices associated with the MCU chip 21 in the MCU main control module 20, and the capacitor and resistor devices associated with the AFE chip 31 in the AFE module 30. The chip capacitor and resistor devices 80 in the embodiment of the utility model each include two connecting terminals.

[0056] The front side of the substrate 10 is provided with a pad group for electrically connecting the chip capacitor and resistor devices 80 in each module. Each chip capacitor and resistor device package corresponds to a pad group. Each pad group includes two pads 81. The size of the pads 81 is smaller than the size of the pads 81 of the corresponding chip capacitor and resistor device 80 on the PCB board. The two pads 81 in each pad group are respectively connected to the two connecting terminals of the chip capacitor and resistor device 80, and the pads 81 in each pad group and the bridging area between the pads 81 are provided with interconnected solder mask windows 83. A prohibited wiring area 84 is provided between the two pads 81 of each pad group of the chip capacitor and resistor device package.

[0057] The system-level packaged ECG monitoring chip also includes a SiP packaging plastic seal 90 arranged on each module. After the modules are laid out according to the above layout structure and then electrically connected, all modules can be sealed into a whole through the SiP packaging plastic seal 90.

[0058] The AFE module 30 is used to collect human ECG signals, and amplify, filter, signal condition, and perform analog-to-digital conversion on the collected ECG signals, and transmit the processed signals to the MCU main control module 20. The MCU main control module 20 is the core control component of the ECG monitoring product, and is responsible for data processing, algorithm implementation, system control, user interface interaction, power interface, communication interface and other functions. The MCU main control module 20 is electrically connected to the AFE module 30, the RF antenna module 40, the crystal oscillator module 50, the VDD power module 60, and the AVDD power module 70. The RF antenna module 40 is responsible for the high-frequency signal transmission and reception between the SiP packaged chip and the external circuit module, realizing the wireless communication function, and sending the ECG data collected by the ECG product to the mobile phone APP or the cloud server. The crystal oscillator module 50 is responsible for providing the clock signal required inside the SiP packaged chip to realize functions such as data transmission and synchronous counting.

[0059] In the embodiment of the utility model, the above-mentioned layout structure is adopted, and the MCU main control module 20 is arranged in the middle of the left side of the substrate 10, and the AFE module 30, the RF antenna module 40, and the crystal oscillator module 50 are respectively arranged on the right side, below, and above the MCU main control module 20, taking into account the distribution characteristics of the pins of the MCU chip 21, so that the connection between each module and the corresponding pins of the MCU chip 21 is the shortest, and the signal interference is minimized. In practical applications, the position relationship between the MCU chip 21 and the AFE chip 31 is first determined according to the positions of the pins of the MCU chip 21 and the AFE chip 31, so that the connection between the corresponding pins of the two is the shortest, and then the positions of other modules other than the AFE module are set according to the pin positions of the MCU chip 21, so that the pin connection between the MCU chip 21 and these modules is the shortest. In the embodiment of the utility model, both the MCU chip 21 and the AFE chip 31 need to be connected to the digital power supply and the analog power supply at the same time. After the positions of the MCU chip 21 and the AFE chip 31 are determined, the pins related to the digital power supply in the MCU chip 21 and the AFE chip 31 are mainly concentrated in the upper part, and the pins related to the analog power supply are mainly concentrated in the lower part. Therefore, the VDD power supply module 60 is set above the AFE module, and the AVDD power supply module 70 is set below the AFE module, which complies with the principle of the shortest line, and at the same time makes the entire layout structure symmetrical and compact, and the overall volume occupied by the packaged chip is minimized.

[0060] In some embodiments of the present invention, the MCU chip 21 is packaged in a wafer-level chip package and connected to the pad on the front side of the substrate 10 through a BGA solder joint 211. Specifically, in some embodiments of the present invention, the MCU chip 21 is a BGA package with a 10x10 solder ball array, and a 10x10 solder ball array is correspondingly arranged on the front side of the substrate 10, which is connected one by one to the solder balls on the MCU chip 21.

[0061] In some embodiments of the utility model, the front side of the AFE chip 31 is connected to the pad on the front side of the substrate 10 through a bonding wire 32, and the back side is connected to the pad with a window on the front side of the substrate 10 through a heat dissipation adhesive 33. Specifically, in some embodiments of the utility model, the pad on the front side of the AFE chip 31 is bound to the pad on the substrate through a gold wire. The utility model has no restrictions on the material of the binding wire. In addition to the gold wire, aluminum wire, copper wire, etc. can also be used. A solder resist window 83 is provided at a position corresponding to the heat dissipation adhesive on the back side of the AFE chip 31 on the front side of the substrate 10. A solder resist layer 82 is provided on the substrate 10. The solder resist window 83 is a window area formed by partially hollowing out the solder resist layer 82. The solder resist window 83 causes the copper foil on the substrate 10 to be exposed. The bottom of the AFE chip 31 can be fixed on the copper foil of the substrate 10 through the heat dissipation adhesive, which is conducive to heat dissipation. A grounding via is also provided at the position of the substrate 10 corresponding to the AFE chip 31, and the via is used to further enhance the heat dissipation effect.

[0062] In other embodiments of the present invention, the AFE chip 31 is packaged in a wafer-level chip package and connected to the pads on the front side of the substrate 10 through BGA solder joints. Compared with the wire bonding method, the AFE chip 31 packaged in a wafer-level chip package is larger in size.

[0063] In the embodiment of the utility model, in order to prevent signal interference, the interconnection line between the RF antenna module 40 and the MCU chip 21 is set to a non-turning line with uniform width, and a ground wrap design is adopted. The ground wrap design specifically refers to enclosing the connection between the RF antenna module and the corresponding pins of the MCU chip 21 through the via of the ground signal. The design of non-turning lines makes the routing distance short and straight. If the RF antenna module 40 is placed at other positions on the substrate, the connection line between the MCU chip is long and may need to turn, which is prone to signal interference loss, especially interference from high-frequency signals such as antenna WIFI.

[0064] In the embodiment of the utility model, the crystal oscillator module 50 includes a crystal oscillator and two filter capacitors, the two filter capacitors are arranged close to the crystal oscillator pins to maintain a short signal loop, and the entire crystal oscillator module 50 adopts a grounding design. The grounding design specifically refers to surrounding the entire crystal oscillator module 50 through vias of the ground signal.

[0065] In the embodiment of the utility model, the substrate 10 adopts a 6-layer stacked board structure, the first layer from the front to the back of the substrate 10 is provided with pads of various devices, the second layer is a digital signal and analog signal ground layer, the third and fourth layers are signal routing layers, the fifth layer is a digital power supply and analog power supply layer, and the sixth layer is provided with a solder ball array 11. Among them, the solder ball array design of the sixth layer can lead out more pins and provide more interfaces to the outside.

[0066] In the embodiment of the utility model, the VDD power module 60 is a 3.3V digital power supply, and the AVDD power module 70 is a 3V analog power supply. In practical applications, according to the needs of different chips and chip capacitor resistor devices 80, the connection lines between the chip and chip capacitor resistor device 80 and the VDD power module 60 and the AVDD power module 70 are designed.

[0067] In one embodiment of the utility model, the AFE chip 31 is connected to the substrate 10 by bonding wires, the size of the SiP package substrate is 8x8mm, the sixth layer of the substrate 10 from top to bottom is designed as a 9x9 solder ball array, the MCU main control module 20 is 500μm away from the left side margin of the substrate 10, the width of the MCU main control module 20 along the left and right directions of the substrate 10 is 4400um, the AFE module 30 is set at 600μm on the right side of the MCU main control module, the width of the AFE module 30 along the left and right directions of the substrate 10 is 2060um, the right side of the AFE module 30 is 440um away from the right side margin of the substrate 10, the RF antenna module 40 is set 300μm below the MCU chip 21, and the crystal oscillator module 50 is set 800μm above the MCU chip 21. After testing, the above layout structure and size can ensure signal transmission and normal product functions. Among them, when the distance between the RF antenna module 40 and the MCU chip 21 is less than 300μm, the process difficulty is relatively large, and when it is greater than 300μm, the signal loss is relatively large. After simulation and testing, the distance value of 300μm can meet the impedance matching requirements of the signal.

[0068] In the embodiment of the utility model, the sizes of the chip capacitor and resistor devices include 01005 and 0201. Among them, 01005 refers to a chip capacitor and resistor device with a length and width of 0.01 inches and 0.005 inches respectively, and 0201 refers to a chip capacitor and resistor device with a length and width of 0.02 inches and 0.01 inches respectively. In order to make the overall package size smaller, the embodiment of the utility model designs a new pad and solder mask structure for the chip capacitor and resistor devices of 01005 and 0201 sizes.

[0069] Traditional PCB chip capacitor and resistor device packaging is generally used for devices above 0201 size, such as Figure 3-5 As shown, the outermost portion is a package outline 91, and two solder pads 81 are arranged inside the package outline 91. The solder resist layer window 83 of the solder pad is square in design and is generally located in the middle position inside the solder pad 81. A solder resist layer 82 is arranged in the bridge between the two solder pads 81. There is no prohibited wiring area 84 in the bridge area between the two solder pads 81. The bridge area between the two solder pads 81 of some larger-sized devices can be used to set circuits.

[0070] The chip capacitor and resistor device packaging in the embodiment of the present invention is miniaturized, with a focus on small chip capacitor and resistor devices of sizes 01005 and 0201, where 01005 refers to a chip capacitor and resistor device with a length and width of 0.01 inches and 0.005 inches, respectively, and 0201 refers to a chip capacitor and resistor device with a length and width of 0.02 inches and 0.01 inches, respectively. The terminals of these devices are very small, and the solder mask layer in the bridging area in the middle of the pad of the traditional PCB board design structure can easily affect the welding quality. In order to make the overall package size smaller and the welding quality better, the embodiment of the present invention designs a new pad and solder mask layer structure for chip capacitor and resistor devices of sizes 01005 and 0201. First, relative to the PCB board design, the size of the pad 81 is reduced; at the same time, the square solder mask layer window 83 structure in the pad in the PCB board design is adjusted. Figure 6-8 As shown, the utility model designs the solder mask window 83 of the pad into a "wing-shaped" shape, and connects the square solder mask windows 83 in the two pads 81 and the bridge between the pads 81, forming a "wing-shaped" solder mask window 83 structure. Compared with the two independent solder mask windows 83 in the PCB board, the "wing-shaped" connected solder mask windows 83 can increase the flux volatilization channel during the welding process in the subsequent assembly welding process, avoid cold soldering, and improve the welding quality. At the same time, because the pad is smaller, in order to avoid the risk of bridging tin, a "wing-shaped" connected solder mask window 83 is set between the pads 81. Figure 7 The "I-shaped" forbidden wiring area 84 shown. In the embodiment of the utility model, for the chip capacitor and resistor devices of two sizes of 01005 and 0201, the package size, pad, solder mask window, and forbidden wiring area of ​​the chip device are shown in Table 1, where "before optimization" represents the traditional PCB board package design, and "after optimization" represents the design of the embodiment of the utility model. The meanings of the list items such as L, W, A, B, and C can be found in the attached Figure 3 , 4 , 6, 7 corresponding annotations:

[0071] Table 1: Package size design of chip SMD devices (unit: μm)

[0072]

[0073] It should be noted that in Table 1, the pad sizes corresponding to "A", "B" and "C" refer to the original pad sizes during design. For the SMD (Solder Mask Defined) pad definition method, the visible pad area after packaging is the solder mask window area on the pad.

[0074] It can be calculated from Table 1 that after the adjustment of the pad and the solder mask window in the embodiment of the utility model, the package size of the chip capacitor and resistor devices of models 0201 and 01005 is reduced to 81.4% and 62.6% of the original respectively. The above ratios are calculated based on the size data of the package outline 91.

[0075] In the system-level packaged ECG monitoring chip prepared by the embodiment scheme of the utility model, when the AFE chip is connected to the substrate through bonding wires, and except for some large-capacity capacitors that select 0201-type chip capacitor devices, the remaining chip capacitor and resistor devices are all 01005-type, the current of the ECG product is tested to be reduced from about 64mA to 10mA, which is about 15.6% of the original current. Taking into account different working modes, it is estimated that the power consumption can be reduced to about 30% of the original current. Compared with PCB assembled products, SIP packaged chips are used, and the total size of all functional modules such as the MCU main control module and the AFE module included in the SiP packaged chip is reduced from about 35X35mm to 8X8mm, and the size of the SiP packaged chip is about 5.2% of the original current. Considering the connectors, power input ports, etc. on the periphery of the SiP chip after packaging, it is estimated that the overall size of the ECG product can be reduced to about 25% of the original current.

[0076] The utility model proposes a system-level packaging structure for an ECG monitoring chip, which integrates various modules of ECG products through SiP technology. Specifically, the MCU main control module is set in the middle of the left side of the substrate, the AFE module, the RF antenna module, and the crystal oscillator module are respectively set on the right, bottom, and top of the MCU main control module, and the VDD power supply module and the AVDD power supply module are respectively set on the upper and lower sides of the AFE module, so that the connection between each module is the shortest, the layout is symmetrical and compact, and the pad size is reduced for chip capacitors and resistors, and the solder mask window design is optimized. The "wing-shaped" solder mask window and the "I-shaped" prohibited wiring area avoid the problems of cold soldering and tinning, and improve the welding quality. Compared with the traditional PCB design method, this solution significantly shortens the package size and internal signal path, thereby greatly reducing signal loss, ensuring high performance and high stability of signal transmission, and reducing the overall power consumption of the product, which is of great significance to promoting the development of wearable medical devices in the direction of lightness and flexibility.

[0077] The above are only specific implementation methods of the present invention, which cannot be used to limit the scope of the present invention. Equal changes made by ordinary technicians in this technical field based on this creation, as well as changes well known to technicians in this field, should still fall within the scope of the present invention.

Claims

1. A system-level packaging structure of an electrocardiogram monitoring chip, characterized in that: include: A substrate (10) comprising a front side and a back side arranged opposite to each other, the front side being provided with solder pads electrically connected to each module, and the back side being provided with a solder ball array (11); An MCU main control module (20) is arranged in the middle of the left side of the front side of the substrate (10), and the MCU main control module (20) comprises an MCU chip (21); An AFE module (30) is arranged on the right side of the MCU main control module (20), and the AFE module (30) comprises an AFE chip (31); An RF antenna module (40) is arranged below the MCU main control module (20); A crystal oscillator module (50) is arranged above the MCU main control module (20); A VDD power supply module (60), arranged above the AFE module (30), the VDD power supply module (60) providing digital power for each module; An AVDD power supply module (70) is arranged below the AFE module (30), and the AVDD power supply module (70) provides analog power for each module; The MCU main control module (20) and the AFE module (30) both include a plurality of chip capacitor and resistor components (80); The front side of the substrate (10) is provided with a pad group for electrically connecting the chip capacitor resistor device (80); each chip capacitor resistor device package corresponds to a pad group; each pad group includes two pads (81); the size of the pads (81) is smaller than the size of the pads (81) of the corresponding chip capacitor resistor device (80) on the PCB board; and interconnected solder resist layer openings (83) are provided in the pads (81) of each pad group and in the bridging area between the pads (81).

2. The electrocardiogram monitoring chip system-level packaging structure according to claim 1, characterized in that: A prohibited wiring area (84) is arranged between two pads (81) of each pad group of the chip type capacitor and resistor device package.

3. The electrocardiogram monitoring chip system-level packaging structure according to claim 1, characterized in that: The MCU chip (21) is packaged in a wafer-level chip packaging manner and is connected to a solder pad on the front side of the substrate (10) via a BGA solder point (211).

4. The electrocardiogram monitoring chip system-level packaging structure according to claim 1, characterized in that: The front side of the AFE chip (31) is connected to the pad on the front side of the substrate (10) via a bonding wire (32), and the back side is connected to the pad with a window on the front side of the substrate (10) via a heat dissipation adhesive (33).

5. The electrocardiogram monitoring chip system-level packaging structure according to claim 4, characterized in that: A grounding via is provided at a position of the substrate (10) corresponding to the AFE chip (31).

6. The electrocardiogram monitoring chip system-level packaging structure according to claim 1, characterized in that: The interconnection line between the RF antenna module (40) and the MCU chip (21) is set as a non-bending line with a uniform width, and adopts a ground-wrapped design.

7. The electrocardiogram monitoring chip system-level packaging structure according to claim 1, characterized in that: The crystal oscillator module (50) comprises a crystal oscillator and two filter capacitors. The two filter capacitors are arranged close to the crystal oscillator pins to maintain a shorter signal loop, and the entire crystal oscillator module (50) adopts a ground-enclosed design.

8. The electrocardiogram monitoring chip system-level packaging structure according to claim 1, characterized in that: The substrate (10) adopts a 6-layer stacked board structure, wherein the first layer from the front side to the back side of the substrate (10) is provided with solder pads of various devices, the second layer is a digital signal and analog signal grounding layer, the third layer and the fourth layer are signal routing layers, the fifth layer is a digital power supply layer and an analog power supply layer, and the sixth layer is provided with a solder ball array (11).

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