Hardware-in-the-loop test chip single board, test system and test bench
By designing hardware in-ring test chip boards, the problems of cumbersome operation, low testing efficiency and high cost when testing vehicle chargers in the existing technology are solved, and the effects of simplifying operations, improving testing efficiency and reducing testing costs are achieved.
Patent Information
- Application Number
- CN202420432319.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-06
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-03-06
AI Technical Summary
When testing vehicle-mounted chargers, existing hardware-in-loop testing equipment requires frequent design and replacement of tooling boards and wiring harnesses, resulting in cumbersome operation, low testing efficiency and high cost.
A hardware-in-ring test chip single board is designed, including a control chip and a plurality of first interfaces, and the type and arrangement order of the first interface matches the second interface of the hardware-in-ring test device. Through the wiring harness connection, multiple tests of the same type of control chip are realized without the need to redesign the tooling board and wiring harness.
The operation steps are simplified, the testing efficiency is improved, the testing cost is reduced, and the signal interference caused by the cross-harness is avoided, which improves the reliability and stability of signal transmission.
Smart Images
Figure CN222689773U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of testing, and in particular to a hardware-in-the-loop test chip single board, a test system and a test bench. Background Art
[0002] Currently, when using hardware-in-the-loop test equipment for testing, since the interface type of the hardware-in-the-loop test equipment is fixed, the product to be tested must match the interface of the hardware-in-the-loop test equipment.
[0003] Therefore, each on-board charger product needs to produce a tooling board and a wiring harness connected to the interface according to the control chip. Even products using the same chip need to produce different tooling boards and wiring harnesses. As the number of products to be tested increases, the number of tooling boards and wiring harnesses that need to be produced also increases.
[0004] As attached Figure 1 As shown, when using the hardware-in-the-loop test equipment for testing, one end of the wiring harness is connected to the chip interface on the product to be tested (i.e., the interface of the tooling board to be tested), and the other end of the wiring harness is matched and connected to the interface of the hardware-in-the-loop test equipment. Since the number and type of interfaces of the tooling board to be tested are large, the number of wiring harnesses that need to be connected is huge, resulting in cross-setting of the wiring harnesses connected to the interface of the tooling board to be tested and the interface of the hardware-in-the-loop test equipment; when replacing another product to be tested, even if it is a product to be tested using the same chip, because the number of interfaces and interface definitions are different, the tooling board needs to be redesigned, and the originally connected wiring harness needs to be removed, and then rearranged and connected to the new wiring harness, resulting in very cumbersome operation, low testing efficiency, and increased testing costs. Utility Model Content
[0005] In view of this, the utility model provides a hardware-in-the-loop test chip board, a test system and a test bench, which are used to solve the problems in the prior art that the operation of making tooling boards, wiring harnesses and wiring in testing on-board chargers with hardware-in-the-loop test equipment is very cumbersome, the test efficiency is low, and the test cost is high.
[0006] To achieve one or part or all of the above purposes or other purposes, the technical solution of the utility model is a hardware-in-the-loop test chip single board, including a tooling board, on which a control chip and a plurality of first interfaces connected to the control chip are provided, the hardware-in-the-loop test chip single board is connected to a hardware-in-the-loop test device having a plurality of second interfaces, wherein the interface type of the first interface is the same as the interface type of the second interface;
[0007] The interface type arrangement order of the plurality of first interfaces matches the interface type arrangement order of the second interfaces;
[0008] Each of the first interfaces is connected to the second interface whose interface type matches that of the first interface via a wiring harness.
[0009] Furthermore, the plurality of first interfaces are all located on the same side of the tooling plate and are arranged horizontally.
[0010] Furthermore, the interface type of the first interface includes one or more of a PWM_out interface, a PWM_in interface, a SCI interface, a CAN interface, an ADC interface, a DAC interface, an IO interface, a UART interface, an I2C interface, a VCC interface or a GND interface.
[0011] The utility model also provides a hardware-in-the-loop test system, including a hardware-in-the-loop test device, a controller and a hardware-in-the-loop test chip board as described above, wherein the hardware-in-the-loop test device is connected to the hardware-in-the-loop test chip board via a wiring harness, and the hardware-in-the-loop test device receives a test program sent by the controller to test the hardware-in-the-loop test chip board.
[0012] The utility model also provides a hardware-in-the-loop test bench, comprising the hardware-in-the-loop test system as described above.
[0013] Compared with the prior art, the utility model has at least the following beneficial effects:
[0014] The utility model connects all interfaces of the control chip and connects them to the first interface corresponding to the tooling board, and at this time, the interface type arrangement order of the first interface on the tooling board can be correspondingly set according to the interface type arrangement order of the second interface of the hardware-in-the-loop test equipment. It is designed as a hardware-in-the-loop test chip single board specifically for testing the same type of control chip. In this way, when testing different products of the same type of control chip, there is no need to redesign the tooling board, the wiring harness, and rewire the second interface. As long as the program in the control chip on the hardware-in-the-loop test chip single board is updated, it can be reused many times. In this way, products of the same type of control chip but different projects can also use the same hardware-in-the-loop test chip single board. In this way, the hardware-in-the-loop test chip single board proposed by the utility model can simplify the operating steps, improve the test efficiency, and reduce the test cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present invention; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order.
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0017] Figure 1 It is a schematic diagram of the interface connection between the existing hardware-in-the-loop test equipment and the product to be tested in the background technology;
[0018] Figure 2 A schematic diagram of the interface connection between a hardware-in-the-loop test chip board and a hardware-in-the-loop test device provided in one embodiment of the utility model;
[0019] Figure 3 A schematic diagram of an interface connection between a hardware-in-the-loop test chip board and a hardware-in-the-loop test device provided by another embodiment of the present invention;
[0020] Figure 4 A schematic diagram of the interface connection between a hardware-in-the-loop test chip board and a hardware-in-the-loop test device provided in yet another embodiment of the present invention.
[0021] Reference numerals:
[0022] 1. Tooling board;
[0023] 10. First interface;
[0024] 101, PWM_out interface; 102, PWM_in interface; 103, SCI interface; 104, CAN interface; 105, ADC interface; 106, DAC interface; 107, IO interface; 108, UART interface; 109, I2C interface; 110, VCC interface; 111, GND interface;
[0025] 2. Hardware-in-the-loop test equipment;
[0026] 20. Second interface. DETAILED DESCRIPTION
[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model. Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the utility model, rather than implying that each embodiment of the utility model must have the described features. In addition, it should be noted that this specification describes many features. Although certain features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.
[0028] The principle and structure of the present utility model are described in detail below with reference to the accompanying drawings and embodiments.
[0029] In view of the problems that the existing hardware-in-the-loop test equipment 2 is very cumbersome to operate, has low test efficiency and high test cost, and in order to break through the hardware limitations of the hardware-in-the-loop test equipment 2, the utility model divides the hardware-in-the-loop test chip board (the English name of the hardware-in-the-loop is Hardware in the Loop, abbreviated as HIL, the same in the whole text) according to the model of the control chip, and makes a special hardware-in-the-loop test chip board for each model of the control chip, so as to realize the testing of multiple products (the product is the control chip used in the on-board charger, the same in the whole text) on the hardware-in-the-loop test chip board of the same model of the control chip, without resetting and replacing the new tooling board 1, wiring harness and wiring. And the hardware-in-the-loop test chip board, test system and test bench proposed by the utility model are used to test the control chip in the on-board charger.
[0030] Therefore, refer to the attached Figure 2 The utility model proposes a hardware-in-the-loop test chip single board, including a tooling board 1, on which a control chip (not shown, the same throughout the text) and a plurality of first interfaces 10 connected to the control chip are provided. The hardware-in-the-loop test chip single board is connected to a hardware-in-the-loop test device 2 having a plurality of second interfaces 20, wherein the interface type of the first interface 10 is the same as the interface type of the second interface 20.
[0031] The interface type arrangement order of the plurality of first interfaces 10 matches the interface type arrangement order of the second interface 20 of the hardware-in-the-loop testing device 2 .
[0032] Each first interface 10 is connected to a second interface 20 whose interface type matches that of the first interface 10 via a wiring harness.
[0033] Among them, all interfaces of the control chip are connected to the corresponding first interface 10, and at this time, the interface type arrangement order of the first interface 10 on the tooling board 1 can be set according to the interface type arrangement order of the second interface 20 of the hardware-in-the-loop test device 2, and it is designed to be a hardware-in-the-loop test chip single board that specifically provides the same type of control chip for testing. In this way, when testing different products of the same type of control chip, there is no need to redesign the tooling board 1, the wiring harness, and reconnect the second interface 20. As long as the program in the control chip on the hardware-in-the-loop test chip single board is updated, it can be reused many times. In this way, products of the same type of control chip but different projects can also use the same hardware-in-the-loop test chip single board, and only the program in the control chip needs to be updated to achieve automated testing. In this way, the hardware-in-the-loop test chip single board proposed by the utility model can simplify the operating steps, improve test efficiency, and reduce test costs.
[0034] Each first interface 10 is connected to the second interface 20 corresponding to the hardware-in-the-loop test equipment 2 through a wiring harness, and no two wiring harnesses cross each other, which can avoid signal interference and thereby improve the reliability and stability of signal transmission within the wiring harness; ensure the safety of the wiring harness and prevent friction and entanglement of crossed wiring harnesses, which may lead to damage or short circuit of the wiring harness; and facilitate maintenance and management; non-crossed wiring harnesses can make the lines clearer, neater, and easier to identify and manage.
[0035] In one embodiment, in order to facilitate the management and connection of the first interfaces 10 on the tooling board 1 , the plurality of first interfaces 10 are located on the same side of the tooling board 1 and are arranged horizontally.
[0036] Of course, in other embodiments, when the number of first interfaces 10 is too large and not all of the first interfaces 10 can be fully placed on the same side of the tooling board 1, the first interfaces can be set along the edges of the remaining sides of the tooling board 1, and it is no longer necessary to place all of the first interfaces 10 on the same side.
[0037] In a specific embodiment, referring to the attached Figure 2-4 The interface type of the first interface 10 includes one or more of a PWM_out interface 101, a PWM_in interface 102, a SCI interface 103, a CAN interface 104, an ADC interface 105, a DAC interface 106, an IO interface 107, a UART interface 108, an I2C interface 109, a VCC interface 110 or a GND interface 111.
[0038] The PWM_out interface 101 is used to determine whether the control chip can send a first PWM voltage signal to the hardware-in-the-loop test device 2 .
[0039] The PWM_in interface 102 is used to determine whether the control chip can receive the second PWM voltage signal sent by the hardware-in-the-loop test device 2 .
[0040] The SCI interface 103 is used to determine whether the communication function and performance of the control chip are normal.
[0041] The CAN interface 104 is used to determine whether the communication protocol and data transmission function between the control chip and other vehicle-mounted electronic devices are normal.
[0042] The ADC interface 105 is used to determine whether the analog signal output by the control chip to the hardware-in-the-loop test device 2 is normal.
[0043] The DAC interface 106 is used to determine whether the digital signal output by the hardware-in-the-loop test device 2 for controlling chip sampling is normal.
[0044] The IO interface 107 is used to determine whether the input / output signal function of the control chip is normal.
[0045] The UART interface 108 is used to determine whether the communication protocol and data transmission function between the control chip and other devices are normal.
[0046] The I2C interface 109 is used to determine whether the communication and data transmission between the control chip and the external device are normal.
[0047] The VCC interface 110 is used to determine whether the power supply voltage of the control chip is normal.
[0048] The GND interface 111 is used to determine whether the impedance and connection status of the ground line of the control chip are normal.
[0049] In this way, the host computer can obtain the status of the hardware-in-the-loop test chip board connected to the hardware-in-the-loop test device 2 from the hardware-in-the-loop test device 2, specifically:
[0050] Through the PWM_out interface 101, it is obtained whether the control chip in the hardware-in-the-loop test chip board can send the first PWM voltage signal to the hardware-in-the-loop test device 2; through the PWM_in interface 102, it is obtained whether the control chip in the hardware-in-the-loop test chip board can receive the second PWM voltage signal sent by the hardware-in-the-loop test device 2; through the SCI interface 103, it is obtained whether the communication function and performance of the control chip in the hardware-in-the-loop test chip board are operating normally; through the CAN interface 104, it is obtained whether the communication protocol and data transmission function between the control chip in the hardware-in-the-loop test chip board and other on-board electronic devices are operating normally; through the ADC interface 105, it is obtained whether the control chip in the hardware-in-the-loop test chip board can normally output analog signals to the hardware-in-the-loop test device 2; through the DAC interface 1 06 to obtain whether the digital signal sampled by the hardware-in-the-loop test device 2 output by the control chip in the hardware-in-the-loop test chip board is normal; through the IO interface 107 to obtain whether the control chip in the hardware-in-the-loop test chip board can input / output signals normally; through the UART interface 108 to obtain whether the communication protocol and data transmission function between the control chip in the hardware-in-the-loop test chip board and other devices are running normally; through the I2C interface 109 to obtain whether the communication and data transmission function between the control chip in the hardware-in-the-loop test chip board and external devices are running normally; through the VCC interface 110 to obtain whether the power supply voltage of the control chip in the hardware-in-the-loop test chip board is normal; through the GND interface 111 to obtain whether the impedance and connection status of the ground line of the control chip in the hardware-in-the-loop test chip board are normal.
[0051] In this embodiment, one PWM_out interface 101, one PWM_in interface 102, one SCI interface 103, one CAN interface 104, one ADC interface 105, one DAC interface 106, one IO interface 107, one UART interface 108, one I2C interface 109, one VCC interface 110 or one GND interface 111 are used as examples. Of course, the PWM_out interface 101, the PWM_in interface 102, the SCI interface 103, the CAN interface 104, the ADC interface 105, the DAC interface 106, the IO interface 107, the UART interface 108, the I2C interface 109, the VCC interface 110 or the GND interface 111 can be set to two or more respectively according to actual conditions, which is not limited here.
[0052] The first interface 10 and the second interface 20 match each other specifically referring to:
[0053] 1. Reference Figure 2A PWM_out interface 101, a PWM_in interface 102, a SCI interface 103, a CAN interface 104, an ADC interface 105, a DAC interface 106 and an IO interface 107 are sequentially provided on the hardware-in-the-loop test chip board; the hardware-in-the-loop test device 2 is also correspondingly provided with a PWM_out interface, a PWM_in interface, a SCI interface, a CAN interface, an ADC interface, a DAC interface and an IO interface; then the PWM_out interface 101 is connected to the PWM_in interface correspondingly, the PWM_in interface 102 is connected to the PWM_in interface correspondingly, the SCI interface 103 is connected to the SCI interface correspondingly, the CAN interface 104 is connected to the CAN interface correspondingly, the ADC interface 105 is connected to the ADC interface correspondingly, the DAC interface 106 is connected to the DAC interface correspondingly, and the IO interface 107 is connected to the IO interface correspondingly.
[0054] 2. Reference Figure 4 The hardware-in-the-loop test chip board is provided with a PWM_out interface 101, a PWM_in interface 102, an SCI interface 103, a CAN interface 104, an ADC interface 105, a DAC interface 106, an IO interface 107, a UART interface 108, an I2C interface 109, a VCC interface 110 and a GND interface 111; the hardware-in-the-loop test device 2 is also provided with a PWM_out interface, a PWM_in interface, a SCI interface, a CAN interface, an ADC interface, a DAC interface, an IO interface, a UART interface, an I2C interface, a VCC interface 110 and a GND interface 111. CC interface and a GND interface; then the PWM_out interface 101 is connected to the PWM_in interface accordingly, the PWM_in interface 102 is connected to the PWM_in interface accordingly, the SCI interface 103 is connected to the SCI interface accordingly, the CAN interface 104 is connected to the CAN interface accordingly, the ADC interface 105 is connected to the ADC interface accordingly, the DAC interface 106 is connected to the DAC interface accordingly, the IO interface 107 is connected to the IO interface accordingly, the UART interface 108 is connected to the UART interface 108 accordingly, the I2C interface 109 is connected to the I2C interface accordingly, the VCC interface 110 is connected to the VCC interface accordingly, and the GND interface 111 is connected to the GND interface accordingly.
[0055] Of course, in other embodiments (not shown in the figure), the types of the first interface 10 also include interfaces such as LIN interface, GPIO interface and PCIE interface. The LIN interface is used to determine whether the communication protocol, data transmission rate, data integrity and other indicators of the LIN interface of the control chip in the hardware-in-the-loop test chip board are normal, so as to ensure that it can achieve reliable communication; the GPIO interface is used to determine whether the control and monitoring functions of the GPIO interface of the control chip in the hardware-in-the-loop test chip board are operating normally, including input and output functions, interrupt functions, etc.; the PCIE interface is used to determine whether the high-speed data transmission function of the PCIE interface of the control chip in the hardware-in-the-loop test chip board is operating normally, so as to ensure that it can achieve high-speed data transmission.
[0056] In one embodiment, the utility model also proposes a hardware-in-the-loop test system, including a hardware-in-the-loop test device 2, a controller, and a hardware-in-the-loop test chip board as described above, wherein the hardware-in-the-loop test device 2 is connected to the hardware-in-the-loop test chip board via a wiring harness, and the hardware-in-the-loop test device receives a test program sent by the controller to test the hardware-in-the-loop test chip board.
[0057] The controller is used to start the hardware-in-the-loop test device 2 and enable the hardware-in-the-loop test device 2 to start determining whether the function of the first interface 10 of the hardware-in-the-loop test chip board can operate normally.
[0058] In one embodiment, the present invention further provides a hardware-in-the-loop test bench, comprising the hardware-in-the-loop test system as described above.
[0059] Obviously, the embodiments described above are only some embodiments of the utility model, rather than all embodiments. The preferred embodiments of the utility model are given in the accompanying drawings, but they do not limit the patent scope of the utility model. The utility model can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the utility model more thorough and comprehensive. Although the utility model is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to replace some of the technical features therein with equivalents. Any equivalent structure made using the contents of the utility model specification and the accompanying drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the utility model.
Claims
1. A hardware-in-the-loop test chip board, characterized in that: Comprising a tooling board (1), the tooling board (1) being provided with a control chip and a plurality of first interfaces (10) connected to the control chip, the hardware-in-the-loop test chip board being connected to a hardware-in-the-loop test device having a plurality of second interfaces, wherein the interface type of the first interface (10) is the same as the interface type of the second interface; The interface type arrangement order of the plurality of first interfaces (10) matches the interface type arrangement order of the second interfaces; Each of the first interfaces (10) is connected to the second interface of a type matching the interface of the first interface (10) via a wiring harness.
2. The hardware-in-the-loop test chip board according to claim 1, characterized in that: The plurality of first interfaces (10) are all located on the same side of the tooling plate (1) and are arranged horizontally.
3. The hardware-in-the-loop test chip board according to claim 1, characterized in that: The interface type of the first interface (10) comprises one or more of a PWM_out interface (101), a PWM_in interface (102), an SCI interface (103), a CAN interface (104), an ADC interface (105), a DAC interface (106), an IO interface (107), a UART interface (108), an I2C interface (109), a VCC interface (110), or a GND interface (111).
4. A hardware-in-the-loop test system, characterized in that: The method comprises a hardware-in-the-loop test device, a controller and a hardware-in-the-loop test chip board according to any one of claims 1 to 3, wherein the hardware-in-the-loop test device is connected to the hardware-in-the-loop test chip board via a wiring harness. The controller is used to send a test program to the hardware-in-the-loop test device to test the hardware-in-the-loop test chip board.
5. A hardware-in-the-loop test bench, characterized in that: Comprising the hardware-in-the-loop testing system as described in claim 4.