Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device, the array substrate comprises a substrate and a first insulating layer arranged on the substrate, and the first insulating layer is provided with a first opening corresponding to a drain electrode and a second opening corresponding to a touch wire; a flat layer arranged on the first insulating layer, wherein the flat layer is provided with a third opening corresponding to the first opening and a fourth opening corresponding to the second opening; the pixel electrodes are arranged above the flat layer, the guide connection electrodes correspond to the second open holes, the pixel electrodes are electrically connected with the corresponding drain electrodes through the first open holes and the third open holes, and the guide connection electrodes are electrically connected with the corresponding touch control wires through the second open holes and the fourth open holes; the second insulating layer is arranged above the flat layer and covers the pixel electrode and the conductive connection electrode, and the second insulating layer is provided with a fifth opening corresponding to the conductive connection electrode; and a plurality of common electrode blocks arranged above the second insulating layer, wherein the common electrode blocks are electrically connected with the corresponding conductive connection electrodes through the fifth holes.

Description

Technical Field

[0001] The utility model relates to the technical field of displays, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Liquid crystal display panels have the advantages of good image quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and they dominate the field of flat panel displays. With the rapid development of display technology, touch display panels have been widely accepted and used by people, such as smart phones and tablet computers. Touch display panels use embedded touch technology to combine touch panels and liquid crystal display panels into one, and embed the touch panel function into the liquid crystal display panel, so that the liquid crystal display panel has the functions of displaying and sensing touch input at the same time.

[0003] According to the different ways in which the touch sensing layer is set in the display panel, the touch display panel is divided into add-on mode, in-cell and on-cell structures. The in-cell touch screen integrates the touch function into the display screen, which can effectively reduce the thickness of the entire display and simplify the production process, making the product thinner and lighter, and the production cost is lower, thus it is widely popular. At present, for the in-cell touch screen, the touch screen structure is usually set directly on the array substrate, mainly in the array substrate, some structural components used to transmit the display signal are reused as touch electrodes, and the more common is to reuse the common electrode block as the touch electrode. Figure 1 is a schematic diagram of the planar structure of a common electrode block in the prior art, Figure 2 is a schematic diagram of a cross-sectional structure of an array substrate in the prior art, such as Figure 1 and Figure 2 As shown, the array substrate needs to be provided with not only scan lines and data lines 131, but also touch lines 134, and then common signals and touch signals are transmitted to the common electrode block 151 through the touch lines 134. The data lines 131, the source electrodes 132, the drain electrodes 133 and the touch lines 134 need to be covered with a first insulating layer 102, and then covered with a flat layer 103 to flatten the array substrate. The common electrode block 151 and the pixel electrode 141 are arranged above the flat layer 103 and are separated from each other by the second insulating layer 104. The first insulating layer 102 and the planar layer 103 both need to be processed with openings at the corresponding drain electrode 133 to form a first contact hole TH1, and the pixel electrode 141 is connected to the drain electrode 133 through the first contact hole TH1; the first insulating layer 102 and the second insulating layer 104 both need to be processed with openings at the corresponding touch wiring 134 to form a second contact hole TH2, and the common electrode block 151 is connected to the corresponding touch wiring 134 through the second contact hole TH2.

[0004] Figure 3 is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer and the second insulating layer at the second contact hole in the prior art, Figure 4 is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer, the second insulating layer and the common electrode block at the second contact hole in the prior art, such as Figure 3 and Figure 4 As shown, in order to prevent the pixel electrode 141 and the common electrode block 151 from breaking at the opening of the contact hole, the first insulating layer 102 and the second insulating layer 104 usually include an insulating material layer 1 and a slope modification layer 2, and the slope modification layer 2 is stacked on the insulating material layer 1, and the etching rate of the slope modification layer 2 (etching rate of about 24000A / min) is greater than the etching rate of the insulating material layer 1 (etching rate of about 12000A / min), so that the slope at the opening of the contact hole can be reduced. However, since the first insulating layer 102 and the second insulating layer 104 need to be opened at the corresponding touch wiring 134, an under cut phenomenon will occur between the first insulating layer 102 and the second insulating layer 104, which may easily cause the common electrode block 151 to break on the inner wall of the second contact hole TH2, causing abnormal lighting of the product. Utility Model Content

[0005] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present invention is to provide an array substrate, a display panel, and a display device to solve the problem in the prior art that the common electrode block is prone to breakage in the contact hole in contact with the touch wiring.

[0006] The purpose of the utility model is achieved through the following technical solutions:

[0007] The utility model provides an array substrate, comprising:

[0008] substrate;

[0009] A first metal layer, the first metal layer is disposed above the substrate, the first metal layer comprises a scan line and a gate, and the gate is conductively connected to the scan line;

[0010] a gate insulating layer, the gate insulating layer being disposed above the first metal layer and covering the scan line and the gate;

[0011] A semiconductor layer, the semiconductor layer is disposed above the gate insulating layer, and the semiconductor layer includes an active layer corresponding to the gate;

[0012] a second metal layer, the second metal layer being disposed above the gate insulating layer and the semiconductor layer, the second metal layer comprising a data line, a source electrode, a drain electrode and a touch line, the data line being conductively connected to the source electrode, the source electrode being conductively connected to the drain electrode through the active layer, the touch line being parallel to the data line and being arranged alternately, and a plurality of the scan lines being insulated from and crossed by the plurality of the data lines to form a plurality of pixel units;

[0013] A first insulating layer, the first insulating layer is disposed above the second metal layer and covers the data line, the source electrode, the drain electrode, the touch line and the active layer, the first insulating layer is provided with a first opening corresponding to the drain electrode and a second opening corresponding to the touch line;

[0014] a planar layer, the planar layer being disposed above the first insulating layer, the planar layer being provided with a third opening corresponding to the first opening and a fourth opening corresponding to the second opening;

[0015] a first transparent conductive layer, the first transparent conductive layer being disposed above the planar layer, the first transparent conductive layer comprising a pixel electrode corresponding to the pixel unit and a conducting electrode corresponding to the second opening, the pixel electrode being electrically connected to the corresponding drain electrode through the first opening and the third opening, and the conducting electrode being electrically connected to the corresponding touch control trace through the second opening and the fourth opening;

[0016] a second insulating layer, the second insulating layer being disposed above the planar layer and covering the pixel electrode and the conducting electrode, the second insulating layer being provided with a fifth opening corresponding to the conducting electrode;

[0017] A second transparent conductive layer is provided on the second insulating layer, and the second transparent conductive layer comprises a plurality of patterned common electrode blocks, and the common electrode blocks are electrically connected to the corresponding conducting electrodes through the fifth openings.

[0018] Furthermore, the first insulating layer and the second insulating layer both include an insulating material layer and a slope modification layer which are stacked on each other, the slope modification layer of the first insulating layer is stacked on a side of the insulating material layer of the first insulating layer away from the substrate, and the slope modification layer of the second insulating layer is stacked on a side of the insulating material layer of the second insulating layer away from the substrate.

[0019] Furthermore, the first insulating layer is an insulating material layer, the second insulating layer includes an insulating material layer and a slope modification layer, and the slope modification layer of the second insulating layer is stacked on a side of the insulating material layer of the second insulating layer away from the substrate;

[0020] The hole wall slope of the third opening is smaller than the hole wall slope of the first opening, and the edge of the first opening is covered by the flat layer; the hole wall slope of the fourth opening is smaller than the hole wall slope of the second opening, and the edge of the second opening is covered by the flat layer.

[0021] The present application also provides an array substrate, comprising:

[0022] substrate;

[0023] A first metal layer, the first metal layer is disposed above the substrate, the first metal layer comprises a scan line and a gate, and the gate is conductively connected to the scan line;

[0024] a gate insulating layer, the gate insulating layer being disposed above the first metal layer and covering the scan line and the gate;

[0025] A semiconductor layer, the semiconductor layer is disposed above the gate insulating layer, and the semiconductor layer includes an active layer corresponding to the gate;

[0026] a second metal layer, the second metal layer being disposed above the gate insulating layer and the semiconductor layer, the second metal layer comprising a data line, a source electrode, a drain electrode and a touch line, the data line being conductively connected to the source electrode, the source electrode being conductively connected to the drain electrode through the active layer, the touch line being parallel to the data line and being arranged alternately, and a plurality of the scan lines being insulated from and crossed by the plurality of the data lines to form a plurality of pixel units;

[0027] A first insulating layer, the first insulating layer is disposed above the second metal layer and covers the data line, the source electrode, the drain electrode, the touch line and the active layer, the first insulating layer is an insulating material layer, and the first insulating layer is provided with a first opening corresponding to the drain electrode and a second opening corresponding to the touch line;

[0028] a flat layer, the flat layer being disposed above the first insulating layer, the flat layer being provided with a third opening corresponding to the first opening and a fourth opening corresponding to the second opening, the wall slope of the third opening being smaller than the wall slope of the first opening, and the edge of the first opening being covered by the flat layer;

[0029] a first transparent conductive layer, wherein the first transparent conductive layer is disposed above the planar layer, and the first transparent conductive layer comprises a pixel electrode corresponding to the pixel unit, and the pixel electrode is electrically connected to the corresponding drain electrode through the first opening and the third opening;

[0030] a second insulating layer, the second insulating layer being disposed above the planar layer and covering the pixel electrode, the second insulating layer being provided with a fifth opening corresponding to the second opening;

[0031] A second transparent conductive layer is provided on the second insulating layer, the second transparent conductive layer comprises a plurality of patterned common electrode blocks, and the common electrode blocks are electrically connected to the corresponding touch control traces through the second opening and the fifth opening.

[0032] Furthermore, the second insulating layer includes an insulating material layer and a slope modification layer which are stacked on each other, and the slope modification layer of the second insulating layer is stacked on a side of the insulating material layer of the second insulating layer away from the substrate.

[0033] Further, the central axis of the third opening is located on the same straight line as the central axis of the first opening, and all edges of the first opening are covered by the flat layer;

[0034] Or the central axis of the third opening is offset from the central axis of the first opening, and a portion of the edge of the first opening is covered by the flat layer.

[0035] Furthermore, the slope of the hole wall of the fourth opening is smaller than the slope of the hole wall of the second opening, and the edge of the second opening is covered by the flat layer.

[0036] Further, the central axis of the fourth opening is located on the same straight line as the central axis of the second opening, and all edges of the second opening are covered by the flat layer;

[0037] Or the central axis of the fourth opening is offset from the central axis of the second opening, and a portion of the edge of the second opening is covered by the flat layer.

[0038] The present application also provides a display panel, comprising an array substrate, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate, characterized in that the array substrate adopts the array substrate described above.

[0039] The present application also provides a display device, comprising the display panel as claimed in the above claims.

[0040] Beneficial effects of the utility model:

[0041] By forming a pixel electrode and a conducting electrode corresponding to the second opening in the first transparent conductive layer, the conducting electrode can cover the second opening, and the common electrode block is electrically connected to the touch line through the conducting electrode, thereby avoiding the bottom cutting phenomenon between the first insulating layer and the second insulating layer, and preventing the common electrode block from being easily broken in the contact hole contacting the touch line; moreover, the conducting electrode and the pixel electrode are both etched from the first transparent conductive layer, and basically no additional manufacturing process is added. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the planar structure of a common electrode block in the prior art;

[0043] Figure 2 is a schematic diagram of a cross-sectional structure of an array substrate in the prior art;

[0044] Figure 3 is a schematic diagram of the cross-sectional structure of a touch wiring, a first insulating layer, and a second insulating layer at a second contact hole in the prior art;

[0045] Figure 4 It is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer, the second insulating layer and the common electrode block at the second contact hole in the prior art;

[0046] Figure 5 is a schematic diagram of the cross-sectional structure of the array substrate in the first embodiment of the utility model;

[0047] Figure 6 It is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer, the conducting electrode, the second insulating layer and the common electrode block at the second contact hole in the first embodiment of the utility model;

[0048] Figure 7a-7h It is a schematic diagram of the process flow of the array substrate in the first embodiment of the utility model;

[0049] Figure 8 is a schematic diagram of the cross-sectional structure of the array substrate in the second embodiment of the present utility model;

[0050] Fig. 9 is a schematic diagram of the cross-sectional structure of the drain electrode, the first insulating layer, the second insulating layer and the pixel electrode at the first contact hole in the second embodiment of the present utility model;

[0051] Fig.10 is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer, the second insulating layer and the common electrode block at the second contact hole in the second embodiment of the present utility model;

[0052] Fig.11 It is a schematic diagram of the structure of the display device in the utility model when it is in a dark state;

[0053] Fig.12 It is a structural schematic diagram of the display device in the utility model when it is in a bright state. DETAILED DESCRIPTION

[0054] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the present invention, the specific implementation methods, structures, features and effects of the array substrate, display panel and display device proposed by the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments:

[0055] [Example 1]

[0056] Figure 5 is a schematic diagram of the cross-sectional structure of the array substrate in the first embodiment of the utility model, Figure 6 : is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer, the conductive electrode, the second insulating layer and the common electrode block at the second contact hole in the first embodiment of the present utility model, such as Figure 5 and Figure 6 As shown, an array substrate provided in Embodiment 1 of the present invention includes:

[0057] The substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0058] A first metal layer 11 is provided on the substrate 10, and the first metal layer 11 includes a scan line and a gate 111, and the gate 111 is conductively connected to the scan line. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0059] The gate insulating layer 101 is disposed above the first metal layer 11 and covers the scan line and the gate 111. The gate insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0060] The semiconductor layer 12 is disposed above the gate insulating layer 101 , and includes an active layer 121 corresponding to the gate 111 .

[0061] The second metal layer 13 is disposed above the gate insulating layer 101 and the semiconductor layer 12. The second metal layer 13 includes a data line 131, a source electrode 132, a drain electrode 133, and a touch line 134. The data line 131 is conductively connected to the source electrode 132, the source electrode 132 is conductively connected to the drain electrode 133 through the active layer 121, the touch line 134 and the data line 131 are parallel to each other and arranged alternately, and a plurality of scanning lines and a plurality of data lines 131 are insulated from each other and cross-defined to form a plurality of pixel units. The second metal layer 131 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0062] A first insulating layer 102 is disposed above the second metal layer 13 and covers the data line 131, the source 132, the drain 133, the touch wiring 134 and the active layer 121. The first insulating layer 102 is provided with a first opening 102a corresponding to the drain 133 and a second opening 102b corresponding to the touch wiring 134. The drain 133 is exposed from the first opening 102a, and the touch wiring 134 is exposed from the second opening 102b.

[0063] The flat layer 103 is disposed on the first insulating layer 102. The flat layer 103 is provided with a third opening 103a corresponding to the first opening 102a and a fourth opening 103b corresponding to the second opening 102b. The first opening 102a and the third opening 103a together form a first contact hole TH1. The second opening 102b and the fourth opening 103b together form a second contact hole TH2. The drain 133 is exposed from the first contact hole TH1, and the touch wiring 134 is exposed from the second contact hole TH2. Optionally, the size of the third opening 103a is larger than the size of the first opening 102a, so that the first opening 102a is completely exposed from the third opening 103a; the size of the fourth opening 103b is larger than the size of the second opening 102b, so that the second opening 102b is completely exposed from the fourth opening 103b.

[0064] like Figure 6 As shown, in this embodiment, the first insulating layer 102 includes an insulating material layer 1 and a slope modification layer 2 which are stacked on each other, and the slope modification layer 2 of the first insulating layer 102 is stacked on the side of the insulating material layer 1 of the first insulating layer 102 away from the substrate 10. The insulating material layer 1 and the slope modification layer 2 are made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, but the etching rate of the slope modification layer 2 (etching rate of about 24000A / min) is greater than the etching rate of the insulating material layer 1 (etching rate of about 12000A / min), for example, the etching rate of the slope modification layer 2 is twice that of the insulating material layer 1, so that chamfers are formed at the openings of the first opening 102a and the second opening 102b to reduce the slope of the inner wall of the hole, thereby avoiding the problem of the pixel electrode 141 being broken in the first opening 102a.

[0065] Of course, in another embodiment, the first insulating layer 102 may also be only the insulating material layer 1, that is, the first insulating layer 102 does not need to be provided with the slope modification layer 2. The hole wall slope of the third opening 103a is smaller than the hole wall slope of the first opening 102a, and the edge of the first opening 102a is covered by the flat layer 103. It can be understood that the first opening 102a is not completely covered by the flat layer 103, but only the edge is covered by the flat layer 103; the hole wall slope of the fourth opening 103b is smaller than the hole wall slope of the second opening 102b, the central axis of the fourth opening 103b is staggered with the central axis of the second opening 102b, and the edge of the second opening 102b is covered by the flat layer 103. It can be understood that the second opening 102b is not completely covered by the flat layer 103, but only the edge is covered by the flat layer 103. Thus, by setting a flat layer 103 with a relatively gentle hole wall slope to extend into the first opening 102a and the second opening 102b, the pixel electrode 141 in the first opening 102a and the conductive electrode 142 in the second opening 102b can be prevented from being broken. Wherein, the edge of the first opening 102a can be partially covered by the flat layer 103, and the central axis of the third opening 103a is staggered with the central axis of the first opening 102a; or all the edges of the first opening 102a are covered by the flat layer 103, and the central axis of the third opening 103a is located on the same straight line as the central axis of the first opening 102a. The edge of the second opening 102b is partially covered by the flat layer 103, and the central axis of the fourth opening 103b is staggered with the central axis of the second opening 102b; or all the edges of the second opening 102b are covered by the flat layer 103, and the central axis of the fourth opening 103b is located on the same straight line as the central axis of the second opening 102b.

[0066] The first transparent conductive layer 14 is disposed above the flat layer 103. The first transparent conductive layer 14 includes a pixel electrode 141 corresponding to the pixel unit and a conductive electrode 142 corresponding to the second opening 102b. The pixel electrode 141 is electrically connected to the corresponding drain electrode 133 through the first contact hole TH1 (the first opening 102a and the third opening 103a), and the conductive electrode 142 is electrically connected to the corresponding touch wiring 134 through the second contact hole TH2 (the second opening 102b and the fourth opening 103b). The pixel electrode 151 is a block electrode corresponding to the pixel unit, and the conductive electrode 142 is a block electrode corresponding to the second opening 102b. The material of the first transparent conductive layer 14 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0067] The second insulating layer 104 is disposed on the planar layer 103 and covers the pixel electrode 141 and the conductive electrode 142. The second insulating layer 104 is provided with a fifth opening 104a corresponding to the conductive electrode 142. The conductive electrode 142 is exposed from the fifth opening 104a. Figure 6 As shown, the second insulating layer 104 includes an insulating material layer 1 and a slope modification layer 2 which are stacked on each other, and the slope modification layer 2 of the second insulating layer 104 is stacked on the side of the insulating material layer 1 of the second insulating layer 104 away from the substrate 10. The material of the second insulating layer 104 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, but the etching rate of the slope modification layer 2 (etching rate of about 24000A / min) is greater than the etching rate of the insulating material layer 1 (etching rate of about 12000A / min), for example, the etching rate of the slope modification layer 2 is twice that of the insulating material layer 1, so that a chamfer is formed at the opening of the fifth opening 104a to reduce the slope of the inner wall of the hole, thereby avoiding the problem of the common electrode block 151 being broken in the fifth opening 104a.

[0068] The second transparent conductive layer 15 is disposed above the second insulating layer 104. The second transparent conductive layer 15 includes a plurality of patterned common electrode blocks 151. Each common electrode block 151 is electrically connected to the corresponding conductive electrode 142 through the corresponding fifth opening 104a, that is, the common electrode block 151 is electrically connected to the corresponding touch wiring 134 through the conductive electrode 142. The common signal and the touch signal are applied to the common electrode block 151 through the touch wiring 134, so that the common electrode block 151 is reused as a touch electrode. The common electrode block 151 is a slit electrode with a plurality of electrode strips in the area corresponding to the pixel electrode 141. The material of the second transparent conductive layer 15 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0069] Among them, the central axis of the fifth opening 104a is offset from the central axis of the second opening 102b. In the projection direction of the substrate 10, the second opening 102b partially overlaps with the second insulating layer 104, so that more steps are formed on the inner wall of the fifth opening 104a. Since transparent conductive materials are more easily deposited on the steps, the problem of breakage of the common electrode block 151 in the fifth opening 104a can be further avoided.

[0070] Optionally, a third metal layer and a third insulating layer covering the third metal layer are also provided on the substrate 10. The third metal layer and the third insulating layer are located between the substrate 10 and the first metal layer 11. The third metal layer includes peripheral routing located in the non-display area. That is, by setting the third metal layer to make peripheral routing, the frame can be reduced to achieve a narrow frame design.

[0071] Figure 7a-7h Schematic diagram of the process flow of the array substrate in the first embodiment of the present utility model. Figure 7a to Figure 7h As shown, the manufacturing method of the above array substrate includes:

[0072] like Figure 7aAs shown, a substrate 10 is provided. The substrate 10 can be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0073] A first metal layer 11 is formed on the substrate 10, and the first metal layer 11 is etched to form a patterned scan line and a gate 111 in the first metal layer 11, and the gate 111 is conductively connected to the scan line. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0074] A gate insulating layer 101 is formed on the first metal layer 11 to cover the scan line and the gate 111. The gate insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0075] like Figure 7b As shown, a semiconductor layer 12 is formed on the gate insulating layer 101 , and the semiconductor layer 12 is etched to form a patterned active layer 121 , where the active layer 121 corresponds to the gate 111 .

[0076] like Figure 7c As shown, a second metal layer 13 is formed on the gate insulating layer 101 and the semiconductor layer 12, and the second metal layer 13 is etched to form a patterned data line 131, a source electrode 132, a drain electrode 133 and a touch line 134 in the second metal layer 13. The data line 131 is conductively connected to the source electrode 132, and the source electrode 132 is conductively connected to the drain electrode 133 through the active layer 121. The touch line 134 and the data line 131 are parallel to each other and arranged alternately. A plurality of scanning lines and a plurality of data lines 131 are insulated from each other and cross-defined to form a plurality of pixel units. The second metal layer 131 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0077] like Figure 7dAs shown, a first insulating layer 102 is formed above the second metal layer 13 to cover the data line 131, the source 132, the drain 133, the touch wiring 134 and the active layer 121. The first insulating layer 102 is etched to form a first opening 102a corresponding to the drain 133 and a second opening 102b corresponding to the touch wiring 134 in the first insulating layer 102. The drain 133 is exposed from the first opening 102a, and the touch wiring 134 is exposed from the second opening 102b.

[0078] like Figure 7e As shown, a flat layer 103 is formed on the first insulating layer 102, and the flat layer 103 is etched to form a third opening 103a corresponding to the first opening 102a and a fourth opening 103b corresponding to the second opening 102b in the flat layer 103. The first opening 102a and the third opening 103a together form a first contact hole TH1, and the second opening 102b and the fourth opening 103b together form a second contact hole TH2. The drain 133 is exposed from the first contact hole TH1, and the touch wiring 134 is exposed from the second contact hole TH2.

[0079] In this embodiment, reference Figure 6 As shown, the first insulating layer 102 includes an insulating material layer 1 and a slope modification layer 2 which are stacked on each other. The slope modification layer 2 of the first insulating layer 102 is stacked on the side of the insulating material layer 1 of the first insulating layer 102 away from the substrate 10, and the insulating material layer 1 and the slope modification layer 2 are etched simultaneously. The insulating material layer 1 and the slope modification layer 2 are made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, but the etching rate of the slope modification layer 2 (etching rate of about 24000A / min) is greater than the etching rate of the insulating material layer 1 (etching rate of about 12000A / min), for example, the etching rate of the slope modification layer 2 is twice that of the insulating material layer 1, so that chamfers are formed at the openings of the first opening 102a and the second opening 102b to reduce the slope of the inner wall of the hole, thereby avoiding the problem of the pixel electrode 141 being broken in the first opening 102a.

[0080] like Figure 7fAs shown, a first transparent conductive layer 14 is formed on the flat layer 103, and the first transparent conductive layer 14 is etched to form a patterned pixel electrode 141 and a conductive electrode 142 on the first transparent conductive layer 14. The pixel electrode 141 corresponds to the pixel unit, and the conductive electrode 142 corresponds to the second opening 102b. The pixel electrode 141 is electrically connected to the corresponding drain electrode 133 through the first contact hole TH1 (the first opening 102a and the third opening 103a), and the conductive electrode 142 is electrically connected to the corresponding touch wiring 134 through the second contact hole TH2 (the second opening 102b and the fourth opening 103b). The pixel electrode 151 is a block electrode corresponding to the pixel unit, and the conductive electrode 142 is a block electrode corresponding to the second opening 102b. The material of the first transparent conductive layer 14 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0081] like Figure 7g As shown, a second insulating layer 104 covering the pixel electrode 141 and the conductive electrode 142 is formed on the planar layer 103, and the second insulating layer 104 is etched to form a fifth opening 104a corresponding to the conductive electrode 142 in the second insulating layer 104, and the conductive electrode 142 is exposed from the fifth opening 104a. Figure 6 As shown, the second insulating layer 104 includes an insulating material layer 1 and a slope modification layer 2 which are stacked on each other. The slope modification layer 2 of the second insulating layer 104 is stacked on the side of the insulating material layer 1 of the second insulating layer 104 away from the substrate 10, and the insulating material layer 1 and the slope modification layer 2 are etched simultaneously. The material of the second insulating layer 104 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, but the etching rate of the slope modification layer 2 (etching rate of about 24000A / min) is greater than the etching rate of the insulating material layer 1 (etching rate of about 12000A / min), for example, the etching rate of the slope modification layer 2 is twice that of the insulating material layer 1, so that a chamfer is formed at the opening of the fifth opening 104a to reduce the slope of the inner wall of the hole, thereby avoiding the problem of the common electrode block 151 being broken in the fifth opening 104a.

[0082] like Figure 7hAs shown, a second transparent conductive layer 15 is formed on the second insulating layer 104, and the second transparent conductive layer 15 is etched to form a plurality of patterned common electrode blocks 151 in the second transparent conductive layer 15, each of which is electrically connected to the corresponding conductive electrode 142 through the corresponding fifth opening 104a, that is, the common electrode block 151 is electrically connected to the corresponding touch wiring 134 through the conductive electrode 142, and a common signal and a touch signal are applied to the common electrode block 151 through the touch wiring 134, so that the common electrode block 151 is reused as a touch electrode. The common electrode block 151 is a slit electrode with a plurality of electrode strips in the area corresponding to the pixel electrode 141. The material of the second transparent conductive layer 15 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0083] Among them, the central axis of the fifth opening 104a is offset from the central axis of the second opening 102b. In the projection direction of the substrate 10, the second opening 102b partially overlaps with the second insulating layer 104, so that more steps are formed on the inner wall of the fifth opening 104a. Since transparent conductive materials are more easily deposited on the steps, the problem of breakage of the common electrode block 151 in the fifth opening 104a can be further avoided.

[0084] Optionally, before forming the first metal layer 11, the process further includes forming a third metal layer on the substrate 10, etching the third metal layer, and forming a patterned peripheral wiring in the non-display area. Then, a third insulating layer covering the peripheral wiring is formed on the substrate 10. That is, by providing the third metal layer to make the peripheral wiring, the frame can be reduced to achieve a narrow frame design.

[0085] [Example 2]

[0086] Figure 8 is a schematic diagram of the cross-sectional structure of the array substrate in the second embodiment of the present utility model, Fig. 9 is a schematic diagram of the cross-sectional structure of the drain electrode, the first insulating layer, the second insulating layer and the pixel electrode at the first contact hole in the second embodiment of the present utility model, Fig.10 is a schematic diagram of the cross-sectional structure of the touch wiring, the first insulating layer, the second insulating layer and the common electrode block at the second contact hole in the second embodiment of the present utility model, such as Figure 8-Figure 10 As shown, the second embodiment of the utility model provides an array substrate, including:

[0087] The substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0088] A first metal layer 11 is provided on the substrate 10, and the first metal layer 11 includes a scan line and a gate 111, and the gate 111 is conductively connected to the scan line. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0089] The gate insulating layer 101 is disposed above the first metal layer 11 and covers the scan line and the gate 111. The gate insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0090] The semiconductor layer 12 is disposed above the gate insulating layer 101 , and includes an active layer 121 corresponding to the gate 111 .

[0091] The second metal layer 13 is disposed above the gate insulating layer 101 and the semiconductor layer 12. The second metal layer 13 includes a data line 131, a source electrode 132, a drain electrode 133, and a touch line 134. The data line 131 is conductively connected to the source electrode 132, the source electrode 132 is conductively connected to the drain electrode 133 through the active layer 121, the touch line 134 and the data line 131 are parallel to each other and arranged alternately, and a plurality of scanning lines and a plurality of data lines 131 are insulated from each other and cross-defined to form a plurality of pixel units. The second metal layer 131 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0092] The first insulating layer 102 is disposed above the second metal layer 13 and covers the data line 131, the source electrode 132, the drain electrode 133, the touch wiring 134 and the active layer 121. Fig.10 As shown, the first insulating layer 102 is an insulating material layer 1, that is, in this embodiment, the first insulating layer 102 does not need to be provided with a slope modification layer 2. The first insulating layer 102 is provided with a first opening 102a corresponding to the drain 133 and a second opening 102b corresponding to the touch wiring 134, the drain 133 is exposed from the first opening 102a, and the touch wiring 134 is exposed from the second opening 102b.

[0093] The planar layer 103 is disposed above the first insulating layer 102. The planar layer 103 is provided with a third opening 103a corresponding to the first opening 102a and a fourth opening 103b corresponding to the second opening 102b. The first opening 102a and the third opening 103a together form a first contact hole TH1. Fig. 9 As shown, the wall slope of the third opening 103a is smaller than the wall slope of the first opening 102a, and the edge of the first opening 102a is covered by the flat layer 103. It can be understood that the first opening 102a is not completely covered by the flat layer 103, but only the edge is covered by the flat layer 103. Therefore, by setting the flat layer 103 with a gentler wall slope to extend into the first opening 102a, the problem of the pixel electrode 141 being broken in the first opening 102a can be avoided. Among them, part of the edge of the first opening 102a can be covered by the flat layer 103, and the central axis of the third opening 103a is staggered with the central axis of the first opening 102a; or all the edges of the first opening 102a can be covered by the flat layer 103, and the central axis of the third opening 103a is located on the same straight line as the central axis of the first opening 102a.

[0094] Optionally, the size of the fourth opening 103b is larger than the size of the second opening 102b, so that the second opening 102b is completely exposed from the fourth opening 103b. In other embodiments, the wall slope of the fourth opening 103b is smaller than the wall slope of the second opening 102b, and the edge of the second opening 102b is covered by the flat layer 103. For example, all edges of the second opening 102b may be covered by the flat layer 103, and the central axis of the fourth opening 103b is located on the same straight line as the central axis of the second opening 102b; or, part of the edge of the second opening 102b may be covered by the flat layer 103, and the central axis of the fourth opening 103b is staggered with the central axis of the second opening 102b.

[0095] The first transparent conductive layer 14 is disposed on the flat layer 103, and includes a pixel electrode 141 corresponding to the pixel unit, and the pixel electrode 141 is electrically connected to the corresponding drain electrode 133 through the first contact hole TH1 (the first opening 102a and the third opening 103a). The pixel electrode 151 is a block electrode corresponding to the pixel unit, and the material of the first transparent conductive layer 14 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0096] The second insulating layer 104 is disposed above the flat layer 103 and covers the pixel electrode 141. The second insulating layer 104 is provided with a fifth opening 104a corresponding to the second opening 102b. The touch line 134 is exposed from the second opening 102b, the fourth opening 103b and the fifth opening 104a. The second opening 102b, the fourth opening 103b and the fifth opening 104a together form a second contact hole TH2. Since the first insulating layer 102 is not provided with a slope modification layer 2, there will be no problem of bottom cutting between the first insulating layer 102 and the second insulating layer 104. Fig.10 As shown, the second insulating layer 104 includes an insulating material layer 1 and a slope modification layer 2 which are stacked on each other, and the slope modification layer 2 of the second insulating layer 104 is stacked on the side of the insulating material layer 1 of the second insulating layer 104 away from the substrate 10. The material of the second insulating layer 104 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, but the etching rate of the slope modification layer 2 (etching rate of about 24000A / min) is greater than the etching rate of the insulating material layer 1 (etching rate of about 12000A / min), for example, the etching rate of the slope modification layer 2 is twice that of the insulating material layer 1, so that a chamfer is formed at the opening of the fifth opening 104a to reduce the slope of the inner wall of the hole, thereby avoiding the problem of the common electrode block 151 being broken in the fifth opening 104a.

[0097] The second transparent conductive layer 15 is disposed above the second insulating layer 104. The second transparent conductive layer 15 includes a plurality of patterned common electrode blocks 151. Each common electrode block 151 is electrically connected to the corresponding touch wiring 134 through the corresponding second contact hole TH2 (the second opening 102b, the fourth opening 103b and the fifth opening 104a), that is, the common electrode block 151 is directly electrically connected to the corresponding touch wiring 134, and a common signal and a touch signal are applied to the common electrode block 151 through the touch wiring 134, so that the common electrode block 151 is reused as a touch electrode. The common electrode block 151 is a slit electrode with a plurality of electrode strips in the area corresponding to the pixel electrode 141. The material of the second transparent conductive layer 15 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0098] Among them, the central axis of the fifth opening 104a is offset from the central axis of the second opening 102b. In the projection direction of the substrate 10, the second opening 102b partially overlaps with the second insulating layer 104, so that more steps are formed on the inner wall of the fifth opening 104a. Since transparent conductive materials are more easily deposited on the steps, the problem of breakage of the common electrode block 151 in the fifth opening 104a can be further avoided.

[0099] Optionally, a third metal layer and a third insulating layer covering the third metal layer are also provided on the substrate 10. The third metal layer and the third insulating layer are located between the substrate 10 and the first metal layer 11. The third metal layer includes peripheral routing located in the non-display area. That is, by setting the third metal layer to make peripheral routing, the frame can be reduced to achieve a narrow frame design.

[0100] The method for manufacturing the array substrate in the second embodiment is substantially the same as the method for manufacturing the array substrate in the first embodiment, except that:

[0101] A planar layer 103 is formed on the first insulating layer 102, and the planar layer 103 is etched to form a third opening 103a corresponding to the first opening 102a and a fourth opening 103b corresponding to the second opening 102b in the planar layer 103, and the first opening 102a and the third opening 103a together form a first contact hole TH1. Fig. 9 As shown, the wall slope of the third opening 103a is smaller than the wall slope of the first opening 102a, and the edge of the first opening 102a is covered by the flat layer 103. It can be understood that the first opening 102a is not completely covered by the flat layer 103, but only the edge is covered by the flat layer 103. Therefore, by setting the flat layer 103 with a gentler wall slope to extend into the first opening 102a, the problem of the pixel electrode 141 being broken in the first opening 102a can be avoided. Among them, part of the edge of the first opening 102a can be covered by the flat layer 103, and the central axis of the third opening 103a is staggered with the central axis of the first opening 102a; or all the edges of the first opening 102a can be covered by the flat layer 103, and the central axis of the third opening 103a is located on the same straight line as the central axis of the first opening 102a.

[0102] A first transparent conductive layer 14 is formed on the flat layer 103, and the first transparent conductive layer 14 is etched to form a patterned pixel electrode 141 on the first transparent conductive layer 14. The pixel electrode 141 corresponds to the pixel unit, and the pixel electrode 141 is electrically connected to the corresponding drain 133 through the first contact hole TH1 (the first opening 102a and the third opening 103a). Among them, the pixel electrode 151 is a block electrode corresponding to the pixel unit. The material of the first transparent conductive layer 14 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). That is, in this embodiment, when the first transparent conductive layer 14 is etched, it is not necessary to form the conductive electrode 142.

[0103] A second insulating layer 104 is formed on the flat layer 103 to cover the pixel electrode 141 and the conductive electrode 142. The second insulating layer 104 is etched to form a fifth opening 104a corresponding to the second opening 102b in the second insulating layer 104. The touch wiring 134 is exposed from the second opening 102b, the fourth opening 103b and the fifth opening 104a. The second opening 102b, the fourth opening 103b and the fifth opening 104a together form a second contact hole TH2. In another embodiment, since the first insulating layer 102 is not provided with a slope modification layer 2, there is no problem of bottom cutting between the first insulating layer 102 and the second insulating layer 104, so that the fifth opening 104a and the second opening 102b can be etched together, that is, when the first insulating layer 102 is etched, the second opening 102b can be not etched first.

[0104] A second transparent conductive layer 15 is formed on the second insulating layer 104, and the second transparent conductive layer 15 is etched to form a plurality of patterned common electrode blocks 151. Each common electrode block 151 is electrically connected to the corresponding touch wiring 134 through the corresponding second contact hole TH2 (the second opening 102b, the fourth opening 103b and the fifth opening 104a), that is, the common electrode block 151 is directly electrically connected to the corresponding touch wiring 134, and a common signal and a touch signal are applied to the common electrode block 151 through the touch wiring 134, so that the common electrode block 151 is reused as a touch electrode. The common electrode block 151 is a slit electrode with a plurality of electrode strips in the area corresponding to the pixel electrode 141. The material of the second transparent conductive layer 15 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0105] It should be understood by those skilled in the art that the rest of the structure and process technology of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0106] Fig.11 It is a schematic diagram of the structure of the display device in the utility model in a dark state. Fig.12 Schematic diagram of the structure of the display device in the present invention when it is in a bright state. Fig.11 and Fig.12 As shown, the present application further provides a display panel, comprising an array substrate, a color filter substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 located between the array substrate and the color filter substrate 20. The array substrate is the array substrate described above.

[0107] The liquid crystal layer 30 uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy, such as Figure 6As shown, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color filter substrate 20 and the array substrate, and the alignment direction of the positive liquid crystal molecules close to the color filter substrate 20 is antiparallel to the positive liquid crystal molecules close to the array substrate. Of course, in other embodiments, the liquid crystal layer 30 may also use negative liquid crystal molecules, and the negative liquid crystal molecules in the liquid crystal layer 30 may be aligned perpendicular to the color filter substrate 20 and the array substrate, that is, similar to the alignment mode of the VA display mode.

[0108] On the color filter substrate 20, a plurality of color resist layers 22 corresponding to the pixel units SP and a black matrix (BM) 21 for separating the plurality of color resist layers 22 from each other are provided on the side facing the liquid crystal layer 30. A black matrix 21 is provided between any two adjacent columns and rows of pixel units SP. The color resist layer 22 includes red (R), green (G), and blue (B) color resist materials, which correspond to forming red, green, and blue pixel units, respectively. The black matrix 21 is located between the red, green, and blue pixel units, so that adjacent pixel units are separated from each other by the black matrix 21.

[0109] Furthermore, an upper polarizer 51 is disposed on the side of the color filter substrate 20 away from the liquid crystal layer 30 , and a lower polarizer 52 is disposed on the side of the array substrate away from the liquid crystal layer 30 . The light transmission axis of the upper polarizer 51 is perpendicular to the light transmission axis of the lower polarizer 52 .

[0110] The color filter substrate 20 and the array substrate can be made of transparent substrates such as glass, acrylic and polycarbonate. The common electrode block 21 and the pixel electrode 22 can be made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0111] The utility model further provides a display device, comprising a display panel and a backlight module 40. The backlight module 40 is located below the display panel and is used to provide a backlight source for the display panel.

[0112] The backlight module 40 can be an edge-type backlight module or a direct-type backlight module. Preferably, the backlight module 40 adopts a collimated backlight (CBL) mode, which can collect light and ensure the display effect.

[0113] The backlight module 40 includes a backlight source 41 and an anti-peep layer 43, and the anti-peep layer 43 is used to narrow the range of the light emission angle. A brightness enhancement film 42 is also provided between the backlight source 41 and the anti-peep layer 43, and the brightening film 42 increases the brightness of the backlight module 40. Among them, the anti-peep layer 43 is equivalent to a miniature shutter structure, which can block light with a larger incident angle and allow light with a smaller incident angle to pass through, thereby reducing the angle range of light passing through the anti-peep layer 43. The anti-peep layer 43 includes a plurality of parallel light-blocking walls and a light-transmitting hole located between two adjacent light-blocking walls, and light-absorbing materials are provided on both sides of the light-blocking walls. Of course, the backlight source 41 can also be a light-collecting backlight source, so there is no need to set the anti-peep layer 43, but the light-collecting backlight source is more expensive than the conventional backlight source.

[0114] In this document, the directional words such as up, down, left, right, front, and back are defined by the positions of the structures in the drawings and the positions of the structures relative to each other, just for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the directional words should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second" used in this document are only used to distinguish names and are not used to limit quantity and order.

[0115] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that: include: A substrate (10); A first metal layer (11), the first metal layer (11) being disposed above the substrate (10), the first metal layer (11) comprising a scanning line and a gate (111), the gate (111) being conductively connected to the scanning line; A gate insulating layer (101), the gate insulating layer (101) being disposed above the first metal layer (11) and covering the scanning line and the gate (111); A semiconductor layer (12), the semiconductor layer (12) being disposed above the gate insulating layer (101), the semiconductor layer (12) comprising an active layer (121) corresponding to the gate (111); a second metal layer (13), the second metal layer (13) being disposed above the gate insulating layer (101) and the semiconductor layer (12), the second metal layer (13) comprising a data line (131), a source electrode (132), a drain electrode (133) and a touch wiring (134), the data line (131) being conductively connected to the source electrode (132), the source electrode (132) being conductively connected to the drain electrode (133) via the active layer (121), the touch wiring (134) and the data line (131) being parallel to each other and arranged alternately, and a plurality of the scanning lines and the plurality of the data lines (131) being insulated from each other and crossing to define a plurality of pixel units; a first insulating layer (102), the first insulating layer (102) being disposed above the second metal layer (13) and covering the data line (131), the source electrode (132), the drain electrode (133), the touch wiring (134) and the active layer (121), the first insulating layer (102) being provided with a first opening (102a) corresponding to the drain electrode (133) and a second opening (102b) corresponding to the touch wiring (134); a flat layer (103), the flat layer (103) being disposed above the first insulating layer (102), the flat layer (103) being provided with a third opening (103a) corresponding to the first opening (102a) and a fourth opening (103b) corresponding to the second opening (102b); a first transparent conductive layer (14), the first transparent conductive layer (14) being arranged above the flat layer (103), the first transparent conductive layer (14) comprising a pixel electrode (141) corresponding to the pixel unit and a conducting electrode (142) corresponding to the second opening (102b), the pixel electrode (141) being electrically connected to the corresponding drain electrode (133) through the first opening (102a) and the third opening (103a), and the conducting electrode (142) being electrically connected to the corresponding touch wiring (134) through the second opening (102b) and the fourth opening (103b); a second insulating layer (104), the second insulating layer (104) being disposed above the flat layer (103) and covering the pixel electrode (141) and the conductive electrode (142), the second insulating layer (104) being provided with a fifth opening (104a) corresponding to the conductive electrode (142); A second transparent conductive layer (15), the second transparent conductive layer (15) is arranged above the second insulating layer (104), the second transparent conductive layer (15) comprises a plurality of patterned common electrode blocks (151), and the common electrode blocks (151) are electrically connected to the corresponding conductive electrodes (142) through the fifth openings (104a).

2. The array substrate according to claim 1, characterized in that: The first insulating layer (102) and the second insulating layer (104) both comprise an insulating material layer (1) and a slope modification layer (2) which are stacked on top of each other; the slope modification layer (2) of the first insulating layer (102) is stacked on a side of the insulating material layer (1) of the first insulating layer (102) which is away from the substrate (10); and the slope modification layer (2) of the second insulating layer (104) is stacked on a side of the insulating material layer (1) of the second insulating layer (104) which is away from the substrate (10).

3. The array substrate according to claim 1, characterized in that: The first insulating layer (102) is an insulating material layer (1), the second insulating layer (104) comprises an insulating material layer (1) and a slope modification layer (2), and the slope modification layer (2) of the second insulating layer (104) is stacked on a side of the insulating material layer (1) of the second insulating layer (104) away from the substrate (10); The wall slope of the third opening (103a) is smaller than the wall slope of the first opening (102a), and the edge of the first opening (102a) is covered by the flat layer (103); the wall slope of the fourth opening (103b) is smaller than the wall slope of the second opening (102b), and the edge of the second opening (102b) is covered by the flat layer (103).

4. An array substrate, characterized in that: include: A substrate (10); A first metal layer (11), the first metal layer (11) being disposed above the substrate (10), the first metal layer (11) comprising a scanning line and a gate (111), the gate (111) being conductively connected to the scanning line; A gate insulating layer (101), the gate insulating layer (101) being disposed above the first metal layer (11) and covering the scanning line and the gate (111); A semiconductor layer (12), the semiconductor layer (12) being disposed above the gate insulating layer (101), the semiconductor layer (12) comprising an active layer (121) corresponding to the gate (111); a second metal layer (13), the second metal layer (13) being disposed above the gate insulating layer (101) and the semiconductor layer (12), the second metal layer (13) comprising a data line (131), a source electrode (132), a drain electrode (133) and a touch wiring (134), the data line (131) being conductively connected to the source electrode (132), the source electrode (132) being conductively connected to the drain electrode (133) via the active layer (121), the touch wiring (134) and the data line (131) being parallel to each other and arranged alternately, and a plurality of the scanning lines and the plurality of the data lines (131) being insulated from each other and crossing to define a plurality of pixel units; a first insulating layer (102), the first insulating layer (102) being disposed above the second metal layer (13) and covering the data line (131), the source electrode (132), the drain electrode (133), the touch wiring (134) and the active layer (121), the first insulating layer (102) being an insulating material layer (1), the first insulating layer (102) being provided with a first opening (102a) corresponding to the drain electrode (133) and a second opening (102b) corresponding to the touch wiring (134); a flat layer (103), the flat layer (103) being disposed above the first insulating layer (102), the flat layer (103) being provided with a third opening (103a) corresponding to the first opening (102a) and a fourth opening (103b) corresponding to the second opening (102b), the wall slope of the third opening (103a) being smaller than the wall slope of the first opening (102a), and the edge of the first opening (102a) being covered by the flat layer (103); a first transparent conductive layer (14), the first transparent conductive layer (14) being arranged above the flat layer (103), the first transparent conductive layer (14) comprising a pixel electrode (141) corresponding to the pixel unit, the pixel electrode (141) being electrically connected to the corresponding drain electrode (133) through the first opening (102a) and the third opening (103a); a second insulating layer (104), the second insulating layer (104) being disposed above the planar layer (103) and covering the pixel electrode (141), the second insulating layer (104) being provided with a fifth opening (104a) corresponding to the second opening (102b); A second transparent conductive layer (15), the second transparent conductive layer (15) being disposed above the second insulating layer (104), the second transparent conductive layer (15) comprising a plurality of patterned common electrode blocks (151), the common electrode blocks (151) being electrically connected to the corresponding touch control traces (134) through the second opening (102b) and the fifth opening (104a).

5. The array substrate according to claim 4, characterized in that: The second insulating layer (104) comprises an insulating material layer (1) and a slope modification layer (2) which are stacked on each other, and the slope modification layer (2) of the second insulating layer (104) is stacked on a side of the insulating material layer (1) of the second insulating layer (104) away from the substrate (10).

6. The array substrate according to claim 4, characterized in that: The central axis of the third opening (103a) is located on the same straight line as the central axis of the first opening (102a), and all edges of the first opening (102a) are covered by the flat layer (103); Or the central axis of the third opening (103a) is offset from the central axis of the first opening (102a), and a portion of the edge of the first opening (102a) is covered by the flat layer (103).

7. The array substrate according to claim 4, characterized in that: The slope of the hole wall of the fourth opening (103b) is smaller than the slope of the hole wall of the second opening (102b), and the edge of the second opening (102b) is covered by the flat layer (103).

8. The array substrate according to claim 7, characterized in that: The central axis of the fourth opening (103b) and the central axis of the second opening (102b) are located on the same straight line, and all edges of the second opening (102b) are covered by the flat layer (103); Or the central axis of the fourth opening (103b) is offset from the central axis of the second opening (102b), and a portion of the edge of the second opening (102b) is covered by the flat layer (103).

9. A display panel, comprising an array substrate, a color filter substrate (20) arranged opposite to the array substrate, and a liquid crystal layer (30) located between the array substrate and the color filter substrate (20), characterized in that: The array substrate adopts the array substrate as claimed in any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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