Circuit structure for improving stability of LDO (low dropout regulator)

Abstract

The utility model discloses a circuit structure for improving the stability of LDO, including low dropout linear regulator circuit and low dropout linear regulator circuit connected negative capacitance generation circuit, low dropout linear regulator circuit includes adjusting tube and first amplifier, the output end of first amplifier is connected with the gate of adjusting tube, the output end of first amplifier is connected with the gate of adjusting tube, the output end of first amplifier is connected with the gate of adjusting tube, and the negative capacitance generation circuit is connected with the negative capacitance generation circuit in the low dropout linear regulator circuit. The first amplifier is an error amplifier; according to the technical scheme provided by the utility model, besides a known method for increasing the pole frequency of an internal node by adding source follower isolation, a new method is provided for increasing the pole frequency of the internal node, and by utilizing the Miller principle, a negative capacitance generation circuit in the low-dropout linear voltage regulator circuit is adopted, so that the high-voltage linear voltage regulator can be used for increasing the pole frequency of the internal node. Therefore, an equivalent capacitor with a reduced capacitance value is formed, so that the time constant of a node at the joint of the error amplifier and the adjusting tube is reduced, the pole frequency is increased, an output port can be changed into a dominant pole, the phase margin of the LDO is improved, and the stability of the LDO is ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of low voltage drop linear regulators, in particular to a circuit structure for improving the stability of LDO. Background Art

[0002] Nowadays, low-dropout linear regulators (LDOs) are used more and more frequently, and this circuit is indispensable in many circuits. However, during the use of the low-dropout linear regulator, the low-dropout linear regulator circuit may become unstable. Since the high output impedance of the error amplifier and the large parasitic capacitance of the adjustment tube form a large RC product, a low-frequency pole is formed at this node, which is not conducive to forming a main pole at the output voltage node. The existing solution is to insert a source follower between the error amplifier and the adjustment tube. By isolating the error amplifier and the adjustment tube, the high output impedance of the error amplifier and the large parasitic capacitance of the adjustment tube are not present at the same node, thereby pushing up the pole frequency of the internal node, which is conducive to forming a low-frequency main pole at the output voltage node. However, this method of isolating high impedance and large capacitance does not effectively reduce the large capacitance of the adjustment tube. Utility Model Content

[0003] Technical problems to be solved by utility models

[0004] The technical problem to be solved by the utility model is to provide a circuit structure for improving the stability of an LDO, thereby solving the problem that an LDO main pole is formed incorrectly, resulting in an LDO instability.

[0005] Technical Solution

[0006] In order to solve the above problems, the technical solution provided by the utility model is:

[0007] A circuit structure for improving LDO stability comprises a low voltage drop linear regulator circuit and a negative capacitance generating circuit connected in the low voltage drop linear regulator circuit.

[0008] Furthermore, the low voltage dropout linear regulator circuit includes an adjustment tube and a first amplifier, and an output terminal of the first amplifier is connected to a gate of the adjustment tube.

[0009] Furthermore, the first amplifier is an error amplifier.

[0010] Furthermore, the adjustment tube is a Pmos tube.

[0011] Furthermore, the negative capacitance generating circuit is connected to a node where the first amplifier and the adjusting tube are connected.

[0012] Furthermore, the negative capacitance generating circuit includes a second amplifier and a Miller capacitor connected to the second amplifier.

[0013] Furthermore, the low voltage dropout linear regulator circuit further includes a first resistor, a second resistor and a load.

[0014] Further, the drain of the adjustment tube is connected to the output voltage, the drain of the adjustment tube is connected to the second resistor, the second resistor is connected in series with the first resistor, the first resistor is grounded, the output voltage is connected in parallel with the load, and the load is grounded.

[0015] Further, a non-phase input terminal of the first amplifier is connected between the second resistor and the first resistor, and an inverting input terminal of the first amplifier is connected to a reference voltage.

[0016] Beneficial Effects

[0017] Compared with the prior art, the technical solution provided by the utility model has the following beneficial effects:

[0018] The technical solution provided by the utility model proposes a new method to push up the pole frequency of the internal node in addition to the known method of adding source follower isolation to push up the pole frequency of the internal node. By utilizing the Miller principle and adopting the negative capacitance generating circuit in the low voltage difference linear regulator circuit, an equivalent capacitance with a smaller capacitance value is formed to reduce the time constant of the node at the connection between the error amplifier and the adjustment tube, push up the pole frequency, and facilitate the output port to become the main pole, thereby improving the phase margin of the LDO and ensuring the stability of the LDO. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a circuit structure for improving LDO stability proposed by the utility model;

[0020] Figure 2 Schematic diagram of the circuit structure of LDO in the prior art. DETAILED DESCRIPTION

[0021] In order to further understand the content of the utility model, the utility model is described in detail in conjunction with the accompanying drawings and embodiments.

[0022] Combined with Figure 1-2 A circuit structure for improving the stability of LDO uses Miller's theorem to generate negative capacitance, reduces the node capacitance at the adjustment gate, and pushes up the pole frequency here, thereby facilitating the pole of the output port to become the main pole.

[0023] The invention comprises a low voltage difference linear regulator circuit LDO and a negative capacitance generating circuit connected in the low voltage difference linear regulator circuit LDO.

[0024] The low-dropout linear regulator circuit LDO includes an adjustment tube P1, a first amplifier AMP1, a first resistor R1, a second resistor R2 and a load.

[0025] The first amplifier AMP1 is an error amplifier, the adjustment tube is a PMOS tube, and the output terminal of the first amplifier AMP1 is connected to the gate of the adjustment tube P1.

[0026] The negative capacitance generating circuit is connected to a node where the first amplifier AMP1 and the adjusting tube P1 are connected.

[0027] The negative capacitance generating circuit includes a second amplifier AMP2 and a Miller capacitor C1 connected to the second amplifier AMP2.

[0028] The drain of the adjustment tube P1 is connected to the output voltage Vout, the drain of the adjustment tube P1 is connected to the second resistor R2, the second resistor R2 is connected in series with the first resistor R1, the first resistor R1 is grounded, the output voltage Vout is connected in parallel with the load, and the load is grounded.

[0029] A non-inverting input terminal of the first amplifier AMP1 is connected between the second resistor R2 and the first resistor R1 , and an inverting input terminal of the first amplifier AMP1 is connected to a reference voltage Vref.

[0030] At the node between the error amplifier AMP1 and the adjustment tube P1, the Miller capacitor is used to generate an equivalent input negative capacitance. Since this negative capacitance and the parasitic capacitance of the adjustment tube P1 are in parallel, the total equivalent capacitance can be smaller than the parasitic capacitance of P1, so that the RC product of this node is small and the pole becomes larger.

[0031] The principle is: according to Miller's theorem, when AMP2 is a common-mode amplifier circuit and the gain is A, the equivalent capacitance of AMP2 input is (1-A) x C1. If A is much larger than 1, it is approximately equal to -A x C1. Note that this capacitance is a negative capacitance. This negative capacitance is in parallel with the parasitic capacitance of the adjustment tube P1, so the equivalent capacitance of these two parallel capacitors can be smaller than the parasitic capacitance of P1.

[0032] Therefore, C in the RC constant of this node becomes smaller, and the pole frequency here becomes larger, which is conducive to the pole at the output vout becoming the main pole, thereby improving the phase margin and ensuring the stability of the low voltage drop linear regulator circuit LDO.

[0033] like Figure 2 As shown, the principle of the existing LDO circuit is to output vout = vref (1 + R2 / R1). When the load changes and causes vout to fluctuate, the resistor string voltage divider feedbacks the signal to the input of the error amplifier and then the output signal adjusts the gate of the PMOS tube P1 to adjust vout, completing the negative feedback adjustment process, with the purpose of ensuring that Vout is constant when the load changes.

[0034] The defect of the existing LDO circuit is that when we hope to have a main pole at the output Vout, the high output impedance of the error amplifier and the large parasitic capacitance of the adjustment tube P1 form a large RC product, causing this node to form a low-frequency pole and become the main pole, which is not conducive to forming a main pole at the output Vout.

[0035] By comparing the LDO circuit using the negative capacitance generating circuit and the LDO circuit not using the negative capacitance generating circuit, the numerical formula of the pole angular frequency w is:

[0036] The pole angular frequency w of the circuit generated by using negative capacitance is: w=1 / Rout*(C+(1-A)xC1).

[0037] Rout is the output resistance of the node, C is the parasitic capacitance, which mainly comes from the gate-source parasitic capacitance of the adjustment tube PMOS, and C1 is the Miller capacitance.

[0038] The pole angular frequency w of the circuit without negative capacitance generation is w=1 / Rout*C.

[0039] Rout is the output resistance of the node, and C is the parasitic capacitance, which mainly comes from the gate-source parasitic capacitance of the adjustment tube PMOS.

[0040] It can be seen that since A is a positive value, it can be seen that the appropriate A and C1 can reduce the value of C, thereby increasing W. Since the main pole is the pole with the lowest frequency, the above comparison shows that the technical solution of using a negative capacitance generation circuit can increase the pole frequency of the node and push this pole frequency to a higher frequency, so that it does not become the main pole, thereby making it easier for the pole frequency of the output node of the LDO to become the main pole. The distance between the main pole and the secondary main pole must be far enough to ensure the phase margin and stability. Therefore, the solution of using a negative capacitance generation circuit is used to push the node pole away, thereby increasing the distance between the main pole and the secondary main pole, thereby improving the phase margin of the LDO and ensuring the stability of the LDO.

[0041] The above technical solution generates negative capacitance and connects it in parallel with large parasitic capacitance, so that the equivalent cap is reduced, the time constant is reduced, the pole frequency is increased, and the pole frequency of the internal node is pushed up, which is beneficial for the pole at the output node to become relatively lower. In this way, the difference between the two poles becomes larger, which is beneficial to improve stability.

[0042] The above schematically describes the present invention and its implementation methods, which are not restrictive. The drawings show only one implementation method of the present invention, and the actual structure is not limited thereto. Therefore, if ordinary technicians in this field are inspired by it and design structural methods and embodiments similar to the technical solution without creativity without departing from the purpose of the present invention, they should all fall within the protection scope of the present invention.

Claims

1. A circuit structure for improving the stability of LDO, characterized in that: The invention comprises a low voltage difference linear voltage regulator circuit and a negative capacitance generating circuit connected in the low voltage difference linear voltage regulator circuit.

2. A circuit structure for improving LDO stability according to claim 1, characterized in that: The low voltage difference linear regulator circuit comprises an adjustment tube and a first amplifier, wherein an output terminal of the first amplifier is connected to a gate of the adjustment tube.

3. A circuit structure for improving LDO stability according to claim 2, characterized in that: The first amplifier is an error amplifier.

4. A circuit structure for improving LDO stability according to claim 3, characterized in that: The adjustment tube is a Pmos tube.

5. A circuit structure for improving LDO stability according to claim 2, characterized in that: The negative capacitance generating circuit is connected to the node where the first amplifier and the adjusting tube are connected.

6. A circuit structure for improving LDO stability according to claim 1, characterized in that: The negative capacitance generating circuit includes a second amplifier and a Miller capacitor connected to the second amplifier.

7. A circuit structure for improving LDO stability according to claim 4, characterized in that: The low voltage dropout linear regulator circuit further includes a first resistor, a second resistor and a load.

8. A circuit structure for improving LDO stability according to claim 7, characterized in that: The drain of the adjustment tube is connected to the output voltage, the drain of the adjustment tube is connected to the second resistor, the second resistor is connected in series with the first resistor, the first resistor is grounded, the output voltage is connected in parallel with the load, and the load is grounded.

9. A circuit structure for improving LDO stability according to claim 8, characterized in that: A non-inverting input terminal of the first amplifier is connected between the second resistor and the first resistor, and an inverting input terminal of the first amplifier is connected to a reference voltage.

Images