Semiconductor package

Abstract

The utility model provides a semiconductor package. In one embodiment, an interposer may include: a plurality of first redistribution layers including a first electrical inline structure having a first line width and a first line pitch embedded in a first dielectric material; and a plurality of second redistribution layers including second electrical inline structures embedded in a second dielectric material having a second line width and a second line pitch such that the second line width is greater than the first line width and such that the second line pitch is greater than the first line pitch. The first dielectric material may be one of a polyimide, benzocyclobutene, or a polybenzobisoxazole, and the second dielectric material may include an inorganic particulate material dispersed in an epoxy resin. The interposer may also include a protective layer comprising a second dielectric material formed over the first redistribution layer and a surface layer comprising the first dielectric material formed as part of the second redistribution layer.

Description

Technical Field

[0001] The utility model relates to a semiconductor package. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and layers of semiconductor material on a semiconductor substrate; and patterning the various material layers using lithography to form circuit components and circuit elements thereon. Tens, hundreds, or thousands of integrated circuits (ICs) are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer are singulated by sawing along scribe lines between the integrated circuits. The individual dies are typically packaged individually, for example, in a multi-chip module or other type of package.

[0003] In addition to the ongoing effort to pursue smaller electronic components, continued improvements in the packaging of components provide smaller packages that occupy less area than previous packages. Exemplary approaches include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC), 3-dimensional integrated circuit (3DIC), wafer level package (WLP), package on package (PoP), system on chip (SoC), or system on integrated circuit (SoIC) devices. Some of these three-dimensional devices (e.g., 3DIC, SoC, SoIC) are prepared by placing chips on top of chips at the semiconductor wafer level. Because the length of the interconnects between the stacked chips is reduced, these three-dimensional devices provide improved integration density and other advantages, such as faster speed and higher bandwidth. However, there are numerous challenges associated with the fabrication and operation of three-dimensional devices, including mechanical issues associated with thermal expansion mismatches between package components leading to warpage, cracking, delamination, etc. Utility Model Content

[0004] An embodiment of the utility model provides a semiconductor package, comprising: an intermediate layer, comprising: a plurality of first redistribution layers, comprising a first electrical interconnect structure having a first line width and a first line spacing embedded in a first dielectric material; and a plurality of second redistribution layers, comprising a second electrical interconnect structure having a second line width and a second line spacing embedded in a second dielectric material, wherein the second line width is greater than the first line width, and wherein the second line spacing is greater than the first line spacing.

[0005] In some embodiments, the present invention provides another semiconductor package, including: an interposer, including: a flat geometry structure, including a first surface and a second surface; a plurality of first redistribution layers, including a first electrically interconnected structure formed in a first dielectric material near the first surface; a plurality of second redistribution layers, including a second electrically interconnected structure formed in a second dielectric material near the second surface, wherein the first dielectric material has greater elasticity than the second dielectric material, and wherein the plurality of second redistribution layers further include a surface layer comprising the first dielectric material, the surface layer being formed near the second surface of the interposer, so that the surface layer partially surrounds the second electrically interconnected structure.

[0006] In some embodiments, the present invention provides a method for forming an intermediate layer, comprising: forming a plurality of first redistribution layers on a first carrier substrate, the plurality of first redistribution layers comprising a first electrical interconnect structure having a first line width and a first line spacing embedded in a first dielectric material; and forming a plurality of second redistribution layers on the plurality of first redistribution layers, the plurality of second redistribution layers comprising a second electrical interconnect structure having a second line width and a second line spacing embedded in a second dielectric material, wherein the second line width is greater than the first line width, and wherein the second line spacing is greater than the first line spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the embodiments of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A A vertical cross-sectional exploded view of the components of a semiconductor package during the package assembly and surface mounting processes.

[0009] Figure 1B is a vertical cross-sectional view showing an assembled semiconductor package mounted on a surface of a supporting substrate.

[0010] Figure 2is a vertical cross-sectional view of yet another semiconductor package, showing the electrical interconnect structure of the package substrate.

[0011] Figure 3 is a vertical cross-sectional view of yet another semiconductor package including an interposer having a plurality of first redistribution layers and a plurality of second redistribution layers according to various embodiments.

[0012] Figure 4A yes Figure 2 A vertical cross-sectional view of a package substrate of a semiconductor package is shown.

[0013] Figure 4B According to various embodiments Figure 3 A vertical cross-sectional view of a package substrate of a semiconductor package is shown.

[0014] Figure 5 is a vertical cross-sectional view of an intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0015] Figure 6 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0016] Figure 7 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0017] Figure 8 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0018] Fig. 9 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0019] Fig.10 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0020] Fig.11 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0021] Fig.12 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0022] Fig.13 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0023] Fig.14 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0024] Fig.15 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0025] Fig.16 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0026] Fig.17 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0027] Fig.18 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0028] Fig.19A is a vertical cross-sectional view of an embodiment semiconductor package according to various embodiments.

[0029] Fig.19B is a vertical cross-sectional view of yet another embodiment semiconductor package according to various embodiments.

[0030] Fig. 20 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0031] Fig.21 is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor package according to various embodiments.

[0032] Fig. 22 Can be distinguished from Fig. 20 and Fig.21 The intermediate structure shown is a vertical cross-sectional view of another embodiment of a semiconductor package.

[0033] Fig.23 is a flow chart illustrating various operations of a method of forming an interposer in accordance with various embodiments. DETAILED DESCRIPTION

[0034] The following utility model embodiments provide many different embodiments or examples for implementing the various features of the provided target. The following describes specific examples of components and arrangements to simplify the utility model embodiments. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, thereby making the first feature and the second feature may not be in direct contact. In addition, the utility model embodiments may reuse reference numbers and / or letters in the disclosed exemplary embodiments. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0035] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to be of the same material composition and is assumed to have a thickness within the same thickness range.

[0036] Typically, in a semiconductor package, a number of semiconductor integrated circuit (IC) dies (i.e., "chips") may be mounted on a common substrate. The common substrate on which the chips may be mounted may also be referred to as a "package substrate." In some embodiments, electrical connections to the semiconductor package may be achieved by mounting the package substrate on a supporting substrate (e.g., a printed circuit board (PCB)) that includes electrical interconnects.

[0037] An interposer may be advantageously included in a semiconductor package because the interposer may provide a plurality of first redistribution layers (RDLs) and a plurality of second redistribution layers. The first redistribution layers may include a first electrical interconnect structure having a fine line width and line spacing, the first electrical interconnect structure may be configured to provide a high-speed die-to-die (D2D) channel between a first semiconductor die and a second semiconductor die in the semiconductor package, and the plurality of second redistribution layers may include a second electrical interconnect structure, the second electrical interconnect structure may be configured to provide an enhanced power delivery channel relative to a power delivery channel of an alternative interposer. Each of the plurality of first redistribution layers and the plurality of second redistribution layers may be formed in one or more polymer materials that may allow for increased elastic deformation, the increased elastic deformation may thereby reduce thermal stress / strain between components of the semiconductor package and, therefore, may mitigate issues associated with thermally induced deformation, warping, cracking, delamination, etc. The plurality of first redistribution layers may also provide some functionality that is otherwise provided by an alternative interposer, and the plurality of second redistribution layers may provide some functionality that is otherwise provided by a package substrate. As such, a package substrate used in conjunction with the interposers in the various embodiments may require fewer interconnect layers, thereby reducing the complexity of the semiconductor package overall relative to existing package structures.

[0038] In an embodiment, the interlayer may include a plurality of first redistribution layers and a plurality of second redistribution layers, wherein the plurality of first redistribution layers include a first electrical interconnect structure having a first line width and a first line spacing embedded in a first dielectric material, and the plurality of second redistribution layers include a second electrical interconnect structure having a second line width and a second line spacing embedded in a second dielectric material, such that the second line width is greater than the first line width and the second line spacing is greater than the first line spacing. The first dielectric material may be one of polyimide (PI), benzocyclobutene (BCB) or polybenzo-bisoxazole (PBO), and the second dielectric material may include an inorganic particulate material dispersed in an epoxy resin. The interlayer may also include a protective layer including a second dielectric material formed on the first redistribution layer and a surface layer including the first dielectric material formed as a part of the second redistribution layer.

[0039] In yet another embodiment, a semiconductor package is provided. The semiconductor package may include an interposer having a slab geometry having a first surface and a second surface. The interposer may also include a plurality of first redistribution layers and a plurality of second redistribution layers, the plurality of first redistribution layers including a first electrically inline structure formed in a first dielectric material near the first surface, and the plurality of second redistribution layers including a second electrically inline structure formed in a second dielectric material near the second surface. According to an embodiment, the first dielectric material may have greater elasticity than the second dielectric material. The plurality of second redistribution layers may also include a surface layer comprising the first dielectric material, the surface layer being formed near the second surface of the interposer so that the surface layer partially surrounds the second electrically inline structure.

[0040] In yet another embodiment, a method of forming an interposer is provided. The method may include forming a plurality of first redistribution layers on a first carrier substrate and forming a plurality of second redistribution layers on the plurality of first redistribution layers. The plurality of first redistribution layers may include a first electrically interconnected structure having a first line width and a first line spacing embedded in a first dielectric material, and the plurality of second redistribution layers may include a second electrically interconnected structure having a second line width and a second line spacing embedded in a second dielectric material. In various embodiments, the second line width may be greater than the first line width and the second line spacing may be greater than the first line spacing.

[0041] Figure 1A is a vertical cross-sectional exploded view of components of the semiconductor package 100 during the package assembly and surface mounting process. Figure 1B 1 is a vertical cross-sectional view showing an assembled semiconductor package 100 mounted on a surface of a supporting substrate 102 (e.g., a printed circuit board (PCB)). The semiconductor package 100 in this example is a chip-on-wafer-on-substrate (CoWoS). Semiconductor package, however, it should be understood that similar assembly and mounting processes can also be used for other types of semiconductor packages, such as integrated fan-out (InFO) semiconductor package, flip chip semiconductor package, etc.

[0042] Reference Figure 1A and Figure 1B, the semiconductor package 100 may include integrated circuit (IC) semiconductor dies, such as a first semiconductor die 104 and a second semiconductor die 106. During the package assembly process, the first semiconductor die 104 and the second semiconductor die 106 may be mounted to an interposer 108, and the interposer 108 may be mounted to a package substrate 110 to form the semiconductor package 100. The semiconductor package 100 may then be mounted to a support substrate 102 (e.g., a printed circuit board (PCB)) by mounting the package substrate 110 to the support substrate 102 using an array of solder balls 112 on a lower surface 114 of the package substrate 110.

[0043] A parameter that can ensure proper interconnection between the package substrate 110 and the support substrate 102 is that the solder balls 112 can be connected to the mounting surface (ie, Figure 1A During the reflow process, a low degree of co-planarity between the solder balls 112 may result in the following: a solder cold joint (i.e., the solder material does not fully melt, resulting in a poor joint that is susceptible to cracking and separation) and / or solder bridging issues (i.e., solder material from one solder ball 112 contacts material from an adjacent solder ball 112, resulting in an unintentional connection (i.e., an electrical short)).

[0044] During surface mounting of the package substrate 110 onto the support substrate 102 , deformation of the package substrate 110 , such as stress-induced warping of the package substrate 110 , may be a cause of low coplanarity of the solder balls 112 . Figure 1B FIG. 1 shows a package substrate 110 including warpage. The warpage of the package substrate 110 may result in a change in the distance between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102. Such deformation of the package substrate 110 may increase the risk of defective solder connections with the underlying support substrate 102. Figure 1B As shown in, for example, Figure 1B As indicated by arrows 118 in FIG. 1 , deformation of the package substrate 110 may cause at least some of the solder joints between the package substrate 110 and the support substrate 102 to fail completely. Figure 1BIn the exemplary embodiment shown in , the deformation of the packaging substrate 110 may have a bow-shape or a cup-shape, so that the separation between the lower surface 114 of the packaging substrate 110 and the upper surface 116 of the supporting substrate 102 may be smallest at the periphery of the packaging substrate 110 and may increase toward the center of the packaging substrate 110.

[0045] Deformation of the package substrate 110 is not uncommon, especially in the case of semiconductor packages used in high-performance computing applications. These high-performance semiconductor packages 100 are often relatively large and may include a number of semiconductor dies (e.g., 104, 106) mounted to the package substrate 110. The thermal load (thermal load) generated by these semiconductor dies (e.g., 104, 106) and the differences in coefficients of thermal expansion (CTE) often cause warping and other deformation of the package substrate 110 and other components of the semiconductor package 100. Such deformation may pose challenges to the effective solder mounting (solder mounting) of these types of semiconductor package substrates 110 to the supporting substrate 102.

[0046] In various embodiments, the first semiconductor die 104 may be a three-dimensional device, such as a three-dimensional integrated circuit (3DIC), a system-on-chip (SOC), or a system-on-integrated circuit (SoIC) device. Three-dimensional semiconductor devices may be formed by placing chips on top of chips at the semiconductor wafer level. Due to the reduced inline length between stacked chips, these three-dimensional devices may provide improved integration density and other advantages, such as faster speed and higher bandwidth. In some embodiments, the first three-dimensional semiconductor device may also be referred to as a "first die stack".

[0047] The second semiconductor die 106 may be different from the first semiconductor die 104 in terms of its structure, design and / or functionality. The one or more second semiconductor die 106 may be a three-dimensional semiconductor die, which may also be referred to as a "second die stack". In some embodiments, the one or more second semiconductor die 106 may include a memory device, such as a high bandwidth memory (HBM) device. Figure 1A and Figure 1B In the example shown in FIG. 1 , the semiconductor package 100 may include a SOC die stack 104 and a HBM die stack 106 . However, it should be understood that the semiconductor package 100 may also include a greater or lesser number of semiconductor dies.

[0048] Re-reference Figure 1B, the first semiconductor die 104 and the second semiconductor die 106 can be mounted on the interposer 108. In some embodiments, the interposer 108 can be an organic interposer including a polymer dielectric material (e.g., a polyimide material) having a plurality of metal interconnect structures extending therethrough. In other embodiments, the interposer 108 can be a semiconductor interposer (e.g., a silicon interposer) having a plurality of interconnect structures extending therethrough (e.g., silicon through vias). Other suitable configurations of the interposer 108 are also within the contemplated scope of the embodiments of the present invention. The interposer 108 can include a plurality of conductive bonding pads (not shown) located on the upper and lower surfaces of the interposer and a plurality of conductive interconnects extending through the interposer 108 between the upper bonding pads and the lower bonding pads of the interposer 108. The conductive interconnects can distribute and route electrical signals between the first semiconductor die 104, the second semiconductor die 106, and the underlying package substrate 110. Therefore, the interposer 108 can also be referred to as a redistribution layer (RDL).

[0049] A plurality of metal bumps 120 (e.g., micro-bumps) may electrically connect the conductive bonding pads on the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 106 to the conductive bonding pads on the upper surface of the interposer 108. In a non-limiting embodiment, the metal bumps 120 in the form of micro-bumps may include a plurality of first metal stacks (e.g., a plurality of Cu-Ni-Cu stacks) located on the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 106 and a plurality of second metal stacks (e.g., Cu-Ni-Cu stacks) located on the upper surface of the interposer 108. A solder material (e.g., tin (Sn)) may be located between the respective first metal stacks and the second metal stacks to electrically connect the first semiconductor die 104 and the second semiconductor die 106 to the interposer 108. Other suitable materials for the metal bumps 120 are also within the contemplated scope of the embodiments of the present invention.

[0050] After the first semiconductor die 104 and the second semiconductor die 106 are mounted on the interposer 108, as shown in FIG. Figure 1B As shown in , a first bottom filling material portion 122 may be optionally provided in the space surrounding the metal bump 120 and between the bottom surfaces of the first semiconductor die 104, the second semiconductor die 106 and the upper surface of the interposer 108. The first bottom filling material portion 122 may also be disposed in the space that laterally separates the adjacent first semiconductor die 104 and the second semiconductor die 106 of the semiconductor package 100. In various embodiments, the first bottom filling material portion 122 may include an epoxy resin-based material, which may include a composite of a resin and a filler material.

[0051] Re-reference Figure 1B, the interposer 108 can be mounted on a package substrate 110, and the package substrate 110 can provide mechanical support for the interposer 108 and the first semiconductor die 104 and the second semiconductor die 106 mounted on the interposer 108. The package substrate 110 can include suitable materials, such as organic materials (e.g., polymers and / or thermoplastic materials), semiconductor materials (e.g., semiconductor chips (e.g., silicon chips)), ceramic materials, glass materials, combinations thereof, or the like. Other suitable substrate materials are also within the scope of the embodiments of the present invention. In various embodiments, the package substrate 110 may include a plurality of conductive bonding pads (not shown) located in the upper surface 126 of the package substrate 110. A plurality of metal bumps 124 (e.g., controlled collapse chip connection (C4) solder bumps) can electrically connect the conductive bonding pads (not shown) on the bottom surface of the interposer 108 to the conductive bonding pads on the upper surface 126 of the package substrate 110. In various embodiments, the metal bump 124 may include a suitable solder material (such as tin (Sn)). However, other suitable solder materials are also within the scope of the embodiments of the present invention.

[0052] For example, in Figure 1B As shown in , a second bottom fill material portion 128 may be provided in the space surrounding the metal bump 124 and between the bottom surface of the interposer 108 and the upper surface 126 of the package substrate 110. In various embodiments, the second bottom fill material portion 128 may include an epoxy resin-based material, which may include a composite of a resin and a filler material. In some embodiments, a lid or cover (in Figure 1A and Figure 1B The semiconductor die 104 and the semiconductor die 106 may be mounted to the package substrate 110 and may provide an enclosure around the upper surface and the side surfaces of the first semiconductor die 104 and the second semiconductor die 106 .

[0053] As described above, the package substrate 110 can be mounted to a support substrate 102, such as a printed circuit board (PCB). Other suitable support substrates 102 are also within the contemplation of embodiments of the present invention. The package substrate 110 may include a plurality of conductive bonding pads 130 located in the lower surface 114 of the package substrate 110. A plurality of conductive inlines (not shown) may extend through the package substrate 110 between the conductive bonding pads on the upper surface 126 and the lower surface 114 of the package substrate 110. The plurality of solder balls (or bump structures) 112 may electrically connect the conductive bonding pads 130 on the lower surface 114 of the package substrate 110 to the plurality of conductive bonding pads 132 on the upper surface 116 of the support substrate 102.

[0054] The conductive bonding pads 130 of the package substrate 110 and the conductive bonding pads 132 of the support substrate 102 may be formed of a suitable conductive material (e.g., copper). Other suitable conductive materials are also within the scope of the embodiments of the present invention. The plurality of solder balls 112 on the lower surface 114 of the package substrate 110 may form an array of solder balls 112, such as a ball grid array (BGA) having an array pattern corresponding to the array pattern of the conductive bonding pads 132 on the upper surface 116 of the support substrate 102. In a non-limiting example, the array of solder balls 112 may include a grid pattern and may have a pitch (i.e., the distance between the center of each solder ball 112 and the center of each adjacent solder ball 112). In an exemplary embodiment, the pitch may be between about 0.8 mm and 1.0 mm, although larger and smaller pitches may also be used.

[0055] The solder balls 112 may include any suitable solder material, such as tin, lead, silver, indium, zinc, nickel, bismuth, antimony, cobalt, copper, germanium, alloys thereof, combinations thereof, or the like. Other suitable materials for the solder balls 112 are also within the contemplation of the embodiments of the present invention. In some embodiments, the lower surface 114 of the package substrate 110 may include a solder resist (SR) material coating (not shown), which may also be referred to as a "solder mask". The SR material coating may provide a protective coating for the package substrate 110 and any underlying circuit patterns formed on or within the package substrate 110. The SR material coating may also inhibit the solder material from adhering to the lower surface 114 of the package substrate 110 during the reflow process. In embodiments in which the lower surface 114 of the package substrate 110 includes the SR material coating, the SR material coating may include a plurality of openings that may expose the conductive bonding pads 130.

[0056] In various embodiments, each of the conductive bonding pads 130 in different regions of the package substrate 110 may have the same size and shape. Figure 1A and Figure 1B In the embodiment shown in , the surface of the conductive bonding pad 130 may be substantially coplanar with the lower surface 114 (which may include a solder resist (SR) coating in some embodiments) of the package substrate 110. Alternatively, the surface of the conductive bonding pad 130 may be recessed relative to the lower surface 114 of the package substrate 110. In some embodiments, the surface of the conductive bonding pad 130 may be raised relative to the lower surface 114 of the package substrate 110.

[0057] Re-reference Figure 1A and Figure 1B, solder balls 112 may be provided on corresponding conductive bonding pads 130. In one non-limiting example, the conductive bonding pads 130 may have a width dimension between about 500 microns and about 550 microns (e.g., ˜530 microns), and the solder balls 112 may have an outer diameter between about 600 microns and about 650 microns (e.g., ˜630 microns), although larger and smaller dimensions of the solder balls 112 and / or the conductive bonding pads 130 are also within the contemplation of the embodiments of the present invention.

[0058] The first solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250° C.) to melt the solder balls 112 and to bond the solder balls 112 to the conductive bonding pads 130. After the first reflow process, the package substrate 110 may be cooled to re-solidify the solder balls 112. After the first solder reflow process, the solder balls 112 may bond to the conductive bonding pads 130. Each solder ball 112 may extend a vertical height from the lower surface 114 of the package substrate 110, which may be less than an outer diameter of the solder ball 112 before the first reflow process. For example, in the case where the outer diameter of the solder ball 112 is between about 600 microns and about 650 microns (e.g., ˜630 microns), the vertical height of the solder ball 112 may be between about 500 microns and about 550 microns (e.g., ˜520 microns) after the first reflow process.

[0059] In various embodiments, such as Figure 1B The process of mounting the package substrate 110 onto the support substrate 102 as shown in may include aligning the package substrate 110 over the support substrate 102 so that the solder balls 112 in contact with the conductive bonding pads 130 of the package substrate 110 may be located over corresponding bonding pads (e.g., conductive bonding pads 132) on the support substrate 102. Then, a second solder reflow process may be performed. The second solder reflow process may include subjecting the package substrate 110 to a high temperature (e.g., at least about 250° C.) to thereby melt the solder balls 112 and cause the first solder balls 112 to adhere to corresponding conductive bonding pads 132 on the support substrate 102. Surface tension may cause the semi-liquid solder to maintain alignment of the package substrate 110 with the support substrate 102 while the solder material cools and solidifies. When the solder balls 112 are solidified, the package substrate 110 can be located above the upper surface 116 of the support substrate 102 at a stand-off distance. In some embodiments, the stand-off distance can be between approximately 0.4 mm and 0.5 mm, but larger or smaller stand-off distances are also within the scope of the embodiments of the present invention.

[0060] After the package substrate 110 is mounted on the support substrate 102, as shown in FIG. Figure 1BAs shown in , a third underfill material portion 134 may be provided in the space surrounding the solder balls 112 and between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102. In various embodiments, the third underfill material portion 134 may include an epoxy resin-based material, which may include a composite of a resin and a filler material.

[0061] Figure 2 FIG. 2 is a vertical cross-sectional view of another semiconductor package 200, which shows the electrical interconnect structures (206a1, 206a2) of the first package substrate 110a. The semiconductor package 200 may be similar to Figure 1A and Figure 1B The semiconductor package 100 is shown. In this regard, the semiconductor package 200 may include a first semiconductor die 104 and two second semiconductor dies 106 mounted to a first interposer 108a. Figure 1A and Figure 1B As described above, the first interposer 108 a may be mounted to the first package substrate 110 a. The semiconductor package 200 may include a first underfill material portion 122 disposed in a space laterally separating adjacent first and second semiconductor dies 104 and 106 of the semiconductor package 200 .

[0062] The semiconductor package 200 may also include an epoxy molding compound (EMC) that may be applied to the gaps formed between the first interposer 108a, the first semiconductor die 104, and the second semiconductor die 106 to thereby form a multi-die EMC frame 202. The EMC material may include an epoxy resin compound that may be hardened (i.e., cured) to provide a dielectric material portion having sufficient stiffness and mechanical strength. The EMC material may include an epoxy resin, a hardener, silicon dioxide (as a filler material), and other additives. Depending on the viscosity and flowability, the EMC material may be provided in liquid form or solid form.

[0063] Liquid EMC may provide better handling, good flowability, fewer voids, better filling, and fewer flow marks. Solid EMC may provide less cure shrinkage, better standoff, and less die drift. High filler content (e.g., 85 weight percent) in the EMC material may reduce time in mold, reduce mold shrinkage, and reduce mold warpage. Uniform filler size distribution in the EMC material may reduce flow marks and may enhance flowability. The curing temperature of the EMC material may be in the range of 125° C. to 150° C. The EMC frame 202 may be cured at the curing temperature to form an EMC matrix that laterally encapsulates each of the first semiconductor die 104 and the second semiconductor die 106. Excess portions of the EMC frame 202 may be removed from above a level including the top surfaces of the semiconductor die (104, 106) by a planarization process such as chemical mechanical polishing (CMP).

[0064] Figure 2 The semiconductor package 200 shown may be configured as a CoWoS device in which the first semiconductor die 104 may be configured as a SoC die and the second semiconductor die 106 may each be configured as an HBM die. In this regard, the first semiconductor die 104 may include a central processing unit (CPU), a memory interface, an on-chip input / output device, an input / output interface, and an auxiliary storage interface, as well as other components such as a radio modem and / or a graphics processing unit (GPU). The first semiconductor die 104 may also include digital signal processing functions, and may also include analog signal processing functions, mixed signal processing functions, and / or radio frequency signal processing functions. Each of the second semiconductor dies 106 may be configured as a high-speed computer memory interface for a 3D stacked synchronous dynamic random-access memory (SDRAM). For example, in some embodiments, the second semiconductor die 106 may include a stack formed of up to eight DRAM dies and an optional base die, which may include buffer circuitry and test logic.

[0065] The stack may be connected to a memory controller on a GPU or CPU via a substrate (e.g., a first interposer 108a). Alternatively, in other embodiments, the second semiconductor die 106 may be stacked directly on a CPU chip or a GPU chip (not shown). Within the stack, the DRAM die may be interconnected in a vertical direction via through-silicon vias (TSVs) and microbumps (also not shown). In one embodiment, the first interposer 108a may be a silicon interposer that may provide finely spaced inline structures (not shown) that may enable a short and fast electrical communication path between the first semiconductor die 104 and the second semiconductor die 106.

[0066] like Figure 2 As shown in , the first packaging substrate 110a may include a core structure 204a and various inline structures (206a1, 206a2). For example, the first packaging substrate 110a may include a first inline structure 206a1 formed below the core structure 204a and a second inline structure 206a2 formed above the core structure 204a. In this example, the core structure 204a may include two layers of electrical inlines, and the first inline structure 206a1 and the second inline structure 206a2 may each include nine layers of electrical inlines. In other embodiments, other numbers of inline layers may also be provided. The core structure 204a may include electrical inlines formed in a fiber-reinforced composite material, and the first inline structure 206a1 and the second inline structure 206a2 may each include electrical inlines formed in a polymer material.

[0067] The interconnect layer in the first packaging substrate 110a can provide electrical routing from the semiconductor die (104, 106) to the supporting substrate 102 (see, for example, Figure 1A and Figure 1B ). As mentioned above Figure 1A and Figure 1BAs described, due to the differences in relative sizes, mechanical properties and thermal expansion coefficients of various components of the semiconductor package 200, various mechanical distortions and degradations may occur in the semiconductor package 200. In this regard, the thermal stress / thermal strain generated between the first semiconductor die 104, the second semiconductor die 106, the first silicon interposer 108a and the first package substrate 110a may result in delamination / cracks of the first bottom filling material portion 122 and the multi-die EMC frame 202, cracks in the metal bumps (120, 124), etc. In addition, in some cases, the surface roughness of the second interconnect structure 206a2 may result in mechanically weak and / or poor electrical connection between the first package substrate 110a and the first interposer 108a, which may result in short circuit / open circuit phenomena and / or insertion loss, especially at high signal frequencies. As described below with reference to Figures 3 to 22 As described in more detail, various embodiments of the interposer structure (eg, the second interposer 108 b ) may alleviate some or all of these issues.

[0068] Figure 3 1 is another semiconductor package 300 including a second interposer 108b having a plurality of first redistribution layers 302a and a plurality of second redistribution layers 302b according to various embodiments. The semiconductor package 300 may include a first semiconductor die 104 and a second semiconductor die 106 electrically and mechanically connected to the second interposer 108b by a plurality of metal bumps 120 (e.g., microbumps). The semiconductor package 300 may include a first underfill material portion 122 disposed in a space separating the first semiconductor die 104 and the second semiconductor die 106 laterally, and a multi-die EMC frame 202 partially surrounding the first semiconductor die 104 and the second semiconductor die 106. The second interposer 108b may be electrically and mechanically connected to a second package substrate 110b using a plurality of metal bumps 124 (e.g., C4 solder bumps). A second underfill material portion 128 may be provided in the space surrounding the metal bump 124 and between the bottom surface of the second interposer 108b and the upper surface of the second packaging substrate 110b. The second packaging substrate 110b may also include a plurality of solder balls (or bump structures) 112 so that the second packaging substrate 110b may be electrically and mechanically connected to the support substrate 102 (e.g., see Figure 1B ).like Figure 3 As shown in FIG. 1 , one or more integrated passive devices 301 may also be electrically and mechanically bonded to the second interposer 108 b .

[0069] As in Figure 2In the exemplary semiconductor package 200 shown, the semiconductor package 300 may be configured as a CoWoS device, in which the first semiconductor die 104 may be configured as a SoC die, and the second semiconductor die 106 may be configured as an HBM die. Figure 2 The semiconductor package 200 shown is different. Figure 3 The second interposer 108b may have Figure 2 The electrical properties and mechanical properties of the silicon first interposer 108a of the semiconductor package 200 shown are different from the electrical properties and mechanical properties of the silicon first interposer 108a of the semiconductor package 200. In this regard, in contrast to the silicon first interposer 108a of the semiconductor package 200, each of the plurality of first redistribution layers 302a and the plurality of second redistribution layers 302b can be formed in one or more polymer materials that can allow for increased elastic deformation. The increased elastic deformation can thereby reduce thermal stress / thermal strain between the second interposer 108b and the second package substrate 110b and between the second interposer 108b and other components of the semiconductor package 300 (including the first semiconductor die 104, the second semiconductor die 106 and the EMC frame 202). In this way, Figure 3 The illustrated second interposer 108b may alleviate issues associated with thermally induced deformation, warping, cracking, delamination, and the like.

[0070] The plurality of first redistribution layers 302a may include a first electrical interconnect structure 304a having a fine line width and line spacing, and the plurality of second redistribution layers 302b may include a second electrical interconnect structure 304b having a larger line width and line spacing. In this regard, the first electrical interconnect structure 304a may have a first line width between 1 micron and 5 microns and a first line spacing between 1 micron and 5 microns. The second electrical interconnect structure 304b may have a second line width between 8 microns and 50 microns and a second line spacing between 8 microns and 50 microns. In various embodiments, the first electrical interconnect structure 304a may include a first thickness between 1 micron and 5 microns, and the second electrical interconnect structure 304b may include a second thickness between 5 microns and 18 microns. In various embodiments, the plurality of first redistribution layers 302a may include two to six layers of first electrical interconnect structures 304a embedded in the first dielectric material 306a, and the plurality of second redistribution layers 302b may include four to eight layers of second electrical interconnect structures 304b embedded in the second dielectric material 306b. Other embodiments may also include various other numbers of first electrical interconnect structures 304a and second electrical interconnect structures 304b.

[0071] The plurality of first redistribution layers 302a may provide Figure 2The silicon first interposer 108a of the semiconductor package 200 shown in FIG. 2 provides some functionality, while the plurality of second redistribution layers 302b can provide functionality that would otherwise be provided by Figure 2 The first package substrate 110a of the semiconductor package 200 is shown to provide some functionality. In this regard, the plurality of first redistribution layers 302a can be configured to provide a high-speed die-to-die channel between the first semiconductor die 104 and the second semiconductor die 106, and the plurality of second redistribution layers 302b can be configured to provide a high-speed die-to-die channel with respect to the first semiconductor die 104 and the second semiconductor die 106. Figure 2 The plurality of second redistribution layers 302b may also be configured such that the plurality of metal bumps 124 may have a power delivery channel enhanced relative to the power delivery channel of the first interposer 108a of silicon of the semiconductor package 200. Figure 2 The pitch of the corresponding metal bumps 124 of the semiconductor package 200 is loose (ie, larger) than that of the metal bumps 124 of the semiconductor package 200 shown. Figure 4A and Figure 4B In more detail, Figure 3 The second package substrate 110b of the semiconductor package 300 may have a relatively Figure 2 The structure of the first package substrate 110 a of the semiconductor package 200 is shown to be simpler (eg, having fewer interconnect layers).

[0072] The first electrical interconnect structures 304a of the plurality of first redistribution layers 302a may be embedded in the first dielectric material 306a, and the second electrical interconnect structures 304b of the plurality of second redistribution layers 302b may be embedded in the second dielectric material 306b. According to various embodiments, the first dielectric material 306a may include a first polymer, and the second dielectric material 306b may include an inorganic particulate material dispersed in the second polymer. The first polymer may include one of polyimide (PI), benzocyclobutene (BCB), polybenzobisoxazole (PBO), or any polymer material having similar properties. The second polymer may include a polymer resin (e.g., epoxy resin, cyanate ester, etc.), and the inorganic particulate material may include silicon dioxide powder or other similar particulate materials. Each of the first dielectric material 306a and the second dielectric material 306b can be configured to enable the formation of redistribution layer vias and redistribution layer traces using a process that allows the dielectric materials (306a, 306b) to be photolithographically patterned, etched (and / or laser drilled), and electroplated to form conductive traces and conductive vias. The first dielectric material 306a can be configured to enable the formation of fine features, and the second dielectric material 306b can be configured to enable the formation of larger features.

[0073] The first dielectric material 306a can be configured to have a greater elasticity than the second dielectric material 306b. As such, the second dielectric material 306b can be a stronger material (eg, having a greater modulus), which can be used to strengthen the central region of the second interposer 108b. Figure 2 The core structure 204a of the first package substrate 110a can strengthen the first package substrate 110a in a similar manner. In contrast, the first dielectric material 306a of the plurality of first redistribution layers 302a can allow for relatively large elastic deformations, which can be used to reduce thermal stress / strain at the interface between the second interposer 108b and other components of the semiconductor package 300 (including the first semiconductor die 104, the second semiconductor die 106, the first underfill material portion 122, and the EMC frame 202).

[0074] like Figure 3 As shown in , the first electrical interconnect structure 304a can be electrically connected to the second electrical interconnect structure 304b, so that the second interposer 108b has a flat plate geometry having a first surface 308a and a second surface 308b parallel to the first surface 308a. The first surface 308a may include an electrical micro-bump structure (e.g., a metal bump 120), which can be electrically connected to the first electrical interconnect structure 304a of the plurality of first redistribution layers 302a. Similarly, the second surface 308b may include an electrical bonding pad structure 310, which is electrically connected to the second electrical interconnect structure 304b of the plurality of second redistribution layers 302b. The second interposer 108b may also include a protective layer 312, which is formed on the first surface 308a, so that the protective layer 312 is formed on the plurality of first redistribution layers 302a and partially surrounds the electrical micro-bump structure 120. The protection layer 312 may be formed of the second dielectric material 306 b to thereby strengthen the interface between the second interposer 108 b and other components of the semiconductor package 300 , including the first semiconductor die 104 , the second semiconductor die 106 , the first underfill material portion 122 , and the EMC frame 202 .

[0075] The plurality of second redistribution layers 302b may further include a surface layer 314, which is formed proximate to the second surface 308b of the second interposer 108b, such that the surface layer 314 may partially surround the electrical bonding pad structure 310. The surface layer 314 may be formed of the first dielectric material 306a, which, as described above, may have greater elasticity than the second dielectric material 306b. As such, the surface layer 314 may allow for a greater degree of elastic deformation than the elastic deformation of the second dielectric material 306b. Such elastic deformation may thereby reduce thermally induced stress / strain that may otherwise occur between the second interposer 108b and the second packaging substrate 110b.

[0076] Figure 4A According to various embodiments Figure 2 The vertical cross-sectional view of the first package substrate 110a of the semiconductor package 200 is shown, and Figure 4B According to various embodiments, Figure 3 FIG. 1 is a vertical cross-sectional view of a second package substrate 110 b used in the semiconductor package 300. As described above, Figure 3 The second package substrate 110b of the semiconductor package 300 may have a relatively Figure 2 The structure of the semiconductor package 200 shown is a simpler structure. In this regard, as described above with reference to Figure 3 As described above, due to the presence of the plurality of second redistribution layers 302b, Figure 3 The second interposer 108b shown may provide some functionality that is otherwise provided by the first packaging substrate 110a. In this way, some second redistribution layers 302b of the second interposer 108b may eliminate the need for some electrical interconnects of the first packaging substrate 110a, thereby enabling the second packaging substrate 110b to have fewer electrical interconnect layers.

[0077] Each of the first packaging substrate 110a and the second packaging substrate 110b may include a corresponding core structure (204a, 204b), and the core structures may each have a similar structure (e.g., two or more electrical interconnect layers). Similarly, each of the first packaging substrate 110a and the second packaging substrate 110b may include a corresponding first interconnect structure (206a1, 206b1) formed below the corresponding core structure (204a, 204b) and a corresponding second interconnect structure (206a2, 206b2) formed above the corresponding core structure (204a, 204b). However, as Figure 4B As shown in FIG. 1 , the first and second interline structures 206 b 1 and 206 b 2 of the second packaging substrate 110 b may include fewer electrical interline layers than the corresponding first and second interline structures 206 a 1 and 206 a 2 of the first packaging substrate 110 a .

[0078] For example, the first inline structure 206a1 and the second inline structure 206a2 of the first packaging substrate 110a may each include nine inline layers, whereas the corresponding first inline structure 206b1 and the second inline structure 206b2 of the second packaging substrate 110b may each include three inline layers. In other embodiments, various other numbers of inline layers may be formed in the first packaging substrate 110a and the second packaging substrate 110b, but in general, when used in conjunction with the second interposer 108b, the second packaging substrate 110b may have fewer inline layers than the first packaging substrate 110a. A semiconductor package (e.g., semiconductor package 300) including a simplified packaging substrate (e.g., second packaging substrate 110b) may exhibit reduced thermally induced deformation, warping, cracking, delamination, etc., and may therefore embody Figure 3 The semiconductor package 300 is shown relative to Figure 2 A further improvement of the semiconductor package 200 is shown.

[0079] Figure 5 3 is a vertical cross-sectional view of an intermediate structure 500 that can be used to form a semiconductor package 300 according to various embodiments. In a first operation, a protective layer 312 can be formed over a first carrier substrate 502a. In this regard, a layer of a second dielectric material 306b can be removably attached to the first carrier substrate 502a using an adhesive (not shown). The adhesive can be selected to have a material composition that enables deactivation by applying heat or ultraviolet radiation so that the adhesive can be deactivated, thereby allowing the first carrier substrate 502a to be removed in a subsequent processing operation.

[0080] As described above, the second dielectric material 306b may include an inorganic particulate reinforcing phase formed in a polymer resin material. The second dielectric material 306b may be provided as a film in an uncured state, the film including one or more resins (e.g., epoxy resin, cyanate ester), a hardener, and a filler. The film may be bonded to the first carrier substrate 502a using the above-mentioned adhesive. The film may then be cured by subjecting the film to an annealing process in which the film is subjected to a high temperature for a specific period of time. For example, the film may be maintained at a temperature between 100°C and 200°C for 15 minutes to 60 minutes. For example, a first annealing process may be performed at 100°C for 30 minutes, followed by a second annealing process at 200°C for 30 minutes. The one or more annealing processes may be used to cause cross-linking to thereby cure the second polymer (i.e., the second polymer of the second dielectric material 306b) to thereby form the protective layer 312.

[0081] The protective layer 312 may then be patterned to form a via hole (not shown), which may then be filled with a conductive material to form the electrical micro-bump structure 120 described above. In an exemplary embodiment, a laser drilling process may be performed to produce a via hole (not shown) in the protective layer 312. The laser drilling process may remove a portion of the protective layer 312 so that the hole may extend through the protective layer. The electrical micro-bump structure 120 may then be formed by filling the via hole with a conductive material (e.g., copper) using a deposition process (e.g., electroplating). Other suitable conductive materials and deposition processes are also within the scope of the envision of the embodiments of the present invention. In various embodiments, a seed layer (e.g., a Ti / Cu layer) may be deposited (e.g., by sputtering) before depositing the conductive material.

[0082] Figure 6 is a vertical cross-sectional view of yet another intermediate structure 600 that may be used to form the semiconductor package 300 according to various embodiments. Figure 5 The intermediate structure 500 is shown to form the intermediate structure 600 by forming the plurality of first redistribution layers 302a on the protective layer 312. Each of the plurality of first redistribution layers 302a can be formed by performing a plurality of operations. In a first operation, a layer of a first dielectric material 306a can be formed on the protective layer 312 when forming an initial layer, or a layer of a first dielectric material 306a can be formed on a previous layer when forming a subsequent layer of the plurality of first redistribution layers 302a. As described above, the first dielectric material 306a can include a first polymer, which can include PI, BCB, PBO, or any polymer material having similar properties. A spin-coating process can be performed to produce a layer of the first polymer. In various embodiments, the layer of the first polymer can have a thickness between 4 microns and 7 microns.

[0083] In yet another operation, a patterned photoresist (not shown) may be formed over the layer of first polymer. The patterned photoresist may be formed by forming a blanket layer of photoresist material and then patterning the photoresist using photolithography techniques. In yet another operation, the patterned photoresist may be used to etch the first polymer to form a patterned first polymer layer including features (e.g., via holes), which may then be filled with a conductive material to form a portion of the first electrical interconnect structure 304a. In yet another operation, the patterned photoresist may be removed (e.g., by dissolving with a solvent, or by dry film stripping), and a seed layer (e.g., a Ti / Cu seed layer) may be formed (e.g., by sputtering) over the patterned first polymer layer.

[0084] In another operation, another patterned photoresist (e.g., including features corresponding to line traces) may be formed, and a first electrical interconnect structure 304a may be formed by depositing (e.g., by electroplating) a conductive material (e.g., Cu, Ni, etc.) on the patterned photoresist and the first polymer layer. In another operation, the patterned photoresist may be removed (e.g., by dissolving with a solvent, or by dry film stripping), and the seed layer may be removed (e.g., by etching). The above operations may be repeated multiple times to generate corresponding other first redistribution layers 302a. Figure 6 As shown in FIG. 1 , when the top layer of the plurality of first redistribution layers 302a is produced, larger conductive features (eg, conductive lines 304b1) may be formed that may serve as the first layer of the plurality of second electrical interconnect structures 304b of the second redistribution layer 302b.

[0085] Figure 7 is a vertical cross-sectional view of yet another intermediate structure 700 that may be used to form the semiconductor package 300 according to various embodiments. Figure 6 The intermediate structure 600 is formed by forming the first second redistribution layer 302b of the plurality of second redistribution layers 302b on the plurality of first redistribution layers 302a to form the intermediate structure 700. In this regard, a layer of second dielectric material 306b may be formed on the plurality of first redistribution layers 302a. Figure 6 As described, the top layer of the plurality of first redistribution layers 302a may include conductive lines 304b1, which may form the lowest level of the second electrically interconnected structure 304b. As shown, the second electrically interconnected structure 304b may include conductive lines 304b1 and electrically conductive vias 304b2.

[0086] Each of the plurality of second redistribution layers 302b may be formed by performing a plurality of operations. In a first operation, when forming an initial layer, a layer of second dielectric material 306b may be formed on a top layer of the plurality of first redistribution layers 302a, or when forming a subsequent layer of the plurality of second redistribution layers 302b, a layer of second dielectric material 306b may be formed on a previous layer. Figure 5 As described, the second dielectric material 306b may include an inorganic particulate reinforcement phase formed in a polymer resin material. The second dielectric material 306b may be provided as a film in an uncured state, the film comprising one or more resins (e.g., epoxy resin, cyanate ester), a hardener, and a filler. The film may be placed on a previous layer (e.g., placed on a top layer of the plurality of first redistribution layers 302a when forming an initial layer, or placed on a previously formed layer of the plurality of second redistribution layers 302b), and the film may be subjected to a first annealing process. For example, the first annealing process may be performed at 100°C for 30 minutes. The first annealing process may soften the second dielectric material 306b without curing / crosslinking the second dielectric material 306b, thereby enabling the second dielectric material 306b to conform to an underlying structure (e.g., a conductive line 304b1 of an underlying layer). Then, a second annealing process may be performed, for example, at 200° C. for 30 minutes, to thereby cure / cross-link the second dielectric material 306 b .

[0087] In yet another operation, a laser drilling operation may be performed to produce a via hole (not shown), which may then be filled with a conductive material to form a via 304b2. In yet another operation, a seed layer (e.g., a Ti / Cu seed layer) may be formed over the second dielectric material 306b and within the via hole. In yet another operation, a patterned photoresist may be formed over the seed layer. The patterned photoresist may be formed by forming a blanket layer formed of a photoresist and patterning the photoresist using a photolithography technique. The patterned photoresist may be used to define a line structure, which may then be filled with a conductive material (e.g., Ni, Cu, etc.) to form a conductive line 304b1. The opening of the patterned photoresist may be located over the previously formed via hole, so that when the conductive material is deposited, the conductive line 304b1 and the via 304b2 may be formed in a single operation and may be electrically connected to each other. In yet another operation, a conductive material (e.g., Ni, Cu, etc.) may be deposited (e.g., by electroplating) to thereby fill the patterned portions of the patterned photoresist to thereby form conductive lines 304b1 and vias 304b2. In yet another operation, the patterned photoresist may be removed (e.g., by dissolving with a solvent, or by dry film stripping), and the seed layer may be removed (e.g., by etching). The above operations may be repeated multiple times to generate corresponding additional layers of the plurality of second redistribution layers 302b, such as, for example, in Figure 8 and Fig. 9 as shown in .

[0088] Figure 8 is a vertical cross-sectional view of yet another intermediate structure 800 that may be used to form the semiconductor package 300 according to various embodiments. Figure 7 The intermediate structure 700 shown is repeated above with reference to Figure 7 The operations described above are to generate additional layers of the plurality of second redistribution layers 302b to form the intermediate structure 800. In this example, Figure 8 An intermediate structure 800 is shown, and the intermediate structure 800 includes a Figure 7 In various embodiments, the plurality of second redistribution layers 302b may be provided with three additional layers above the first layer of the plurality of second redistribution layers 302b, for a total of four layers. Figure 8 The additional layers of the plurality of second redistribution layers 302b are formed on the intermediate structure 800. Alternatively, or in addition to forming the additional layers, as described below with reference to Fig. 9 A more detailed description can also be found in Figure 8 The intermediate structure 800 is shown with a surface layer 314 formed thereon (see, for example, Figure 3 ).

[0089] Fig. 9 is a vertical cross-sectional view of yet another intermediate structure 900 that may be used to form the semiconductor package 300 according to various embodiments. Figure 8 The intermediate structure 800 shown is obtained by using the same Figure 6 The surface layer 314 is formed by techniques similar to those described above to form the intermediate structure 900. In this regard, two additional layers of the plurality of second redistribution layers 302b may be embedded within the first dielectric material 306a. Figure 3 As described, the use of the first dielectric material 306a can enable the surface layer 314 to have a greater degree of elasticity relative to the harder second dielectric material 306b. The surface layer 314 can be formed using operations similar to those used to form the plurality of first redistribution layers 302a. For example, a first polymer (e.g., PI, BCB, PBO, etc.) can be formed by a spin coating process. A patterned photoresist can then be formed over the first polymer layer, and the patterned photoresist can be used to etch the first polymer to form a through-hole (not shown). The patterned photoresist can then be removed, and a seed layer can be formed.

[0090] In yet another operation, yet another patterned photoresist (e.g., including features corresponding to the traces) may be formed, and additional second electrical interconnect structures 304b may be formed by depositing (e.g., by electroplating) a conductive material (e.g., Cu, Ni, etc.) over the patterned photoresist and the first polymer layer. In yet another operation, the patterned photoresist may be removed (e.g., by dissolving with a solvent, or by dry film stripping), and the seed layer may be removed (e.g., by etching). The above operations may be repeated multiple times to produce corresponding additional layers of the surface layer 314. In this exemplary embodiment, the surface layer 314 is shown as having two layers of second electrical interconnect structures 304b, but various numbers of additional layers of second electrical interconnect structures 304b may also be provided in other embodiments. In addition, as Fig. 9 As shown in FIG. 3 , in the last layer of the surface layer 314, an electrical bonding pad structure 310 may be formed, and the electrical bonding pad structure 310 may be electrically connected to the second electrical interconnect structure 304b of the plurality of second redistribution layers 302b. The electrical bonding pad structure 310 may be formed by filling (e.g., by electroplating) corresponding features in a patterned photoresist by performing operations similar to those described above.

[0091] Fig.10 is a vertical cross-sectional view of yet another intermediate structure 1000 that may be used to form the semiconductor package 300 according to various embodiments. Fig. 9 The intermediate structure 900 is shown to form the intermediate structure 1000 by attaching the second carrier substrate 502b to the surface layer 314 and electrically bonding the pad structure 310, removing the first carrier substrate 502a, and inverting the resulting structure. In this regard, the second carrier substrate 502b can be removably attached using an adhesive 1002, which can be selected to have a material composition that allows deactivation by applying heat or ultraviolet radiation so that the adhesive can be deactivated, thereby enabling the second carrier substrate 502b to be removed in a subsequent processing operation. Similarly, the first carrier substrate 502a can be removed by applying a heat treatment or by applying ultraviolet radiation to deactivate the adhesive (not shown) between the first carrier substrate 502a and the protective layer 312. Once the adhesive has been deactivated, the first carrier substrate 502a can be removed.

[0092] Fig.11 is a vertical cross-sectional view of yet another intermediate structure 1100 that may be used to form the semiconductor package 300 according to various embodiments. Fig.10The intermediate structure 1000 is formed by forming an additional bonding structure 1102 (e.g., a C4 bump 1102) on the electrical micro-bump structure 120. In this regard, the additional bonding structure 1102 may include a micro-pillar 1102a and a solder cap 1102b. As shown, the first semiconductor die 104 and the second semiconductor die 106 may then be positioned relative to the bonding structure 1102 so that the bonding structure 1102 may be aligned with the corresponding bonding structure 1104 of the first semiconductor die 104 and the second semiconductor die 106.

[0093] Fig.12 is a vertical cross-sectional view of yet another intermediate structure 1200 that may be used to form the semiconductor package 300 according to various embodiments, and Fig.13 is a vertical cross-sectional view of yet another intermediate structure 1300 that may be used to form the semiconductor package 300 according to various embodiments. Fig.11 The intermediate structure 1100 is formed by contacting the bonding structures 1104 of the first semiconductor die 104 and the second semiconductor die 106 with the corresponding additional bonding structures 1102 of the second interposer 108b and performing a reflow operation. Fig.12 The intermediate structure 1200 is shown. The reflow operation can melt the solder cap 1102b of the additional bonding structure 1102 and form mechanical and electrical bonds between the second interposer 108b and the first semiconductor die 104 and between the second interposer 108b and the second semiconductor die 106 upon cooling.

[0094] Then, you can Fig.12 The intermediate structure 1200 is formed by forming a first bottom filling material portion 122 Fig.13 In the intermediate structure 1300 shown, the first underfill material portion 122 is disposed in the space separating the first semiconductor die 104 and the second semiconductor die 106 in the lateral direction, in the space between the first semiconductor die 104 and the second interposer 108 b, and in the space between the second semiconductor die 106 and the second interposer 108 b. Then, the multi-die EMC frame 202 may be formed to, for example, partially surround the first semiconductor die 104 and the second semiconductor die 106, as described in more detail above.

[0095] Fig.14 is a vertical cross-sectional view of yet another intermediate structure 1400 that may be used to form the semiconductor package 300 according to various embodiments. Fig.13The intermediate structure 1300 is shown by attaching a third carrier substrate 502c to the top surface of the intermediate structure 1300 (e.g., including the top surface of the first semiconductor die 104 and the second semiconductor die 106), removing the second carrier substrate 502b, and inverting the resulting structure to form the intermediate structure 1400. In this regard, the third carrier substrate 502c can be removably attached using an adhesive 1002, which can be selected to have a material composition that can be deactivated by applying heat or ultraviolet radiation so that the adhesive can be deactivated, thereby allowing the third carrier substrate 502c to be removed in a subsequent processing operation. Similarly, the second carrier substrate 502b can be removed by applying a heat treatment or applying ultraviolet radiation to deactivate the adhesive 1002 between the second carrier substrate 502b and the surface layer 314. Once the adhesive has been deactivated, the second carrier substrate 502b can be removed.

[0096] Fig.15 is a vertical cross-sectional view of yet another intermediate structure 1500 that may be used to form the semiconductor package 300 according to various embodiments, and Fig.16 is a vertical cross-sectional view of yet another intermediate structure 1600 that can be used to form the semiconductor package 300 according to various embodiments. Fig.14 The intermediate structure 1400 is formed by attaching the integrated passive device 301 to the second intermediate layer 108b to form the intermediate structure 1500. Fig.15 The intermediate structure 1500 is formed by attaching the second packaging substrate 110b to the Fig.15 The intermediate structure 1500 is formed into the intermediate structure 1600. Then, the semiconductor package 300 can be formed by removing the third carrier substrate 502c from the intermediate structure 1600. In this regard, the third carrier substrate 502c can be removed by applying a heat treatment or by applying ultraviolet radiation to deactivate the adhesive 1002. Once the adhesive has been deactivated, the third carrier substrate 502c can be removed. In various embodiments, as described below with reference to Figures 17 to 19B As described in more detail, the second packaging substrate 110b may have Figure 4B Simplified structure of the description.

[0097] Fig.17 1 is a vertical cross-sectional view of yet another intermediate structure 1700 that can be used to form the semiconductor package 300. Fig.17 As shown in, for example, the above reference Figures 5 to 14 The method described forms a plurality of intermediate structures 1400 on the third carrier substrate 502c (see Fig.14 Similarly, a plurality of second packaging substrates 110 b may be formed separately and positioned above the corresponding plurality of intermediate structures 1400 .

[0098] Fig.18 1 is a vertical cross-sectional view of yet another intermediate structure 1800 that may be used to form the semiconductor package 300 according to various embodiments. Fig.18 As shown in, you can Fig.17 The intermediate structure 1700 shown is formed by attaching the plurality of second packaging substrates 110b to the corresponding intermediate structure 1400 to form an intermediate structure 1800. In this regard, the second interposer 108b can be electrically and mechanically connected to a second packaging substrate 110b having a plurality of metal bumps 124 (e.g., C4 solder bumps), and the metal bumps 124 are reflowed to form electrical and mechanical connections by performing a reflow operation. A second bottom fill material portion 128 can be provided in the space surrounding the metal bumps 124 and between the bottom surface of the second interposer 108b and the upper surface of the second packaging substrate 110b. A dicing frame (not shown) can then be attached to the intermediate structure 1800, and the third carrier substrate 502c can be removed. The intermediate structure 1800 can then be singulated / diced along the dicing streets / dicing channels 1802 to produce further semiconductor packages (300a, 300b), as described below with reference to Fig.19A and Fig.19B More detailed description.

[0099] Fig.19A is a vertical cross-sectional view of an embodiment semiconductor package 300a according to various embodiments, and Fig.19B 1 is a vertical cross-sectional view of another embodiment of a semiconductor package 300b according to various embodiments, wherein the semiconductor packages 300a and 300b are each formed by dicing the intermediate structure 1800. Fig.19A As shown in , after the intermediate structure 1800 is cut, the second package substrate 110b may have a width 1902 that may be less than the width 1904 of the second interposer 108b. Alternatively, after the cutting, the second embodiment semiconductor package 300b may be further trimmed so that the width 1902 of the second package substrate 110b is approximately equal to the width 1904 of the second interposer 108b. In other embodiments, the second embodiment semiconductor package 300b may be trimmed as shown below with reference to Figure 20 to Figure 22 The semiconductor package 300 c is formed in which the width 1902 of the second package substrate 110 b is greater than the width 1904 of the second interposer 108 b .

[0100] Fig. 20 is a vertical cross-sectional view of yet another intermediate structure 2000 that may be used to form a semiconductor package 300c according to various embodiments, and Fig.21 is a vertical cross-sectional view of yet another intermediate structure 2100 that may be used to form a semiconductor package 300 c according to various embodiments. Fig. 22Can be distinguished from Fig. 20 and Fig.21 The vertical cross-sectional view of the semiconductor package 300c formed by the intermediate structures 2000 and 2100 is shown. Fig.14 The intermediate structure 1400 is shown as being formed by forming an additional bonding structure 2002 (eg, a C4 bump) on the intermediate structure 1400 so that the additional bonding structure 2002 is mechanically and electrically connected to the second electrical interconnect structure 304 b .

[0101] Then, the intermediate structure 2000 may be formed by removing the third carrier substrate 502c from the intermediate structure 2000 and positioning the resulting structure on a separately formed second packaging substrate 110b. Fig.21 The intermediate structure 2100 is shown. Fig.21 As shown in , the width 1902 of the second package substrate 110b can be greater than the width 1904 of the second interposer 108b. Then, the semiconductor package 300c can be formed from the intermediate structure 2100 by attaching the second interposer 108b to the second package substrate 110b by performing a reflow operation to form an electrical and mechanical connection between the additional bonding structure 2002 of the second interposer 108b and the second package substrate 110b. Then, the semiconductor package 300c can be formed as shown in FIG. Fig. 22 As shown in FIG. 2 , a second underfill material portion 128 is provided in the space surrounding the additional bonding structure 2002 and between the bottom surface of the second interposer 108 b and the upper surface of the second packaging substrate 110 b .

[0102] Fig.23 2 is a flow chart illustrating various operations of a method 2300 of forming an interposer (e.g., a second interposer 108b) according to various embodiments. In operation 2302, the method 2300 may include forming a plurality of first redistribution layers 302a on a first carrier substrate 502a, the plurality of first redistribution layers 302a including first electrical interconnect structures 304a having a first line width and a first line spacing embedded in a first dielectric material 306a. In operation 2304, the method 2300 may include forming a plurality of second redistribution layers 302b on the plurality of first redistribution layers 302a, the plurality of second redistribution layers 302b including second electrical interconnect structures 304b having a second line width and a second line spacing embedded in a second dielectric material 306b. In various embodiments, the second line width may be greater than the first line width, and the second line spacing may be greater than the first line spacing.

[0103] In operation 2306, method 2300 may include forming a plurality of electrical bonding pad structures 310, the plurality of electrical bonding pad structures 310 may be electrically connected to the second electrical interconnect structures 304b of the plurality of second redistribution layers 302b. In operation 2308, method 2300 may include attaching a second carrier substrate 502b over the plurality of electrical bonding pad structures 310 and removing the first carrier substrate 502a. In operation 2310, method 2300 may include forming electrical micro-bump structures (120, 1102), the electrical micro-bump structures (120, 1102) may be electrically connected to the first electrical interconnect structures 304a of the plurality of first redistribution layers 302a. According to the method 2300, the operation 2302 of forming the plurality of first redistribution layers 302a may further include embedding the first electrical interconnect structure 304a in one of polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). According to the method 2300, the operation 2304 of forming the plurality of first redistribution layers 302a may further include embedding the second electrical interconnect structure 304b in an inorganic particulate material dispersed in an epoxy resin.

[0104] According to the method 2300, the operation 2302 of forming the plurality of first redistribution layers 302a may further include forming a protective layer 312 on the plurality of first redistribution layers 302a, such that the protective layer 312 partially surrounds the electrical micro-bump structure (120, 1102). According to various embodiments, the protective layer 312 may be formed of a second dielectric material 306b. According to the method 2300, the operation 2304 of forming the plurality of second redistribution layers 302b may further include forming a surface layer 314 on the plurality of second redistribution layers 302b, such that the surface layer 314 partially surrounds the plurality of electrical bonding pad structures 310. According to various embodiments, the surface layer 314 may be formed of a first dielectric material 306a.

[0105] With reference to all the drawings and according to various embodiments of the present invention, a semiconductor package (300, 300a, 300b, 300c) is provided. The semiconductor package (300, 300a, 300b, 300c) may include an interposer 108b, the interposer 108b may include a plurality of first redistribution layers 302a and a plurality of second redistribution layers 302b, the plurality of first redistribution layers 302a including a first electrical interconnect structure 304a having a first line width and a first line spacing embedded in a first dielectric material 306a, the plurality of second redistribution layers 302b including a second electrical interconnect structure 304b having a second line width and a second line spacing embedded in a second dielectric material 306b.

[0106] In various embodiments, the second line width may be greater than the first line width, and the second line spacing may be greater than the first line spacing. For example, in some embodiments, the first line width may be between 1 micron and 5 microns, and the first line spacing may be between 1 micron and 5 microns. Furthermore, in some embodiments, the second line width may be between 8 microns and 50 microns, and the second line spacing may be between 8 microns and 50 microns. In some embodiments, the first electrical interconnect structure 304a may have a first thickness that may be between 1 micron and 5 microns, and the second electrical interconnect structure 304b may have a second thickness that may be between 5 microns and 18 microns.

[0107] In various embodiments, the first dielectric material 306a may include a first polymer, and the second dielectric material 306b may include an inorganic particulate material dispersed in the second polymer. In some embodiments, the plurality of first redistribution layers 302a may include two to six first electrical interconnect structures 304a embedded in the first dielectric material 306a, and the plurality of second redistribution layers 302b may include four to eight second electrical interconnect structures 304b embedded in the second dielectric material 306b. In addition, in some embodiments, the first polymer may include one of PI, BCB, or PBO, and the second polymer may include epoxy resin. The inorganic particulate material may include silicon dioxide powder.

[0108] In various embodiments, the semiconductor package (300, 300a, 300b, 300c) may further include a semiconductor die (104, 106) electrically connected to the interposer 108b. In various embodiments, the first electrical interconnect structure 304a may be electrically connected to the second electrical interconnect structure 304b, such that the interposer 108b may have a planar geometry having a first surface 308a and a second surface 308b that may be parallel to the first surface 308a (e.g., see Figure 3 The first surface 308a may include an electrical micro-bump structure (120, 1102) electrically connected to the first electrical interconnect structure 304a of the plurality of first redistribution layers 302a, and the second surface 308b may include an electrical bonding pad structure 310 electrically connected to the second electrical interconnect structure 304b of the plurality of second redistribution layers 302b. In addition, the semiconductor die (104, 106) may be electrically connected to the electrical micro-bump structure.

[0109] According to various embodiments, the interposer 108b may further include a protective layer 312 formed on the first surface 308a, such that the protective layer 312 may be formed on the plurality of first redistribution layers 302a and may partially surround the electrical micro-bump structure (120, 1102). In various embodiments, the protective layer 312 may be formed of a second dielectric material 306b. In yet other embodiments, the plurality of second redistribution layers 302b may further include a surface layer 314 formed proximate to the second surface 308b of the interposer 108b, such that the surface layer 314 partially surrounds the electrical bonding pad structure 310. The surface layer 314 may be formed of a first dielectric material 306a.

[0110] According to yet another embodiment, a semiconductor package (300, 300a, 300b, 300c) is provided. The semiconductor package (300, 300a, 300b, 300c) may include an interposer 108b having a planar geometry including a first surface 308a and a second surface 308b. The interposer 108b may also include a plurality of first redistribution layers 302a, the plurality of first redistribution layers 302a including a first electrical interconnect structure 304a formed in a first dielectric material 306a near the first surface 308a. The interposer 108b may also include a plurality of second redistribution layers 302b, the plurality of second redistribution layers 302b including a second electrical interconnect structure 304b formed in a second dielectric material 306b near the second surface 308b. In various embodiments, the first dielectric material 306a may have greater elasticity than the second dielectric material 306b. In some embodiments, the plurality of second redistribution layers 302b may further include a surface layer 314 including the first dielectric material 306a, the surface layer 314 being formed close to the second surface 308b of the interposer 108b such that the surface layer 314 partially surrounds the second electrical interconnect structure 304b.

[0111] In various embodiments, the plurality of first redistribution layers 302a may have a first line width between 1 micron and 5 microns and a first line spacing between 1 micron and 5 microns. Similarly, the second redistribution layer 302b may have a second line width between 8 microns and 50 microns and a second line spacing between 8 microns and 50 microns. According to various embodiments, the first dielectric material 306a may include a first polymer, the first polymer being one of PI, BCB or PBO, and the second dielectric material 306b may include an inorganic particulate material dispersed in an epoxy resin.

[0112] According to various embodiments, the semiconductor package (300, 300a, 300b, 300c) may further include a semiconductor die (104, 106). In addition, in some embodiments, the first surface 308a of the interposer 108b may include an electrical micro-bump structure (120, 1102) electrically connected to the first electrical interconnect structure 304a of the plurality of first redistribution layers 302a. Similarly, the second surface 308b of the interposer 108b may include an electrical bonding pad structure 310 electrically connected to the second electrical interconnect structure 304b of the plurality of second redistribution layers 302b. According to various embodiments, in various embodiments, the semiconductor die (104, 106) may be electrically connected to the electrical micro-bump structure (120, 1102).

[0113] In some embodiments, the semiconductor package (300, 300a, 300b, 300c) may further include a protective layer 312 formed on the first surface 308a, such that the protective layer 312 is formed on the plurality of first redistribution layers 302a and partially surrounds the electrical micro-bump structure (120, 1102). The protective layer 312 may be formed of a second dielectric material 306b. In various embodiments, the semiconductor package (300, 300a, 300b, 300c) may further include a package substrate (e.g., a second package substrate 110b) electrically connected to the electrical bonding pad structure 310 of the interposer 108b.

[0114] The disclosed interposer 108b may be advantageous by providing a plurality of first redistribution layers 302a and a plurality of second redistribution layers 302b. The first redistribution layers 302a may include a first electrical interconnect structure 304a having a fine line width and line spacing, the first electrical interconnect structure 304a may be configured to provide a high-speed die-to-die (D2D) channel between a first semiconductor die 104 and a second semiconductor die 106 in a semiconductor package (300, 300a, 300b, 300c), and the plurality of second redistribution layers 302b may include a second electrical interconnect structure 304b, the second electrical interconnect structure 304b may be configured to provide an enhanced power delivery channel relative to the power delivery channel of an alternative interposer. Each of the plurality of first electrical interconnect structures 304a and the plurality of second electrical interconnect structures 304b may be formed in one or more polymer materials that may allow for increased elastic deformation, which may thereby reduce thermal stress / strain between components of the semiconductor package (300, 300a, 300b, 300c), and may thus alleviate issues associated with thermally induced deformation, warping, cracking, delamination, etc. The plurality of first redistribution layers 302a may also provide some functionality that is otherwise provided by alternative interposers, and the plurality of second redistribution layers 302b may provide some functionality that is otherwise provided by alternative package substrates. As such, the package substrate 110b used in conjunction with the disclosed interposer 108b may require fewer interconnect layers, thereby reducing the complexity of the semiconductor package (300, 300a, 300b, 300c) overall relative to existing package structures.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily use the embodiments of the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A semiconductor package, characterized in that: include: The intermediary layer includes: A plurality of first redistribution layers, including a first electrical interconnect structure having a first line width and a first line spacing and embedded in a first dielectric material; as well as A plurality of second redistribution layers, including a second electrical interconnect structure having a second line width and a second line spacing and embedded in a second dielectric material, wherein the second line width is greater than the first line width, and The second line spacing is greater than the first line spacing.

2. The semiconductor package according to claim 1, wherein: The first line width is between 1 micron and 5 microns; and The first line spacing is between 1 micron and 5 microns.

3. The semiconductor package according to claim 2, wherein: The second line width is between 8 micrometers and 50 micrometers; and The second line spacing is between 8 micrometers and 50 micrometers.

4. The semiconductor package according to claim 1, wherein: The first electrical interconnect structure comprises a first thickness between 1 micrometer and 5 micrometers; and The second electrical interconnect structure includes a second thickness between 5 microns and 18 microns.

5. The semiconductor package according to claim 1, wherein: The plurality of first redistribution layers include two to six layers of the first electrical interconnect structures embedded in the first dielectric material.

6. A semiconductor package, characterized in that: include: The intermediary layer includes: A flat plate geometry comprising a first surface and a second surface; a plurality of first redistribution layers including a first electrical interconnect structure formed in a first dielectric material proximate to the first surface; a plurality of second redistribution layers including a second electrical interconnect structure formed in a second dielectric material near the second surface, The first dielectric material has greater elasticity than the second dielectric material, and The plurality of second redistribution layers further include a surface layer comprising the first dielectric material, wherein the surface layer is formed close to the second surface of the interposer, such that the surface layer partially surrounds the second electrical interconnect structure.

7. The semiconductor package according to claim 6, wherein: Also included are semiconductor dies, wherein: The first surface includes an electrical micro-bump structure electrically connected to the first electrical interconnect structures of the plurality of first redistribution layers; The second surface includes an electrical bonding pad structure electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers; and The semiconductor die is electrically connected to the electrical micro-bump structure.

8. The semiconductor package according to claim 7, wherein: The invention also includes a protection layer including the second dielectric material, wherein the protection layer is formed on the first surface, so that the protection layer is formed on the plurality of first redistribution layers and partially surrounds the electrical micro-bump structure.

9. The semiconductor package according to claim 7, wherein: Also included is a packaging substrate electrically connected to the electrical bonding pad structure of the interposer.

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