Package structure

Abstract

A package structure includes a substrate having a first surface and a second surface. The second surface is opposite to the first surface. The package structure includes a plurality of through substrate via (TSV) structures formed in a substrate. The width of the substrate through hole structure is gradually reduced from the first surface to the second surface. The package structure includes a chip bonded to the first surface of the substrate. The package structure also includes a plurality of dies bonded to the first surface of the substrate and adjacent to the chip. The package structure also includes a molding material formed between the chip and the die. In addition, the package structure includes a plurality of bump structures connected to the through substrate via structure on the second surface.

Description

Technical Field

[0001] The embodiments of the utility model relate to a packaging structure, and more particularly to a packaging structure in which a substrate is thinned after a molding material is supplied to a gap between a chip and a die. Background Art

[0002] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Individual dies are usually packaged separately. The package not only provides protection for the semiconductor device from environmental contamination, but also provides a connection interface for the semiconductor device packaged therein.

[0003] Three dimensional integrated circuit (3DIC) is the latest development in semiconductor packaging, in which multiple semiconductor dies are stacked on top of each other, such as package-on-package (PoP) and system-in-package (SiP) packaging technologies. Some 3D integrated circuits are prepared at the semiconductor wafer level by placing dies on top of dies. 3D integrated circuits offer improved integration density and other advantages, such as faster speed and higher bandwidth, due to, for example, shortened interconnect lengths between stacked dies. However, there are still many challenges associated with 3D integrated circuits. Utility Model Content

[0004] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0005] An embodiment of the utility model provides a packaging structure, including a substrate having a first surface and a second surface. The second surface is relative to the first surface. This packaging structure includes a plurality of through substrate via (TSV) structures formed in the substrate. The width of the substrate through-hole structure gradually decreases from the first surface to the second surface. The packaging structure includes a chip bonded to the first surface of the substrate. The packaging structure also includes a plurality of grains bonded to the first surface of the substrate and adjacent to the chip. The packaging structure also includes a molding material formed between the chip and the grains. In addition, the packaging structure includes a plurality of bump structures connected to the substrate through-hole structure on the second surface.

[0006] According to one embodiment of the present invention, a bonding film is further included, which is located above the first surface, wherein a plurality of bonding pads are located in the bonding film and are electrically connected to the plurality of substrate through-hole structures.

[0007] According to one embodiment of the present invention, the plurality of substrate through hole structures are arranged to spread throughout the substrate, and a portion of the plurality of substrate through hole structures is staggered with the plurality of bonding pads.

[0008] According to one embodiment of the present invention, the plurality of bonding pads are distributed more densely in a first region overlapping the chip than in a second region overlapping the plurality of dies.

[0009] According to one embodiment of the present invention, the device further comprises: a thermal interface material formed above the chip and the plurality of dies; and a heat sink formed above the thermal interface material.

[0010] According to one embodiment of the present invention, the present invention further includes: a plurality of heat dissipation chips, which are bonded to each side of the chip and electrically isolated from the chip.

[0011] According to one embodiment of the present invention, a plurality of heat dissipation chips are symmetrically arranged around the chip.

[0012] According to one embodiment of the present invention, a surface area of ​​the plurality of substrate through-hole structures on the first surface is greater than a surface area of ​​the plurality of substrate through-hole structures on the second surface.

[0013] According to one embodiment of the present invention, a plurality of substrate through-hole structures are evenly distributed on the substrate.

[0014] According to one embodiment of the present invention, a width of the plurality of substrate through-hole structures on the first surface is greater than a width of the plurality of substrate through-hole structures on the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The concepts of the disclosed embodiments are better understood according to the following detailed description and in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make a clear description. Similar features are indicated by similar reference numerals throughout the specification and drawings.

[0016] Figures 1A to 1H are cross-sectional views illustrating various stages of forming a package structure according to some embodiments of the present disclosure.

[0017] Figure 2 is a cross-sectional view showing a package structure according to some embodiments of the present disclosure.

[0018] Figure 3 is a cross-sectional view showing a package structure according to some embodiments of the present disclosure.

[0019] Figure 4 is a top view showing a packaging structure according to some embodiments of the present disclosure.

[0020] Figure 5 is a top view showing a packaging structure according to some embodiments of the present disclosure.

[0021] Figure 6 is a cross-sectional view illustrating a packaging device according to some embodiments of the present disclosure.

[0022] Figure 7 is a cross-sectional view illustrating a packaging device according to some embodiments of the present disclosure.

[0023] Figure 8 is a cross-sectional view illustrating a packaging device according to some embodiments of the present disclosure.

[0024] The reference numerals are as follows:

[0025] 10: Packaging structure

[0026] 50: Grain (semiconductor grain)

[0027] 60: Chip (heat dissipation chip)

[0028] 61: Top

[0029] 62: Side wall

[0030] 80: Chip

[0031] 81: Top

[0032] 82: Side wall

[0033] 100: Base

[0034] 100A: First surface

[0035] 100B: Second surface

[0036] 102,104: Dielectric layer

[0037] 110: Through-substrate via structure (TSV structure)

[0038] 112:Metalized pattern

[0039] 114: Conductive characteristics

[0040] 115:Internal connection structure

[0041] 120: Bonding film

[0042] 122: Bonding pad

[0043] 130: Bonding film

[0044] 132: Bonding pad

[0045] 140: Bonding film

[0046] 142: Bonding pad

[0047] 150: Molding material

[0048] 151: Top

[0049] 153: Bottom

[0050] 160: Bump structure

[0051] 170: Thermal interface material

[0052] 180: Radiator

[0053] 500: Packaging device

[0054] 510:Semiconductor grains

[0055] 520: Fan-out redistribution structure

[0056] 521: Dielectric layer

[0057] 522: Conductive layer

[0058] 530: Conductive connector

[0059] 540: Bottom filling layer

[0060] 550: Integrated fan-out via

[0061] 600: Packaging device

[0062] 610: contact bump

[0063] 620: Intermediary layer

[0064] 630: Redistribution structure

[0065] 640: Conductive connector

[0066] 700: Packaging device

[0067] 710:Semiconductor grains

[0068] 720: Bottom filling layer

[0069] 730: Contact pad

[0070] 740: Bottom base

[0071] 750: Conductive connector DETAILED DESCRIPTION

[0072] The following disclosure provides many different embodiments or examples to implement different features of the embodiments of the present disclosure. Reference numerals and / or letters may be repeated in the various examples described in the present disclosure. These repetitions are for the purpose of simplicity and clarity, and do not in themselves indicate any relationship between the various embodiments and / or configurations disclosed. In addition, specific examples of components and configurations are described below to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only for demonstration and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an additional feature formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself specify the relationship between the various embodiments and / or configurations described.

[0073] Additionally, spatially relative terms may be used herein. For example, "below," "below," "lower," "above," "higher," and similar terms may be used to describe the relationship between one element or feature and another element or features shown in the accompanying drawings. These spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted similarly.

[0074] Figures 1A to 1H 1 is a cross-sectional view showing various stages of forming a package structure 10 according to some embodiments of the present disclosure. For example, the substrate 100 includes a semiconductor substrate, including, for example, doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate 100 includes other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP) or a combination of the foregoing. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the substrate 100 has a first surface 100A (sometimes referred to as a front side) and a second surface 100B (sometimes referred to as a back side). In some embodiments, the first surface 100A is relative to the second surface 100B. The first surface 100A is connected to the second surface 100B via the sidewall of the substrate 100. In some embodiments, the first surface 100A is parallel to the second surface 100B.

[0075] In some embodiments, the interconnect structure 115 is formed in the substrate 100. In some embodiments, the interconnect structure 115 includes a plurality of through-substrate via (TSV) structures 110, a plurality of metallization patterns 112, and a plurality of conductive features 114. In some embodiments, the through-substrate via structure 110 is formed in the substrate 100 and in a dielectric layer 102 formed on the substrate 100. However, the present disclosure is not limited thereto. In some other embodiments, the dielectric layer 102 may be omitted, and the through-substrate via structure 110 is completely located in the substrate 100.

[0076] In some embodiments, the dielectric layer 102 includes, for example, silicon dioxide (SiO 2 ), phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the dielectric layer 102 is formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), etc.

[0077] In some embodiments, the formation of the substrate through-hole structure 110 includes forming a plurality of grooves on the first surface 100A of the substrate 100. In some embodiments, the grooves extend into the substrate 100 and penetrate the dielectric layer 102 (if present) to electrically and physically couple the metallization pattern 112 above. In some embodiments, the substrate through-hole structure 110 has a tapered profile in a cross-sectional view. For example, the width of the substrate through-hole structure 110 gradually decreases from the first surface 100A to the second surface 100B. However, the present disclosure is not limited thereto. In some other embodiments, the substrate through-hole structure 110 may have a rectangular profile in a cross-sectional view. In some embodiments, the substrate through-hole structure 110 is formed of tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing. However, the present disclosure is not limited thereto.

[0078] The metallization pattern 112 and the conductive features 114 are surrounded by the dielectric layer 104 for proper insulation, thereby reducing the risk of forming a short circuit. In some embodiments, the dielectric layer 104 includes one or more layers of, for example, silicon dioxide (SiO 2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. In some embodiments, dielectric layer 104 is formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), and the like. In some embodiments, dielectric layer 104 is formed using the same material or method as dielectric layer 102. However, the present disclosure is not limited thereto. In some embodiments, dielectric layer 104 is formed using a different material or method than dielectric layer 102.

[0079] In some embodiments, one or more devices (not shown separately) are formed in the dielectric layers 102, 104 on or above the first substrate 100 and are electrically connected to the through-substrate structure 110, the metallization pattern 112, and / or the conductive feature 114. In some embodiments, the device is an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. For example, according to some embodiments of the present disclosure, the device is a metal-oxide-semiconductor field effect transistor (MOSFET).

[0080] In some embodiments, the metallization pattern 112 includes metal lines, and the conductive features 114 include vias formed in the dielectric layer 104. For example, the metallization pattern 112 and / or the conductive features 114 include conductive materials such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the substrate through-hole structure 110, the metallization pattern 112, and / or the conductive features 114 are formed of the same material. In some other embodiments, the substrate through-hole structure 110, the metallization pattern 112, and / or the conductive features 114 are formed of different materials.

[0081] Thus, the substrate through-hole structure 110 is electrically connected to the metallization pattern 112 and the conductive feature 114 to form a conductive path connected to the external environment (e.g., other semiconductor dies or external devices). For example, when the device in the substrate 100 is a transistor, the substrate through-hole structure 110 can be coupled to the gate or source / drain region of the transistor. The source / drain region can be referred to as a source or a drain individually or collectively, depending on the context.

[0082] like Figure 1B As shown, a bonding film 120 is formed on the substrate 100 to perform a bonding process. For example, the material of the bonding film 120 includes SiON, SiO 2, any other suitable material, or a combination of the foregoing materials. In some embodiments, a plurality of bonding pads 122 are formed in the bonding film 120. For example, the bonding pads 122 include, for example, tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination of the foregoing materials. In some embodiments, the bonding pads 122 correspond to the chips 80 to be bonded (e.g. Figure 1C However, the present disclosure is not limited thereto. In some embodiments, the bonding pads 122 are more densely distributed in a first region overlapping with (directly below) the chip 80 than in a second region overlapping with the die 60 .

[0083] like Figure 1C As shown, the chip 80 is bonded above the first surface 100A of the substrate 100. For example, the chip 80 may be a device die, a package encapsulating a device die, a system-on-chip (SoC) die including a plurality of device dies packaged as a system, etc. The chip 80 may be or may include a logic die, a memory die, an input / output die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die in the chip 80 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile device die, a microcontrol unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die in the chip 80 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The chip 80 may include a semiconductor substrate and an interconnect structure, which are not separately shown in this embodiment.

[0084] In addition, another bonding film 140 is formed on the chip 80 to perform a bonding process. For example, the material of the bonding film 140 includes SiON, SiO 2 , any other suitable material, or a combination of the foregoing. In some embodiments, the material of the bonding film 140 is the same as the material of the bonding film 120. Although two bonding films (e.g., the bonding film 120 and the bonding film 140) are shown in the present disclosure, it should be understood that the present disclosure may also employ one or more (two or more) bonding films.

[0085] In some embodiments, a plurality of bonding pads 142 are formed in the bonding film 140. For example, the bonding pads 142 include, for example, tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the bonding pads 142 are each aligned with the bonding pads 122 above the first surface 100A of the substrate 100 to form an electrical connection between the chip 80 and the interconnect structure 115.

[0086] In some embodiments, a plurality of die 60 are also bonded above the first surface 100A of the substrate 100. For example, the die 60 is formed based on a semiconductor material (e.g., silicon or any other suitable semiconductor material). Therefore, the die 60 may sometimes be referred to as a "semiconductor die 60". In some embodiments, the die 60 is bonded adjacent to the chip 80 and is electrically isolated from the chip 80. These die 60 are configured to help dissipate heat energy generated during the operation of the chip 80. Therefore, the die 60 may also be referred to as a "heat dissipation die 60".

[0087] In addition, another bonding film 130 is formed on the die 60 to perform a bonding process. For example, the material of the bonding film 130 includes SiON, SiO 2 , any other suitable material or a combination of the foregoing. In some embodiments, the material of the bonding film 130 is the same as the material of the bonding film 120. Although two bonding films (e.g., bonding film 120 and bonding film 130) are shown in the present disclosure, it should be understood that the present disclosure may also adopt one or more layers (more than two layers) of bonding films. In some embodiments, bonding pads for bonding the die 60 are not formed in the corresponding (i.e., overlapping) regions of the bonding film 130 and the bonding film 120. However, the present disclosure is not limited thereto.

[0088] Then, if Figure 1DAs shown, the molding material 150 is supplied to the first surface 100A of the substrate 100 and covers the chip 80 and the die 60. After the molding material 150 is formed, the molding material 150 will encapsulate the chip 80 and the die 60 above the first surface 100A of the substrate 100. In some embodiments, the molding material 150 may include an epoxy molding compound (EMC). For example, the molding material 150 includes polymethylmethacrylate (PMMA), acrylonitrile butadiene styrene (ABS), polyamide (PA), polycarbonate (PC), polyethylene (PE), polyoxymethylene (POM), polypropylene (PP), polystyrene (PS), thermoplastic elastomer (TPE), thermoplastic polyurethane (TPU), epoxy resin, etc. In some embodiments, the molding material 150 is supplied by compression molding, transfer molding, etc. In some embodiments, the molding material 150 is supplied in a liquid or semi-liquid form and then solidified, which increases the fluidity of the molding material 150, so that the gap with a high aspect ratio between the chip 80 and the die 60 can be filled at a relatively fast speed.

[0089] Next, if Figure 1EAs shown, a planarization process (e.g., chemical mechanical polishing (CMP), molding compound grinding (MCG), or any other suitable planarization process) may be performed to remove and planarize the upper surface of the molding material 150. As a result, the top surface 151 of the molding material 150, the top surface 61 of the die 60, and the top surface 81 of the chip 80 are substantially coplanar (within process variations). In some embodiments, the molding material 150 fills the gap between the chip 80 and the die 60 with a relatively high aspect ratio, and the width of the gap may be defined as the width between the sidewall 82 of the chip 80 and the sidewall 62 of the adjacent die 60. The height of the gap may be defined as the height between the top surface 151 of the molding material 150 (which may be coplanar with the top surface 81 of the chip 80) and the bottom surface 153 (which may be coplanar with the top surface of the bonding film 120). In some embodiments, the molding material 150 fills the gap by more than about 20 μm. As a result, a taller chip 80 and die 60 can be bonded above the first surface 100A of the substrate 100 , and the heights of the chip 80 and die 60 will not be limited by the formation of the molding material 150 .

[0090] like Figure 1F As shown, the substrate 100 is thinned to reveal the substrate through hole structure 110 on the second surface 100B of the substrate 100. That is, after the thinning process, the bottom surface of the substrate through hole structure 110 can be substantially coplanar with the second surface 100B. In some embodiments, the substrate 100 is trimmed in a direction perpendicular to the first surface 100A and the second surface 100B of the substrate 100. In some embodiments, the substrate 100 is thinned using a polishing process, a grinding process, any other suitable process, or a combination of the foregoing processes. More specifically, the second surface 100B of the substrate can be subjected to a polishing process and / or a grinding process. In the present embodiment, the second surface 100B of the substrate 100 is thinned, and the chip 80 and the semiconductor die 60 are located above the first surface 100A of the substrate 100. Therefore, no carrier is required to form the package structure 10, so process cost and time can be saved. Furthermore, since the forming process of the package structure 10 is simplified (specifically, bonding and removal of the carrier are omitted, and the substrate 100 is processed without turning over the substrate 100 ), the yield of the package structure 10 can be increased.

[0091] like Figure 1GAs shown, a plurality of bump structures 160 are formed on the exposed substrate through hole structure 110. That is, the bump structure 160 is formed on the second surface 100B of the substrate 100 and covers the exposed surface of the substrate through hole structure 110. In some embodiments, the contact area between the metallization pattern 112 and the substrate through hole structure 110 is greater than the contact area between the substrate through hole structure 110 and the bump structure 160. That is, the surface area of ​​the substrate through hole structure 110 on the first surface 100A is greater than the surface area of ​​the substrate through hole structure 110 on the second surface 100B. In some embodiments, the bump structure 160 may include a controlled collapse chip connection (C4) bump, a solder bump, a copper bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), a ball grid array (BGA) bump, a copper pillar, etc.

[0092] like Figure 1H As shown, a thermal interface material (TIM) 170 is selectively disposed on the chip 80 and the die to enhance the heat dissipation of the package structure 10. More specifically, the thermal interface material 170 completely covers the top surface of the chip 80 and the die 60 to dissipate the generated heat. In some embodiments, the thermal interface material 170 also covers the top surface of the molding material 150. However, the present disclosure is not limited to this. In some embodiments, the thermal interface material 170 can selectively expose the molding material 150. In this way, process costs can be saved.

[0093] In addition, a heat sink 180 may be mounted above the chip 80 and the die 60. For example, the heat sink 180 may be placed, attached, and / or adhered (e.g., by epoxy adhesive and / or other types of adhesive) to the thermal interface material 170 (if present) via a connector (e.g., screws, pins, and / or other similar hardware). In some embodiments, the heat sink 180 may be mounted directly above the chip 80 and the die 60. For example, the heat sink 180 may include a fan and / or other similar types of hardware to dissipate heat generated during use of the chip 80 to an environment external to the chip 80. However, the present disclosure is not limited thereto.

[0094] Figure 2 1 is a cross-sectional view showing a package structure 10 according to some embodiments of the present disclosure. It is worth noting that the package structure 10 of this embodiment may include Figure 1GThe same or similar elements of the package structure 10 shown in the figure are represented by the same or similar reference numerals and will not be described in detail in the following paragraphs. Figure 2 As shown, the package structure 10 includes a substrate 100, an internal connection structure 115, a chip 80 and a plurality of dies 60. The chip 80 and the dies 60 are bonded above the first surface 100A of the substrate 100 through a plurality of bonding films 120, 130 and 140. In the present embodiment, the substrate through-hole structure 110 is evenly distributed on the substrate 100. That is, the dies 60 overlap with some substrate through-hole structures 110 in the normal direction perpendicular to the first surface 100A. Therefore, the internal connection structure 115 can be more flexibly wired, and the bump structure 160 below can also be formed on the entire substrate 100. Therefore, the substrate 100 can adopt various configurations of the chip 80 and the dies 60. In some embodiments, the substrate through-hole structures 110 are separated from each other at fixed intervals. However, the present disclosure is not limited thereto.

[0095] Figure 3 FIG. 1 is a cross-sectional view showing a package structure 10 according to some embodiments of the present disclosure. It is worth noting that the package structure 10 of the present embodiment may include the same or similar elements as the package structure 10 shown in FIG. 1 . These elements will be represented by the same or similar reference numerals and will not be described in detail in the following paragraphs. Figure 3 As shown, the package structure 10 includes a substrate 100, an internal connection structure 115, a chip 80 and a plurality of dies 60. The chip 80 and the dies 60 are bonded above the first surface 100A of the substrate 100 through a plurality of bonding films 120, 130 and 140. In the present embodiment, the substrate through hole structure 110 is formed to be spread throughout the substrate 100, and at least one bonding pad 132 is formed in the bonding film 130 for bonding the dies 60. The bonding pad 132 is aligned with the bonding pad 122 below. For example, the sidewalls of the bonding pad 132 are substantially coplanar with the corresponding sidewalls of the bonding pad 122 in the vertical direction (which is, for example, parallel to the Z axis). In some embodiments, the heat dissipation dies 60 each include a metal pattern (not shown separately) that is physically connected to the bonding pad 132 and electrically isolated from the chip 80. Therefore, the heat dissipation effect can be further improved.

[0096] Figure 4 FIG. 1 is a top view showing a package structure 10 according to some embodiments of the present disclosure. Figure 4As shown, a plurality of semiconductor dies 50 and 60 are bonded above the first surface 100A of the substrate 100 and around the chip 80. In some embodiments, the semiconductor die 50 may include active and / or passive devices and be electrically connected to the chip 80 to improve the performance of the package structure 10. Examples of the semiconductor die 50 include various devices, such as transistors, capacitors, resistors, combinations thereof, etc., and these devices may be used to meet the structural and functional requirements designed for the package structure 10. In some embodiments, any suitable method may be used to form the semiconductor die 50.

[0097] The semiconductor die around the chip 80 also includes a heat dissipation die 60 electrically isolated from the chip 80. In some embodiments, the heat dissipation die 60 is bonded to each side of the chip 80. In some embodiments, the heat dissipation chips 60 are symmetrically arranged around the chip 80 to provide a uniform heat dissipation effect for the package structure 10. It is worth noting that the arrangement of the semiconductor die 50 and 60 shown in this embodiment is only an example. A person skilled in the art of the present disclosure can adjust the positions of the semiconductor die 50 and 60 as needed according to the content of the present disclosure.

[0098] Figure 5 FIG. 1 is a top view showing a package structure 10 according to some embodiments of the present disclosure. It is worth noting that the package structure 10 of this embodiment may include Figure 4 The same or similar elements of the package structure 10 shown in the figure are represented by the same or similar reference numerals and will not be described in detail in the following paragraphs. Figure 5 As shown, a plurality of semiconductor dies 50 and a plurality of heat dissipation dies 60 are bonded above the first surface 100A of the substrate 100 and are located around the chip 80. In some embodiments, the heat dissipation die 60 is bonded at a corner of the chip 80 to enhance the local heat dissipation of the package structure 10. Similarly, it is worth noting that the arrangement of the semiconductor dies 50 and 60 shown in this embodiment is only an example, and a person skilled in the art of the present disclosure can adjust the positions of the semiconductor dies 50 and 60 as required according to the content of the present disclosure. All possible configurations of the semiconductor dies 50 and 60 are covered within the scope of the present disclosure.

[0099] Figures 6 to 8 1 is a cross-sectional view showing packaged devices 500, 600, and 700 including package structure 10 according to some embodiments. Additional features may be added to packaged devices 500, 600, and 700, and some of the features described below may be replaced, modified, or deleted in other embodiments of packaged devices 500, 600, and 700. For clarity, Figures 6 to 8 The packaging structure 10 is simplified.

[0100] In addition to the package structure 10, the package device 500 includes a semiconductor die 510, a fan-out redistribution structure 520, a plurality of conductive connectors 530, an underfill layer 540, and a plurality of integrated fan-out (InFO) through vias (TIVs) 550. The term "fan-out" means that the input / output (I / O) pads on the package structure 10 can be redistributed to a larger area than the package structure 10 itself, thereby increasing the number of I / O pads packaged on the surface of the package structure 10.

[0101] The semiconductor die 510 may be a logic die, a memory die, a passive device die, an analog die, a micro-electromechanical system (MEMS) die, a radio frequency (RF) die, or a combination thereof. For example, the logic die may be a central processing unit die, a system-on-chip (SoC) die, a system-on-integrated-chip (SOIC) die, a microcontroller die, etc. The memory die may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) memory die, a flash memory (NAND) die, etc.

[0102] The fan-out redistribution layer 520 may include a plurality of dielectric layers 521 and a plurality of conductive layers 522. The conductive connector 530 is formed above the conductive layer 522 exposed from the dielectric layer 521. In some embodiments, the conductive connector 530 is a controlled collapse chip connection (C4) bump, a solder bump, a copper bump, a microbump, a bump formed by electroless nickel palladium immersion gold technology (ENEPIG), a ball grid array (BGA) bump, a copper pillar, etc. The bottom fill layer 540 is formed to surround the package structure 10. In some embodiments, the bottom fill layer 540 is made of or includes a polymer material. The bottom fill layer 540 may include an epoxy resin. In some embodiments, the bottom fill layer 540 includes a filler dispersed in an epoxy resin. In some embodiments, the formation of the bottom fill layer 540 involves an injection process, a spin coating process, a dispensing process, a film lamination process, an application process, one or more other applicable processes, or a combination of the foregoing processes. In some embodiments, a thermal curing process is used during the formation of the bottom fill layer 540. Integrated fan-out vias 550 penetrate the bottom fill layer 540 to provide electrical connection.

[0103] In addition to the package structure 10 , the package device 600 includes a plurality of contact bumps 610 , an interposer 620 , a redistribution structure 630 , and a plurality of conductive connectors 640 .

[0104] The contact bump 610 is formed under the package structure 10 to provide an electrical connection. The interposer 620 can be made of silicon materials, organic (laminated) materials, polymer-based materials, etc. The interposer 620 can be attached to a carrier such as a printed circuit board (PCB). The redistribution structure 630 may include metal lines and vias to provide electrical connections to connect power, ground, and signals from the top surface of the interposer 620 to the bottom surface of the interposer 620. In some embodiments, the conductive connector 640 is a controlled collapse chip connection (C4) bump, a solder bump, a copper bump, a micro bump, a bump formed by electroless nickel palladium immersion gold technology (ENEPIG), a ball grid array (BGA) bump, a copper pillar, etc.

[0105] In addition to the package structure 10 , the package device 700 includes a semiconductor die 710 , an underfill layer 720 , a plurality of contact pads 730 , a bottom substrate 740 , and a plurality of conductive connectors 750 .

[0106] The semiconductor die 710 may be a logic die, a memory die, a passive device die, an analog die, a microelectromechanical system (MEMS) die, a radio frequency (RF) die, or a combination thereof. Examples of logic die include a central processing unit die, a system on chip (SoC) die, a system on integrated chip (SOIC) die, a microcontroller die, etc. The memory die may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth (HBM) memory die, a flash (NAND) memory die, etc. The contact pad 730 is formed in the bottom fill layer 720 to provide an electrical connection. In some embodiments, the conductive connector 750 is a controlled collapse chip connection (C4) bump, a solder bump, a copper bump, a microbump, a bump formed by electroless nickel palladium immersion gold technology (ENEPIG), a ball grid array (BGA) bump, a copper pillar, etc. In some embodiments, the package structure 10 may be connected to the bottom substrate 740 by a flip chip bonding technique.

[0107] Other features and processes may also be included. For example, a test structure may be included to help verify the testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3D integrated circuit; 3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate that allows testing of a 3D package or 3DIC, the use of probes, the use of probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods described in the present disclosure can be used in conjunction with test methods that incorporate intermediate verification of known good die to increase yield and reduce costs.

[0108] As described above, the present disclosure relates to a packaging structure and a method for forming the same. The method for forming the packaging structure includes thinning the substrate after supplying a molding material to the gap between the chip and the die. In this way, the packaging structure can be formed without a carrier, thereby saving process costs and time. Since the formation process of the packaging structure is simplified, the yield of the packaging structure can be improved. Specifically, the bonding and removal processes of the carrier are omitted, and the substrate 100 is processed without flipping. In addition, the packaging structure includes a plurality of heat dissipation grains, which provide uniform or locally enhanced heat dissipation for the packaging structure depending on the positions of the heat dissipation grains around the chip.

[0109] According to some embodiments, a method for manufacturing a package structure includes forming an interconnect structure in a substrate. The method also includes bonding a chip above the substrate and electrically connecting to the interconnect structure. The method includes bonding a plurality of dies above the substrate and adjacent to the chip. The method also includes supplying a molding material to a gap between the chip and the dies. In addition, the method includes thinning the substrate after supplying the molding material to the gap between the chip and the dies.

[0110] In some embodiments, the method further includes forming a plurality of bump structures on the interconnect structure. After the substrate is thinned, the bottom surface of the interconnect structure is exposed, and the bump structures are connected to the bottom surface of the interconnect structure.

[0111] In some embodiments, the method further includes forming a bonding film on the substrate and forming a plurality of bonding pads in the bonding film, wherein the bonding pads are more densely distributed in a first region overlapping the chip than in a second region overlapping the die.

[0112] In some embodiments, forming an interconnect structure in a substrate includes forming a plurality of substrate through hole structures from a first surface to a second surface, wherein a width of the substrate through hole structure on the first surface is greater than a width of the substrate through hole structure on the second surface, and a bonding pad is formed above the first surface.

[0113] In some embodiments, the die includes a plurality of heat sink dies electrically isolated from the chip.

[0114] In some embodiments, the heat sink dies are symmetrically arranged around the chip.

[0115] In some embodiments, the method further includes forming a plurality of trenches on the first surface of the substrate, filling the trenches with a conductive material to form a plurality of substrate through-hole structures in the substrate, forming a dielectric layer above the first surface of the substrate, and forming a plurality of metal patterns in the dielectric layer, wherein the metal patterns are electrically connected to the substrate through-hole structures.

[0116] According to some embodiments, a method for manufacturing a package structure includes forming a plurality of through substrate via (TSV) structures in a substrate. The method includes bonding a chip above a first surface of the substrate and electrically connecting to a first plurality of through substrate via structures of the through substrate via structures. The method includes bonding a heat dissipation die above the first surface of the substrate and adjacent to the chip. The heat dissipation die overlaps with a second plurality of through substrate via structures of the through substrate via structures in a normal direction perpendicular to the first surface. The method includes supplying a molding material to a gap between the chip and the heat dissipation die. The method also includes thinning the substrate from a second surface relative to the first surface.

[0117] In some embodiments, the method further includes forming a plurality of bonding pads in the bonding film over the first surface, wherein the bonding pads are electrically connected to the first plurality of through substrate via structures.

[0118] In some embodiments, the through-substrate via structures are evenly distributed on the substrate.

[0119] In some embodiments, the heat sink die is electrically isolated from the chip.

[0120] In some embodiments, bonding the heat sink die further comprises aligning a bonding pad of the heat sink die with a bonding pad on the substrate.

[0121] In some embodiments, the step of bonding the chip and the heat sink die includes making the top surface of the chip flush with the top surface of the heat sink die.

[0122] In some embodiments, when the substrate is thinned from the second surface of the substrate to reveal the substrate through-hole structure, the chip and the heat dissipation die are located above the first surface of the substrate.

[0123] In some embodiments, the method further includes forming a plurality of bump structures on the exposed through substrate via structures, wherein a surface area of ​​the through substrate via structures on the first surface is greater than a surface area of ​​the through substrate via structures on the second surface.

[0124] According to some embodiments, a packaging structure includes a substrate having a first surface and a second surface. The second surface is relative to the first surface. The packaging structure includes a plurality of through substrate via (TSV) structures formed in the substrate. The width of the through substrate via structure gradually decreases from the first surface to the second surface. The packaging structure includes a chip bonded to the first surface of the substrate. The packaging structure also includes a plurality of dies bonded to the first surface of the substrate and adjacent to the chip. The packaging structure also includes a molding material formed between the chip and the dies. In addition, the packaging structure includes a plurality of bump structures connected to the through substrate via structure on the second surface.

[0125] In some embodiments, the package structure further includes a bonding film located above the first surface, wherein a plurality of bonding pads are located in the bonding film and electrically connected to the substrate through-hole structure.

[0126] In some embodiments, the through substrate via structure is disposed throughout the substrate, and a portion of the through substrate via structure is staggered with the bonding pad.

[0127] In some embodiments, the packaging structure further includes a thermal interface material and a heat sink. The thermal interface material is formed above the chip and the die. The heat sink is formed above the thermal interface material.

[0128] In some embodiments, the package structure further includes a plurality of heat dissipation dies bonded to each side of the chip and electrically isolated from the chip.

[0129] The features of many embodiments are summarized above so that those skilled in the art to which the present disclosure belongs can better understand the various embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Various changes, substitutions and modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A packaging structure, characterized in that: include: A substrate having a first surface and a second surface opposite to the first surface; A plurality of substrate through-hole structures are located in the substrate, wherein a width of the plurality of substrate through-hole structures gradually decreases from the first surface to the second surface; a chip bonded to the first surface of the substrate; A plurality of dies bonded to the first surface of the substrate and adjacent to the chip; a molding material, located between the chip and the plurality of dies; as well as A plurality of bump structures are connected to the plurality of substrate through hole structures on the second surface.

2. The packaging structure according to claim 1, characterized in that: The invention also comprises a bonding film located above the first surface, wherein a plurality of bonding pads are located in the bonding film and electrically connected to a plurality of the substrate through hole structures.

3. The packaging structure according to claim 2, characterized in that: The plurality of substrate through hole structures are arranged to spread over the substrate, and a portion of the plurality of substrate through hole structures is staggered with the plurality of bonding pads.

4. The packaging structure according to claim 2, characterized in that: The bonding pads are more densely distributed in a first region overlapping the chip than in a second region overlapping the dies.

5. The packaging structure according to claim 1, characterized in that: Also includes: a thermal interface material formed on the chip and the plurality of dies; as well as A heat sink is formed above the thermal interface material.

6. The packaging structure according to claim 1, characterized in that: Also includes: A plurality of heat dissipation chips are bonded to each side of the chip and are electrically isolated from the chip.

7. The packaging structure according to claim 6, characterized in that: The plurality of heat dissipation chips are symmetrically arranged around the chip.

8. The packaging structure according to claim 1, characterized in that: A surface area of ​​the plurality of substrate through hole structures on the first surface is greater than a surface area of ​​the plurality of substrate through hole structures on the second surface.

9. The packaging structure according to claim 1, characterized in that: A plurality of substrate through-hole structures are evenly distributed on the substrate.

10. The packaging structure according to claim 1, wherein: A width of the plurality of substrate through hole structures on the first surface is greater than a width of the plurality of substrate through hole structures on the second surface.

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