Package structure

Abstract

A packaging structure comprises a first chip structure and an interconnection structure, and the interconnection structure is located above the first chip structure. The package structure also includes a dielectric bonding structure over the interconnect structure and a metal bonding structure laterally surrounded by the dielectric bonding structure. A top surface of the metal bonding structure is substantially coplanar with a top surface of the dielectric bonding structure. The package structure also includes a conductive via connected to the metal bonding structure and laterally surrounded by the dielectric bonding structure. In addition, the package structure includes a second chip structure directly bonded to the dielectric bonding structure and the metal bonding structure. The package structure also includes a capacitor element beside the conductive via and laterally surrounded by the dielectric bonding structure.

Description

Technical Field

[0001] The embodiments of the utility model relate to a packaging structure and a forming method thereof, and more particularly to an integrated chip packaging structure with a capacitor and a forming method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer components and / or higher levels of integration. Functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while feature size (i.e., the smallest component that can be created using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Chip packaging can not only protect semiconductor devices from environmental pollutants, but also provide a connection interface for the semiconductor devices packaged therein. Smaller packaging structures that occupy less space or have a lower height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further increase the density and functionality of semiconductor dies. These relatively new semiconductor die packaging technologies face manufacturing challenges. Utility Model Content

[0005] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0006] An embodiment of the utility model provides a packaging structure. The packaging structure includes a first chip structure. The first chip structure has a first metal bonding structure and a first conductive via. The first conductive via is in direct contact with the first metal bonding structure. The first chip structure also has a first dielectric layer, which laterally surrounds the first metal bonding structure and the first conductive via. The surface of the first dielectric layer is substantially coplanar with the surface of the first metal bonding structure. The packaging structure also includes a second chip structure, which is located above the first chip structure. The second chip structure has a second metal bonding structure, which is in direct contact with the first metal bonding structure. The second chip structure also has a second conductive via, which is in direct contact with the second metal bonding structure. The second chip structure also has a second dielectric layer, which laterally surrounds the second metal bonding structure and the second conductive via. The surface of the second dielectric layer is substantially coplanar with the surface of the second metal bonding structure, and the second dielectric layer is in direct contact with the first dielectric layer. The packaging structure also includes a capacitor element, which is located between the first metal bonding structure and the bottom surface of the first conductive via.

[0007] According to one embodiment of the present invention, the first chip structure has a third metal bonding structure and a third conductive via, the third conductive via is in direct contact with the third metal bonding structure, the first dielectric layer laterally surrounds the third metal bonding structure and the third conductive via, the surface of the first dielectric layer and the surface of the third metal bonding structure are substantially coplanar, the capacitor element has a first electrode and a second electrode, the first electrode is electrically connected to the first conductive via, and the second electrode is electrically connected to the third conductive via.

[0008] According to one embodiment of the present invention, the capacitor element further comprises a third electrode and a fourth electrode, the third electrode is electrically connected to the first conductive via, and the fourth electrode is electrically connected to the third conductive via.

[0009] According to one embodiment of the present invention, a portion of the second electrode is located between the first electrode and the third electrode, and a portion of the third electrode is located between the second electrode and the fourth electrode.

[0010] According to one embodiment of the present invention, the first conductive via is in direct contact with the side wall of the first electrode, and the third conductive via is in direct contact with the side wall of the second electrode.

[0011] According to one embodiment of the present invention, the device further comprises: a second capacitor element located between the second metal bonding structure and the top surface of the second conductive via.

[0012] An embodiment of the utility model also provides a packaging structure. The packaging structure includes a first chip structure and an interconnection structure, wherein the interconnection structure is located above the first chip structure. The packaging structure also includes a dielectric bonding structure and a metal bonding structure, wherein the dielectric bonding structure is located above the interconnection structure, and the metal bonding structure is laterally surrounded by the dielectric bonding structure. The top surface of the metal bonding structure is substantially coplanar with the top surface of the dielectric bonding structure. The packaging structure also includes a conductive via, which is connected to the metal bonding structure and is laterally surrounded by the dielectric bonding structure. In addition, the packaging structure includes a second chip structure, which is directly bonded to the dielectric bonding structure and the metal bonding structure. The packaging structure also includes a capacitor element, which is located next to the conductive via and is laterally surrounded by the dielectric bonding structure.

[0013] According to one embodiment of the present invention, the device further comprises: a third chip structure laterally spaced apart from the first chip structure, wherein the interconnection structure extends across opposite side walls of the first chip structure and the third chip structure.

[0014] According to one embodiment of the present invention, the capacitor element has an electrode, and the conductive through hole is in direct contact with a side wall of the electrode.

[0015] According to one embodiment of the present invention, the device further comprises: a second capacitor element located between the capacitor element and the interconnection structure, wherein the second capacitor element has a second electrode, and the second electrode is electrically connected to the conductive through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The utility model is made complete according to the following detailed description and the attached drawings. It should be noted that according to the general practice of this industry, the various components are not necessarily drawn to scale. In fact, the size of various components may be arbitrarily enlarged or reduced to make the description clear.

[0017] Figures 1A to 1F are cross-sectional views of various stages of a process of forming a package structure according to some embodiments.

[0018] Figure 2 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0019] FIG. 3A to FIG. 3I are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0020] Figure 4 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0021] FIG. 5A to FIG. 5I is a cross-sectional view of a process for forming a portion of a package structure according to some embodiments.

[0022] 6A to 6F are cross-sectional views of various stages in forming a portion of a package structure according to some embodiments.

[0023] Figure 7 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0024] FIG. 8A to FIG. 8E are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0025] The reference numerals are as follows:

[0026] 100: Carrier substrate

[0027] 102A, 102B, 802A, 802B, 826A, 826B: Chip structure

[0028] 104,204,804:Semiconductor substrate

[0029] 106,206,809A,809B: front side interconnection part

[0030] 106a, 106b, 106c, 106d, 108, 116a, 116b, 208, 326, 326a; 326b, 808a, 812: dielectric layer

[0031] 110,114,210,214,808b,814,814': Conductive parts

[0032] 112,810:Through chip vias

[0033] 114: Conductive parts

[0034] 118,218,718,818,834:Capacitor components

[0035] 122,222,336P,336G,336S,336P1,336P2,336G1,336G2,336S1,336S2,822,832: Conductive bonding structure

[0036] 120M, 220M, 820M, 830M: Metal joint structure

[0037] 120V, 220V, 820V, 830V: Conductive through hole

[0038] 130a, 130b, 130c: insulation layer

[0039] 132a, 132b, 132c: conductive parts

[0040] 134: Under-bump metallization structure

[0041] 136,606,840: Conductive bumps

[0042] 216,816,828: Dielectric bonding structure

[0043] 302, 302a, 302b, 324, 324a, 324b: Etching stop layer

[0044] 304,312,504,510: Capacitor electrode layer

[0045] 306,313: Patterned mask element

[0046] 308A,308B,308C,314A,314B,314C,318A,318B,318C,322A,322B,322C,506A,506B,506C,512,512A,512B: Capacitor electrodes

[0047] 310,316,320,508: Capacitor dielectric layer

[0048] 328: Opening

[0049] 330:Through hole

[0050] 332: Barrier layer

[0051] 334: Conductive filling layer

[0052] 502: Highlight structure

[0053] 602,836: Protective layer

[0054] 604,838: Redistribution structure

[0055] 800: Wafer

[0056] 806: Device part

[0057] 811: Interconnection structure

[0058] R: Region DETAILED DESCRIPTION

[0059] The following utility model content provides many different embodiments or examples to implement the different characteristic components of the present case. The following utility model content describes specific examples of each component and its arrangement to simplify the description. Of course, these are only examples and are not intended to be limiting. For example, if the utility model describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the utility model may reuse the same reference symbols and / or marks in various examples. These repetitions are for the purpose of simplicity and clarity, and are not used to limit the specific relationship between the different embodiments and / or structures discussed.

[0060] In addition, spatially related terms such as "below," "beneath," "below," "above," "on," and similar terms are used to facilitate description of the relationship between one element or feature and another element or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted accordingly.

[0061] Some embodiments of the present invention are described below. Additional steps may be provided before, during and / or after the multiple stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional features may be added to the semiconductor device structure. Some of the features described may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of operations, these operations may still be performed in another logical order.

[0062] Embodiments of the present invention may be related to packaging structures, such as three-dimensional (3D) packaging, 3D-IC devices, and 2.5D packaging. Embodiments of the present invention form a packaging structure, which includes a substrate carrying one or more dies or packages and a protective element (e.g., a protective cover) located next to the dies or packages. The protective element may also have the function of an anti-warping element and / or a heat dissipation element.

[0063] Other features and processes may also be included. For example, test structures for assisting in verification testing of 3D packages, 3D-IC devices, and / or 2.5D packages may be included. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate to facilitate testing using a probe or a probe card. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods of the utility model described herein may be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0064] Figures 1A to 1F is a cross-sectional view of various stages of a process of forming a package structure according to some embodiments. Figure 1A As shown, in some embodiments, a chip structure (or a structure including a chip) 102A is disposed above a carrier substrate 100. The carrier substrate 100 may be a carrier chip. The carrier chip may include a semiconductor wafer (e.g., a silicon wafer), a dielectric wafer (e.g., a glass wafer), or similar materials.

[0065] In some embodiments, the chip structure 102A is a semiconductor wafer including a plurality of semiconductor chips. After a dicing process, a plurality of semiconductor chips separated from each other can be obtained. In some other embodiments, the chip structure 102A is a single semiconductor chip.

[0066] In some embodiments, the chip structure 102A includes a semiconductor substrate 104. In some embodiments, the semiconductor substrate 104 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 104 may include silicon or other elemental semiconductor materials (e.g., germanium). The semiconductor substrate 104 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 104 includes a semiconductor layer epitaxially grown on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0067] In some other embodiments, the semiconductor substrate 104 includes a compound semiconductor. For example, the compound semiconductor includes a X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 A III-V compound semiconductor of the defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. Each proportion is greater than or equal to 0 and is equal to 1 when added together. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors or combinations thereof. Other suitable substrates including II-VI compound semiconductors may also be used.

[0068] In some embodiments, the semiconductor substrate 104 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be manufactured by an oxygen ion implantation (SIMOX) process, a wafer bonding process, other applicable methods or a combination thereof. In some other embodiments, the semiconductor substrate 104 includes a multilayer structure. For example, the semiconductor substrate 104 includes a silicon germanium layer formed on a bulk silicon layer.

[0069] Various device elements are formed in or over the semiconductor substrate 104. Examples of these device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), etc.), diodes, or other suitable elements. These device elements may be formed using various processes, including deposition, etching, implantation, photolithography, annealing, and / or other suitable processes.

[0070] The chip structure 102A includes a front-side interconnection portion 106. The front-side interconnection portion 106 includes a plurality of dielectric layers 108 and a plurality of conductive features 110 surrounded by the dielectric layers 108. The conductive features 110 may include conductive contacts, conductive lines, and conductive vias.

[0071] The dielectric layer 108 may be made of or include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxynitride, other suitable materials or combinations thereof. The conductive component 110 may be made of or include copper, tungsten, cobalt, aluminum, other suitable materials or combinations thereof. Forming the front-side interconnect 106 may involve multiple deposition processes, patterning processes, planarization processes, other suitable processes or combinations thereof.

[0072] The device elements of the chip structure 102A are interconnected through the front-side interconnect portion 106 to form an integrated circuit device, such as a logic device, a memory device (e.g., a static random access memory SRAM), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, one or more other types of devices, or a combination thereof.

[0073] In some embodiments, Figure 1A As shown, the chip structure 102A includes a plurality of through-chip vias 112 extending into the interior of the semiconductor substrate 104. Each through-chip via 112 may be electrically connected to one or more conductive features 110 formed in the front-side interconnection portion 106. In some embodiments, a dielectric layer is formed between the semiconductor substrate 104 and the through-chip via 112 to prevent a short circuit between the through-chip via 112 and the semiconductor substrate 104.

[0074] In some embodiments, Figure 1A As shown, the front-side interconnect portion 106 also includes a conductive component 114. The conductive component 114 may be made of copper, aluminum, other suitable materials, or a combination thereof or include the foregoing materials. In some embodiments, the conductive component 114 serves as a conductive pad or a redistribution layer. Each conductive component 114 may be electrically connected to one or more conductive components 110 below it. In some embodiments, the thickness of each conductive component 114 is greater than the thickness of the conductive component 110 below it. The thickness of each conductive component 114 may be in the range of about 2.5 μm to about 4.5 μm. The thickness of the top metal of the conductive component 110 may be in the range of about 0.5 μm to about 1 μm.

[0075] like Figure 1BAs shown, according to some embodiments, a dielectric layer 116a is deposited over the front-side interconnection portion 106. The dielectric layer 116a may be made of or include silicon oxide, carbon-containing silicon oxide, silicon oxynitride, other suitable materials or combinations thereof. The dielectric layer 116a may be deposited using a chemical vapor deposition (CVD) process or a similar process. In some embodiments, before the dielectric layer 116a is formed, one or more thermal operations may be performed to improve the quality of the device elements of the chip structure 102A.

[0076] Subsequently, in some embodiments, one or more capacitor elements 118 are formed, such as Figure 1B The formation of capacitor element 118 will be described in more detail later.

[0077] like Figure 1B As shown, in some embodiments, a dielectric layer 116b is then deposited over the capacitor element 118. The material and formation method of the dielectric layer 116b may be the same or similar to that of the dielectric layer 116a.

[0078] Then, according to some embodiments, Figure 1B As shown, a plurality of conductive bonding structures 122 are formed. In some embodiments, the conductive bonding structures 122 penetrate the dielectric layers 116a, 116b and the capacitor element 118. In some embodiments, the conductive bonding structures 122 are electrically connected to the conductive component 114. In some embodiments, some of the conductive bonding structures 122 and the capacitor element 118 are electrically connected to each other.

[0079] In some embodiments, each conductive bonding structure 122 includes a metal bonding structure 120M and a conductive via 120V. The conductive via 120V is in direct contact with the metal bonding structure 120M. In some embodiments, the metal bonding structure 120M and the conductive via 120V are two connected parts of a single conductive structure formed in the same process.

[0080] In some embodiments, Figure 1B As shown, the dielectric layer 116b is substantially coplanar with the top surface of the metal bonding structure 120M. In some embodiments, forming the conductive bonding structure 122 involves one or more planarization processes to ensure that the dielectric layer 116b is substantially coplanar with the top surface of the metal bonding structure 120M. For example, a chemical mechanical polishing (CMP) process is used.

[0081] Dielectric layers 116a and 116b together form a dielectric bonding structure that laterally surrounds conductive bonding structure 122 and capacitor element 118. In some embodiments, capacitor element 118 is located next to conductive via 120V. In some embodiments, capacitor element 118 is located between metal bonding structure 120M and the bottom surface of conductive via 120V.

[0082] As described above, in some embodiments, one or more thermal operations are then performed to improve the quality of the device elements of the chip structure 102A. Since the capacitor element 118 is formed above the dielectric layer 116a after the thermal operation, the thermal operation can be prevented from negatively affecting the performance and reliability of the capacitor element 118. Since the capacitor element 118 is formed in the dielectric bonding structure, more available space is obtained in the front side interconnect portion 106 for routing. The performance of the chip structure 102A can be improved.

[0083] like Figure 1C As shown, according to some embodiments, the chip structure (or structure including a chip) 102B is taken out and is ready to be joined to the chip structure 102A. In some embodiments, the chip structure 102B is a semiconductor wafer including a plurality of semiconductor chips. Through a dicing process, a plurality of semiconductor chips separated from each other can be obtained. In some other embodiments, the chip structure 102A is a single semiconductor chip.

[0084] In some embodiments, similar to the chip structure 102A, the chip structure 102B includes a semiconductor substrate 204 having a plurality of device elements formed therein or thereon. The chip structure 102B also includes a front side interconnection portion 206. Similar to the front side interconnection portion 106 of the chip structure 102A, the front side interconnection portion 206 includes a plurality of dielectric layers 208 laterally surrounding a plurality of conductive features 210 and 214. In some embodiments, each conductive feature 214 is thicker than each conductive feature 210.

[0085] In some embodiments, a dielectric bonding structure 216 and a plurality of conductive bonding structures 222 are formed over the front-side interconnection portion 206 of the chip structure 102B. Similar to the conductive bonding structure 122, in some embodiments, each conductive bonding structure 222 includes a metal bonding structure 220M and a conductive via 220V.

[0086] like Figure 1D As shown, according to some embodiments, the chip structures 102A and 102B are interconnected by direct bonding. The direct bonding may be a hybrid bonding including metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, no tin-containing solder element is formed between the chip structures 102A and 102B.

[0087] In some embodiments, the chip structure 102B is directly placed on the dielectric layer 116b and the conductive bonding structure 122. Therefore, the dielectric layer 116b of the chip structure 102A is in direct contact with the dielectric bonding structure 216 of the chip structure 102B. The conductive bonding structure 122 of the chip structure 102A is in direct contact with the conductive bonding structure 222 of the chip structure 102B.

[0088] Prior to placing the chip structure 102B, a planarization process is performed to provide a highly planarized bonding surface. In some embodiments, there is no gap between the dielectric layer 116b and the dielectric bonding structure 216. In some embodiments, there is no gap between the conductive bonding structures 122 and 222. In some embodiments, a thermal operation is then used to enhance the bonding between the conductive bonding structures 122 and 222. The temperature of the thermal operation may be in the range of about 100°C to about 500°C.

[0089] like Figure 1E As shown, in some embodiments, the carrier substrate 100 is removed. Then, the chip structure 102A is thinned using a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other applicable processes or a combination thereof. As a result, the through chip via 112 that was originally covered by the semiconductor substrate 104 is exposed. In some embodiments, the through chip via 112 protrudes from the bottom surface of the chip structure 102A.

[0090] like Figure 1F As shown, in some embodiments, a redistribution structure including a plurality of insulating layers 130a, 130b, and 130c and a plurality of conductive components 132a, 132b, and 132c is formed over the semiconductor substrate 104 and the through chip via 112. Forming the redistribution structure may involve a plurality of thin film forming processes, a plurality of patterning processes, a plurality of planarization processes, other applicable processes, or a combination thereof.

[0091] The insulating layers 130a-130c may be made of or include a polymer material. The polymer material may be made of or include polybenzoxazole (PBO), polyimide, epoxy-based resin, other applicable polymer materials, or a combination thereof. In some other embodiments, the insulating layers 130a-130c are made of or include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, other applicable dielectric materials, or a combination thereof. In some embodiments, the formation of the individual insulating layers 130a-130c involves a spin coating process, a spray coating process, a chemical vapor deposition (CVD) process, other applicable processes, or a combination thereof.

[0092] The conductive components 132a-132c may be made of or include copper, titanium, aluminum, gold, platinum, cobalt, tungsten, other suitable materials or combinations thereof. The formation of each conductive component 132a-132c may involve the use of an electroplating process, an electrochemical plating process, a CVD process, a physical vapor deposition (PVD) process, other suitable processes or combinations thereof.

[0093] Then, according to some embodiments, Figure 1F As shown, an under bump metallization (UBM) structure 134 and a conductive bump 136 are formed. The conductive bump 136 may include a solder material. The solder material may be a tin-containing material. The tin-containing material may further include copper, silver, gold, aluminum, lead, one or more other applicable materials or a combination thereof. In some other embodiments, the tin-containing material is lead-free.

[0094] In some embodiments, a sawing process is used to separate the structure into a plurality of package structures. Figure 1F One of the package structures is shown. The package structure may be a system on an integrated chip (SoIC) integrated in another package. The package may include multiple chip structures bonded to an interposer substrate, which is further bonded to another substrate. Alternatively, the package may include multiple chip structures surrounded by a protective layer and a redistribution structure formed on the sheet structure and the protective layer.

[0095] In some embodiments, Figure 1F As shown, the capacitor element 118 is formed around the conductive via of the conductive bonding structure 122 of a single chip structure (eg, chip structure 102A). However, the embodiments of the present invention are not limited thereto. Various changes and / or modifications may be made to the embodiments of the present invention.

[0096] Figure 2 2 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, one or more capacitor elements 218 are formed. The capacitor element 218 is located next to the conductive via of the conductive bonding structure 222. The capacitor element 218 is laterally surrounded by the dielectric bonding structure 216. In some embodiments, some capacitor elements 218 and the conductive bonding structure 222 are electrically connected to each other. The formation process of the capacitor element 218 will be described in more detail.

[0097] FIG. 3A to FIG. 3I are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments. Figure 3A to Figure 3I The formation of capacitor element 118 is shown. In some embodiments, Figure 3A to Figure 3I Shown in Figure 1F Capacitor element 118 is formed near region R in FIG. Figure 3A to Figure 3I The method for forming the capacitor element 118 shown in FIG. Figure 2 Capacitor element 218 is shown in FIG.

[0098] like Figure 3A As shown, according to some embodiments, an etch stop layer 302 and a dielectric layer 116a are formed above the conductive component 114. The etch stop layer 302 may be made of nitride, silicon oxynitride, other suitable materials or a combination thereof or may include the aforementioned materials. The etch stop layer 302 may be deposited using a chemical vapor deposition (CVD) process or a similar process. The material and formation method of the dielectric layer 116a may be similar to Figure 1B The material and formation method of the dielectric layer 116a shown in FIG. 1 are the same as or similar to those shown in FIG.

[0099] Then, according to some embodiments, Figure 3A As shown, a capacitor electrode layer 304 is formed on the dielectric layer 116a. The capacitor electrode layer 304 can be made of titanium nitride, tantalum nitride, copper, aluminum, tungsten, cobalt, other applicable materials or combinations thereof or include the aforementioned materials. The capacitor electrode layer 304 can be formed using an electroplating process, an electrochemical plating process, a PVD process, a CVD process, other applicable process methods or combinations thereof.

[0100] like Figure 3A As shown, according to some embodiments, a patterned mask element 306 is formed above the capacitor electrode layer 304. The patterned mask element 306 has a plurality of openings that partially expose the capacitor electrode layer 304. In some embodiments, the patterned mask element 306 is a patterned photoresist layer.

[0101] like Figure 3B As shown, according to some embodiments, the capacitor electrode layer 304 is patterned to form a plurality of capacitor electrodes 308A, 308B, and 308C. In some embodiments, the capacitor electrode layer 304 is partially removed using one or more etching processes with the patterned mask element 306 as an etching mask. Thus, the remaining portion of the capacitor electrode layer 304 forms capacitor electrodes 308A-308C. After the capacitor electrodes 308A-308C are formed, the patterned mask element 306 is removed.

[0102] Then, according to some embodiments, Figure 3B As shown, a capacitor dielectric layer 310 is formed above the dielectric layer 116a and the capacitor electrodes 308A-308C. The capacitor dielectric layer 310 extends along the sidewalls and tops of the capacitor electrodes 308A-308C.

[0103] The capacitor dielectric layer 310 may be made of or include hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide, zirconium titanium oxide, titanium oxide, tantalum oxide, strontium titanium oxide, barium titanium oxide, barium strontium titanium oxide, lead zirconium titanium oxide, other applicable materials or combinations thereof. The capacitor dielectric layer 310 may be formed using a CVD process, an atomic layer deposition (ALD) process, a spin coating process, other applicable process methods or combinations thereof.

[0104] In some embodiments, the capacitor dielectric layer 310 is a single layer. In some other embodiments, the capacitor dielectric layer 310 includes multiple sub-layers. In some embodiments, some of the sub-layers are made of different materials.

[0105] like Figure 3C As shown, according to some embodiments, a capacitor electrode layer 312 is formed on the capacitor dielectric layer 310. The material and formation method of the capacitor electrode layer 312 may be the same as or similar to that of the capacitor electrode layer 304.

[0106] Then, if Figure 3C As shown, according to some embodiments, a patterned mask element 313 is formed above the capacitor electrode layer 312. The patterned mask element 313 has a plurality of openings that partially expose the capacitor electrode layer 312. In some embodiments, the patterned mask element 313 is a patterned photoresist layer.

[0107] like Figure 3D As shown, according to some embodiments, the capacitor electrode layer 312 is patterned to form a plurality of capacitor electrodes 314A, 314B, and 314C. In some embodiments, the capacitor electrode layer 312 is partially removed using one or more etching processes with the patterned mask element 313 as an etching mask. Thus, the remaining portion of the capacitor electrode layer 312 forms capacitor electrodes 314A to 314C. After the capacitor electrodes 314A to 314C are formed, the patterned mask element 313 is removed.

[0108] Then, if Figure 3D As shown, according to some embodiments, a capacitor dielectric layer 316 is formed above the capacitor dielectric layer 310 and the capacitor electrodes 314A-314C. The capacitor dielectric layer 316 extends along the sidewalls and tops of the capacitor electrodes 314A-314C. In some embodiments, the capacitor dielectric layer 316 is in direct contact with the capacitor dielectric layer 310.

[0109] The material and formation method of capacitor dielectric layer 316 may be the same or similar to the material and formation method of capacitor dielectric layer 310. In some embodiments, capacitor dielectric layer 316 and 310 are made of the same material. In some other embodiments, capacitor dielectric layer 316 and 310 are made of different materials.

[0110] In some embodiments, the capacitor dielectric layer 316 is a single layer. In some other embodiments, the capacitor dielectric layer 316 includes multiple sub-layers. In some embodiments, some of the sub-layers are made of different materials.

[0111] like Figure 3E As shown, according to some embodiments, capacitor electrodes 318A, 318B and 318C, capacitor dielectric layer 320 and capacitor electrodes 322A, 322B and 322C are formed. The materials and forming methods of capacitor electrodes 318A-318C and 322A-322C may be the same or similar to the materials and forming methods of capacitor electrodes 308A-308C and 314A-314C. The materials and forming methods of capacitor dielectric layer 320 may be the same or similar to the materials and forming methods of capacitor dielectric layers 310 and 316. Figure 3E As shown, in some embodiments, a portion of capacitor electrode 314A is located between capacitor electrodes 308A and 318A. Figure 3E As shown, in some embodiments, a portion of capacitor electrode 318A is located between capacitor electrodes 314A and 322A.

[0112] like Figure 3F As shown, according to some embodiments, in Figure 3E A dielectric layer 116 b, an etch stop layer 324, and a dielectric layer 326 are sequentially deposited on the structure shown in FIG. The materials and formation methods of the dielectric layers 116 b and 326 may be the same as or similar to those of the dielectric layer 116 a. The materials and formation methods of the etch stop layer 324 may be the same as or similar to those of the etch stop layer 302.

[0113] like Figure 3G As shown, according to some embodiments, dielectric layer 326 and etch stop layer 324 are partially removed. Thus, a plurality of openings 328 are formed. Openings 328 may be formed using one or more photolithography processes and one or more etching processes. In some embodiments, openings 328 are trenches. In some embodiments, openings 328 extend slightly into dielectric layer 116b.

[0114] like Figure 3H As shown, according to some embodiments, the dielectric layers 116b and 116a, the capacitor electrodes 308A-308C, 314A-314C, 318A-318C and 322A-322C, the capacitor dielectric layers 310, 316 and 320 and the etch stop layer 302 are partially removed. Thus, a plurality of through holes 330 are formed. The through holes 330 may be formed using one or more photolithography processes and one or more etching processes. The through holes 330 expose the conductive component 114. In some embodiments, the plurality of through holes 330 are formed simultaneously using the same etching process. Figure 3HAs shown, in some embodiments, the through hole 330 and the opening 328 together expose the sidewalls of the capacitor electrodes 308A, 314A, and 322A.

[0115] like Fig. 3I As shown, according to some embodiments, conductive bonding structures 336P, 336G, and 336S are formed in the opening 328 and the through hole 330. Each conductive bonding structure 336P, 336G, and 336S may be used as Figure 1F and Figure 2 The conductive bonding structure 122 shown in FIG. Each conductive bonding structure 336P, 336G and 336S can be used as Figure 2 In some embodiments, the conductive bonding structures 336P, 336G, and 336S are formed simultaneously.

[0116] like Fig. 3I As shown, in some embodiments, each of the conductive bonding structures 336P, 336G, and 336S includes a barrier layer 332 and a conductive filling layer 334. The barrier layer 332 may be made of or include titanium nitride, tantalum nitride, other suitable materials, or a combination thereof. The barrier layer 332 may be deposited using a CVD process, an ALD process, a PVD process, other suitable processes, or a combination thereof.

[0117] The conductive filling layer 334 may be made of or include copper, tungsten, aluminum, cobalt, other suitable materials or combinations thereof. In some embodiments, after forming the barrier layer 332 , a conductive material layer may be formed to overfill the opening 328 and the via 330 .

[0118] The conductive material layer may be formed by electroplating, electrochemical plating, CVD, ALD, FCVD, PVD, other suitable processes or combinations thereof. Subsequently, a planarization process (e.g., CMP) is performed to remove the portion of the conductive material layer outside the opening 328 and the through hole 330. Fig. 3I As shown, the remaining portion of the conductive material layer forms a conductive fill layer 334. During the planarization process, the portion of the barrier layer 332 outside the opening 328 and the through hole 330 is also removed. The planarization process may help provide a highly planarized bonding surface, thereby facilitating a subsequent bonding process with another chip structure.

[0119] like Fig. 3IAs shown, according to some embodiments, capacitor element 118 is formed. In some embodiments, conductive bonding structures 336P and 336G are used to provide electrical connections between power and ground, respectively. In some embodiments, conductive bonding structure 336P is electrically connected to capacitor electrodes 308A and 318A. In some embodiments, conductive bonding structure 336P is in direct contact with the sidewalls of capacitor electrodes 308A and 318A. In some embodiments, conductive bonding structure 336G is electrically connected to capacitor electrodes 314A and 322A. In some embodiments, conductive bonding structure 336G is in direct contact with the sidewalls of capacitor electrodes 314A and 322A.

[0120] In some embodiments, the conductive bonding structure 336S is used to provide an electrical connection with the signal net of the chip structure 102A. Fig. 3I As shown, in some embodiments, the conductive bonding structure 336S penetrates the capacitor dielectric layers 310, 316, and 320. In some embodiments, the conductive bonding structure 336S is in direct contact with the capacitor dielectric layers 310, 316, and 320. In some embodiments, the conductive bonding structure 336S is electrically isolated from the capacitor electrodes 308A-308C, 314A-314C, and 322A-322C.

[0121] Various changes and / or modifications may be made to the embodiments of the present invention. Figure 4 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, more capacitor elements are formed, including capacitor elements 118A and 118B.

[0122] In some embodiments, for forming Fig. 3I The process of forming the structure shown in FIG. 1 may be repeated two or more times. Figure 4 The structure shown in Fig. 3I Similar to the embodiment in, Figure 4 The structure shown in FIG. 1 includes etch stop layers 302a, 302b, 324a and 324b, dielectric layers 106a, 106b, 106c, 106d, 326a and 326b, capacitor elements 118A and 118b, and conductive bonding structures 336P1, 336P2, 336G1, 336G2, 336S1 and 336S2.

[0123] Various changes and / or modifications may be made to the embodiments of the present invention. FIG. 5A to FIG. 5I is a cross-sectional view of a process for forming a portion of a package structure according to some embodiments.

[0124] Figure 5A to Figure 5I The formation of capacitor element 518 is shown. In some embodiments, Figure 5A to Figure 5I The method for forming the capacitor element 518 shown in FIG. 5 can be used to form Figure 1F The capacitor element 118 is located near the middle region R. In some embodiments, Figure 5A to Figure 5I The method for forming the capacitor element 518 shown in FIG. 5 can be used to form Figure 2 Capacitor element 218 is shown in FIG.

[0125] and Figure 3A The embodiment shown in is similar to that shown in Figure 5A As shown, an etch stop layer 302 and a dielectric layer 116 a are formed over the conductive feature 114 in accordance with some embodiments.

[0126] like Figure 5B As shown, according to some embodiments, a protruding structure 502 is formed above the dielectric layer 116a. The protruding structure 502 may be made of a dielectric material. The protruding structure 502 may be made of silicon oxide, silicon nitride, silicon oxynitride, other suitable materials or combinations thereof. A dielectric material layer may be deposited above the dielectric layer 116a. Then, a portion of the dielectric material layer is removed. Thus, the remaining portion of the dielectric material layer forms the protruding structure 502.

[0127] As shown in FIG5C , according to some embodiments, a capacitor electrode layer 504 is formed on the dielectric layer 116a and the protruding structure 502. The capacitor electrode layer 504 extends along the sidewall and top of the protruding structure 502. The material and formation method of the capacitor electrode layer 504 may be the same as or similar to that of the capacitor electrode layer 304.

[0128] like Figure 5D As shown in FIG. 1 , according to some embodiments, the capacitor electrode layer 504 is partially removed. One or more photolithography processes and one or more etching processes may be used to partially remove the capacitor electrode layer 504. Figure 5D As shown, the remaining portion of the capacitor electrode layer 504 forms a plurality of capacitor electrodes 506A, 506B and 506C.

[0129] like Figure 5E As shown, according to some embodiments, a capacitor dielectric layer 508 is formed above the capacitor electrodes 506A-506C and the dielectric layer 116a. The material and formation method of the capacitor dielectric layer 508 may be the same or similar to the material and formation method of the capacitor dielectric layer 310. In some embodiments, the capacitor dielectric layer 508 is a single layer. In some other embodiments, the capacitor dielectric layer 508 includes a plurality of sub-layers. In some embodiments, some sub-layers are made of different materials.

[0130] like Fig. 5F As shown, according to some embodiments, a capacitor electrode layer 510 is formed on the capacitor dielectric layer 508. The material and formation method of the capacitor electrode layer 510 may be the same as or similar to that of the capacitor electrode layer 504.

[0131] like Figure 5G As shown, according to some embodiments, the capacitor electrode layer 510 is partially removed. One or more photolithography processes and one or more etching processes may be used to partially remove the capacitor electrode layer 510. Figure 5G As shown, the remaining portion of the capacitor electrode layer 510 forms a plurality of capacitor electrodes 512A and 512B.

[0132] and Figure 3E to Figure 3F The embodiment shown is similar to Figure 5H As shown, according to some embodiments, a dielectric layer 116 b , an etch stop layer 324 , and a dielectric layer 326 are sequentially formed.

[0133] and Figure 3G to Figure 3I The embodiment shown is similar to Fig.5I As shown, according to some embodiments, conductive bonding structures 336P, 336G, and 336S are formed. Each conductive bonding structure 336P, 336G, and 336S includes a barrier layer 332 and a conductive filling layer 334. Each conductive bonding structure 336P, 336G, and 336S can be used as Figure 1F and Figure 2 The conductive bonding structure 122 shown in FIG. Each conductive bonding structure 336P, 336G and 336S can be used as Figure 2 The conductive bonding structure 222 is shown in FIG.

[0134] like Fig.5I As shown, according to some embodiments, a capacitor element 518 is formed. In some embodiments, the conductive bonding structures 336P and 336G are used to provide electrical connections to power and ground, respectively. In some embodiments, the conductive bonding structure 336P is electrically connected to the capacitor electrode 506A. In some embodiments, the conductive bonding structure 336P is in direct contact with the sidewall of the capacitor electrode 506A. In some embodiments, the conductive bonding structure 336G is electrically connected to the capacitor electrode 512A. In some embodiments, the conductive bonding structure 336G is in direct contact with the sidewall of the capacitor electrode 512A.

[0135] In some embodiments, the conductive bonding structure 336S is used to provide an electrical connection with the signal net of the chip structure 102A. Fig.5I As shown, in some embodiments, the conductive bonding structure 336S penetrates the capacitor dielectric layer 508. In some embodiments, the conductive bonding structure 336S is in direct contact with the capacitor dielectric layer 508. In some embodiments, the conductive bonding structure 336S is electrically isolated from the capacitor electrodes 506A-506C and 512A-512B.

[0136] In some embodiments, a wafer-on-wafer (WoW) process is used to form a package structure. However, the embodiments of the present invention are not limited thereto. Various changes and / or modifications may be made to the embodiments of the present invention. In some embodiments, a chip-on-wafer (CoW) process is used to form a package structure.

[0137] 6A to 6F is a cross-sectional view of different stages of forming a portion of a package structure according to some embodiments. Fig. 6A As shown, the formation Figure 1B In some embodiments, the chip structure (or a structure including a chip) 102A is a semiconductor wafer.

[0138] and Figure 1C The embodiment shown in is similar to that shown in Figure 6B As shown, according to some embodiments, chip structure 102B is picked up and prepared to be bonded with chip structure 102A. In some embodiments, chip structure 102B is tested to ensure good quality before bonding with chip structure 102A. In some embodiments, as shown in FIG. Figure 6B As shown, chip structure 102A (eg, semiconductor wafer) is wider than chip structure 102B.

[0139] and Figure 1D The embodiment shown in is similar to that shown in Figure 6C As shown, according to some embodiments, the chip structure 102B is bonded to the chip structure 102A by dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, no solder element containing tin is formed between the chip structures 102A and 102B.

[0140] like Fig.6D As shown, according to some embodiments, a protective layer 602 is formed above the chip structure 102A to laterally surround the chip structure 102B. The protective layer 602 may be made of a molding material or include a molding material. The molding material may include an epoxy-based material dispersed with a filler (e.g., silica fiber). Alternatively, the protective layer 602 may be made of a material such as silica or include the aforementioned material. A planarization process may be performed to partially remove the protective layer 602 to expose the chip structure 102B. Thus, the heat dissipation performance of the chip structure 102B may be improved.

[0141] like Fig. 6EAs shown, according to some embodiments, the carrier substrate 100 is removed. Then, the chip structure 102A is thinned using a planarization process. The planarization process may include a CMP process, a grinding process, an etching process, other applicable processes or a combination thereof. As a result, the through-chip via 112 that was originally covered by the semiconductor substrate 104 is exposed. In some embodiments, the through-chip via 112 protrudes from the bottom surface of the chip structure 102A.

[0142] and Figure 1F The embodiment shown in is similar to that shown in Fig. 6F As shown, according to some embodiments, a redistribution structure 604 and a conductive bump 606 are formed. In some embodiments, a sawing process is used to separate the structure into multiple package structures. Fig. 6F One of the package structures is shown. The package structure may be a system on an integrated chip (SoIC), which may be further integrated into another package. The package may include multiple chip structures, the chip structures are bonded to an intermediate substrate, and the intermediate substrate is further bonded to another substrate. Alternatively, the package may include multiple chip structures surrounded by a protective layer and a redistribution structure formed on the chip structure and the protective layer.

[0143] Various changes and / or modifications may be made to the embodiments of the present invention. Figure 7 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 2 The embodiment shown in is similar to that shown in Figure 7 As shown, one or more capacitor elements 718 are formed. The capacitor elements 718 are located next to the conductive vias of the conductive bonding structure 222. The capacitor elements 718 are laterally surrounded by the dielectric bonding structure 216 of the chip structure 102B. In some embodiments, some of the capacitor elements 718 and the conductive bonding structure 222 are electrically connected to each other. Figure 3A to Figure 3I , Figure 4 and / or Figure 5A-Figure 5I Capacitor element 718 is formed by the method shown in .

[0144] As described above, in some embodiments, the package structure is formed using a chip-on-wafer (CoW) process. Various changes and / or modifications may be made to the embodiments of the present invention. In some embodiments, a plurality of chip structures are provided above a carrier wafer. Thus, Fig. 8A As shown, a reconstructed wafer is formed.

[0145] FIG. 8A to FIG. 8E is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. Fig. 8AAs shown, a plurality of chip structures 802A and 802B are fixed on a carrier wafer 800. The chip structures 802A and 802B are laterally spaced apart from each other. A dielectric layer 812 is formed in the gaps between the chip structures. Fig. 8A As shown, a reconstructed wafer is formed.

[0146] In some embodiments, each chip structure 802A and 802B is similar to chip structure 102A. Each chip structure 802A and 802B includes a semiconductor substrate 804 and a device portion 806. A plurality of device elements, such as transistors, are formed in the device portion 806. The chip structures 802A and 802B also include front-side interconnect portions 809A and 809B. Each front-side interconnect portion 809A and 809B is used to form interconnections between the device elements formed in the device portion 806. Similar to the front-side interconnect portion 106, each front-side interconnect portion 809A and 809B includes a plurality of dielectric layers 808a and a plurality of conductive components 808b. The chip structures 802A and 802B also include through-chip vias 810.

[0147] According to some embodiments, Figure 8B As shown, an interconnect structure 811 is formed above the reconstructed wafer. The interconnect structure 811 extends across the opposite sidewalls of the chip structures 802A and 802B. The interconnect structure 811 includes a plurality of dielectric layers 812 and a plurality of conductive components 814. Figure 8B As shown, some conductive features 814 (eg, conductive features 814 ′) are used to form electrical connections between chip structures 802A and 802B.

[0148] Subsequently, similar to the above embodiment, Figure 8B As shown, according to some embodiments, a dielectric bonding structure 816 and a conductive bonding structure 822 are formed over the interconnect structure 811. Similar to the conductive bonding structure 122, each conductive bonding structure 822 may include a metal bonding structure 820M and a conductive via 820V.

[0149] like Figure 8B As shown, in some embodiments, a capacitor element 818 is formed around the conductive via 820V. Figure 3A to Figure 3I , Figure 4 and / or Figure 5A-Figure 5I Capacitor element 818 is formed by the method shown in .

[0150] with Figure 6B to Figure 6C The embodiment shown in is similar to that shown in Figure 8C As shown, according to some embodiments, the plurality of chip structures 826A and 826B are directly bonded to the dielectric bonding structure 816 and the conductive bonding structure 822. In some embodiments, no tin-containing element is formed therebetween.

[0151] and Figure 6B to Figure 6C Similar to the chip structure 102B shown in FIG. 8 , each chip structure 826A and 826B includes a dielectric bonding structure 828 and a plurality of conductive bonding structures 832. Similar to the conductive bonding structure 122, each conductive bonding structure 832 may include a metal bonding structure 830M and a conductive via 830V.

[0152] like Figure 8C As shown, in some embodiments, a capacitor element 834 is formed next to the conductive via 830V. Figure 3A to Figure 3I , Figure 4 and / or Figure 5A-Figure 5I Capacitor element 834 is formed by the method shown in .

[0153] like Fig.8D As shown, according to some embodiments, a protection layer 836 is formed over the interconnect structure 811 to laterally surround the chip structures 826A and 826B. The material and formation method of the protection layer 836 may be the same as Fig.6D The material and forming method of the protection layer 602 are the same or similar.

[0154] like Fig. 8E As shown, according to some embodiments, the carrier wafer 800 is removed. Then, the chip structures 802A and 802B are thinned using a planarization process. The planarization process may include a CMP process, a grinding process, an etching process, other applicable processes or combinations thereof. Thus, the through-chip vias 810 that were originally covered by the semiconductor substrate 804 are exposed. In some embodiments, the through-chip vias 810 protrude from the bottom surfaces of the chip structures 802A and 802B.

[0155] and Figure 1F The embodiment shown in is similar to that shown in Fig. 8E As shown, according to some embodiments, a redistribution structure 838 and a conductive bump 840 are formed. In some embodiments, a sawing process is used to separate the structure into a plurality of package structures. Fig. 8E One of the package structures is shown in FIG. The package structure may be a system on an integrated chip (SoIC), which may be further integrated into another package. The package may include a plurality of chip structures, the chip structures are bonded to an intermediate substrate, and the intermediate substrate is further bonded to another substrate. Alternatively, the package may include a plurality of chip structures surrounded by a protective layer and a redistribution structure formed on the chip structures and the protective layer.

[0156] The embodiment of the utility model forms a packaging structure, which includes a stack of multiple chip structures. The chip structures are directly bonded to each other through dielectric-to-dielectric bonding and metal-to-metal bonding. The metal-to-metal bonding is achieved by using a conductive bonding structure. Each conductive bonding structure includes a metal bonding structure and a conductive through hole located directly below the metal bonding structure. A capacitor element is formed next to the conductive through hole. Therefore, more space available for wiring is obtained in the interconnection structure part of the chip structure. The performance and reliability of the packaging structure are improved.

[0157] According to some embodiments, a method for forming a package structure is provided. The method for forming a package structure includes forming a capacitor element above a first chip structure and forming a dielectric layer above the capacitor element. The method for forming a package structure also includes forming a conductive bonding structure in the dielectric layer. The top surface of the conductive bonding structure is substantially coplanar with the top surface of the dielectric layer. The conductive bonding structure penetrates the capacitor element and is electrically connected to the capacitor element. The method for forming a package structure also includes connecting a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

[0158] In some embodiments, forming the capacitor element includes forming a first capacitor electrode above the first chip structure and forming a first capacitor dielectric layer above the first capacitor electrode and the first chip structure. Forming the capacitor element also includes forming a second capacitor electrode above the first capacitor dielectric layer.

[0159] In some embodiments, the method for forming a package structure further includes removing a portion of the dielectric layer and the capacitor element to form an opening. The opening exposes a side wall of the first capacitor electrode. In addition, the method for forming a package structure includes forming a conductive bonding structure in the opening.

[0160] In some embodiments, the method of forming a package structure further includes partially removing the dielectric layer and the capacitor element to form a second opening. The second opening exposes the sidewall of the second capacitor electrode. In addition, the method of forming a package structure includes forming a second conductive bonding structure in the second opening.

[0161] In some embodiments, the opening and the second opening are formed simultaneously.

[0162] In some embodiments, the conductive bonding structure and the second conductive bonding structure are formed simultaneously.

[0163] In some embodiments, the method for forming a package structure further includes forming a third conductive bonding structure penetrating the dielectric layer and the first capacitor dielectric layer, wherein the third conductive bonding structure is electrically isolated from the first capacitor electrode and the second capacitor electrode.

[0164] In some embodiments, forming the capacitor element further includes forming a second capacitor dielectric layer above the second capacitor electrode and the first capacitor dielectric layer and forming a third capacitor electrode above the second capacitor dielectric layer. In addition, forming the capacitor element includes forming a third capacitor dielectric layer above the third capacitor electrode and the second capacitor dielectric layer and forming a fourth capacitor electrode above the third capacitor dielectric layer.

[0165] In some embodiments, the conductive bonding structure is in direct contact with the sidewalls of the first capacitor electrode and the third capacitor electrode, and the second conductive bonding structure is in direct contact with the sidewalls of the second capacitor electrode and the fourth capacitor electrode.

[0166] In some embodiments, the method for forming a package structure further includes disposing a third chip structure beside the first chip structure and forming a protection layer laterally surrounding the first chip structure and the third chip structure before forming the capacitor element. After forming the dielectric layer, the dielectric layer extends across opposite sidewalls of the first chip structure and the second chip structure.

[0167] According to some embodiments, a packaging structure is provided. The packaging structure includes a first chip structure. The first chip structure has a first metal bonding structure and a first conductive via. The first conductive via is in direct contact with the first metal bonding structure. The first chip structure also has a first dielectric layer, which laterally surrounds the first metal bonding structure and the first conductive via. The surface of the first dielectric layer is substantially coplanar with the surface of the first metal bonding structure. The packaging structure also includes a second chip structure, which is located above the first chip structure. The second chip structure has a second metal bonding structure, which is in direct contact with the first metal bonding structure. The second chip structure also has a second conductive via, which is in direct contact with the second metal bonding structure. The second chip structure also has a second dielectric layer, which laterally surrounds the second metal bonding structure and the second conductive via. The surface of the second dielectric layer is substantially coplanar with the surface of the second metal bonding structure, and the second dielectric layer is in direct contact with the first dielectric layer. The packaging structure also includes a capacitor element, which is located between the first metal bonding structure and the bottom surface of the first conductive via.

[0168] In some embodiments, the first chip structure has a third metal bonding structure and a third conductive via, and the third conductive via is in direct contact with the third metal bonding structure. The first dielectric layer laterally surrounds the third metal bonding structure and the third conductive via. The surface of the first dielectric layer is substantially coplanar with the surface of the third metal bonding structure. The capacitor element has a first electrode and a second electrode. The first electrode is electrically connected to the first conductive via. The second electrode is electrically connected to the third conductive via.

[0169] In some embodiments, the capacitor element further comprises a third electrode and a fourth electrode, wherein the third electrode is electrically connected to the first conductive via, and the fourth electrode is electrically connected to the third conductive via.

[0170] In some embodiments, a portion of the second electrode is located between the first electrode and the third electrode. A portion of the third electrode is located between the second electrode and the fourth electrode.

[0171] In some embodiments, the first conductive via is in direct contact with a sidewall of the first electrode. The third conductive via is in direct contact with a sidewall of the second electrode.

[0172] In some embodiments, the package structure further includes a second capacitor element located between the second metal bonding structure and a top surface of the second conductive via.

[0173] According to some embodiments, a packaging structure is provided. The packaging structure includes a first chip structure and an interconnection structure, wherein the interconnection structure is located above the first chip structure. The packaging structure also includes a dielectric bonding structure and a metal bonding structure, wherein the dielectric bonding structure is located above the interconnection structure, and the metal bonding structure is laterally surrounded by the dielectric bonding structure. The top surface of the metal bonding structure is substantially coplanar with the top surface of the dielectric bonding structure. The packaging structure also includes a conductive via, which is connected to the metal bonding structure and is laterally surrounded by the dielectric bonding structure. In addition, the packaging structure includes a second chip structure, which is directly bonded to the dielectric bonding structure and the metal bonding structure. The packaging structure also includes a capacitor element, which is located next to the conductive via and is laterally surrounded by the dielectric bonding structure.

[0174] In some embodiments, the package structure further includes a third chip structure, the third chip structure is laterally spaced apart from the first chip structure, and the interconnect structure extends across opposite sidewalls of the first chip structure and the third chip structure.

[0175] In some embodiments, the capacitor element has an electrode, and the conductive via is in direct contact with a sidewall of the electrode.

[0176] In some embodiments, the package structure further includes a second capacitor element, the second capacitor element is located between the capacitor element and the interconnect structure, the second capacitor element has a second electrode, and the second electrode is electrically connected to the conductive via.

[0177] The foregoing text summarizes the components of many embodiments so that those skilled in the art can better understand the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the novel spirit and scope of the present invention. Various changes, substitutions or modifications can be made to the present invention without departing from the novel spirit and scope of the present invention.

Claims

1. A packaging structure having an integrated chip with a capacitor, characterized in that: The packaging structure comprises: A first chip structure, wherein the first chip structure has: a first metal bonding structure; a first conductive via, wherein the first conductive via is in direct contact with the first metal bonding structure; and a first dielectric layer laterally surrounding the first metal bonding structure and the first conductive via, wherein a surface of the first dielectric layer is substantially coplanar with a surface of the first metal bonding structure; The second chip structure is located above the first chip structure, wherein the second chip structure has: a second metal bonding structure, wherein the second metal bonding structure is in direct contact with the first metal bonding structure; a second conductive via, wherein the second conductive via is in direct contact with the second metal bonding structure; and a second dielectric layer laterally surrounding the second metal bonding structure and the second conductive via, wherein a surface of the second dielectric layer is substantially coplanar with a surface of the second metal bonding structure, and the second dielectric layer is in direct contact with the first dielectric layer; and A capacitor element is located between the first metal bonding structure and the bottom surface of the first conductive via.

2. The packaging structure according to claim 1, characterized in that: The first chip structure has a third metal bonding structure and a third conductive via, wherein the third conductive via is in direct contact with the third metal bonding structure. The first dielectric layer laterally surrounds the third metal bonding structure and the third conductive via, The surface of the first dielectric layer is substantially coplanar with the surface of the third metal bonding structure, The capacitor element has a first electrode and a second electrode, The first electrode is electrically connected to the first conductive via, and The second electrode is electrically connected to the third conductive via.

3. The packaging structure according to claim 2, characterized in that: The capacitor element further comprises a third electrode and a fourth electrode, The third electrode is electrically connected to the first conductive via, and The fourth electrode is electrically connected to the third conductive via.

4. The packaging structure according to claim 3, characterized in that: A portion of the second electrode is located between the first electrode and the third electrode, and A portion of the third electrode is located between the second electrode and the fourth electrode.

5. The packaging structure according to claim 2, characterized in that: The first conductive via is in direct contact with a side wall of the first electrode, and The third conductive via is in direct contact with a side wall of the second electrode.

6. The packaging structure according to claim 1, characterized in that: Also includes: A second capacitor element is located between the second metal bonding structure and a top surface of the second conductive via.

7. A packaging structure, characterized in that: The packaging structure comprises: A first chip structure; an interconnect structure, located above the first chip structure; a dielectric bonding structure located above the interconnect structure; a metal bonding structure laterally surrounded by the dielectric bonding structure, wherein a top surface of the metal bonding structure is substantially coplanar with a top surface of the dielectric bonding structure; a conductive via connected to the metal bonding structure and laterally surrounded by the dielectric bonding structure; A second chip structure directly bonded to the dielectric bonding structure and the metal bonding structure; and A capacitor element is located adjacent to the conductive via and is laterally surrounded by the dielectric bonding structure.

8. The packaging structure according to claim 7, characterized in that: Also includes: The third chip structure is laterally spaced apart from the first chip structure, wherein the interconnect structure extends across opposite sidewalls of the first chip structure and the third chip structure.

9. The packaging structure according to claim 7, characterized in that: The capacitor element has an electrode, and the conductive via is in direct contact with a sidewall of the electrode.

10. The packaging structure according to claim 9, characterized in that: Also includes: The second capacitor element is located between the capacitor element and the interconnect structure, wherein the second capacitor element has a second electrode, and the second electrode is electrically connected to the conductive via.

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