Package structure

Abstract

A package structure includes a chip structure, an interconnect dielectric layer, an interconnect conductive structure, a transmission line, and a magnetic structure. Bonding to the substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; an interconnect dielectric layer is formed over the chip structure. The package structure also includes an interconnect conductive structure formed in the interconnect dielectric layer; the transmission line is formed in the interconnection dielectric layer. The package structure also includes a magnetic structure formed in the interconnect dielectric layer and separated from the transmission line by the interconnect dielectric layer. In addition, the magnetic structure is electrically isolated from the chip structure and the interconnection conductive structure.

Description

Technical Field

[0001] The embodiments of the utility model relate to packaging technology, and in particular to a packaging structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have resulted in semiconductor devices with more sophisticated functionality and / or higher levels of integration. Functional density (i.e., the number of devices interconnected per chip area) has increased while geometry size (i.e., the smallest component produced during the manufacturing process) has decreased. This process of device size miniaturization generally provides the benefits of increased production efficiency and reduced associated costs.

[0003] The chip package not only provides protection for the semiconductor device from environmental pollution, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures that occupy less space or have a lower height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies. These relatively new semiconductor die packaging technologies face manufacturing challenges. Utility Model Content

[0005] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0006] In some embodiments, a packaging structure is provided, which includes a chip structure bonded to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; an interconnect dielectric layer formed above the chip structure; an interconnect conductive structure formed in the interconnect dielectric layer; a transmission line formed in the interconnect dielectric layer; and a magnetic structure formed in the interconnect dielectric layer and separated from the transmission line by the interconnect dielectric layer, wherein the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structure.

[0007] According to one embodiment of the present invention, the magnetic structure includes: a first magnetic portion formed on a first side of the transmission line; and a second magnetic portion formed on a second side of the transmission line, wherein the first side is opposite to the second side, and wherein the distance between the first magnetic portion and the second magnetic portion in a first direction is greater than the size of the transmission line in the first direction.

[0008] According to one embodiment of the present invention, the magnetic structure further includes: a third magnetic portion formed on a third side of the transmission line, wherein the third magnetic portion directly contacts the first magnetic portion and the second magnetic portion.

[0009] According to one embodiment of the present invention, the magnetic structure further includes: a fourth magnetic portion formed on a fourth side of the transmission line, wherein the fourth magnetic portion directly contacts the first magnetic portion and the second magnetic portion.

[0010] According to one embodiment of the present invention, the third magnetic part further includes a plurality of third magnetic units that are laterally spaced apart from each other.

[0011] In some embodiments, a packaging structure is provided, which includes a chip structure bonded to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; a dielectric layer formed above the substrate and covering the sidewall surface of the chip structure; a dielectric through-hole formed through the dielectric layer; and an interconnection structure formed above the dielectric layer and the chip structure, wherein the interconnection structure includes: a transmission line electrically connected to the chip structure; a magnetic structure separated from the transmission line by a first space, wherein the magnetic structure is electrically isolated from the transmission line, the chip structure and the dielectric through-hole; and an interconnection dielectric layer formed around the transmission line and the magnetic structure, wherein the interconnection dielectric layer fills the first space between the magnetic structure and the transmission line.

[0012] According to one embodiment of the present invention, the magnetic structure includes: a first top magnetic part, located above the transmission line; a first bottom magnetic part, located below the transmission line; and a plurality of first magnetic units, spaced apart from each other in a first direction and connecting the first top magnetic part and the first bottom magnetic part in a second direction.

[0013] According to one embodiment of the present invention, the first top magnetic portion is longitudinally oriented along a third direction, and the first bottom magnetic portion is longitudinally oriented along a fourth direction, wherein the fourth direction is different from the third direction.

[0014] According to one embodiment of the present invention, the magnetic structure also includes: a second top magnetic portion overlapping the transmission line and spaced apart from the first top magnetic portion; and a plurality of second magnetic units spaced apart from each other in the first direction and connected to the second top magnetic portion and the first bottom magnetic portion in the second direction.

[0015] According to one embodiment of the present invention, the magnetic structure also includes: a second bottom magnetic portion, located below the transmission line and spaced apart from the first bottom magnetic portion; and a plurality of third magnetic units, spaced apart from each other in the first direction and connected to the second top magnetic portion and the second bottom magnetic portion in the second direction, wherein the plurality of first magnetic units and the plurality of third magnetic units are on a first side of the transmission line, and the plurality of second magnetic units are on a second side of the transmission line opposite to the first side. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0017] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Fig. 1I , Figure 1J , Figure 1K A schematic cross-sectional view showing an intermediate stage of manufacturing a package structure according to some embodiments.

[0018] Figure 1K-1 An enlarged cross-sectional schematic diagram showing a transmission line of a magnetic structure and a packaging structure according to some embodiments.

[0019] Figure 1K-2 A schematic perspective view of a magnetic structure is shown according to some embodiments.

[0020] Figure 1K-3 According to some embodiments, along Figure 1K-2 Line Y-Y' shows a schematic cross-sectional view of the magnetic structure.

[0021] Figure 1K-2 ' shows a schematic perspective view of a magnetic structure according to some embodiments.

[0022] Figure 2A A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0023] Figure 2B A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0024] Figure 2C A schematic cross-sectional view of a package structure according to some embodiments is shown.

[0025] Figure 3A , Figure 3B and Figure 3C An enlarged cross-sectional schematic diagram of a magnetic structure according to some embodiments is shown.

[0026] Figure 4A and Figure 4B An enlarged cross-sectional schematic diagram of a magnetic structure according to some embodiments is shown.

[0027] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F and Figure 5G An enlarged cross-sectional schematic diagram of a magnetic structure according to some embodiments is shown.

[0028] Figure 6 A schematic perspective view of a package structure according to some embodiments is shown.

[0029] Figure 7 A schematic top view of a package structure according to some embodiments is shown.

[0030] Figure 8 A schematic perspective view of a package structure according to some embodiments is shown.

[0031] The reference numerals are as follows:

[0032] 10: Bottom wafer

[0033] 20,20a,20b,20c,20-1,20-2: Chip structure

[0034] 100,100a,100b,100c,100d,100e,100f:Package structure

[0035] 102,202: base

[0036] 104,204: Installation area

[0037] 110, 210, 310, 310b, 310c: Interconnection structure

[0038] 112,212,376: Conductive structure

[0039] 114,214: Intermetallic dielectric layer

[0040] 116,120,132,216,220,232,302,362: Dielectric layer

[0041] 118,134,234: Conductive pad

[0042] 122,222: vias

[0043] 130,230:Joint structure

[0044] 240: substrate through hole

[0045] 304,304-1,304-2: Dielectric vias

[0046] 306: seed layer

[0047] 312,322,332,342,352: Interconnect dielectric layer

[0048] 314,318,374: Opening

[0049] 316,316-1,316-2,326,336,346,356: Interconnection conductive structure

[0050] 372: Protective layer

[0051] 378: Conductive bump

[0052] 400,400',400a,400b,400c,400-3a,400-3b,400-3c,400-4a,400-4b,400-5a,400-5b,400-5c,400-5d,400-5e,400-5f,400-5g,400d,400e: Magnetic structure

[0053] 402,402-3a,402-3b,402-3c,402-4a,402-4b,402-5a,402-5c,402-5e,402-5g,404,404-3a, 404-3b,404-3c,404-4a,404-4b,404-5b,404-5c,404-5d,404-5e,406,406-3a,406-3b,406- 3c,406-4a,406-4b,406-5b,406-5c,406-5d,406-1,406-2,406-3,406-4,406-5,406-6,406-7,406-8,408,408-3a,408-3b,408-3c,408-4a,408-4b,408-5d,408-5d,408-5e,408-5f: Magnetic part

[0054] 402-1, 402-2, 402-3, 402-4: Bottom magnetic part

[0055] 408-1,408-2,408-3,408-4,408-5: Top magnetic part

[0056] 402_TS,404_TS,406_TS,408_TS,502_TS: Top surface

[0057] 402_BS,404_BS,406_BS,408_BS,502_BS: Bottom surface

[0058] 402_SS1,402_SS2,404_SS1,404_SS2,406_SS1,406_SS2,408_SS1,408_SS2,502_SS1,502_SS2: side wall surface

[0059] 404_U,406_U: Magnetic unit

[0060] 501,503:Metal wire

[0061] 502: Transmission line

[0062] 502-1,502-2,502-3:Partial

[0063] D1,D2,D3,D4: distance DETAILED DESCRIPTION

[0064] It should be understood that the following disclosure provides many different embodiments or examples to implement different parts of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the utility model. For example, the size of the component is not limited to the scope or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed in direct contact, and may also include an additional component that can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the appearance structure.

[0065] Some variations of the embodiments are described herein. In the various views and display embodiments, similar reference symbols are used to mark similar elements. It should be understood that additional operations may be provided before, during, or after the method, and for other embodiments of the method, some of the operations described may be replaced or eliminated.

[0066] Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used to conveniently describe the relationship of one element or component to another (plural) element or component in the drawings. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used would be interpreted accordingly.

[0067] The present invention may be related to packaging structures, such as three-dimensional (3D) packaging, three-dimensional integrated circuit devices, and 2.5D packaging. The present invention forms a packaging structure, which includes a substrate that carries one or more dies or packages and a protective element (such as a protective cover) located next to the dies or packages. The protective element may also serve as a warpage control element and / or a heat dissipation element.

[0068] Other components and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packages, three-dimensional integrated circuit devices, and / or 2.5D packages. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate to allow testing using probes or probe cards and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods that may be used herein may be used in conjunction with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0069] A packaging structure and a method for manufacturing the same are provided. The packaging structure may include a plurality of chip bonding structures bonded to a substrate by hybrid bonding. A transmission line is formed to connect at least two chip structures, and a magnetic structure is formed adjacent to the transmission line. The magnetic structure may help improve the impedance of the transmission line, thereby reducing the current consumption of the final packaging structure. Therefore, the packaging structure can be applied to novel portable products, such as new generation smartphones (e.g., 5G, 6G), tablet computers, automobiles, Internet of Things (IoT) devices, and cloud computing devices with high clock frequencies (e.g., greater than about 5 to about 10 GBPS) / wired communication frequencies.

[0070] Figure 1A to Figure 1K The cross-sectional view of the intermediate stage of manufacturing the package structure 100 according to some embodiments is shown. Figures 1A to 1K The present invention is simplified to provide a better understanding of the concepts of the present invention. Additional components may be included in the package structure 100, and some of the components described below may be replaced, modified, or eliminated.

[0071] First, according to some embodiments, such as Figure 1AAs shown, a bottom wafer 10 is formed. In some embodiments, the bottom wafer 10 includes a device region 104 formed in a substrate 102 and an interconnect structure 110 formed above the substrate 102. In some embodiments, the substrate 102 is a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0072] In some embodiments, the device region 104 includes various device elements, such as active devices, passive components, conductive portions, and / or insulating materials. Examples of device elements may include, but are not limited to, transistors, diodes, and / or other applicable elements. Examples of transistors may include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BTJs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), or the like. Various processes may be performed to form the device elements, such as deposition, etching, photolithography, annealing, and other applicable processes. The transistors in the device region 104 may be used in various applications, such as 5G devices, artificial intelligence (AI) devices, Internet of Things (IoT) devices, automotive devices, system-on-chip (SoC) devices, high performance computing (HPC) devices, neural network processing unit (NPU) devices, graphics processing unit (GPU) devices, central processing unit (CPU) devices, field programmable gate array (FPGA) devices, or the like. In addition, transistors in different regions may have different functions.

[0073] The interconnect structure 110 may include a plurality of metallization layers, and each metallization layer may include a metallization pattern formed in a dielectric layer. The metallization pattern may be electrically coupled to a device (e.g., a transistor) in a device region 104 of the substrate 102. In some embodiments, the interconnect structure 110 includes a conductive structure 112, such as a metal line and a metal via, formed in one or more inter-metal dielectric (IMD) layers 114. In some embodiments, the conductive structure 112 may be configured to transfer a signal, or may be connected to ground. The interconnect structure 110 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

[0074] In some embodiments, the intermetallic dielectric layer 114 includes a plurality of dielectric layers made of a low dielectric constant material having a dielectric constant value less than 7. In some embodiments, the intermetallic dielectric layer 114 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. The intermetallic dielectric layer 114 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes. In some embodiments, the conductive structure 112 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or a combination of the foregoing. The conductive structure 112 may be formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0075] In some embodiments, the interconnect structure 110 further includes a dielectric layer 116 and a conductive pad 118 formed on the dielectric layer 116. In addition, the conductive pad 118 further extends through the dielectric layer 116 and is connected to the conductive structure 112. In some embodiments, the conductive pad 118 is an aluminum pad. In some embodiments, the dielectric layer 116 is made of a low dielectric constant material having a dielectric constant value less than 7. In some embodiments, the dielectric layer 116 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like.

[0076] Thereafter, according to some embodiments, a dielectric layer 120 is formed over the dielectric layer 116 and the conductive pad 118, and a via 122 is formed through the dielectric layer 120. In some embodiments, the via 122 is electrically connected to the conductive structure 112. In some embodiments, the dielectric layer 120 includes a plurality of dielectric layers made of a low dielectric constant material having a dielectric constant value less than 7. In some embodiments, the dielectric layer 120 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. In some embodiments, the via 122 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof.

[0077] Next, according to some embodiments, a bonding structure 130 is formed over the interconnect structure 110. In some embodiments, the bonding structure 130 includes a dielectric layer 132 and a conductive pad 134 formed in the dielectric layer. In some embodiments, the conductive pad 134 is electrically connected to the via 122. In some embodiments, the dielectric layer 132 is made of a low dielectric constant material having a dielectric constant value less than 7. In some embodiments, the dielectric layer 132 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. In some embodiments, the conductive pad 134 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof.

[0078] According to some embodiments, Figure 1A As shown, after forming the base wafer 10, the chip structure 20 is bonded to the base wafer 10 by dielectric-to-dielectric bonding and metal-to-metal bonding. In other words, according to some embodiments, the chip structure 20 is bonded to the base wafer 10 by bumpless bonding (i.e., no bumps are formed between the chip structure 20 and the base wafer 10). Figure 1A Only one chip structure 20 is shown, but multiple chip structures 20 may be bonded to the base wafer 10. In some embodiments, a pick-and-place process is performed so that known good dies may be picked up and placed onto the base wafer 10 as chip structures 20.

[0079] More specifically, according to some embodiments, the chip structure 20 includes a substrate 202, a device region 204 formed in the substrate 202, an interconnect structure 210 formed above the substrate 202, and a bonding structure 230 formed above the interconnect structure 210. Similar to the interconnect structure 110, the interconnect structure 210 includes an intermetallic dielectric layer 214, dielectric layers 216 and 220, a conductive structure 212, and a via 222. In addition, the bonding structure 230 includes a dielectric layer 232 and a conductive pad 234 formed in the dielectric layer 232. In some embodiments, through substrate vias (TSVs) 240 are formed through the substrate 202 and electrically connected to the conductive structure 212 in the interconnect structure 210. In some embodiments, the through substrate vias 240 are made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof.

[0080] The processes and materials used to form the intermetal dielectric layer 214, dielectric layers 216 and 220, the conductive structure 212, the via 222, the dielectric layer 232 and the conductive pad 234 may be similar to or the same as the processes and materials used to form the intermetal dielectric layer 114, dielectric layers 116 and 118, the conductive structure 112, the via 122, the dielectric layer 132 and the conductive pad 134 described above, and therefore are not described in detail herein.

[0081] In some embodiments, the chip structure 20 is bonded to the substrate 102 by hybrid bonding. The hybrid bonding may include metal-to-metal bonding and dielectric-to-dielectric bonding. That is, no soldering elements are formed between the bottom wafer 10 and the chip structure 20. In some embodiments, the hybrid bonding includes bonding the bonding structure 230 to the bonding structure 130. In some embodiments, the dielectric layer 232 is bonded to the dielectric layer 132, and the conductive pad 234 is bonded to the conductive pad 134.

[0082] In some embodiments, a thermal operation is performed to enhance the bonding between the conductive pads 134 and 234. The temperature of the thermal operation may be in a range of about 100° C. to about 700° C. for about 1 hour to 3 hours.

[0083] According to some embodiments, Figure 1B As shown, after the chip structure 20 is bonded to the interconnect structure 110 of the bottom wafer 10, a dielectric layer 302 is formed over the bonding structure 130. More specifically, according to some embodiments, the dielectric layer 302 is formed over the bonding structure 130, around the sidewalls of the chip structure 20, and over the top surface of the chip structure 20, and a planarization process is performed until the top surface of the chip structure 20 is exposed from the dielectric layer 302.

[0084] In some embodiments, the dielectric layer 302 comprises silicon oxide or a low dielectric constant dielectric material, wherein the dielectric constant value (k value) of the low dielectric constant dielectric material is less than the dielectric constant value of silicon oxide. In some embodiments, the low dielectric constant dielectric material comprises a porous organic silicate film (e.g., SiOCH), tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon nitride carbon (SiCN), silicon oxycarbide (SiOCN), spin-on silicon-based polymer dielectrics, or a combination thereof. In some embodiments, the planarization process may comprise a grinding process, a chemical mechanical polishing (CMP) process, an etching process, a dry grinding process, one or more other applicable processes, or a combination thereof. In some embodiments, dielectric layer 302 has a thickness in a range from about 10 μm to about 30 μm.

[0085] According to some embodiments, Figure 1C As shown, after forming the dielectric layer 302, a through dielectric via (TDV) 304 is formed through the dielectric layer 302. The dielectric via 304 is configured to vertically pass through the dielectric layer 302 to provide electrical connection in the vertical direction. In some embodiments, the dielectric via 304 is vertically connected to the conductive pad 134. In some embodiments, the dielectric via 304 includes a dielectric via 304-1 connected to a ground voltage and a dielectric via 304-2 connected to a power supply voltage.

[0086] More specifically, a via trench may be formed through dielectric layer 302, and the via trench exposes a portion of conductive pad 134. Then, according to some embodiments, a seed layer 306 is formed over the exposed portion of conductive pad 134, and a conductive material is formed over the seed layer 306 in the via trench to form dielectric via 304.

[0087] In some embodiments, seed layer 306 may be made of titanium (Ti), cobalt (Co), copper (Cu), TiCu or the like. In some embodiments, dielectric via 304 is made of a conductive material, such as Cu, Al, W or other applicable conductive materials. After the conductive material is formed in the via trench, a chemical mechanical polishing (CMP) process may be performed to remove excess material overfilling the via trench. Dielectric via 304 may have various shapes in a top view, such as a plate (e.g., circular) or a strip. In some embodiments, dielectric via 304-1 has a strip shape, while dielectric via 304-2 has a plate shape.

[0088] According to some embodiments, after forming the dielectric via 304, the interconnect structure 310 is formed on the dielectric layer 302. First, according to some embodiments, such as Figure 1D As shown, interconnect dielectric layer 312 is formed over dielectric layer 302 and chip structure 20, and opening 314 is formed in interconnect dielectric layer 312. In some embodiments, interconnect dielectric layer 312 is made of a low dielectric constant material having a dielectric constant value less than 7. In some embodiments, interconnect dielectric layer 312 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. In some embodiments, interconnect dielectric layer 312 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0089] Next, according to some embodiments, such as Figure 1E As shown, interconnect conductive structure 316 is formed in opening 314. In some embodiments, interconnect conductive structure 316 includes interconnect conductive structure 316-1 directly connected to dielectric via 304-1 (e.g., connected to a ground voltage) and interconnect conductive structure 316-2 directly connected to dielectric via 304-2 (e.g., connected to a power supply voltage). In some embodiments, interconnect conductive structure 316 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or a combination of the foregoing. The conductive material can be formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process. In addition, after forming the conductive material, a grinding process, such as a chemical mechanical grinding process, can be performed. Furthermore, before forming interconnect conductive structure 316, a seed layer (not shown) can also be formed above opening 314. The seed layer may be made of titanium (Ti), cobalt (Co), copper (Cu), TiCu, or the like.

[0090] According to some embodiments, Figure 1FAs shown, after forming the interconnect conductive structure 316 , an opening 318 is formed in the interconnect dielectric layer 312 . More specifically, according to some embodiments, the dielectric layer 302 is patterned to form the opening 318 . In some embodiments, the opening 318 partially exposes the top surface of the chip structure 20 .

[0091] Then, according to some embodiments, such as Figure 1G As shown, the magnetic portion 402 is formed in the opening 318. In some embodiments, the magnetic portion 402 directly contacts the top surface of the chip structure 20. In some embodiments, the magnetic portion 402 is made of a magnetic material (e.g., a material having a high magnetic permeability). In some embodiments, the magnetic portion 402 is made of a material containing iron, nickel, cobalt, or an alloy of the foregoing. In some embodiments, the magnetic portion 402 is made of a material containing a nickel-zinc-copper-iron oxide alloy, a yttrium-bismuth-iron oxide alloy, a nickel-iron alloy, a cobalt-tantalum-zirconium alloy. In some embodiments, the magnetic portion 402 is formed by performing a spin coating process to form a 40% Ni-40% Zn-20% Cu-Fe2O4 alloy or an 80% Y-20% Bi-Fe5O 12 In some embodiments, the magnetic portion 402 is formed by performing an electroplating deposition process to form a Ni-20% Fe alloy. In some embodiments, the magnetic portion 402 is formed by performing a sputtering process to form a Ni-20% Fe alloy or a Co-4.5% Ta-4% Zr alloy.

[0092] According to some embodiments, Figure 1G As shown, after forming the magnetic material, a chemical mechanical polishing process may be performed until the top surface of the interconnect dielectric layer 312 is exposed to form a magnetic portion 402 in the interconnect dielectric layer 312. In some embodiments, the top surface of the magnetic portion 402 is substantially flush with the top surface of the interconnect dielectric layer 312 and the top surface of the interconnect conductive structure 316.

[0093] Next, according to some embodiments, such as Figure 1HAs shown, interconnection dielectric layers 322 and 332 are formed above the interconnection dielectric layer 312, and interconnection conductive structures 326 and 336 are formed in the interconnection dielectric layers 322 and 332. The formation of the interconnection dielectric layers 322 and 332 and the interconnection conductive structures 326 and 336 may be similar to or the same as the formation of the above-mentioned interconnection dielectric layer 312 and the interconnection conductive structure 316, so they are not repeated here. In addition, according to some embodiments, the transmission line 502 is also formed in the interconnection dielectric layer 332. The formation of the transmission line 502 may be similar to or the same as the formation of the interconnection conductive structures 326 and 336. In some embodiments, the transmission line 502 and the interconnection conductive structures 326 and 336 are made of the same material and formed in the same process. In some embodiments, the transmission line 502 connects at least two chip structures 20 formed in the package structure 100.

[0094] Then, according to some embodiments, such as Fig. 1I As shown, interconnect dielectric layers 342 and 352 are formed over interconnect dielectric layer 332, and interconnect conductive structures 346 and 356 are formed in interconnect conductive structures 342 and 352. The interconnect dielectric layers 312, 322, 332, 342, 352 with the interconnect conductive structures 316, 326, 336, 346, 356 may be considered as interconnect structure 310. In addition, according to some embodiments, magnetic portions 404, 406, 408 are formed in the interconnect dielectric layers 322, 332, 342, 352 of the interconnect structure 310. The magnetic portions 402, 404, 406, 408 may be considered as a magnetic structure 400 surrounding the transmission line 502. The magnetic structure 400 is configured to shield the transmission line, and thus the impedance of the transmission line 502 may be improved.

[0095] More specifically, interconnect dielectric layer 342 may be formed over interconnect dielectric layer 332, interconnect conductive structure 336, and transmission line 502, and interconnect conductive structure 336 may be formed in interconnect dielectric layer 332. Thereafter, magnetic via trenches may be formed through interconnect dielectric layers 342, 332, 322 to expose a portion of magnetic portion 402. Then, magnetic portions 404 and 406 may be formed in magnetic via trenches. After forming magnetic portions 404 and 406, interconnect dielectric layer 352 may be formed over interconnect dielectric layer 342, interconnect conductive structure 346, and magnetic portions 404 and 406, and then interconnect conductive structure 356 may be formed in interconnect dielectric layer 352. After forming the interconnect conductive structure 356, a magnetic via trench may be formed in the interconnect dielectric layer 352 to expose the top surface of the magnetic portions 404 and 406, and a magnetic portion 408 may be formed in the magnetic via trench in the interconnect dielectric layer 352. The formation of the interconnect dielectric layers 342 and 352, the interconnect conductive structures 346 and 356, and the magnetic portions 404, 406, 408 may be similar to or the same as the formation of the dielectric layer 112, the interconnect conductive structure 316, and the magnetic portion 402 described above, and thus will not be described in detail herein. It should be understood that the order in which the above elements are formed is merely an example, but is not limited thereto. For example, the magnetic portions 404 and 406 may be formed together with the magnetic portion 408 after forming the interconnect dielectric layer 352 and the interconnect conductive structure 356.

[0096] According to some embodiments, Figure 1J As shown, after forming the magnetic structure 400, a dielectric layer 362 is formed on the interconnect structure 310, and a protective layer 372 is formed on the dielectric layer 362. In some embodiments, the dielectric layer 362 is made of a nitride material, such as silicon nitride (SiN x ), Silicon Oxynitride (SiON x ), a combination of the foregoing or multiple layers or the like. In some embodiments, the dielectric layer 362 has a thickness in the range of about 200 nm to about 800 nm. In some embodiments, the protective layer 372 is made of polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer materials or a combination of the foregoing. In some embodiments, the protective layer 372 has a thickness in the range of about 2.5 μm to about 5 μm.

[0097] Then, according to some embodiments, such as Figure 1JAs shown, an opening 374 is formed through the dielectric layer 362 and the protective layer 372 to expose the interconnect conductive structure 356. The opening 374 can be formed by forming a photoresist structure having an opening that exposes a portion of the dielectric layer 362 and the protective layer 372, and then removing the photoresist structure. Thereafter, the exposed portions of the dielectric layer 362 and the protective layer 372 can be removed by a suitable etching process.

[0098] According to some embodiments, Figure 1K As shown, after the opening 374 is formed, a conductive structure 376 is formed in the opening 374, and a conductive bump 378 is formed above the conductive structure 376 to form the package structure 100. The conductive structure 376 may also include a protruding portion (not shown) protruding from the top surface of the protective layer 372. The protruding portion of the conductive structure 376 can be used as a bonding pad so that a conductive bump 378 can be formed thereon later. In some embodiments, the conductive bump 378 is made of a solder material, such as Sn and Ag or other applicable conductive materials (such as gold). The conductive bump 378 can be a microbump, a bump formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, a ball grid array (BGA) bump, or the like.

[0099] Figure 1K-1 The enlarged cross-sectional view of the transmission line 502 of the magnetic structure 400 and the packaging structure 100 according to some embodiments is shown. Figure 1K-1 As described above, according to some embodiments, the magnetic structure 400 includes magnetic portions 402, 404, 406, 408 surrounding the transmission line 502. In addition, according to some embodiments, the magnetic structure 400 is separated from the transmission line 502 by the interconnecting dielectric layers 322, 332, 342.

[0100] like Figure 1K-1As shown, transmission line 502 may include top surface 502_TS, bottom surface 502_BS, sidewall surface 502_SS1, and sidewall surface 502_SS2. In addition, magnetic portion 402 may include top surface 402_TS, bottom surface 402_BS, sidewall surface 402_SS1, and sidewall surface 402_SS2. Magnetic portion 404 may include top surface 404_TS, bottom surface 404_BS, sidewall surface 404_SS1, and sidewall surface 404_SS2. Magnetic portion 406 may include top surface 406_TS, bottom surface 406_BS, sidewall surface 406_SS1, and sidewall surface 406_SS2. Magnetic portion 408 may include top surface 408_TS, bottom surface 408_BS, sidewall surface 408_SS1, and sidewall surface 408_SS2. The sidewall pair transmission line 502 includes sidewall surfaces 502_SS1 and 502_SS2 , a top surface 502_TS, and a bottom surface 502_BS.

[0101] In some embodiments, the bottom surface 502_BS of the transmission line 502 is vertically spaced a distance D1 from the top surface 402_TS of the magnetic portion 402. In some embodiments, the sidewall surface 502_SS1 of the transmission line 502 is laterally spaced a distance D2 from the sidewall surface 404_SS2 of the magnetic portion 404. In some embodiments, the sidewall surface 502_SS2 of the transmission line 502 is laterally spaced a distance D3 from the sidewall surface 406_SS1 of the magnetic portion 406. In some embodiments, the top surface 502_TS of the transmission line 502 is vertically spaced a distance D4 from the bottom surface 408_BS of the magnetic portion 408. In some embodiments, the distances D1, D2, D3, D4 are in the range of about 0.1 μm to about 20 μm.

[0102] In addition, since the transmission line 502 is surrounded by (e.g., wrapped around) the magnetic structure 400 without directly contacting the magnetic structure 400, the distance between the magnetic portions on both sides of the transmission line 502 is greater than the size of the transmission line 502. In some embodiments, the distance between the sidewall surface 404_SS2 of the magnetic portion 404 and the sidewall surface 406_SS1 of the magnetic portion 406 is greater than the size (e.g., width) of the transmission line 502 in the X direction, such as Figure 1K-1 Similarly, according to some embodiments, the distance between the bottom surface 408_BS of the magnetic portion 408 and the top surface 402_TS of the magnetic portion 402 is greater than the dimension (eg, height) of the transmission line 502 in the Z direction, as shown in FIG. Figure 1K-1 shown.

[0103] In some embodiments, the width of the magnetic portions 404 and 406 decreases gradually from top to bottom, such as Figure 1K-1In some embodiments, the sidewall surface 404_SS1 of the magnetic portion 404 has a top edge that contacts the magnetic portion 408 and a bottom edge that contacts the magnetic portion 402. In some embodiments, the top edge of the sidewall surface 404_SS1 of the magnetic portion 404 is substantially aligned with the sidewall surface 408_SS1 of the magnetic portion 408, while the bottom edge of the sidewall surface 404_SS1 of the magnetic portion 404 is recessed from the sidewall surface 402_SS1 of the magnetic portion 402.

[0104] Similarly, the sidewall surface 406_SS2 of the magnetic portion 406 has a top edge that contacts the magnetic portion 408 and a bottom edge that contacts the magnetic portion 402. In some embodiments, the top edge of the sidewall surface 406_SS2 of the magnetic portion 406 is substantially aligned with the sidewall surface 408_SS2 of the magnetic portion 408, while the bottom edge of the sidewall surface 406_SS2 of the magnetic portion 406 is recessed from the sidewall surface 402_SS2 of the magnetic portion 402.

[0105] As described above, the magnetic structure 400 is configured to improve the impedance of the transmission line 502. That is, the magnetic structure 400 is formed to serve as a shield for the transmission line 502, rather than for electrical connection. Therefore, according to some embodiments, the magnetic structure 400 is electrically isolated from the chip structure 20 and the interconnection conductive structures 316, 326, 336, 346, 356 formed in the interconnection structure 310. In some embodiments, the magnetic structure 400 is electrically isolated from any other conductive structure (e.g., dielectric via 304) in the package structure 100.

[0106] In some embodiments, magnetic structure 400 is spaced apart from transmission line 502 by spaces filled with interconnect dielectric layers 322, 332, 342. That is, interconnect dielectric layer 332 is laterally sandwiched between magnetic portion 404 and transmission line 502 and between magnetic portion 406 and transmission line 502, according to some embodiments. In some embodiments, interconnect dielectric layer 322 is vertically sandwiched between magnetic portion 402 and transmission line 502, and interconnect dielectric layer 342 is vertically sandwiched between magnetic portion 408 and transmission line 502. In some embodiments, magnetic structure 400 partially overlaps chip structure 20 and directly contacts chip structure 20.

[0107] Figure 1K-2 A schematic perspective view of a magnetic structure 400 is shown according to some embodiments. Figure 1K-3 According to some embodiments, along Figure 1K-2 The cross-sectional view of the magnetic structure 400 is shown by the line Y-Y'. Figure 1K-2 and Figure 1K-3As described above, according to some embodiments, the magnetic structure 400 includes magnetic portions 402 , 404 , 406 , 408 surrounding the transmission line 502 , and the magnetic structure 400 is separated from the transmission line 502 by the interconnecting dielectric layers 322 , 332 , 342 .

[0108] In some embodiments, the transmission line 502 extends along the Y direction to electrically connect two chip structures (not shown). Figure 1K-2 As shown, the magnetic portion 406 includes a plurality of magnetic units 406_U aligned along the Y direction, and the magnetic portion 404 includes a plurality of magnetic units 404_U aligned along the Y direction. The magnetic units 404_U and 406_U can be formed by forming a plurality of through-hole trenches in the interconnect dielectric layers 322, 332, 342 along the Y direction, and then filling the through-hole trenches with magnetic materials. In other words, no complicated manufacturing process is required. In addition, the magnetic structure 400 with the magnetic units 404_U and 406_U forms a strong and stable structure, providing extremely high reliability.

[0109] In addition, the magnetic units 406_U are formed on the same side of the transmission line 502. In some embodiments, the magnetic units 406_U are spaced apart from each other laterally (e.g., in the Y direction). Furthermore, the magnetic units 406_U contact the magnetic portions 402 and 408 in the Z direction. In some embodiments, each magnetic unit 406_U has a top width and a bottom width, and in the Y direction, the top width is greater than the bottom width, such as Figure 1K-3 In some embodiments, the width of each magnetic unit 406_U gradually decreases in the Z direction.

[0110] According to some embodiments, magnetic unit 404_U is formed on the same side of transmission line 502, and magnetic unit 404_U and magnetic unit 406_U are formed on opposite sides of transmission line 502. In some embodiments, magnetic units 404_U are spaced apart from each other laterally (e.g., in the Y direction). In addition, magnetic units 404_U contact magnetic portions 402 and 408 in the Z direction. In some embodiments, each magnetic unit 404_U has a top width and a bottom width, and in the Y direction, the top width is greater than the bottom width. In some embodiments, the width of each magnetic unit 404_U gradually decreases in the Z direction.

[0111] Figure 1K-2 ' shows a schematic perspective view of a magnetic structure 400' according to some embodiments. Figure 1K-2According to some embodiments, similar to the magnetic structure 400 , the magnetic structure 400 ′ includes magnetic portions 402 , 404 , 406 , 408 surrounding the transmission line 502 , and the magnetic structure 400 ′ is separated from the transmission line 502 by interconnecting dielectric layers 322 , 332 , 342 .

[0112] In some embodiments, the transmission line 502 extends along the Y direction to electrically connect two chip structures (not shown). Figure 1K-2 ', the magnetic portions 404 and 406 also extend continuously in the Y direction. That is, the transmission line 502 is formed in a space substantially surrounded by the magnetic structure 400', and thus the transmission line 502 can achieve higher current and power saving performance. The process and materials used to form the magnetic structure 400' may be similar to or the same as the process and materials used to form the magnetic structure 400 described above, and thus will not be described in detail herein.

[0113] Figure 2A A cross-sectional schematic diagram of a package structure 100a is shown according to some embodiments. According to some embodiments, the package structure 100a may be similar to the package structure 100 described above, except that the magnetic structure does not vertically overlap the chip structure. The process and materials used to form the package structure 100a may be similar to or the same as the process and materials used to form the package structure 100 described above, and thus will not be described in detail herein.

[0114] More specifically, according to some embodiments, Figure 2A As shown, the package structure 100a includes a chip structure 20a bonded to a base wafer 10 by hybrid bonding and a magnetic structure 400a formed around a transmission line 502 and spaced apart from the transmission line 502. In addition, according to some embodiments, the magnetic structure 400a is formed without vertically overlapping (i.e., in the Z direction) the chip structure 20a. That is, according to some embodiments, the magnetic structure 400a is spaced apart from the chip structure 20a laterally (e.g., in the X direction and the Y direction).

[0115] The process and materials used to form the magnetic structure 400a and the chip structure 20a may be similar to or the same as the process and materials used to form the magnetic structure 400 and the chip structure 20, and thus will not be described in detail herein. Figure 1K-2 or Figure 1K-2 'The structure shown.

[0116] Figure 2BA cross-sectional schematic diagram of a package structure 100b is shown according to some embodiments. According to some embodiments, the package structure 100b may be similar to the package structure 100 described above, except that the magnetic structure is vertically spaced apart from the chip structure. The process and materials used to form the package structure 100b may be similar to or the same as the process and materials used to form the package structure 100 described above, and thus will not be described in detail herein.

[0117] More specifically, according to some embodiments, Figure 2B As shown, the package structure 100b includes a chip structure 20b bonded to the bottom wafer 10 by hybrid bonding and a magnetic structure 400b formed around the transmission line 502 and spaced apart from the transmission line 502. In addition, the magnetic structure 400b is buried in the interconnect structure 310b. The interconnect structure 310b may include a plurality of interconnect dielectric layers having interconnect conductive structures formed therein below the interconnect dielectric layer 312 and / or above the interconnect dielectric layer 352. Therefore, according to some embodiments, the magnetic structure 400b vertically (i.e., in the Z direction) overlaps the chip structure 20b, but is spaced apart from the chip structure 20b vertically (i.e., in the Z direction).

[0118] The processes and materials used to form the magnetic structure 400b, the chip structure 20b, and the interconnection structure 310b may be similar to or the same as the processes and materials used to form the magnetic structure 400, the chip structure 20, and the interconnection structure 310, and thus will not be described in detail herein. Figure 1K-2 or Figure 1K-2 'The structure shown.

[0119] Figure 2C A cross-sectional schematic diagram of a package structure 100c is shown according to some embodiments. According to some embodiments, the package structure 100c may be similar to the package structure 100a described above, except that the magnetic structure is vertically spaced apart from the chip structure. The process and materials used to form the package structure 100c may be similar to or the same as the process and materials used to form the package structures 100, 100a, and 100b described above, and thus will not be described in detail herein.

[0120] More specifically, according to some embodiments, Figure 2C As shown, the package structure 100c includes a chip structure 20c bonded to the bottom wafer 10 by hybrid bonding and a magnetic structure 400c formed around the transmission line 502 and spaced apart from the transmission line 502. In addition, the magnetic structure 400c is buried in the interconnect structure 310c. The interconnect structure 310c may include a plurality of interconnect dielectric layers having interconnect conductive structures formed therein below the interconnect dielectric layer 312 and / or above the interconnect dielectric layer 352. Therefore, according to some embodiments, the magnetic structure 400c vertically (i.e., in the Z direction) overlaps the chip structure 20c and is spaced apart from the chip structure 20c vertically (i.e., in the Z direction).

[0121] The processes and materials used to form the magnetic structure 400c, the chip structure 20c, and the interconnection structure 310c may be similar to or the same as the processes and materials used to form the magnetic structure 400, the chip structure 20, and the interconnection structure 310, and thus will not be described in detail herein. Figure 1K-2 or Figure 1K-2 'The structure shown.

[0122] Figure 3A , Figure 3B , Figure 3C An enlarged cross-sectional schematic diagram of magnetic structures 400-3a, 400-3b, and 400-3c is shown according to some embodiments. According to some embodiments, magnetic structures 400-3a, 400-3b, and 400-3c may be similar to the above-mentioned magnetic structures 400 or 400', except that the materials used to form different parts of the magnetic structures 400-3a, 400-3b, and 400-3c are different. The process and materials used to form the magnetic structures 400-3a, 400-3b, and 400-3c may be similar to or the same as the process and materials used to form the magnetic structure 400, and therefore are not described in detail herein. In addition, the magnetic structures 400-3a, 400-3b, and 400-3c may be applied to the above-mentioned packaging structures 100, 100a, 100b, and 100c.

[0123] More specifically, according to some embodiments, magnetic structure 400-3a includes magnetic portions 402-3a, 404-3a, 406-3a, 408-3a. In some embodiments, magnetic portions 402-3a and 408-3a are made of a first magnetic material, and magnetic portions 404-3a and 406-3a are made of a second magnetic material different from the first magnetic material.

[0124] According to some embodiments, magnetic structure 400-3b includes magnetic portions 402-3b, 404-3b, 406-3b, 408-3b. In some embodiments, magnetic portion 402-3b is made of a first magnetic material, and magnetic portions 404-3b, 406-3b, 408-3b are made of a second magnetic material different from the first magnetic material.

[0125] According to some embodiments, the magnetic structure 400-3c includes magnetic portions 402-3c, 404-3c, 406-3c, 408-3c. In some embodiments, the magnetic portions 402-3c, 404-3c, 406-3c are made of a first magnetic material, and the magnetic portion 408-3c is made of a second magnetic material different from the first magnetic material.

[0126] Figure 4A and Figure 4BSchematic diagrams of enlarged cross-sections of magnetic structures 400-4a and 400-4b are shown according to some embodiments. According to some embodiments, magnetic structures 400-4a and 400-4b may be similar to the magnetic structure 400 described above, except that the spatial relationship of the magnetic parts is different. The process and materials used to form magnetic structures 400-4a and 400-4b may be similar to or the same as the process and materials used to form magnetic structures 400 or 400' described above, so they are not repeated here. In addition, magnetic structures 400-4a and 400-4b may be applied to the above-mentioned packaging structures 100, 100a, 100b, 100c.

[0127] More specifically, according to some embodiments, the magnetic structure 400-4a includes magnetic portions 402-4a, 404-4a, 406-4a, and 408-4a. Figure 4A As shown, the magnetic portions 404-4a, 406-4a are recessed from the sidewalls of the magnetic portions 402-4a, 408-4a. In some embodiments, the distance between the magnetic portions 404-4a, 406-4a in the X direction is greater than the width of the transmission line 502 in the X direction, but less than the width of the magnetic portion 408-4a and the width of the magnetic portion 402-4a in the X direction. In some embodiments, the distance between the magnetic portion 404-4a and the transmission line 502 is approximately equal to the distance between the magnetic portion 406-4a and the transmission line 502. In some embodiments, the magnetic portions 402-4a, 404-4a, 406-4a, 408-4a are made of the same or different magnetic materials, similar to the magnetic structures 400, 400-3a, 400-3b, 400-3c described above.

[0128] According to some embodiments, the magnetic structure 400-4b includes magnetic portions 402-4b, 404-4b, 406-4b, 408-4b. According to some embodiments, as Figure 4BAs shown, similar to the magnetic portion 404-4a described above, the magnetic portion 404-4b is recessed from the sidewalls of the magnetic portions 402-4b and 408-4b. On the other hand, according to some embodiments, the top edge of the sidewall surface of the magnetic portion 406-4b is substantially aligned with the sidewall surface of the magnetic portion 408-4b, and the bottom edge of the sidewall surface of the magnetic portion 406-4b is recessed from the sidewall surface of the magnetic portion 402-4b. In some embodiments, the distance between the magnetic portions 404-4b and 406-4b in the X direction is greater than the width of the transmission line 502 in the X direction, but less than the width of the magnetic portion 408-4b and the width of the magnetic portion 402-4b in the X direction. In some embodiments, the distance between the magnetic portion 404-4b and the transmission line 502 is less than the distance between the magnetic portion 406-4b and the transmission line 502. In some embodiments, the magnetic portions 402 - 4 b , 404 - 4 b , 406 - 4 b , 408 - 4 b are made of the same or different magnetic materials, similar to the magnetic structures 400 , 400 - 3 a , 400 - 3 b , 400 - 3 c described above.

[0129] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G Schematic diagrams of enlarged cross-sections of magnetic structures 400-5a, 400-5b, 400-5c, 400-5d, 400-5e, 400-5f, 400-5g are shown according to some embodiments. According to some embodiments, magnetic structures 400-5a, 400-5b, 400-5c, 400-5d, 400-5e, 400-5f, 400-5g may be similar to the magnetic structures 400 or 400' described above, except that some magnetic parts are omitted. The processes and materials used to form magnetic structures 400-5a, 400-5b, 400-5c, 400-5d, 400-5e, 400-5f, 400-5g may be similar to or the same as the processes and materials used to form magnetic structure 400 described above, and thus are not described in detail herein. In addition, the magnetic structures 400 - 5 a , 400 - 5 b , 400 - 5 c , 400 - 5 d , 400 - 5 e , 400 - 5 f , and 400 - 5 g may be applied to the above-mentioned package structures 100 , 100 a , 100 b , and 100 c .

[0130] More specifically, according to some embodiments, the magnetic structure 400-5a includes magnetic portions 402-5a and 408-5a. That is, the magnetic portions 404 and 406 of the magnetic structure 400 are omitted. Since the magnetic portions 402-5a and 408-5a are formed on both sides of the transmission line 502, the energy loss of the transmission line 502 during operation can still be reduced. In addition, the formation of the magnetic portions 402-5a and 408-5a can be applied to the formation of the interconnect structure 310 without requiring an additional complex manufacturing process. In some embodiments, the magnetic portions 402-5a and 408-5a are made of the same magnetic material. In some embodiments, the magnetic portions 402-5a and 408-5a are made of different magnetic materials.

[0131] According to some embodiments, the magnetic structure 400-5b includes magnetic portions 404-5b and 406-5b. That is, the magnetic portions 402 and 408 of the magnetic structure 400 are omitted. Since the magnetic portions 404-5b and 406-5b are formed on both sides of the transmission line 502, the energy loss of the transmission line 502 during operation can still be reduced. In some embodiments, the magnetic portions 404-5b and 406-5b are made of the same magnetic material. In some embodiments, the magnetic portions 404-5b and 406-5b are made of different magnetic materials.

[0132] According to some embodiments, the magnetic structure 400-5c includes magnetic portions 402-5c, 404-5c, and 406-5c. That is, the magnetic portion 408 of the magnetic structure 400 is omitted. As described above, the magnetic portions 402-5c, 404-5c, and 406-5c are formed on three sides of the transmission line 502, so that the energy loss of the transmission line 502 during operation can still be reduced. In some embodiments, the magnetic portions 402-5c, 404-5c, and 406-5c are made of the same magnetic material. In some embodiments, the magnetic portions 402-5c, 404-5c, and 406-5c are made of different magnetic materials.

[0133] According to some embodiments, the magnetic structure 400-5d includes magnetic portions 404-5d, 406-5d, and 408-5d. That is, the magnetic portion 402 of the magnetic structure 400 is omitted. As described above, the magnetic portions 404-5d, 406-5d, and 408-5d are formed on three sides of the transmission line 502, so that the energy loss of the transmission line 502 during operation can still be reduced. In some embodiments, the magnetic portions 404-5d, 406-5d, and 408-5d are made of the same magnetic material. In some embodiments, the magnetic portions 404-5d, 406-5d, and 408-5d are made of different magnetic materials.

[0134] According to some embodiments, the magnetic structure 400-5e includes magnetic portions 402-5e, 404-5e, and 408-5e. That is, the magnetic portion 406 of the magnetic structure 400 is omitted. As described above, the magnetic portions 402-5e, 404-5e, and 408-5e are formed on three sides of the transmission line 502, so that the energy loss of the transmission line 502 during operation can still be reduced. In some embodiments, the magnetic portions 402-5e, 404-5e, and 408-5e are made of the same magnetic material. In some embodiments, the magnetic portions 402-5e, 404-5e, and 408-5e are made of different magnetic materials.

[0135] According to some embodiments, the magnetic structure 400-5f includes a magnetic portion 408-5f. That is, the magnetic portions 402, 404, 406 of the magnetic structure 400 are omitted. Since the magnetic portion 408-5f is formed adjacent to the transmission line 502, the energy loss of the transmission line 502 during operation can still be reduced. In addition, the formation of the magnetic portion 408-5f can be applied to the formation of the interconnect structure 310 without requiring an additional complex manufacturing process.

[0136] According to some embodiments, the magnetic structure 400-5g includes a magnetic portion 402-5g. That is, the magnetic portions 404, 406, 408 of the magnetic structure 400 are omitted. Since the magnetic portion 402-5g is formed adjacent to the transmission line 502, the energy loss of the transmission line 502 during operation can still be reduced. In addition, the formation of the magnetic portion 402-5g can be applied to the formation of the interconnect structure 310 without requiring an additional complex manufacturing process.

[0137] Figure 6 A schematic perspective view of a package structure 100d is shown according to some embodiments. Figure 6 The present invention is simplified to better understand the concept of the present invention. According to some embodiments, the package structure 100d may be similar to the package structure 100 described above, except that the magnetic structure is formed in a coil shape around the transmission line 502. The process and materials used to form the package structure 100d may be similar to or the same as the process and materials used to form the package structure 100 described above, and thus will not be described in detail herein.

[0138] More specifically, according to some embodiments, Figure 6As shown, the transmission line 502 electrically connects the chip structures 20-1 and 20-2. In addition, according to some embodiments, the magnetic structure 400d is formed around the transmission line 502 and is separated from the transmission line 502 by an interconnection dielectric layer (such as the interconnection dielectric layers 312, 322, 332 described above). Since the magnetic structure 400d is formed around the transmission line 502, the energy loss of the transmission line 502 during operation can be reduced. In addition, the formation of the magnetic structure 400d can be applied to the formation of an interconnection structure (such as the interconnection structure 310 described above) without requiring an additional complex manufacturing process.

[0139] In some embodiments, magnetic structure 400d includes bottom magnetic portions 402-1, 402-2, 402-3, and 402-4, top magnetic portions 408-1, 408-2, 408-3, 408-4, and 408-5, and magnetic portions 406-1, 406-2, 406-3, 406-4, 406-5, 406-6, 406-7, and 406-8. In addition, according to some embodiments, similar to Figure 1K-2 In the structure shown, each of the magnetic portions 406-1, 406-2, 406-3, 406-4, 406-5, 406-6, 406-7 and 406-8 includes a magnetic unit 406_U that is laterally spaced apart from each other. In some embodiments, the magnetic portions 406-1, 406-3, 406-5, 406-7 are formed on a first side of the transmission line 502, and the magnetic portions 406-2, 406-4, 406-6, 406-8 are formed on a second side of the transmission line 502.

[0140] In some embodiments, the top of magnetic portion 406-1 is physically connected to top magnetic portion 408-1, and the bottom of magnetic portion 406-1 is physically connected to bottom magnetic portion 402-1. In some embodiments, the top of magnetic portion 406-2 is physically connected to top magnetic portion 408-2, and the bottom of magnetic portion 406-2 is physically connected to bottom magnetic portion 402-1. In some embodiments, the top of magnetic portion 406-3 is physically connected to top magnetic portion 408-2, and the bottom of magnetic portion 406-3 is physically connected to bottom magnetic portion 402-2. In some embodiments, the top of magnetic portion 406-4 is physically connected to top magnetic portion 408-3, and the bottom of magnetic portion 406-4 is physically connected to bottom magnetic portion 402-2.

[0141] In some embodiments, the top of magnetic portion 406-5 is physically connected to top magnetic portion 408-3, and the bottom of magnetic portion 406-5 is physically connected to bottom magnetic portion 402-3. In some embodiments, the top of magnetic portion 406-6 is physically connected to top magnetic portion 408-4, and the bottom of magnetic portion 406-6 is physically connected to bottom magnetic portion 402-3. In some embodiments, the top of magnetic portion 406-7 is physically connected to top magnetic portion 408-4, and the bottom of magnetic portion 406-7 is physically connected to bottom magnetic portion 402-4. In some embodiments, the top of magnetic portion 406-8 is physically connected to top magnetic portion 408-5, and the bottom of magnetic portion 406-8 is physically connected to bottom magnetic portion 402-4.

[0142] In some embodiments, transmission line 502 includes portions 502-1, 502-2, and 502-3 extending in different directions. In some embodiments, portion 502-1 is longitudinally oriented in a first direction, portion 502-2 is longitudinally oriented in a second direction, and portion 502-3 is longitudinally oriented in a third direction. In some embodiments, top magnetic portion 408-1 and bottom magnetic portion 402-1 partially overlap portion 502-1 of transmission line 502 and are longitudinally oriented in a fourth direction and a fifth direction, respectively. In some embodiments, the first direction, the fourth direction, and the fifth direction are different from each other.

[0143] In some embodiments, the top magnetic portion 408-2 and the bottom magnetic portion 402-2 partially overlap the portion 502-2 of the transmission line 502 and are longitudinally oriented along the sixth direction and the seventh direction, respectively. In some embodiments, the second direction, the sixth direction, and the seventh direction are different from each other. In addition, according to some embodiments, the top magnetic portion 408-3 and the bottom magnetic portion 402-3 are also longitudinally oriented along the sixth direction and the seventh direction, respectively.

[0144] In some embodiments, the top magnetic portion 408-4 and the bottom magnetic portion 402-4 partially overlap the portion 502-3 of the transmission line 502 and are longitudinally oriented in the eighth direction and the ninth direction, respectively. In some embodiments, the third direction, the eighth direction, and the ninth direction are different from each other. In addition, the top magnetic portion 408-5 is longitudinally oriented in the tenth direction. The tenth direction is different from the third direction and the eighth direction. In some embodiments, the bottom magnetic portion 402-3 vertically overlaps the portions 502-2 and 502-3 of the transmission line 502.

[0145] By forming magnetic portions extending in different directions, the final magnetic structure 400d may be more stable and have greater reliability. In addition, the arrangement of the magnetic portions may have greater flexibility, so the magnetic structure 400d may be applied to various layouts (e.g., transmission lines with curved shapes) without requiring additional complex manufacturing processes.

[0146] Figure 7 A schematic top view of a package structure 100e is shown according to some embodiments. The package structure 100e may include the package structure 100, 100a, 100b, 100c, or 100d described above. The process and materials used to form the package structure 100e may be similar to or the same as the process and materials used to form the package structure 100, 100a, 100b, 100c, or 100d described above, and thus will not be described in detail herein.

[0147] More specifically, according to some embodiments, Figure 7 As shown, the package structure 100e includes a plurality of chip structures 20, and the transmission line 502 is used to connect the chip structures 20. In addition, the magnetic structure 400e is formed around the transmission line 502 to reduce the energy loss of the final package structure 100e. The magnetic structure 400e may have a structure similar to the above-mentioned magnetic structures 400, 400', 400a to 400c, 400-3a to 400-3c, 400-4a, 400-4b, 400-5a to 400-5g and 400d. In addition, the magnetic structure 400e may have different structures in different regions.

[0148] Figure 8 A schematic perspective view of a package structure 100f is shown according to some embodiments. The package structure 100f may include the package structure 100, 100a, 100b, 100c, or 100d described above. The process and materials used to form the package structure 100f may be similar to or the same as the process and materials used to form the package structure 100, 100a, 100b, 100c, or 100d described above, and thus will not be described in detail herein.

[0149] More specifically, the package structure 100f includes a transmission line 502 and metal lines 501 and 503 formed in the same interconnect dielectric layer (e.g., interconnect dielectric layer 332). Similar to the above description, the magnetic structure 400 is formed around the transmission line 502. On the other hand, the metal lines 501 and 503 are configured to be connected to the ground voltage, and thus the magnetic structure is not formed around the metal lines 501 and 503. Figure 8 The structure shown can also be applied to the above-mentioned package structures 100, 100a, 100b, 100c or 100d. In addition, the magnetic structure 400 in the package structure 100f can be replaced by any of the above-mentioned magnetic structures.

[0150] In general, transmission lines (e.g., high clock frequency (>10GBPS) transmission lines for 5G / 6G) may be formed in a packaging structure to connect chip structures. During operation, electromagnetic radiation is emitted. In addition, the higher the frequency, the more electromagnetic radiation is emitted. Therefore, when transmission lines are applied to packaging structures, the transmission lines may cause increased energy loss. Therefore, in some embodiments of the present invention, magnetic structures (e.g., magnetic structures 400, 400', 400a to 400c, 400-3a to 400-3c, 400-4a, 400-4b, 400-5a to 400-5g and 400d) are formed adjacent to transmission lines (e.g., transmission line 502) to reduce this energy loss. More specifically, the electromagnetic radiation emitted from the transmission line can be reflected by the magnetic material of the magnetic structure, so the electromagnetic radiation can be confined to a relatively small area. That is, the magnetic structure can be used as a current mirror and impedance matching in a package structure, such as at both ends of a coplanar waveguide (CPW) transmission line between two artificial intelligence chips.

[0151] Therefore, energy loss from electromagnetic radiation during operation can be reduced, and the characteristic impedance of the transmission line and the magnetic flux of the packaging process can be increased. In addition, the current and power consumption of the current amplifier with the high characteristic impedance of the transmission line can be reduced. Furthermore, due to the formation of the magnetic structure, the specific transmission line length can be shortened. In addition, according to some embodiments, since the magnetic structure is formed to serve as a shield for the transmission line, the magnetic structure is electrically isolated from the conductive structure and the electronic device in the packaging structure.

[0152] In addition, it should be noted that Figures 1A to 8 The same elements in the present invention may be labeled with the same reference symbols, may include the same or similar materials, and may be formed by the same or similar processes, so for the sake of brevity, these redundant details are omitted. Figures 1A to 8 For the description related to the method, it should be understood that Figures 1A to 8 The disclosed structures are not limited to the method and can exist independently as structures independent of the method. Similarly, Figures 1A to 8 The methods shown are not limited to the disclosed structures but can exist independently of the structures.

[0153] Furthermore, although the above disclosed method is shown and described as a series of actions or events, it should be understood that in some other embodiments, the order of the drawings of these actions or events can be changed. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described above. In addition, all illustrated actions may not be required to implement one or more aspects or embodiments described above. Furthermore, the above one or more actions can be performed as one or more separate actions and / or stages.

[0154] Furthermore, the terms "approximately", "substantially", "about" used above take into account small variations and may vary in different technologies and are within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, these terms can represent both the situation where the event or situation occurs exactly and the situation where the event or situation occurs in a very close manner.

[0155] Embodiments for forming a package structure may be provided. The package structure may include bonding a chip structure to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding. In addition, an interconnect structure is formed above the chip structure, and a transmission line is formed in the interconnect structure. In addition, a magnetic structure is formed adjacent to the transmission line, so that energy loss of the transmission line during operation can be reduced. Therefore, energy loss of the final device can also be reduced.

[0156] In some embodiments, a package structure is provided. The package structure includes a chip structure bonded to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; and an interconnect dielectric layer formed above the chip structure. The package structure also includes an interconnect conductive structure formed in the interconnect dielectric layer; and a transmission line formed in the interconnect dielectric layer. The package structure also includes a magnetic structure formed in the interconnect dielectric layer and separated from the transmission line by the interconnect dielectric layer. In addition, the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structure.

[0157] In some other embodiments, the magnetic structure includes: a first magnetic portion formed on a first side of the transmission line; and a second magnetic portion formed on a second side of the transmission line, wherein the first side is opposite to the second side, and wherein a distance between the first magnetic portion and the second magnetic portion in a first direction is greater than a dimension of the transmission line in the first direction.

[0158] In some other embodiments, a distance between the first magnetic portion and a first sidewall of the transmission line on the first side is different from a distance between the second magnetic portion and a second sidewall of the transmission line on the second side.

[0159] In some other embodiments, the first magnetic portion and the second magnetic portion are made of different materials.

[0160] In some other embodiments, the magnetic structure further includes: a third magnetic portion formed on a third side of the transmission line, wherein the third magnetic portion directly contacts the first magnetic portion and the second magnetic portion.

[0161] In some other embodiments, the magnetic structure further includes: a fourth magnetic portion formed on a fourth side of the transmission line, wherein the fourth magnetic portion directly contacts the first magnetic portion and the second magnetic portion.

[0162] In some other embodiments, the third magnetic portion further includes a plurality of third magnetic units that are laterally spaced apart from each other.

[0163] In some other embodiments, each of the plurality of third magnetic units has a top width and a bottom width, and the top width is greater than the bottom width.

[0164] In some embodiments, a packaging structure is provided. The packaging structure includes a chip structure, which is bonded to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; and a dielectric layer, which is formed above the substrate and covers the sidewall surface of the chip structure. The packaging structure also includes a dielectric via formed through the dielectric layer; and an interconnection structure, which is formed above the dielectric layer and the chip structure. In addition, the interconnection structure includes: a transmission line, which is electrically connected to the chip structure; and a magnetic structure, which is separated from the transmission line by a first space. In addition, the magnetic structure is electrically isolated from the transmission line, the chip structure and the dielectric via. The interconnection structure also includes an interconnection dielectric layer, which is formed around the transmission line and the magnetic structure, and the interconnection dielectric layer fills the first space between the magnetic structure and the transmission line.

[0165] In some other embodiments, the magnetic structure includes: a first top magnetic portion located above the transmission line; a first bottom magnetic portion located below the transmission line; and a plurality of first magnetic units spaced apart from each other in a first direction and connecting the first top magnetic portion and the first bottom magnetic portion in a second direction.

[0166] In some other embodiments, a width of each of the plurality of first magnetic units gradually decreases in the second direction.

[0167] In some other embodiments, wherein the first top magnetic portion is longitudinally oriented along a third direction and the first bottom magnetic portion is longitudinally oriented along a fourth direction, wherein the fourth direction is different from the third direction.

[0168] In some other embodiments, the magnetic structure further includes: a second top magnetic portion overlapping the transmission line and spaced apart from the first top magnetic portion; and a plurality of second magnetic units spaced apart from each other in the first direction and connected to the second top magnetic portion and the first bottom magnetic portion in the second direction.

[0169] In some other embodiments, the magnetic structure further includes: a second bottom magnetic portion, located below the transmission line and spaced apart from the first bottom magnetic portion; and a plurality of third magnetic units, spaced apart from each other in a first direction and connected to the second top magnetic portion and the second bottom magnetic portion in a second direction, wherein the plurality of first magnetic units and the plurality of third magnetic units are on a first side of the transmission line, and the plurality of second magnetic units are on a second side of the transmission line opposite to the first side.

[0170] In some other embodiments, the magnetic structure partially overlaps the chip structure and directly contacts the chip structure.

[0171] In some embodiments, a method for forming a package structure is provided. The method includes forming a first bonding structure above a substrate, and the first bonding structure includes a first dielectric layer and a first conductive pad formed in the first dielectric layer. The method also includes bonding a second bonding structure of a chip structure to the first bonding structure, and the second bonding structure includes a second dielectric layer and a second conductive pad formed in the second dielectric layer, and the second conductive pad is bonded to the first conductive pad, and the second dielectric layer is bonded to the first dielectric layer. The method also includes forming a third dielectric layer around the chip structure above the first bonding structure; and forming a dielectric via through the third dielectric layer and electrically connected to the first conductive pad. The method also includes forming an interconnect structure above the third dielectric layer, including: forming a first interconnect dielectric layer; and forming a second interconnect dielectric layer above the first interconnect dielectric layer. In addition, a transmission line is formed in the second interconnect dielectric layer. The method also includes forming a third interconnect dielectric layer above the second interconnect dielectric layer; and forming a first magnetic portion through the first interconnect dielectric layer, the second interconnect dielectric layer, and the third interconnect dielectric layer. In addition, the transmission line is electrically connected to the chip structure and electrically isolated from the first magnetic portion.

[0172] In some other embodiments, the step of forming an interconnect structure above the third dielectric layer further includes: forming a second magnetic portion through the first interconnect dielectric layer, the second interconnect dielectric layer and the third interconnect dielectric layer, wherein the second magnetic portion and the first magnetic portion are on both sides of the transmission line.

[0173] In some other embodiments, the step of forming an interconnect structure above the third dielectric layer further includes: forming a fourth interconnect dielectric layer above the third interconnect dielectric layer; and forming a third magnetic portion in the fourth interconnect dielectric layer, wherein the third magnetic portion contacts the top of the first magnetic portion, and the third interconnect dielectric layer is vertically sandwiched between the transmission line and the third magnetic portion.

[0174] In some other embodiments, the step of forming an interconnect structure above the third dielectric layer further includes: forming a fifth interconnect dielectric layer above the third dielectric layer; and forming a fourth magnetic portion in the fifth interconnect dielectric layer, wherein the fourth magnetic portion contacts the bottom of the first magnetic portion, and the first interconnect dielectric layer is vertically sandwiched between the transmission line and the fourth magnetic portion.

[0175] In some other embodiments, the first magnetic portion includes a plurality of first magnetic units formed on the same side of the transmission line.

[0176] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the utility model from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the utility model, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the embodiments of the utility model. Various changes, substitutions or modifications can be made to the embodiments of the utility model without departing from the spirit and scope of the embodiments of the utility model.

Claims

1. A packaging structure, characterized in that: include: A chip structure is bonded to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; an interconnect dielectric layer formed above the chip structure; an interconnect conductive structure formed in the interconnect dielectric layer; a transmission line formed in the interconnect dielectric layer; and A magnetic structure is formed in the interconnect dielectric layer and separated from the transmission line by the interconnect dielectric layer, wherein the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structure.

2. The packaging structure according to claim 1, characterized in that: The magnetic structure comprises: a first magnetic portion formed on a first side of the transmission line; and A second magnetic portion is formed on a second side of the transmission line, wherein the first side is opposite to the second side, and wherein a distance between the first magnetic portion and the second magnetic portion in a first direction is greater than a dimension of the transmission line in the first direction.

3. The packaging structure according to claim 2, characterized in that: The magnetic structure also includes: A third magnetic portion is formed on a third side of the transmission line, wherein the third magnetic portion directly contacts the first magnetic portion and the second magnetic portion.

4. The packaging structure according to claim 3, characterized in that: The magnetic structure also includes: A fourth magnetic portion is formed on a fourth side of the transmission line, wherein the fourth magnetic portion directly contacts the first magnetic portion and the second magnetic portion.

5. The packaging structure according to claim 3 or 4, characterized in that: The third magnetic portion also includes a plurality of third magnetic units that are laterally spaced apart from each other.

6. A packaging structure, characterized in that: include: A chip structure is bonded to a substrate by dielectric-to-dielectric bonding and metal-to-metal bonding; a dielectric layer formed on the substrate and covering the sidewall surface of the chip structure; a dielectric via formed through the dielectric layer; and An interconnect structure is formed above the dielectric layer and the chip structure, wherein the interconnect structure comprises: a transmission line electrically connected to the chip structure; a magnetic structure separated from the transmission line by a first space, wherein the magnetic structure is electrically isolated from the transmission line, the chip structure and the dielectric via; and An interconnect dielectric layer is formed around the transmission line and the magnetic structure, wherein the interconnect dielectric layer fills the first space between the magnetic structure and the transmission line.

7. The packaging structure according to claim 6, characterized in that: The magnetic structure comprises: a first top magnetic portion located above the transmission line; a first bottom magnetic portion located below the transmission line; as well as A plurality of first magnetic units are spaced apart from each other in a first direction and connected to the first top magnetic portion and the first bottom magnetic portion in a second direction.

8. The packaging structure according to claim 7, characterized in that: The first top magnetic portion is longitudinally oriented along a third direction, and the first bottom magnetic portion is longitudinally oriented along a fourth direction, wherein the fourth direction is different from the third direction.

9. The packaging structure according to claim 7 or 8, characterized in that: The magnetic structure also includes: a second top magnetic portion overlapping the transmission line and spaced apart from the first top magnetic portion; as well as A plurality of second magnetic units are spaced apart from each other in the first direction and connected to the second top magnetic portion and the first bottom magnetic portion in the second direction.

10. The packaging structure according to claim 9, characterized in that: The magnetic structure also includes: a second bottom magnetic portion, located below the transmission line and spaced apart from the first bottom magnetic portion; as well as a plurality of third magnetic units spaced apart from each other in the first direction and connected to the second top magnetic portion and the second bottom magnetic portion in the second direction, The plurality of first magnetic units and the plurality of third magnetic units are on a first side of the transmission line, and the plurality of second magnetic units are on a second side of the transmission line opposite to the first side.

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