E-band high-gain millimeter wave low-noise amplifier

Abstract

The utility model relates to an E-band high-gain millimeter wave low-noise amplifier, which aims to solve the problems of low voltage gain, low sensitivity and the like of the conventional low-noise amplifier. The low noise amplifier comprises an input matching circuit, an output matching circuit, an inter-stage matching circuit and four stages of cascade circuits, and each stage of cascade circuit comprises a grid electrode bias circuit, a drain electrode bias circuit and a common source electrode transistor. The drain electrode and the grid electrode of the common source transistor in each stage of cascade circuit are respectively connected with a drain electrode bias circuit and a grid electrode bias circuit, the adjacent cascade circuits are connected through an inter-stage matching circuit, and the drain electrode bias circuit comprises a filtering stabilizing circuit. The inter-stage matching circuit between the adjacent cascade circuits is composed of an inter-stage capacitor and an inter-stage microstrip line which are connected in series. The gain of the E-band low-noise amplifier can reach more than 20dB, the typical value of the noise coefficient is 5dB within the broadband of 75-90GHz, and the E-band low-noise amplifier has higher sensitivity.

Description

Technical Field

[0001] The utility model belongs to the field of communication technology equipment and millimeter wave integrated circuits, and specifically relates to a broadband low-noise amplifier with high gain, high flatness and compact size working in the E band, which can be used in the radio frequency front end of a communication receiver. Background Art

[0002] The E-band in the millimeter wave frequency band is gradually becoming an important part of wireless communication and remote sensing technology due to its unique advantages in high data transmission rate and high-resolution imaging. In the field of wireless communication, the E-band allows extremely high-speed point-to-point communication, which is crucial for the next generation of high-speed networks such as 5G and future 6G networks, and can support large amounts of data transmission in cities and high-density scenarios. At the same time, due to the short wavelength characteristics of the E-band, it is also used in precision radar systems such as automotive anti-collision radar and satellite remote sensing to provide high-resolution terrain and object imaging. In addition, the E-band also shows its potential in security scanning, medical imaging, scientific research and other fields.

[0003] As the first active stage of the wireless communication system receiver, the low noise amplifier is used to amplify the useful signal received by the antenna under the interference of complex external environmental factors while ensuring low noise. High-performance low noise amplifiers can greatly improve the sensitivity of the communication system and ensure the communication quality. The existing low noise amplifier structures mainly adopt the following methods:

[0004] 1) Common-gate amplifier: The structure is as follows Figure 1 As shown in (a), it can provide a lower input impedance, which makes it perform well in matching with source impedance, especially for low impedance sources, and can provide a wider bandwidth, suitable for broadband signal processing. However, its voltage gain is low, and when using short-channel transistors commonly used in millimeter-wave low-noise amplifiers, it exhibits severe high-frequency parasitic effects and poor noise figure;

[0005] 2) Common source amplifier with parallel resistor at input end: Figure 1 The parallel resistor shown in (b) can improve the linearity of the transistor, thereby reducing signal distortion, and can also reduce instability caused by input reflection and improve the overall stability of the amplifier. However, in millimeter-wave applications, the gain of the amplifier will be reduced due to the influence of the parallel resistor, which is unacceptable in millimeter-wave systems because high-frequency signals usually require higher gain to ensure transmission efficiency and signal integrity.

[0006] 3) Parallel-series feedback amplifier: Figure 1The topology in (c) uses parallel resistors and series resistor feedback to complete the impedance matching at the input. Due to the use of a resistor feedback structure, the layout area is small, and it has a relatively stable voltage gain and input and output impedance within a wide band, so it is widely used in broadband amplifier design. However, the structure of adding resistors at the input inevitably introduces additional thermal noise, resulting in high power consumption and noise.

[0007] 4) Source negative feedback common source amplifier: Figure 1 The structure design of (d) is simple, the power supply voltage requirement is low, the DC power consumption is small, the gain loss is small, and the operating frequency is adjustable. However, its gate-source capacitance C gs With L g The formed LC resonance only occurs at a specific frequency, so broadband matching cannot be achieved. This will limit the operating frequency band of the amplifier and make it only suitable for narrowband amplifiers.

[0008] In summary, the design of E-band low-noise amplifiers still faces great challenges, and it is of great significance to realize broadband, high-gain, high-flatness, and low-noise amplifiers. Utility Model Content

[0009] The utility model aims to solve the problems of low voltage gain and low system sensitivity of the existing low noise amplifier, and provides an E-band high-gain millimeter wave low noise amplifier.

[0010] The utility model discloses an E-band high-gain millimeter-wave low-noise amplifier, which comprises an input matching circuit, an output matching circuit, an inter-stage matching circuit and a four-stage cascade circuit, wherein each stage of the cascade circuit comprises a gate bias circuit, a drain bias circuit and a common source transistor, the common source transistors in the four-stage cascade circuit are respectively a first common source transistor, a second common source transistor, a third common source transistor and a fourth common source transistor, the drain and the gate of the common source transistor in each stage of the cascade circuit are respectively connected to the drain bias circuit and the gate bias circuit, and adjacent cascade circuits are connected via an inter-stage matching circuit;

[0011] The input matching circuit is connected to the gate of the first common source transistor through the DC blocking capacitor C2. The gate of the first common source transistor is also connected to a first-stage gate bias circuit, wherein the first-stage gate bias circuit comprises a microstrip line TL4, a microstrip line TL5, a resistor R1 and a capacitor C1. The first-stage gate bias circuit is powered by a first DC power supply DC1. The microstrip line TL4, the microstrip line TL5 and the resistor R1 are connected in series. The resistor R1 is connected to a connection line between the capacitor C2 and the gate of the first common source transistor. The capacitor C1 is connected in parallel to a connection line between the microstrip line TL4 and the microstrip line TL5. The other end of the capacitor C1 is grounded.

[0012] The drain bias circuit contains a filter stabilization circuit, which is a filter circuit and a filter capacitor connected to the middle resistor in series and the two ends of the connecting microstrip line, respectively. The filter circuit is formed by two capacitors in parallel;

[0013] The interstage matching circuit between adjacent cascade circuits is composed of interstage capacitors and interstage microstrip lines connected in series;

[0014] The drain of the fourth common-source transistor is connected to the output matching circuit via the microstrip line TL22 and the DC blocking capacitor C19 to output a signal.

[0015] The gate bias circuit designed by the utility model increases the input impedance of the gate DC bias circuit from the port of the AC path by adding a large resistor R1, making it much higher than the input impedance of the transistor, thereby shielding the influence of the bias circuit on the AC path. Capacitor C1 is also introduced for power supply filtering.

[0016] The drain DC bias circuit designed by the utility model is added through the λ / 4 microstrip line TL8. For DC signals, the λ / 4 microstrip line is short-circuited by the grounding capacitor at the power supply end and is transmitted almost without loss. For AC signals, the impedance transformation characteristics of the λ / 4 line make the drain DC bias circuit appear open-circuited (visible impedance is infinite) when viewed from the port on the AC path, thereby preventing the leakage of radio frequency AC signals into the bias circuit and improving the efficiency of the amplifier. In the drain DC bias circuit, in order to further filter out the clutter carried in the DC power supply, especially the low-frequency clutter, two capacitors with different capacitance values ​​are used for filtering: the capacitor with a larger capacitance is connected in parallel through C3 and C4 to achieve low-frequency filtering, and the capacitor C5 with a smaller capacitance is used for filtering in the working frequency band. In the frequency band with lower frequencies, the impedance transformation effect of the λ / 4 line is weakened, and clutter leakage may occur. A small resistor R2 is connected in series between the parallel capacitors on the bias line, and the leaked signal is consumed by this small resistor, thereby improving the stability of the circuit.

[0017] The four-stage cascade all adopts the common source form. Due to its structural characteristics, the common source amplifier can provide a very high voltage gain. In the cascade configuration, the gain of each stage can be accumulated to provide a very high total gain, which is particularly important for millimeter wave signals because these signals are susceptible to attenuation during transmission. The input impedance of the common source amplifier is mainly determined by the gate drain resistance and input capacitance, while the output impedance is high, which makes it easier to match with other microwave components (such as transmission lines with an impedance of 50Ω). This easy impedance matching property reduces signal reflections and losses and improves the overall performance of the system. The common source amplifier is easier to implement on the integrated circuit platform due to its simple structure. Compared with other types (such as common gate and common drain), it usually shows better stability in high-frequency applications, which is particularly important for the manufacture of high-density, low-cost millimeter wave electronic devices. When cascading multiple amplifiers, the simplicity of the common source configuration helps to maintain the consistency and scalability of the design.

[0018] The interstage capacitor C11 in the interstage matching circuit designed by the utility model is typical of AC-DC multiplexing. At high frequencies, it is combined with the microstrip line TL15 to achieve matching between the output impedance of the previous stage and the input impedance of the next stage. At direct current, it prevents the drain voltage of the previous stage from being loaded on the gate bias of the next stage, and also avoids the influence of the gate voltage of the next stage on the drain power supply of the previous stage, and also avoids the generation of a direct current path, thereby playing a role in direct current isolation.

[0019] The input and output matching uses a compact T-type matching network, which can provide a wide bandwidth. The broadband matching allows the amplifier to maintain good performance within the broadband without redesigning the matching network for each sub-band. Minimum noise matching is achieved at the input by optimizing the source impedance, and maximum gain matching is achieved at the output, allowing the amplifier to provide high gain while maintaining low noise.

[0020] The utility model proposes an E-band broadband high-gain low-noise amplifier, and analyzes the circuit topology design, transistor usage, input matching, output matching, inter-stage matching, gate bias circuit and drain bias circuit to achieve the design of a high-performance millimeter-wave low-noise amplifier. The E-band low-noise amplifier designed by the utility model has a gain of more than 20dB and a gain flatness of 2dB. Such a high gain can effectively improve the system's ability to detect weak signals, ensuring that the signal will not be overwhelmed by environmental noise or system internal noise in subsequent processing. The excellent gain flatness can ensure that the different frequency components of the signal are amplified to the same degree to prevent signal distortion. The input and output return losses are both more than 10dB. The high input return loss means that the received input signal will only have less energy reflected back to the antenna, ensuring that the signal received by the antenna is maximized by the receiver. High output return loss can reduce signal reflection and reduce interference and multipath effects within the system. In the wide band of 75-90 GHz, the noise coefficient of the low noise amplifier of the utility model is typically 5 dB. The lower noise coefficient can improve the sensitivity of the receiving system while maintaining a higher signal-to-noise ratio to ensure communication quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagrams of the structures of traditional low noise amplifiers, wherein (a) is a schematic diagram of the structure of a traditional common-gate amplifier, (b) is a schematic diagram of the structure of a common-source amplifier with a resistor connected in parallel at the input end, (c) is a schematic diagram of the structure of a parallel-series feedback amplifier, and (d) is a schematic diagram of the structure of a source negative feedback common-source amplifier;

[0022] Figure 2 This is a circuit topology diagram of the E-band high-gain millimeter-wave low-noise amplifier of the utility model;

[0023] Figure 3 This is a diagram of simulation results of the E-band high-gain low-noise amplifier provided in the embodiment. DETAILED DESCRIPTION

[0024] Specific implementation method 1: In this implementation method, the E-band high-gain millimeter-wave low-noise amplifier includes an input matching circuit, an output matching circuit, an inter-stage matching circuit and a four-stage cascade circuit, wherein each stage of the cascade circuit includes a gate bias circuit, a drain bias circuit and a common source transistor, the common source transistors in the four-stage cascade circuit are respectively a first common source transistor, a second common source transistor, a third common source transistor and a fourth common source transistor, the drain and gate of the common source transistor in each stage of the cascade circuit are respectively connected to the drain bias circuit and the gate bias circuit, and adjacent cascade circuits are connected through an inter-stage matching circuit;

[0025] The input matching circuit is connected to the gate of the first common source transistor through the DC blocking capacitor C2. The gate of the first common source transistor is also connected to a first-stage gate bias circuit, wherein the first-stage gate bias circuit comprises a microstrip line TL4, a microstrip line TL5, a resistor R1 and a capacitor C1. The first-stage gate bias circuit is powered by a first DC power supply DC1. The microstrip line TL4, the microstrip line TL5 and the resistor R1 are connected in series. The resistor R1 is connected to a connection line between the capacitor C2 and the gate of the first common source transistor. The capacitor C1 is connected in parallel to a connection line between the microstrip line TL4 and the microstrip line TL5. The other end of the capacitor C1 is grounded.

[0026] The drain bias circuit contains a filter stabilization circuit, which is a filter circuit and a filter capacitor connected to the middle resistor in series and the two ends of the connecting microstrip line, respectively. The filter circuit is formed by two capacitors in parallel;

[0027] The interstage matching circuit between adjacent cascade circuits is composed of interstage capacitors and interstage microstrip lines connected in series;

[0028] The drain of the fourth common-source transistor is connected to the output matching circuit via the microstrip line TL22 and the DC blocking capacitor C19 to output a signal.

[0029] The dimensions of this embodiment are 1.500×1.056 mm 2 The compact size makes this millimeter-wave low-noise amplifier highly integrated and easy to integrate. It is also suitable for use in mobile communication equipment and high-density deployment systems. It is a high-performance low-noise amplifier suitable for multi-scenario applications.

[0030] Specific implementation method 2: The difference between this implementation method and specific implementation method 1 is that the input matching circuit is formed by a T-type matching network composed of microstrip line TL1, microstrip line TL2 and microstrip line TL3.

[0031] Specific implementation method three: This implementation method is different from specific implementation methods one or two in that the output matching circuit is formed by microstrip line TL25, microstrip line TL26 and microstrip line TL27 to form a T-type matching network.

[0032] Specific implementation method 4: This implementation method is different from any one of specific implementation methods 1 to 3 in that the resistance value of the resistor R1 in the first-stage gate bias circuit is 1015Ω.

[0033] Specific implementation example five: This implementation example is different from specific implementation examples one to four in that the gate bias circuit connected to the gates of the second common source transistor, the third common source transistor and the fourth common source transistor is composed of a microstrip line and a resistor connected in series.

[0034] Specific implementation example 6: This implementation example is different from specific implementation examples 1 to 5 in that a circuit consisting of a microstrip line TL9 and a capacitor C7 connected in series is further connected in parallel to the drain of the first common-source transistor.

[0035] This implementation uses TL9 and C7 to form a quasi-high-pass filter with slightly larger low-frequency insertion loss and very small high-frequency insertion loss in the working frequency band, thereby lowering the low-frequency gain and improving the gain flatness of the entire working frequency band.

[0036] Embodiment: The E-band high-gain millimeter-wave low-noise amplifier of this embodiment includes an input matching circuit, an output matching circuit, an inter-stage matching circuit and a four-stage cascade circuit, wherein each stage of the cascade circuit includes a gate bias circuit, a drain bias circuit and a common source transistor, the common source transistors in the four-stage cascade circuit are sequentially a first common source transistor, a second common source transistor, a third common source transistor and a fourth common source transistor, the drain and the gate of the common source transistor in each stage of the cascade circuit are connected to the drain bias circuit and the gate bias circuit respectively, and adjacent cascade circuits are connected through an inter-stage matching circuit;

[0037] The input matching circuit is connected to the gate of the first common source transistor through the DC blocking capacitor C2. The gate of the first common source transistor is also connected to a first-stage gate bias circuit, wherein the first-stage gate bias circuit comprises a microstrip line TL4, a microstrip line TL5, a resistor R1 and a capacitor C1 (1.16 pF). The first-stage gate bias circuit is powered by a first DC power supply DC1. The microstrip line TL4, the microstrip line TL5 and the resistor R1 are connected in series. The resistor R1 is connected to a connection line between the capacitor C2 and the gate of the first common source transistor. The capacitor C1 is connected in parallel to a connection line between the microstrip line TL4 and the microstrip line TL5. The other end of the capacitor C1 is grounded.

[0038] The drain bias circuit is powered by a third DC power supply DC3 (1.5V), the positive electrode of the third DC power supply DC3 is sequentially connected in series with microstrip line TL36, microstrip line TL34, microstrip line TL32 and microstrip line TL28, the negative electrode of the third DC power supply DC3 is grounded, and the other end of the microstrip line TL28 is connected to the drain of the first common source transistor. The first drain bias circuit includes a microstrip line TL6, a first filter stabilization circuit and a microstrip line TL8 (70Ω / 45°) connected in series, and the first filter stabilization circuit is connected to a first filter circuit and a filter capacitor C5 (0.7pF) at both ends of the middle resistor R2 connected in series and the connecting microstrip line TL7, and the first filter circuit is formed by capacitor C3 (2.75pF) and capacitor C4 (1pF) connected in parallel;

[0039] A second drain bias circuit is connected between the microstrip line TL32 and the microstrip line TL28 and the drain of the second common source transistor. The second drain bias circuit includes a microstrip line TL12, a second filter stabilization circuit and a microstrip line TL14 connected in series. The second filter stabilization circuit is connected to a second filter circuit and a filter capacitor C10 at both ends of the series-connected middle resistor R4 and the connecting microstrip line TL13. The second filter circuit is formed by capacitors C8 and C9 connected in parallel.

[0040] A third drain bias circuit is connected between the microstrip line TL32 and the microstrip line TL34 and the drain of the third common source transistor. The third drain bias circuit includes a microstrip line TL17, a third filter stabilization circuit and a microstrip line TL19 connected in series. The third filter stabilization circuit is connected to the middle resistor R6 in series and the two ends of the connecting microstrip line TL18. The third filter circuit and the filter capacitor C14 are respectively connected. The third filter circuit is formed by connecting the capacitor C12 and the capacitor C13 in parallel.

[0041] A fourth drain bias circuit is connected between the microstrip line TL36 and the microstrip line TL34 and the drain of the fourth common source transistor. The fourth drain bias circuit includes a microstrip line TL35, a fourth filter stabilization circuit, an inductor L1 and a microstrip line TL24 connected in series. The other end of the microstrip line TL24 is connected between the microstrip line TL22 and the DC blocking capacitor C19. The fourth filter stabilization circuit is connected to the middle resistor R8 in series and the two ends of the microstrip line TL23, respectively. The fourth filter circuit is formed by connecting capacitors C16 and C17 in parallel.

[0042] The gate bias circuit is powered by a second DC power supply DC2 (-0.4V), the positive electrode of the second DC power supply DC2 is connected in series with microstrip line TL29, microstrip line TL30, microstrip line TL31 and microstrip line TL33 in sequence, the negative electrode of the second DC power supply DC2 is grounded, one end of the second gate bias circuit is connected between microstrip line TL29 and microstrip line TL30, the other end of the second gate bias circuit is connected to the gate of the second common source transistor, the second gate bias circuit is connected in series with microstrip line TL11 and resistor R3; one end of the third gate bias circuit is connected to microstrip line Between TL31 and the microstrip line TL33, the other end of the third gate bias circuit is connected to the gate of the third common-source transistor, and the third gate bias circuit is connected in series by the microstrip line TL16 and the resistor R5; one end of the fourth gate bias circuit is connected to the microstrip line TL33, the other end of the fourth gate bias circuit is connected to the gate of the fourth common-source transistor, and the fourth gate bias circuit is connected in series by the microstrip line TL21 and the resistor R7; a filter capacitor C20 (1.38 pF) is also connected between the microstrip line TL30 and the microstrip line TL31, and the other end of the capacitor C20 is grounded;

[0043] The interstage matching circuit between the first common-source transistor and the second common-source transistor is composed of a capacitor C6 (0.06pF) and a microstrip line TL10 (70Ω / 7.5°) connected in series, and the drain of the first common-source transistor is also connected in parallel with a circuit composed of a microstrip line TL9 (70Ω / 22°) and a capacitor C9 (0.61pF) connected in series; the interstage matching circuit between the second common-source transistor and the third common-source transistor is composed of a capacitor C11 and a microstrip line TL15 connected in series; the interstage matching circuit between the third common-source transistor and the fourth common-source transistor is composed of a capacitor C15 and a microstrip line TL20 connected in series;

[0044] The output signal of the drain of the fourth common-source transistor is connected to the output matching circuit via the microstrip line TL22 and the DC blocking capacitor C19;

[0045] The input matching circuit is composed of a microstrip line TL1 (50Ω / 54°), a microstrip line TL2 (74Ω / 22°) and a microstrip line TL3 (50Ω / 4°) to form a T-type matching network, and the output matching circuit is composed of a microstrip line TL25 (50Ω / 45°), a microstrip line TL26 (50Ω / 61°) and a microstrip line TL27 (50Ω / 17°) to form a T-type matching network.

[0046] In this embodiment, the input signal is introduced through the input matching circuit and the DC blocking capacitor C2 (0.07pF), and the output signal is led out through the DC blocking capacitor C19 (0.42pF) and the output matching circuit. The overlapping part of the gate bias and drain bias microstrip lines is physically isolated by the air bridge. And the noise coefficient calculation formula of the cascade system is:

[0047]

[0048] Where N F is the total noise figure of the cascaded system, N Fn is the noise coefficient of the nth level module in the system, G n is the gain of the nth stage module in the system.

[0049] It can be seen that the system noise coefficient is mainly affected by the noise coefficient of the first stage. In the cascade system, the later the structure, the greater the impact on N F Therefore, if Figure 2 As shown, in the layout of the low noise amplifier, the gate bias circuit of the first stage transistor is separately provided so as to adjust the gate power supply DC1 of the first stage when in use to achieve an optimal noise figure.

[0050] This embodiment uses a 100nm GaAs MMIC process.

[0051] Design of Low Noise Amplifier

[0052] The design of the low noise amplifier in the utility model is based on microwave network theory and transmission line theory. Starting from the basic structure of the low noise amplifier, based on the basic structure of the common source amplifier, a four-stage cascade broadband high gain low noise amplifier circuit topology is proposed. A T-type network is used to achieve input and output matching, the impedance transformation characteristics of the λ / 4 microstrip line are used to achieve drain bias, the circuit stability is improved by capacitor filtering and small series resistors, the AC-DC multiplexed capacitor is used for inter-stage matching, and full-wave electromagnetic simulation is used to predict the scattering parameters of the low noise amplifier layout to repeatedly adjust to achieve the optimal index.

[0053] Processing and testing of low noise amplifiers

[0054] First, an ohmic contact layer is formed by photolithography and metal evaporation, followed by ion implantation, and then a thin film resistor layer is formed by double-layer photolithography and sputtering. Electron beam lithography is used to form a T-type gate, and a selective wet chemical etchant is used to form a gate channel. The remaining metal layers are processed by photolithography, metallization, and stripping processes. The dielectric layer is deposited by chemical vapor deposition, and anisotropic plasma etching is performed on the back of the wafer to form a contact path from the back to the front.

[0055] During the power test, the signal generator outputs a stable sine wave with adjustable frequency and power. The isolator ensures unidirectional signal propagation. Since the input of the spectrum analyzer is sensitive and can only process low-power signals, the output of the low-noise amplifier is connected to an attenuator to reduce the signal power and then input into the spectrum analyzer to read the power. This link can test high-power gain, 1dB compression point and other performance. A network analyzer can be used to perform small signal tests to obtain S parameters. The noise coefficient test uses the Y factor method. This method uses a noise source to determine the noise inside the low-noise amplifier and tests the output power corresponding to when the noise source is turned on and off. The ratio of these two powers is the Y factor. The noise coefficient can be calculated using the following formula:

[0056]

[0057] ENR is the excess noise ratio, and its relationship with frequency is provided by the noise source instrument.

[0058] Depend on Figure 3It can be seen that the gain of the E-band low-noise amplifier designed in this embodiment can reach more than 20dB, and the gain flatness can reach 2dB. Such a high gain can effectively improve the system's ability to detect weak signals, ensuring that the signal will not be overwhelmed by environmental noise or internal system noise in subsequent processing. Excellent gain flatness is of great significance when processing broadband signals, and can ensure that different frequency components of the signal are amplified to the same degree to prevent signal distortion. The input and output return losses are both above 10dB. The high input return loss means that the received input signal will only have less energy reflected back to the antenna, ensuring that the signal received by the antenna is maximized by the receiver. High output return loss can reduce signal reflection and reduce interference and multipath effects within the system. In the broadband of 75-90GHz, the noise coefficient of the low-noise amplifier of this embodiment is typically 5dB. The lower noise coefficient can improve the sensitivity of the receiving system while maintaining a high signal-to-noise ratio to ensure communication quality.

Claims

1. An E-band high-gain millimeter-wave low-noise amplifier, characterized in that The E-band high-gain millimeter-wave low-noise amplifier comprises an input matching circuit, an output matching circuit, an inter-stage matching circuit and a four-stage cascade circuit, wherein each stage of the cascade circuit comprises a gate bias circuit, a drain bias circuit and a common source transistor, the common source transistors in the four-stage cascade circuit are respectively a first common source transistor, a second common source transistor, a third common source transistor and a fourth common source transistor, the drain and the gate of the common source transistor in each stage of the cascade circuit are respectively connected to the drain bias circuit and the gate bias circuit, and adjacent cascade circuits are connected via an inter-stage matching circuit; The input matching circuit is connected to the gate of the first common source transistor through the DC blocking capacitor C2. The gate of the first common source transistor is also connected to a first-stage gate bias circuit, wherein the first-stage gate bias circuit comprises a microstrip line TL4, a microstrip line TL5, a resistor R1 and a capacitor C1. The first-stage gate bias circuit is powered by a first DC power supply DC1. The microstrip line TL4, the microstrip line TL5 and the resistor R1 are connected in series. The resistor R1 is connected to a connection line between the capacitor C2 and the gate of the first common source transistor. The capacitor C1 is connected in parallel to a connection line between the microstrip line TL4 and the microstrip line TL5. The other end of the capacitor C1 is grounded. The drain bias circuit contains a filter stabilization circuit, which is a filter circuit and a filter capacitor connected to the middle resistor in series and the two ends of the connecting microstrip line, respectively. The filter circuit is formed by two capacitors in parallel; The interstage matching circuit between adjacent cascade circuits is composed of interstage capacitors and interstage microstrip lines connected in series; The drain of the fourth common-source transistor is connected to the output matching circuit via the microstrip line TL22 and the DC blocking capacitor C19 to output a signal.

2. The E-band high-gain millimeter-wave low-noise amplifier according to claim 1, characterized in that The input matching circuit is formed of a T-type matching network consisting of microstrip line TL1, microstrip line TL2 and microstrip line TL3.

3. The E-band high-gain millimeter-wave low-noise amplifier according to claim 1, characterized in that The output matching circuit is formed of a T-type matching network consisting of microstrip line TL25, microstrip line TL26 and microstrip line TL27.

4. The E-band high-gain millimeter-wave low-noise amplifier according to claim 1, characterized in that The resistance value of the resistor R1 in the first-stage gate bias circuit is 1015Ω.

5. The E-band high-gain millimeter-wave low-noise amplifier according to claim 1, characterized in that The gate bias circuit connected to the gates of the second common source transistor, the third common source transistor and the fourth common source transistor is composed of a microstrip line and a resistor connected in series.

6. The E-band high-gain millimeter-wave low-noise amplifier according to claim 1, characterized in that The drain of the first common-source transistor is also connected in parallel with a circuit consisting of a microstrip line TL9 and a capacitor C7 connected in series.

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