Abnormal pulse elimination circuit in power-on process

Abstract

The utility model relates to an abnormal pulse elimination circuit in a power-on process. The abnormal pulse elimination circuit comprises an enable signal input port, a first resistor, a time delay circuit, a diode, a triode and an IC chip, the enable signal input port is respectively connected with the first end of the first resistor and the time delay circuit; the second end of the first resistor is grounded; the time-delay circuit is connected with the positive electrode of the diode and is grounded; the base of the triode is connected with the cathode of the diode, the emitter is grounded, and the collector is connected with the enable signal access pin of the IC chip; the enable signal access pin of the IC chip is also connected with a 5V power supply; wherein the conduction voltage drop of the diode is 0.7 V. According to the technical scheme, on the basis of an existing control circuit, the diode is added between the rear end of the time delay circuit and the base electrode of the triode. And the conduction voltage drop of the diode is 0.7 V, so that the interference pulse in the enable signal can be effectively prevented from passing through, and meanwhile, the real enable signal is not influenced to carry out high-level triggering.

Description

Technical Field

[0001] The present application relates to the technical field of pulse elimination circuits, and in particular to a circuit for eliminating abnormal pulses during a power-on process. Background Art

[0002] In the process of powering on the existing control circuit, the enable signal output by the front end has interference pulses, which are sufficient to turn on the transistor in the control circuit, thereby causing the enable signal access pin of the IC chip in the control circuit to be pulled down to a low level. The low-level enable operation of the IC chip may cause malfunction of the peripheral signal. Utility Model Content

[0003] In order to at least to some extent overcome the problem in the related art that the enable signal output by the front end causes interference pulses to the IC chip, the present application provides a circuit for eliminating abnormal pulses during the power-on process.

[0004] The scheme of this application is as follows:

[0005] A circuit for eliminating abnormal pulses during power-on, comprising:

[0006] Enable signal input port, first resistor, delay circuit, diode, triode and IC chip;

[0007] The enable signal input port is respectively connected to the first end of the first resistor and the delay circuit;

[0008] The second end of the first resistor is grounded;

[0009] The delay circuit is connected to the anode of the diode and is grounded at the same time;

[0010] The base of the transistor is connected to the cathode of the diode, the emitter is grounded, and the collector is connected to the enable signal access pin of the IC chip;

[0011] The enable signal access pin of the IC chip is also connected to a 5V power supply;

[0012] Wherein, the conduction voltage drop of the diode is 0.7V.

[0013] Preferably, it also includes:

[0014] A second resistor;

[0015] The enable signal access pin of the IC chip is connected to the power supply through the second resistor.

[0016] Preferably, the delay circuit comprises:

[0017] The third resistor and the delay capacitor;

[0018] A first end of the third resistor is connected to the enable signal input port, and a second end is connected to the anode of the diode;

[0019] The first end of the delay capacitor is connected to the second end of the third resistor, and the second end is grounded.

[0020] Preferably, the IC chip is a CMOS logic chip.

[0021] Preferably, the first resistor is a pull-down resistor, which is used to clamp the potential of the enable signal to ground when there is no signal input.

[0022] Preferably, the second resistor is a pull-up resistor.

[0023] The technical solution provided by the present application may include the following beneficial effects: a circuit for eliminating abnormal pulses during power-on, comprising: an enable signal input port, a first resistor, a delay circuit, a diode, a transistor and an IC chip; the enable signal input port is respectively connected to the first end of the first resistor and the delay circuit; the second end of the first resistor is grounded; the delay circuit is connected to the positive electrode of the diode and is grounded at the same time; the base of the transistor is connected to the negative electrode of the diode, the emitter is grounded, and the collector is connected to the enable signal access pin of the IC chip; the enable signal access pin of the IC chip is also connected to a 5V power supply; wherein the conduction voltage drop of the diode is 0.7V.

[0024] Based on the existing control circuit, this technical solution adds a diode between the back end of the delay circuit and the base of the transistor. The diode has a conduction voltage drop of 0.7V, which can effectively prevent the interference pulse in the enable signal from passing through, while not affecting the real enable signal to trigger at a high level.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0027] Figure 1 It is a circuit structure diagram of a circuit for eliminating abnormal pulses during power-on process provided by an embodiment of the present application;

[0028] Figure 2 It is a schematic diagram of measuring voltage at the access pin of the enable signal of the IC chip in the existing control circuit;

[0029] Figure 3 It is a schematic diagram of measuring voltage at the enable signal access pin of an IC chip in a power-on process abnormal pulse elimination circuit provided by an embodiment of the present application.

[0030] Reference numerals: first resistor R1; second resistor R2; third resistor R3; diode D1; transistor T1; IC chip IC. DETAILED DESCRIPTION

[0031] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0032] A circuit for eliminating abnormal pulses during power-on, comprising:

[0033] Enable signal input port, first resistor R1, delay circuit, diode D1, transistor T1 and IC chip IC;

[0034] The enable signal input port is respectively connected to the first end of the first resistor R1 and the delay circuit;

[0035] A second end of the first resistor R1 is grounded;

[0036] The delay circuit is connected to the anode of the diode D1 and is grounded at the same time;

[0037] The base of transistor T1 is connected to the cathode of diode D1, the emitter is grounded, and the collector is connected to the enable signal access pin of IC chip IC;

[0038] The IC chip IC's enable signal access pin is also connected to a 5V power supply;

[0039] Among them, the conduction voltage drop of the diode D1 is 0.7V.

[0040] In specific practice, the first resistor R1 is a resistor with a resistance value of 2K. The first resistor R1 is a pull-down resistor, which is used to clamp the potential of the enable signal to the ground when there is no signal input.

[0041] The delay circuit includes:

[0042] A third resistor R3 and a delay capacitor C1;

[0043] A first end of the third resistor R3 is connected to the enable signal input port, and a second end is connected to the anode of the diode D1;

[0044] A first end of the delay capacitor C1 is connected to a second end of the third resistor R3 , and a second end is grounded.

[0045] The third resistor R3 is a resistor with a resistance value of 1K, and the delay capacitor C1 is a capacitor with a resistance value of 100uf.

[0046] The diode D1 can be but is not limited to a 1N4148 diode D1. The 1N4148 diode D1 is a small high-speed switching diode D1. It switches relatively quickly and is widely used in circuits with high signal frequencies for one-way conduction isolation, communications, computer boards, television circuits and industrial control circuits.

[0047] The transistor T1 can be, but is not limited to, the MMBT8050 transistor T1.

[0048] The IC chip IC may be, but is not limited to, a 74HCT244PW chip. The 74HCT244PW chip is a high-speed CMOS logic chip, which is mainly used for signal amplification, isolation, and inversion operations in electronic systems.

[0049] It should be noted that the abnormal pulse elimination circuit during the power-on process also includes:

[0050] A second resistor R2;

[0051] The enable signal access pin of the IC chip IC is connected to the power supply through the second resistor R2.

[0052] The second resistor R2 is a pull-up resistor.

[0053] like Figure 1 As shown, pins 1 and 19 of the IC chip IC are connected in parallel to the collector of the transistor T1, and connected to a 5V power supply through a second resistor R2.

[0054] like Figure 2 As shown, during the power-on process of the existing control circuit, the enable signal output by the front end has an interference pulse, which is sufficient to turn on the transistor T1 in the control circuit, thereby causing the enable signal access pin of the IC chip IC in the control circuit to be pulled down to a low level. Figure 2 It can be observed that there is a pulse as high as 512mv when power is turned on. This pulse is enough to turn on the transistor T1, causing the enable signal access pin of the IC chip IC in the control circuit to be pulled down to a low level.

[0055] On the basis of the existing control circuit, this technical solution adds a diode D1 between the back end of the delay circuit and the base of the transistor T1. The conduction voltage drop of the diode D1 is 0.7V, which can effectively prevent the interference pulse in the enable signal from passing through, while not affecting the real enable signal to trigger at a high level. Figure 3 1 is a schematic diagram of measuring voltage at the enable signal access pin of an IC chip IC in a power-on process abnormal pulse elimination circuit provided by an embodiment of the present application, such as Figure 3As shown, the enable signal of the IC chip IC is connected to the pin and stabilized at 5V after power-on. The high level prohibits the output and the peripheral signal will not malfunction.

[0056] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0057] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0058] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0060] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A circuit for eliminating abnormal pulses during power-on, characterized in that: include: Enable signal input port, first resistor, delay circuit, diode, triode and IC chip; The enable signal input port is respectively connected to the first end of the first resistor and the delay circuit; The second end of the first resistor is grounded; The delay circuit is connected to the anode of the diode and is grounded at the same time; The base of the transistor is connected to the cathode of the diode, the emitter is grounded, and the collector is connected to the enable signal access pin of the IC chip; The enable signal access pin of the IC chip is also connected to a 5V power supply; Wherein, the conduction voltage drop of the diode is 0.7V.

2. The abnormal pulse elimination circuit during power-on process according to claim 1, characterized in that: Also includes: A second resistor; The enable signal access pin of the IC chip is connected to the power supply through the second resistor.

3. The abnormal pulse elimination circuit during power-on process according to claim 1, characterized in that: The delay circuit comprises: The third resistor and the delay capacitor; A first end of the third resistor is connected to the enable signal input port, and a second end is connected to the anode of the diode; The first end of the delay capacitor is connected to the second end of the third resistor, and the second end is grounded.

4. The abnormal pulse elimination circuit during power-on process according to claim 1, characterized in that: The IC chip is a CMOS logic chip.

5. The abnormal pulse elimination circuit during power-on process according to claim 1, characterized in that: The first resistor is a pull-down resistor, which is used to clamp the potential of the enable signal to ground when there is no signal input.

6. The abnormal pulse elimination circuit during power-on process according to claim 2, characterized in that: The second resistor is a pull-up resistor.

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