Flash memory unit and integrated assembly comprising same

Abstract

Various embodiments of the utility model relate to a flash memory unit and an integrated body assembly comprising the same, the integrated body assembly comprises: a control gate located on a substrate, the control gate having a first length; a tunneling dielectric on the control gate; a floating gate having a second length and located on the tunneling dielectric, the tunneling dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; the channel is located on the blocking dielectric, and the blocking dielectric separates the channel from the floating gate; and a source / drain terminal on the channel, wherein a first length of the control gate is less than a second length of the floating gate.

Description

Technical Field

[0001] The embodiment of the utility model relates to a flash memory unit and an integrated component including the same. Background Art

[0002] Many modern electronic components contain electronic memory. Electronic memory can be either volatile or non-volatile. Non-volatile memory retains its stored data in the absence of power, while volatile memory loses its stored data when the power is disconnected. Flash memory is a type of non-volatile memory. Flash memory uses electrons tunneling in and out of a floating gate to change the threshold voltage of the flash memory cell. The tunneling of electrons is caused by applying a programming voltage or an erase voltage to the control gate. Utility Model Content

[0003] One aspect of the utility model provides an integrated circuit component, which includes: a control gate located on a substrate, the control gate having a first length; a tunneling dielectric located on the control gate; a floating gate having a second length and located on the tunneling dielectric, the tunneling dielectric separating the control gate and the floating gate; a blocking dielectric located on the floating gate; a channel located on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and a source / drain terminal located on the channel, wherein the first length of the control gate is less than the second length of the floating gate.

[0004] Another aspect of the present invention provides a flash memory cell, which includes: a control gate located in an interlayer dielectric (ILD) layer; a floating gate extending across the control gate, and the floating gate is configured to maintain a charge determined by a programming voltage or an erase voltage applied to the control gate, wherein the charge changes a threshold voltage of the flash memory cell; and a tunneling dielectric extending between the floating gate and the control gate, the tunneling dielectric is configured to allow electrons to pass between the floating gate and the control gate when a programming voltage or an erase voltage is applied, thereby changing the charge of the flash memory cell.

[0005] Another aspect of the present invention provides a method for forming an integrated circuit component, the method comprising: forming an interlayer dielectric (ILD) layer on a substrate; forming a control gate having a first length on the ILD layer; forming a tunneling dielectric on a top surface of the control gate; forming a floating gate having a second length on the tunneling dielectric, the tunneling dielectric separating the floating gate and the control gate, wherein the first length is less than the second length; and forming a blocking dielectric and a channel on the tunneling dielectric, the blocking dielectric separating the floating gate and the channel.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Cross-sectional views of some embodiments of flash memory cells with back-end-of-line (BEOL) layout and inverted tunneling architecture

[0008] FIG. 2A to FIG. 2B The icon shows a cross-sectional view and top view of the layout of the BEOL flash array.

[0009] FIG. 3A to FIG. 3B A cross-sectional view illustrating the operation of a BEOL flash memory array utilizing a tunneling dielectric between a control gate and a floating gate.

[0010] FIG. 4A to FIG. 4G Several cross-sectional views of some embodiments of BEOL flash memory cells and arrays are shown.

[0011] Figure 5 The figures are cross-sectional views of some embodiments of integrated circuits including a BEOL flash memory array and a front-end-of-line (FEOL) transistor array.

[0012] Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 Several cross-sectional views of some embodiments of methods of forming a BEOL flash memory array are illustrated.

[0013] Fig.15 Methods illustrating some embodiments of the present concepts are illustrated in flowchart form. DETAILED DESCRIPTION

[0014] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed by itself.

[0015] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] A flash memory cell includes a control gate and source / drain terminals, and a floating gate is arranged between the control gate and the source / drain terminals. During operation, a programming voltage or an erase voltage applied to the control gate sets the state of the flash memory cell to a "0" state or a "1" state. In a conventional flash memory cell, to set the flash memory cell to a "0" state, a programming voltage is applied to the control gate. The application of the programming voltage pulls electrons from the channel into the floating gate, resulting in an increase in the threshold voltage relative to the "1" state. The increased threshold voltage is due to the electric field of the electrons in the floating gate repelling the electrons in the channel. To set the flash memory cell to a "1" state, an erase voltage is applied to the control gate. The application of the erase voltage pushes the electrons out of the floating gate and back into the channel, resulting in a decrease in the threshold voltage relative to the "0" state. The programming voltage and erase voltage of the flash memory cell depend on the capacitance of both the tunneling dielectric separating the control gate and the floating gate and the blocking dielectric separating the floating gate and the channel. The thickness, length, width and material of the blocking dielectric and tunneling dielectric affect the capacitance.

[0017] In traditional flash memory arrays, flash cells and logic components are formed on the substrate in the same front-end of line (FEOL) process. As different architectures of logic components are developed, such as fin field effect transistors (FinFETS) and all-around gate field effect transistors (GAA-FETS), it is becoming increasingly difficult to use the process used to manufacture logic components to manufacture flash cells.

[0018] In addition, the programming voltage and erase voltage of a flash memory cell depend on the voltage drop across the tunnel oxide. Increasing the voltage drop relative to the voltage applied to the control gate improves the efficiency of the flash memory cell by reducing the magnitude of the programming voltage and the erase voltage. The ratio of the voltage drop to the voltage applied to the control gate depends on the capacitance of the tunnel dielectric between the control gate and the floating gate and the capacitance of the blocking dielectric between the floating gate and the channel. To increase the above ratio, a small tunnel dielectric capacitance relative to the blocking dielectric capacitance may be desirable.

[0019] The capacitance of the blocking dielectric and the tunneling dielectric depends on their respective thickness, length, and width. However, the thickness of the blocking dielectric is optimized for electron transport between the channel and the floating gate. In addition, the thickness of the tunneling dielectric is optimized to prevent electron transport between the control gate and the floating gate, so changing the thickness to change the capacitance is not desirable. The length and width of the tunneling dielectric and the blocking dielectric are also difficult to manipulate because they are often determined by a single gate etch. Therefore, a process that can adjust the length and width of the tunneling dielectric independently of the length and width of the blocking dielectric is desirable.

[0020] Therefore, a method of forming a flash memory component that can be used in conjunction with various designs of logic components while also being able to adjust the length and width of the tunneling dielectric is desirable. The present disclosure provides technology for forming back-end-of-line (BEOL) flash memory cells using an inverted tunneling architecture. By using a BEOL-compatible process to form flash memory cells, the provided technology produces flash memory arrays suitable for embedding with logic components and formed into circuits having different architectures (e.g., fin field effect transistors (FinFETS), all-around gate field effect transistors (GAA-FETS), etc.). In addition, the BEOL-compatible process for forming flash memory cells using an inverted tunneling architecture etches the tunneling dielectric and the blocking dielectric separately, such that the size of the tunneling dielectric is independent of the size of the blocking dielectric. Independently determining the size of the tunneling dielectric and the blocking dielectric allows the capacitance ratio in the final design to be easily adjusted.

[0021] Figure 1 A cross-sectional view 100 of some embodiments of a flash memory cell having a back end of line (BEOL) layout is illustrated.

[0022] A flash memory cell 104 is above a substrate 102. A plurality of interlayer dielectric (ILD) layers 106 separate the flash memory cell 104 from the substrate 102. The flash memory cell 104 includes a control gate 108. A tunneling dielectric 110 covers the control gate 108 and separates the control gate 108 from a floating gate 112. A blocking dielectric 114 covers the floating gate 112 and separates the floating gate from a channel 116. A source / drain terminal 118 covers the channel 116 and is separated by a non-zero distance directly above the tunneling dielectric 110.

[0023] In some embodiments, the tunneling dielectric 110 or the control gate 108 has a first length L1, and the blocking dielectric 114 has a second length L2 that is greater than the first length L1. The difference between the first length L1 and the second length L2 is a factor that causes the capacitance of the tunneling dielectric 110 to be smaller than the capacitance of the blocking dielectric 114. The smaller capacitance of the tunneling dielectric 110 increases the voltage drop across the tunneling dielectric 110 relative to the voltage applied to the control gate 108. The voltage drop across the tunneling dielectric 110 directly affects the tunneling current in the tunneling dielectric 110. Therefore, changing the length L1 of the tunneling dielectric 110 allows the capacitance of the tunneling dielectric 110 to be adjusted, thereby affecting the voltage drop and tunneling current within the tunneling dielectric 110. Since the voltage drop is related to the voltage applied to the control gate 108, changing the length L1 also affects the minimum voltage that can be used to induce a tunneling current in the tunneling dielectric 110. In some additional embodiments, the capacitance of the tunnel dielectric 110 may also be adjusted by making the tunnel dielectric and the blocking dielectric have different widths, by making the tunnel dielectric and the blocking dielectric have different thicknesses, and / or by making the tunnel dielectric and the blocking dielectric have different dielectric constants.

[0024] Thus, by varying the width, length, thickness, and / or dielectric constant of the tunneling dielectric and the blocking dielectric, a relatively low ratio of the tunneling dielectric capacitance to the blocking dielectric capacitance can be achieved. This relatively low ratio increases the voltage drop across the tunneling dielectric relative to the applied voltage. A higher ratio of voltage drop to applied voltage reduces the magnitude of the write and erase voltages applied to the control gate that can be used to set the state of the flash memory cell. Lower write and erase voltages increase the operating efficiency of the flash memory cell.

[0025] FIG. 2A to FIG. 2B The cross-sectional view 200a and the top view 200b of the layout of the BEOL flash memory array are shown. For example, Figure 2A The cross-sectional view 200a can be along Figure 2B The line A-A' in is intercepted. Figure 2B In the layout top view 200 b , multiple ILD layers 106 are omitted for clarity.

[0026] like Figure 2A As shown in the cross-sectional view 200a of FIG. 1 , the BEOL flash memory array includes a plurality of flash memory components arranged in a plurality of ILD layers 106 on a substrate 102. The plurality of flash memory components are separated from each other by one or more ILD layers 106 along a first direction 212. A plurality of source / drain terminals are disposed on the plurality of flash memory components. A plurality of interconnects 202-206 are disposed in the ILD structure located above the plurality of source / drain terminals.

[0027] In some embodiments, the plurality of interconnects may include a plurality of first vias 202 and a plurality of second vias 205. The plurality of first vias 202 extend from the first portions 118a, 118c of the source / drain terminals 118a-118d to the plurality of second interconnects 204. The plurality of second vias 205 extend from the second portions 118b, 118d of the source / drain terminals 118a-118d to the plurality of first interconnects 206. The first portions 118a, 118c and the second portions 118b, 118d of the source / drain terminals 118 alternate along a first direction 212 of the flash memory array. The source / drain terminals 118a-118d cover two of the plurality of floating gates 112a-112c, respectively. For example, the first source / drain terminal 118b covers the first floating gate 112a and the second floating gate 112b, and the second source / drain terminal 118c covers the second floating gate 112b and the third floating gate 112c. The plurality of first interconnects 206 extend in a first direction 212, and the plurality of second interconnects 204 extend in a second direction 214 perpendicular to the first direction 212. The plurality of first vias 202 and the plurality of second vias 205 extend from the source / drain terminals 118a-118d in a third direction 216 perpendicular to both the first direction 212 and the second direction 214.

[0028] like Figure 2B As shown in the top view 200b of the layout, the control gate 108 extends parallel to the second interconnects 204 in the second direction 214 (indicated by the dotted line). The source / drain terminals 118a-118h are arranged in a plurality of columns 218a-218b and a plurality of rows 220a-220d. In the source / drain terminals 118a-118h in the rows 220a-220d, the first portions 118a, 118c of the source / drain terminals are coupled to the plurality of second interconnects 204. In other words, the source / drain terminals 118a-118h that are arranged with the first portions 118a, 118c of the source / drain terminals 118a-118h in the second direction 214 are also coupled to the plurality of second interconnects 204. In addition, the source / drain terminals 118 a - 118 h and the second portions 118 b , 118 d of the source / drain terminals 118 a - 118 h arranged in the second direction 214 are coupled to a plurality of first interconnects 206 (indicated by dashed lines).

[0029] FIG. 3A to FIG. 3B The cross-sectional view 300a and the cross-sectional view 300b illustrate the operation of a BEOL flash memory cell utilizing a tunnel dielectric between a control gate and a floating gate. Figure 3A and Figure 3B .

[0030] The flash memory cell 104 stores 1 bit of information by being in a "0" state or a "1" state. Providing a programming voltage (e.g., in a "program" operation) or an erase voltage (e.g., in an "erase" operation) at the control gate 108 can change the state of the flash memory cell from a "0" state to a "1" state or from a "1" state to a "0" state, respectively. The state of the flash memory cell 104 is changed by changing the charge stored in the floating gate 112. The charge is changed through the tunneling dielectric 110 by electrons tunneling in and out of the floating gate 112. The charge changes the threshold voltage of the flash memory cell, which in turn changes the current detected through the channel 116 during a "read" operation. The blocking dielectric 114 prevents electrons from moving between the floating gate 112 and the channel 116.

[0031] For example, Figure 3A As shown in the cross-sectional view 300a of FIG. 1 , a programming voltage 303 is provided to the control gate 108. The programming voltage 303 is a positive voltage greater than a first minimum value to draw electrons 302 out of the floating gate 112 and cause the electrons 302 to enter the control gate 108 through the tunnel dielectric 110. The first minimum value depends on the voltage drop across the tunnel dielectric 110 (depending on the capacitance of the tunnel dielectric 110) and the capacitance of the blocking dielectric 114. The removal of electrons 302 from the floating gate 112 causes the floating gate 112 to have more positive charge, thereby reducing the threshold voltage of the flash memory cell 104. When a read voltage is subsequently provided to the control gate 108 during a "read" operation, the read voltage is greater than the threshold voltage of the flash memory cell 104, thereby causing a high current to flow through the channel 116.

[0032] like Figure 3B As shown in the cross-sectional view 300b of , an erase voltage 305 is provided to the control gate 108. The erase voltage 305 is a negative voltage less than the second maximum value to push the electrons 304 out of the control gate 108 and allow the electrons 304 to enter the floating gate 112 through the tunnel dielectric 110. The second maximum value depends on the voltage drop across the tunnel dielectric 110 (which depends on the capacitance of the tunnel dielectric 110) and the capacitance of the blocking dielectric 114. Adding the electrons 304 to the floating gate 112 causes the floating gate 112 to have more negative charge, thereby increasing the threshold voltage of the flash memory cell 104. When a read voltage is subsequently provided to the control gate 108 during a "read" operation, the read voltage is less than the threshold voltage of the flash memory cell 104, causing the current flowing through the channel 116 to be less than the threshold voltage of the flash memory cell 104. Figure 3A The current flow through the channel 116 is depicted. The read voltage is lower than the first minimum voltage and higher than the second maximum voltage so that no electrons move between the floating gate and the control gate during the read operation and the state of the flash memory cell is not disturbed.

[0033] Transmitting electrons 302, 304 between the control gate 108 and the floating gate 112 through the tunnel dielectric 110 results in a flash memory cell 104 having a more flexible design than a flash memory cell that transmits electrons between the channel 116 and the floating gate 112. As previously shown, the length L1 (and therefore the capacitance) of the control gate 108 and the tunnel dielectric 110 is independent of the length L2 of the floating gate 112, the blocking dielectric 114, and the channel 116, and the flash memory cell 104 can have a lower programming voltage 303 when the capacitance of the tunnel dielectric 110 is less than the capacitance of the blocking dielectric 114. Therefore, the capacitance of the tunnel dielectric 110 can be controlled, thereby achieving a flexible design of the flash memory cell 104 that can be configured to operate under a wider input voltage range.

[0034] FIG. 4A to FIG. 4G Several cross-sectional views of some alternative embodiments of BEOL flash memory cells and BEOL flash memory arrays are illustrated.

[0035] like Figure 4A As shown in the cross-sectional view 400a of FIG. 1 , in some embodiments, a conductive liner 402 is formed between the source / drain terminal 118 and the channel 116. In some embodiments, for example, the conductive liner 402 is or includes indium gallium zinc oxide (InGaZnO), indium oxide (InO), indium tin oxide (InSnO), indium zinc oxide (InZnO), indium tungsten oxide (InWO), or the like.

[0036] In some embodiments, the thickness t1 of the conductive liner 402 is about 3 nm to 10 nm, about 1 nm to 5 nm, about 4 nm to 15 nm, or in another suitable range. In some embodiments, the thickness t2 of the source / drain terminal 118 is about 10 nm to 40 nm, about 5 nm to 30 nm, about 15 nm to 50 nm, or in another suitable range. In some embodiments, the thickness t3 of the channel 116 is about 4 nm to 20 nm, about 2 nm to 16 nm, about 6 nm to 24 nm, or in another suitable range. In some embodiments, the thickness t4 of the blocking dielectric 114 is about 4 nm to 10 nm, about 2 nm to 8 nm, about 6 nm to 12 nm, or in another suitable range. In some embodiments, the thickness t5 of the floating gate 112 is approximately between 4 nm and 20 nm, approximately between 2 nm and 16 nm, approximately between 6 nm and 24 nm, or in another suitable range. In some embodiments, the thickness t6 of the tunnel dielectric 110 is approximately between 4 nm and 10 nm, approximately between 2 nm and 8 nm, approximately between 6 nm and 12 nm, or in another suitable range. In some embodiments, the thickness t7 of the control gate 108 is approximately between 10 nm and 40 nm, approximately between 5 nm and 30 nm, approximately between 15 nm and 50 nm, or in another suitable range.

[0037] In some embodiments, the first length L1 of the control gate 108 is approximately between 20 nm and 120 nm, approximately between 10 nm and 100 nm, approximately between 30 nm and 140 nm, or within another suitable range. In some embodiments, the third length L3 of the floating gate 112 is approximately between 60 nm and 120 nm, approximately between 50 nm and 100 nm, approximately between 70 nm and 140 nm, or within another suitable range. In some embodiments, the second length L2 (see Figure 1 ) is equal to the third length L3. In some embodiments, the fourth length L4 of the source / drain terminal 118 is approximately between 20 nm and 40 nm, approximately between 15 nm and 30 nm, approximately between 25 nm and 50 nm, or in another suitable range. In some embodiments, the distance d1 separating the source / drain terminals 118 is approximately between 20 nm and 40 nm, approximately between 15 nm and 30 nm, approximately between 25 nm and 50 nm, or in another suitable range.

[0038] like Figure 4BAs shown in the cross-sectional view 400b of FIG. 1 , in some embodiments, the control gate 108 and the tunnel dielectric 110 are offset from the center of the floating gate 112 in the first direction 212 and / or the second direction 214. The offset control gate 108 does not impair the function of the flash memory cell 104. Therefore, the control gate 108 can be offset from the center of the floating gate 112 to solve design rule issues and / or to align with other components of the layer below the control gate 108.

[0039] like Figure 4C As shown in the cross-sectional view 400c of FIG. 1 , in some embodiments, there is a secondary floating gate 404 directly above the tunnel dielectric 110. In some embodiments, the secondary floating gate 404 includes the same material as the floating gate 112. In other embodiments, the secondary floating gate 404 is or includes, for example, a conductive material different from the material of the floating gate 112. The secondary floating gate 404 has a length equal to the first length L1 of the tunnel dielectric 110 and is etched during the same etching process as the tunnel dielectric 110. The secondary floating gate 404 may be included to protect the tunnel dielectric 110 during a subsequent planarization process.

[0040] like Figure 4D As shown in the cross-sectional view 400d of FIG. 4 , in some embodiments, the tunnel dielectric 110 may have a length equal to the third length L3 of the floating gate 112. The process of forming the tunnel dielectric 110 may be performed after the control gate 108 is etched and planarized. Forming the tunnel dielectric 110 after the control gate 108 is planarized is another method to avoid performing a planarization process on the tunnel dielectric 110. Ending the planarization process on the tunnel dielectric 110 may cause damage to the tunnel dielectric 110 and cause the flash memory cell 104 to fail.

[0041] like Figure 4E As shown in the cross-sectional view 400 e of FIG. 4 , in some embodiments, the length of the tunnel dielectric 110 may be between the length of the control gate 108 and the length of the floating gate 112 .

[0042] like Figure 4F As shown in the cross-sectional view 400f of FIG. 1 , in some embodiments, there is a metal layer 406 below the control gate 108. In other embodiments, the control gate 108 is and / or includes a heavily doped (e.g., more than 10 Å per cubic centimeter). 20 atoms of dopant) silicon.

[0043] like Figure 4GAs shown in the cross-sectional view 400g of FIG. 1 , in some embodiments, the blocking dielectric 114 and the channel 116 extend continuously between the source / drain terminals 118a-118d across the plurality of separated floating gates 112. In such embodiments, the blocking dielectric 114 extends continuously across the upper surface of the floating gate 112 and the upper surface of one of the plurality of ILD layers 106. This architecture can remove one or more etching steps from the method of manufacturing, resulting in a more cost-effective and faster process.

[0044] Figure 5 A cross-sectional view 500 of some embodiments of an integrated circuit structure including a BEOL flash array and a FEOL transistor array is shown.

[0045] The integrated circuit structure includes a first flash array 502 on a substrate 102 overlying a FEOL component 504. In some embodiments, a second flash array 506 extends over the first flash array 502. In this way, any number of flash arrays can be embedded in the integrated circuit using BEOL-compatible processes. In some embodiments, a lower BEOL interconnect layer 508 separates the first flash array 502 from the FEOL component 504. In some embodiments, an upper BEOL interconnect layer 510 can cover the first flash array 502. The lower BEOL interconnect layer 508 and the upper BEOL interconnect layer 510 both include a plurality of metal lines 512 and a plurality of vias 514 coupled to the plurality of metal lines 512. In some embodiments, the plurality of vias 514 are coupled to the first flash array 502. The FEOL component 504 includes a plurality of logic components 516 on the substrate 102. The plurality of logic elements 516 may be or include metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate all around field effect transistors (GAAFETs), nanochip field effect transistors, the like, or any combination thereof. Using BEOL processes to form the flash memory arrays results in a more flexible integrated circuit design that can take advantage of evolving transistor technologies.

[0046] Reference Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 , provides cross-sectional views of some embodiments of BEOL flash memory arrays. Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 Although described as a series of actions, it should be understood that these actions are not restrictive, and the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0047] Figure 6 A cross-sectional view 600 of forming a first ILD layer 106a on a substrate 102 is shown. In some embodiments, the first ILD layer 106a includes silicon dioxide (SiO2) or the like. The substrate 102 can be any type of substrate. In some embodiments, the substrate 102 includes a semiconductor body, such as silicon, silicon germanium (SiGe), silicon on insulator (SOI), or the like. The substrate 102 can be a semiconductor wafer, one or more dies on a wafer, and / or any other type of semiconductor body and / or epitaxial layer. In some embodiments, the first ILD layer 106a can surround one or more lower interconnects (e.g., conductive contacts, internal vias, and / or internal metal lines). In some embodiments, the substrate 102 includes a FEOL layer of a component.

[0048] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E Various methods of forming the control gate 108 and the tunnel dielectric 110 are shown in cross-sectional views 700 a , 700 b , 700 c , 700 d , and 700 e .

[0049] In some embodiments, Fig. 7AAs shown, a control gate layer 701 is formed on the first ILD layer 106a, and a tunnel dielectric layer 703 is formed on the control gate layer 701. In some embodiments, the control gate layer 701 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electrochemical plating, electroless plating, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the tunnel dielectric layer 703 is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the control gate layer 701 is or includes, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), heavily doped silicon, a combination of the foregoing, or the like. In some embodiments, the tunnel dielectric layer 703 is or includes, for example, silicon dioxide (SiO2). i O2), silicon nitride (Si3N4), silicon oxynitride (SiON), a combination of the foregoing, or the like.

[0050] The control gate layer 701 and the tunnel dielectric layer 703 are then patterned using a first etching process 702 to form arrays of control gates 108 and tunnel dielectrics 110, respectively. The tunnel dielectric layer 703 and the control gate layer 701 are patterned according to a first mask 711 formed above the tunnel dielectric layer 703. For example, the first etching process 702 may use a dry etching technique suitable for etching through the tunnel dielectric layer 703 and the control gate layer 701. In various embodiments, the first etching process 702 may include plasma etching using tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or the like. In other embodiments, when the control gate layer 701 is a metal, the first etching process 702 may include additional plasma etching using carbon tetrachloride (CCl4), boron trichloride (BCl3), etc. The tunnel dielectric layer 703 and the control gate layer 701 are patterned into the control gate 108 and the tunnel dielectric 110. Then, the first mask 711 is removed.

[0051] After the first etching process 702 and the removal of the first mask 711, the second ILD layer 106b is deposited around the control gate 108 and the tunnel dielectric 110. Then, a planarization process (e.g., a chemical-mechanical planarization (CMP) process) is performed to remove the portion of the second ILD layer 106b above the tunnel dielectric 110. The second ILD layer 106b covers the upper surface of the first ILD layer 106a and the sidewalls of the control gate 108 and the tunnel dielectric 110.

[0052] In other embodiments, Figure 7BAs shown, the control gate layer 701 comprises silicon and is formed on the conformal metal layer 704. In some embodiments, the control gate layer 701 is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the deposition of the control gate layer 701 is followed by an implantation process to implant dopants into the control gate layer 701. The doping concentration of the dopant is greater than 10 20 In some embodiments, the tunnel dielectric layer 703 is formed by annealing the control gate layer 701 in an environment containing oxygen (O2) or water (H2O) to generate a tunnel dielectric layer 703 containing silicon dioxide. In other embodiments, the tunnel dielectric layer 703 can be formed using CVD, PVD, ALD, etc.

[0053] Then, a first etching process 702 is performed to pattern the tunnel dielectric layer 703, the control gate layer 701, and the conformal metal layer 704 to form the tunnel dielectric 110, the control gate 108, and the metal layer 406, respectively. The first etching process 702 patterns the tunnel dielectric layer 703, the control gate layer 701, and the conformal metal layer 704 according to the first mask 711, and then removes the first mask 711. After removing the first mask 711, a second ILD layer 106b is formed by depositing a dielectric material and removing a portion of the dielectric material above the upper surface of the tunnel dielectric 110 using a planarization process.

[0054] In yet other embodiments, Figure 7C As shown, the control gate layer 701 and the tunnel dielectric layer 703 are formed on a sacrificial wafer 706 and then bonded to the conformal metal layer 704 or the ILD layer 106. The sacrificial wafer 706 is then removed in whole or in part. In some embodiments, the sacrificial wafer 706 is removed using a planarization process (e.g., a chemical mechanical planarization (CMP) process, an etch-back process) or some other suitable removal process. This method forms the tunnel dielectric layer 703 and the control gate layer 701 on separate wafers, thereby reducing the heavy pressure on the thermal budget of the integrated circuit.

[0055] A first etching process 702 is then performed to pattern the tunnel dielectric layer 703, the control gate layer 701, and the conformal metal layer 704 to form the tunnel dielectric 110, the control gate 108, and the metal layer 406, respectively. The first etching process 702 patterns the tunnel dielectric layer 703, the control gate layer 701, and the conformal metal layer 704 according to the first mask 711, and then removes the first mask 711. After removing the first mask 711, a second ILD layer 106b is formed by depositing a dielectric material and removing a portion of the dielectric material above the upper surface of the tunnel dielectric 110 using a planarization process. In some embodiments, the planarization process removes a portion of the dielectric material above the upper surface of the sacrificial wafer 706.

[0056] In yet other embodiments, Fig.7D As shown, a secondary floating gate layer 707 is formed on the tunnel dielectric layer 703. The secondary floating gate layer 707 is or includes, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum alloy (TiAl), heavily doped polysilicon, combinations thereof, or the like.

[0057] A first etching process 702 is then performed to pattern the secondary floating gate layer 707, the tunnel dielectric layer 703, the control gate layer 701, and the conformal metal layer 704 to form the secondary floating gate 404, the tunnel dielectric 110, the control gate 108, and the metal layer 406, respectively. The first etching process 702 patterns the secondary floating gate layer 707, the tunnel dielectric layer 703, the control gate layer 701, and the conformal metal layer 704 according to the first mask 711, and then removes the first mask 711. After removing the first mask 711, a second ILD layer 106b is formed by depositing a dielectric material and removing a portion of the dielectric material above the upper surface of the secondary floating gate 404 using a planarization process. During the planarization process, the secondary floating gate 404 covers the tunnel dielectric 110. This results in less damage to the tunnel dielectric 110 , thereby extending the life of the flash memory cell 104 .

[0058] In yet other embodiments, Fig. 7EAs shown, a control gate layer 701 is formed on the first ILD layer 106a using a damascene process. A control gate opening 709 is formed in the first ILD layer 106a using a first etching process 702 according to a second mask 708. The control gate layer 701 is then deposited into the control gate opening 709. After the control gate layer 701 is deposited, a planarization process (e.g., a CMP process) is performed to remove a portion of the control gate layer 701 above the upper surface of the first ILD layer 106a. A tunnel dielectric layer 703 is then deposited on the control gate 108. In some embodiments, the tunnel dielectric layer 703 is not subsequently etched to form the tunnel dielectric 110 (see Figure 1 ).

[0059] Methods Fig. 7A It should be understood that in other embodiments (not shown), the method may alternatively proceed from FIG. 7B to FIG. 7E The embodiment of the present invention continues. Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a floating gate layer 802, a barrier layer 804, and a channel layer 806 are formed on the tunnel dielectric 110. In some embodiments, the floating gate layer 802 is formed using CVD, PVD, ALD, sputtering, electrochemical plating, chemical plating, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the barrier layer 804 and the channel layer 806 are formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the floating gate layer 802 is or includes, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum alloy (TiAl), heavily doped polysilicon, a combination of the foregoing, or the like. In some embodiments, the barrier layer 804 is or includes, for example, hafnium oxide (HFO2), aluminum oxide (Al2O3), hafnium zirconium oxide (HfZrO), a combination of the foregoing, or the like. In some embodiments, the channel layer 806 is or includes, for example, InGaZnO (IGZO), InO, InSnO (ITO), InZnO, InWO, polysilicon, silicon-germanium (SiGe), combinations of the foregoing, or the like.

[0060] like Fig. 9 As shown in the cross-sectional view 900, the floating gate layer 802 is etched (see Figure 8 ), barrier layer 804 (see Figure 8 ) and channel layer 806 (see Figure 8 ) to respectively form the floating gate 112, the blocking dielectric 114 and the channel 116. In some embodiments, the floating gate layer 802 is etched before the blocking layer 804 and the channel layer 806 are formed, so the blocking layer 804 and the channel layer 806 extend continuously above the floating gate 112 without being subsequently etched.

[0061] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a third ILD layer 106c is formed on the floating gate 112, the blocking dielectric 114 and the channel 116. In some embodiments, the third ILD layer 106c is formed using CVD, PVD, ALD, some other suitable deposition process or a combination of the foregoing processes.

[0062] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , the third ILD layer 106c is etched to form a plurality of source / drain openings 1102. The plurality of source / drain openings 1102 extend to the channel 116. In some embodiments, the third ILD layer 106c can be etched using, for example, one or more of a dry etching process, a reactive ion etching (RIE) process, some other etching process, or a combination of the foregoing processes.

[0063] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , source / drain terminals 118a-118d are formed in the source / drain opening 1102 (shown by dashed lines). The source / drain terminals 118a-118d are formed by depositing a source / drain material in the source / drain opening 1102 and then performing a planarization process (e.g., a CMP process) to remove a portion of the source / drain material above the third ILD layer 106c. In some embodiments, the source / drain terminals 118a-118d are or include, for example, titanium nitride (TiN), tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel silicide (NiSi), combinations of the foregoing, or the like. As shown in FIG. Figure 4A As shown, the source / drain terminals may include a conductive pad 402 .

[0064] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a plurality of first vias 202 and a second interconnect 204 are formed over the source / drain terminals 118a-118d. In some embodiments, the plurality of first vias 202 and the second interconnect 204 are formed using a single damascene process. In other embodiments, the plurality of first vias 202 and the second interconnect 204 are formed using a dual damascene process. The plurality of first vias 202 couple the second interconnect 204 to the first portions 118a, 118c of the source / drain terminals 118a-118d. In some embodiments, the first portions 118a, 118c of the source / drain terminals 118a-118d are an even array or an odd array of the source / drain terminals 118a-118d.

[0065] like Fig.14As shown in the cross-sectional view 1400 of , a plurality of second vias 203 and a plurality of first interconnects 206 are formed on the source / drain terminals 118a-118d. In some embodiments, the plurality of second vias 203 and the plurality of first interconnects 206 are formed using a single damascene process. In other embodiments, the plurality of second vias 203 and the plurality of first interconnects 206 are formed using a dual damascene process. The plurality of second vias 203 couple the plurality of first interconnects 206 to the second portions 118b, 118d of the source / drain terminals 118a-118d. In some embodiments, the second portions 118b, 118d of the source / drain terminals 118a-118d are an even array or an odd array of the source / drain terminals 118a-118d. In some embodiments, the source / drain terminals 118a-118d are alternately coupled to the second interconnects 204 and the plurality of first interconnects 206 in the first direction 212.

[0066] Fig.15 Illustrated is a method 1500 of forming a BEOL flash memory cell according to some embodiments. Although this method and other methods illustrated and / or described herein are illustrated as a series of actions or events, it should be understood that the present disclosure is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions may be performed in a different order than illustrated, and / or the actions may be performed simultaneously. In addition, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the illustrated actions or events may be omitted, and other actions or events not illustrated may be included.

[0067] At 1502, an interlayer dielectric (ILD) layer is formed over a substrate. For example, see Figure 6 .

[0068] At 1504, a control gate having a first length is formed on the ILD layer. Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E .

[0069] At 1506, a tunnel dielectric is formed over the top surface of the control gate. Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E .

[0070] At 1508, a floating gate having a second length is formed on the tunnel dielectric, the tunnel dielectric separating the floating gate and the control gate, wherein the first length is less than the second length. Figures 8 to 9 .

[0071] At 1510, a blocking dielectric and a channel are formed on the tunneling dielectric, wherein the blocking dielectric separates the floating gate and the channel. Figures 8 to 9 .

[0072] Therefore, the present invention is directed to a method of forming a BEOL flash memory array having an inverted tunneling architecture.

[0073] Some embodiments relate to an integrated circuit component, including: a control gate located on a substrate, the control gate having a first length; a tunneling dielectric located on the control gate; a floating gate having a second length and located on the tunneling dielectric, the tunneling dielectric separating the control gate from the floating gate; a blocking dielectric located on the floating gate; a channel located on the blocking dielectric, the blocking dielectric separating the channel from the floating gate; and a source / drain terminal located on the channel, wherein the first length of the control gate is less than the second length of the floating gate.

[0074] In some embodiments, the control gate and the source / drain terminals are separated from the substrate by an interlayer dielectric (ILD) layer. In some embodiments, the integrated circuit component further comprises: a first interconnect coupled to a first portion of the source / drain terminal and extending in a first direction; and a second interconnect coupled to a second portion of the source / drain terminal and extending in a second direction, wherein the control gate extends in a second direction perpendicular to the first interconnect. In some embodiments, the tunneling dielectric has a first dielectric constant, and the blocking dielectric has a second dielectric constant, the second dielectric constant being greater than the first dielectric constant. In some embodiments, the integrated circuit component further comprises a liner extending between the source / drain terminal and the channel. In some embodiments, the first length and the second length are measured in the first direction, and wherein the tunneling dielectric has a third length measured in the first direction, the third length being less than the second length. In some embodiments, the floating gate has a first sidewall and a second sidewall, the second sidewall is opposite to the first sidewall and separated in the first direction, and the tunneling dielectric and the control gate are closer to the first sidewall than the second sidewall. In some embodiments, the integrated circuit device further comprises a second floating gate extending between the floating gate and the tunnel dielectric, wherein the second floating gate has a first length. In some embodiments, the blocking dielectric and the channel have a second length.

[0075] Other embodiments relate to a flash memory cell comprising: a control gate located in an interlayer dielectric (ILD), wherein the control gate is configured to apply a programming voltage and an erase voltage to the flash memory cell; a floating gate extending across the control gate, the floating gate being configured to retain a charge determined by a programming voltage or an erase voltage most recently applied to the flash memory cell, wherein the charge changes a threshold voltage of the flash memory cell; and a tunneling dielectric extending between the floating gate and the control gate, the tunneling dielectric being configured to allow electrons to pass between the floating gate and the control gate when a programming voltage or an erase voltage is applied to the flash memory cell.

[0076] In some embodiments, the control gate has a first length measured in a first direction, the floating gate has a second length measured in the first direction, and the second length is greater than the first length. In some embodiments, the tunnel dielectric has a third length measured in the first direction, wherein the third length is less than the second length and greater than the first length. In some embodiments, the above-mentioned flash memory cell also includes a channel separated from the floating gate by a blocking dielectric, wherein the channel is configured to pass current from the first source / drain terminal to the second source / drain terminal based on a voltage measured at the control gate and a charge held by the floating gate. In some embodiments, when the control gate applies a programming voltage to the flash memory cell, the tunnel dielectric is configured to transfer electrons from the floating gate to the control gate, thereby reducing the threshold voltage of the flash memory cell. In some embodiments, when the control gate applies an erase voltage to the flash memory cell, the tunnel dielectric is configured to transfer electrons from the control gate to the floating gate, thereby increasing the threshold voltage of the flash memory cell.

[0077] Still other embodiments relate to a method of forming an integrated circuit component, comprising: forming a control gate having a first length on a substrate; forming a tunneling dielectric on a top surface of the control gate; forming a floating gate having a second length on the tunneling dielectric, the tunneling dielectric separating the floating gate and the control gate, wherein the first length is less than the second length; and forming a blocking dielectric and a channel on the tunneling dielectric, the blocking dielectric separating the floating gate and the channel.

[0078] In some embodiments, forming a floating gate, a blocking dielectric, and a channel on a tunneling dielectric further comprises: depositing a floating gate layer, a blocking layer, and a channel layer on a substrate and a tunneling dielectric; and patterning the floating gate layer, the blocking layer, and the channel layer using an etching process to form a floating gate, a blocking dielectric, and a channel directly above the tunneling dielectric. In some embodiments, forming a floating gate, a blocking dielectric, and a channel on a tunneling dielectric further comprises: depositing a floating gate layer on an ILD layer and a tunneling dielectric; patterning the floating gate layer to form a floating gate directly above the tunneling dielectric; depositing a second ILD layer around and above the floating gate; performing a planarization process on the second ILD layer; and depositing a blocking dielectric and a channel on the second ILD layer and the floating gate. In some embodiments, forming a control gate and a tunneling dielectric on a substrate further comprises: forming a silicon layer on the ILD layer; and performing an annealing process to form a silicon dioxide layer on the silicon layer. In some embodiments, forming a control gate and a tunneling dielectric on the substrate further comprises: forming the tunneling dielectric and the control gate on different wafers; bonding the different wafers to an integrated circuit component; and removing the different wafers, leaving the tunneling dielectric and the control gate on the integrated circuit component.

[0079] It should be understood that in this written description and in the claims, the terms "first", "second", "third", etc. are merely general identifiers used to facilitate description in order to distinguish different components of a figure or different components of a series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these components, and are not intended to describe corresponding components in different illustrated embodiments and / or unillustrated embodiments. For example, a "first dielectric layer" described with respect to a first figure does not necessarily correspond to a "first dielectric layer" described with respect to another figure, and does not necessarily correspond to a "first dielectric layer" in an unillustrated embodiment.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated circuit component, characterized in that: include: A control gate is located on the substrate, and the control gate has a first length; A tunneling dielectric is located on the control gate; A floating gate having a second length and located on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; A blocking dielectric is located on the floating gate; A channel is located on the blocking dielectric, and the blocking dielectric separates the channel from the floating gate; as well as a source / drain terminal located on the channel; The first length of the control gate is smaller than the second length of the floating gate.

2. The integrated circuit assembly according to claim 1, characterized in that: Also included is a pad extending between the source / drain terminal and the channel.

3. The integrated circuit assembly according to claim 1, wherein: The first length and the second length are measured in a first direction, and wherein the tunnel dielectric has a third length measured in the first direction, the third length being smaller than the second length.

4. The integrated circuit assembly according to claim 3, characterized in that: The floating gate has a first sidewall and a second sidewall, the second sidewall is opposite to the first sidewall and separated in the first direction, and the tunneling dielectric and the control gate are closer to the first sidewall than the second sidewall.

5. A flash memory unit, characterized in that: include: A control gate, located in the interlayer dielectric (ILD) layer; a floating gate extending across the control gate and configured to hold a charge determined by a programming voltage or an erase voltage applied to the control gate, wherein the charge changes a threshold voltage of the flash memory cell; and A tunnel dielectric extends between the floating gate and the control gate and is configured to allow electrons to pass between the floating gate and the control gate when the programming voltage or the erasing voltage is applied, thereby changing the charge of the flash memory cell.

6. The flash memory unit according to claim 5, characterized in that: The control gate has a first length measured in a first direction, the floating gate has a second length measured in the first direction, and the second length is greater than the first length.

7. The flash memory unit according to claim 6, characterized in that: The tunnel dielectric has a third length measured in the first direction, wherein the third length is less than the second length and greater than the first length.

8. The flash memory unit according to claim 5, characterized in that: Also included is a channel separated from the floating gate by a blocking dielectric, wherein the channel is configured to pass current from a first source / drain terminal to a second source / drain terminal based on a voltage measured at the control gate and the charge held by the floating gate.

9. The flash memory unit according to claim 8, characterized in that: When the control gate applies the programming voltage to the flash memory cell, the tunnel dielectric is configured to transfer the electrons from the floating gate to the control gate, thereby reducing the threshold voltage of the flash memory cell.

10. The flash memory unit according to claim 8, characterized in that: When the control gate applies the erase voltage to the flash memory cell, the tunnel dielectric is configured to transfer the electrons from the control gate to the floating gate, thereby increasing the threshold voltage of the flash memory cell.

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