Display panel and display device

Abstract

The utility model relates to the field of display panels, particularly provides a display panel and a display device, and aims to solve the problem that an existing structured light projector occupies a large area. In order to achieve the purpose, the display panel comprises a substrate and a functional layer located on the substrate; a first wire, a second wire and an electric connecting part are arranged in the functional layer, a light emitting diode and a first bonding pad are arranged on one side, far away from the substrate, of the functional layer, and a laser is mounted on the first bonding pad; the first driving signal is transmitted to the laser through the electric connecting part, the first wire and the first bonding pad, so that the laser emits light; the second driving signal is transmitted to the light-emitting diode through the second wire, so that the light-emitting diode emits light. The area occupied by the structured light projector can be reduced by integrating the electric connection component of the laser in the functional layer of the display panel; in addition, the laser and the display panel are packaged together and do not need to be packaged independently, so that the area occupied by the structured light projector is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display panels, and specifically provides a display panel and a display device. Background Art

[0002] 3D structured light can obtain the surface data of the measured object more accurately and is often used in fields such as face recognition. The 3D structured light system includes a structured light projector, a camera, and an image acquisition and processing system. The structured light projector emits light (usually an infrared laser) to the measured object, and the camera captures the three-dimensional light pattern formed by the light reflected by the measured object. The captured image is processed by the acquisition and processing system to obtain the surface data of the measured object.

[0003] In mobile phones, tablets and other display devices with face recognition, structured light projection equipment uses modules and is independently integrated on the mobile phone motherboard. Since the module hardware is large in size and is generally set in the display area of ​​the display panel, it occupies a large area of ​​the display panel, thus affecting the display effect. Utility Model Content

[0004] The present disclosure aims to solve the problems of the prior art and provides a display panel and a display device.

[0005] In a first aspect, the present disclosure provides a display panel, comprising: a substrate; a functional layer located on the substrate; a light-emitting diode located on a side of the functional layer away from the substrate; a first solder pad located on a side of the functional layer away from the substrate; a laser located on the first solder pad; a first wiring and an electrical connection component both located in the functional layer, a first drive signal being transmitted to the laser through the electrical connection component, the first wiring and the first solder pad, so that the laser emits light; a second wiring located in the functional layer, a second drive signal being transmitted to the light-emitting diode through the second wiring, so that the light-emitting diode emits light.

[0006] In some exemplary examples, the substrate is a glass substrate or a flexible substrate; a pixel driving circuit is provided in the functional layer; the display panel also includes: a first driving chip, which is provided in the bonding area of ​​the display panel and provides the first driving signal to the first wiring; a second driving chip, which is provided in the bonding area and provides the second driving signal to the second wiring through the pixel driving circuit.

[0007] In some exemplary examples, the substrate is a glass substrate or a flexible substrate; a laser driving circuit and a pixel driving circuit are provided in the functional layer, and the laser driving circuit serves as the electrical connection component; the display panel also includes: a driving chip, which provides a first driving signal to the first wiring through the laser driving circuit, and provides a second driving signal to the second wiring through the pixel driving circuit.

[0008] In some exemplary examples, the light emitting diode is an OLED formed on a side of the functional layer away from the substrate.

[0009] In some exemplary examples, the laser includes a first electrode and a second electrode, both of which are located on a side of the laser close to the first pad; there are two first pads, and the first electrode and the second electrode are respectively located on one of the two first pads.

[0010] In some exemplary examples, the laser includes a first electrode and a second electrode, which are respectively located on a side of the laser close to the first pad and a side of the laser away from the first pad; there is one first pad, and the first electrode is located on the first pad.

[0011] In some exemplary examples, the light emitting diode is a micro LED located on a side of the functional layer away from the substrate.

[0012] In some exemplary examples, the laser includes a first electrode and a second electrode, both located on a side of the laser close to the first pad; there are two first pads, and the first electrode and the second electrode are respectively located on one of the two first pads; the display panel also includes a second pad, which is located on a side of the functional layer away from the substrate; the micro LED includes a third electrode and a fourth electrode, both located on a side of the micro LED close to the second pad; there are two second pads, and the third electrode and the fourth electrode are respectively located on one of the two second pads.

[0013] In some exemplary examples, the laser includes a first electrode and a second electrode, which are respectively located on a side of the laser close to the pad and a side away from the pad; the first pad includes one, and the first electrode is located on the first pad; the display panel also includes a second pad, which is located on a side of the functional layer away from the substrate; the microLED includes a third electrode and a fourth electrode, both of which are located on a side of the micro LED close to the second pad; there are two second pads, and the third electrode and the fourth electrode are respectively located on one of the two second pads.

[0014] In some exemplary examples, the substrate is a silicon-based substrate; the display panel also includes a CMOS driving circuit located in the functional layer, wherein the CMOS driving circuit includes a first CMOS device and a second CMOS device; the light-emitting diode is a WOLED; wherein the first CMOS device serves as an electrical connection component, the first CMOS device provides the first driving signal to the first routing line, and the second CMOS device provides the second driving signal to the second routing line.

[0015] In some exemplary examples, the functional layer further includes a photodiode.

[0016] In some illustrative examples, the laser is a vertical cavity surface emitting laser.

[0017] In some exemplary examples, the display panel includes a display area and a laser area located in the display area, wherein the lasers are formed in the laser area in an array arrangement.

[0018] In a second aspect, the present disclosure provides a display device, comprising the above-mentioned display panel.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The display panel provided by the present disclosure includes a substrate and a functional layer located on the substrate; a first wiring, a second wiring and an electrical connection component are arranged in the functional layer, a light-emitting diode and a first pad are arranged on the side of the functional layer away from the substrate, and a laser is mounted on the first pad; a first driving signal is transmitted to the laser through the electrical connection component, the first wiring and the first pad, so that the laser emits light; a second driving signal is transmitted to the light-emitting diode through the second wiring, so that the light-emitting diode emits light. By integrating the electrical connection component of the laser into the functional layer of the display panel, the area occupied by the structured light projector can be reduced; in addition, the laser is packaged together with the display panel, and does not need to be packaged separately, thereby reducing the area occupied by the structured light projector. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The preferred embodiments of the present disclosure are described below in conjunction with the accompanying drawings, in which:

[0022] Figure 1 A plan view of a display panel provided for at least one embodiment of the present disclosure;

[0023] Figure 2A for Figure 1 The first cross-sectional view of the panel along line AA is shown in the figure;

[0024] Figure 2B for Figure 1 The second cross-sectional view of the panel along line AA is shown in the middle;

[0025] Figure 3A for Figure 1 The first cross-sectional view of the panel along line BB is shown in the middle;

[0026] Figure 3B for Figure 1 The second cross-sectional view of the panel along line BB is shown in the middle;

[0027] Figure 3C for Figure 1 The third cross-sectional view of the panel along line BB is shown in the middle;

[0028] Figure 3D for Figure 1 The fourth cross-sectional view of the panel along line BB is shown in the middle;

[0029] Figure 4A for Figure 1 The third cross-sectional view of the panel along line AA is shown in the middle;

[0030] Figure 4B for Figure 1 The fifth cross-section of the panel along line BB is shown in the middle;

[0031] Figure 4C for Figure 1 The sixth cross-sectional view of the panel along line BB is shown in the middle;

[0032] Figure 4D for Figure 1 The middle shows a cross-section of the panel along line CC;

[0033] Figure 5A for Figure 2A The middle shows a cross-section of the panel during the preparation process;

[0034] Figure 5B for Figure 2B The middle shows a cross-section of the panel during the preparation process;

[0035] Fig. 6A for Figure 3A The middle shows a cross-section of the panel during the preparation process;

[0036] Figure 6B for Figure 3B The middle shows a cross-section of the panel during the preparation process;

[0037] Figure 6C for Figure 3C The middle shows a cross-section of the panel during the preparation process;

[0038] Fig.6D for Figure 3D The middle shows a cross-section of the panel during the preparation process;

[0039] Fig. 7A for Figure 4A The middle shows a cross-section of the panel during the preparation process;

[0040] Figure 7B for Figure 4B A cross-sectional view of the panel during the preparation process is shown in FIG. DETAILED DESCRIPTION

[0041] The preferred embodiments of the present disclosure are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present disclosure and are not intended to limit the protection scope of the present disclosure.

[0042] It should be noted that in the description of the present disclosure, the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present disclosure. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0043] In addition, it should be noted that in the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installation", "setting", and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or the internal connection of two elements. For those skilled in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0044] In current display panels, an opening area is set in the display area, and hardware modules such as cameras and structured light projectors are set in the opening area. Among them, the hardware module of structured light projection needs to be separately set with packaging components and electrical connection components, resulting in a large volume of the structured light projector and a large area occupied by the display area. Therefore, the area in the display area where no display is performed is large, which affects the display effect.

[0045] In view of this, the present disclosure provides a display panel, comprising: a substrate; a functional layer located on the substrate; a light emitting diode located on a side of the functional layer away from the substrate; a first soldering pad located on a side of the functional layer away from the substrate; a laser located on the first soldering pad; a first wiring and an electrical connection component both located in the functional layer, a first driving signal being transmitted to the laser through the electrical connection component, the first wiring and the first soldering pad to cause the laser to emit light; a second wiring located in the functional layer, a second driving signal being transmitted to the light emitting diode through the second wiring to cause the light emitting diode to emit light.

[0046] The display panels and preparation methods of some embodiments of the present disclosure are described below through several specific embodiments.

[0047] Figure 1 A plan view of a display panel provided according to at least one embodiment of the present disclosure.

[0048] like Figure 1As shown, the display panel of the present disclosure includes a substrate 1, the substrate 1 includes a display area AA and a non-display area NA, the non-display area NA surrounds the display area AA, and a laser area 10 is arranged in the display area AA.

[0049] The laser area 10 can be set at any position of the display area AA. For example, the display area AA also includes an opening area 50, and the laser area 10 is set around the opening area 50. For example, the laser area 10 is located at a corner or edge of the display area AA to reduce the influence of the setting of the laser area 10 on the display effect in the display area AA.

[0050] Embodiment 1 - Display panel based on glass-based substrate or flexible substrate

[0051] Figure 2A for Figure 1 The first cross-sectional view of the panel along line AA is shown in FIG.

[0052] like Figure 2A As shown, in the embodiment of the present disclosure, the substrate 1 is specifically a rigid substrate such as glass, quartz, etc., or a flexible substrate such as polyimide (PI), and a functional layer 30 is provided on the substrate 1.

[0053] A pixel array is provided in the display area AA, and the pixel array includes a plurality of sub-pixels. The sub-pixels include a pixel driving circuit 2, a second wiring 3, and a light-emitting diode 4. The second wiring 3 and the pixel driving circuit 2 are located in the functional layer 30, and the light-emitting diode 4 is located on a side of the functional layer 30 away from the substrate 1. The second driving signal is transmitted to the light-emitting diode 4 through the pixel driving circuit 2 and the second wiring 3, so that the light-emitting diode 4 emits light.

[0054] The pixel driving circuit 2 includes a second thin film transistor 21 and a second storage capacitor 22. The second thin film transistor 21 includes a second active layer 211 located on the substrate 1, a second gate insulating layer 212, a second gate electrode 213 and a second interlayer insulating layer 214 located on the side of the second active layer 211 away from the substrate 1, and a second source electrode S2 and a second drain electrode D2 located on the side of the second interlayer insulating layer 214 away from the substrate 1. The second source electrode S2 and the second drain electrode D2 are electrically connected to the two ends of the second active layer 211 through vias. The second storage capacitor 22 includes a third electrode plate 221 and a fourth electrode plate 222. The third electrode plate 221 is arranged in the same layer as the gate electrode, and the fourth electrode plate 222 is located between the second gate insulating layer 212 and the second interlayer insulating layer 214.

[0055] In the embodiments of the present disclosure, two or more film layers are disposed in the same layer, which means that these film layers disposed in the same layer can be formed using the same material layer and the same preparation process (such as a composition process, etc.), thereby simplifying the preparation process of the display panel.

[0056] like Figure 2A As shown, in some examples, the light emitting diode 4 is an OLED formed on the side of the functional layer 30 away from the substrate 1. At this time, the functional layer 30 also includes a second flat layer 23 and an anode layer 31 sequentially arranged on the second source electrode S2, and the anode layer 31 is electrically connected to the second drain electrode D2 through a via. The anode layer 31 is the second wiring 3. The light emitting diode 4 includes a light emitting layer 41 and a cathode layer 44 arranged above the anode layer 31.

[0057] Figure 2B for Figure 1 The second cross-sectional view of the panel along line AA is shown in FIG.

[0058] like Figure 2B As shown, in other examples, the light-emitting diode 4 is a micro LED located on the side of the functional layer 30 away from the substrate 1, and the micro LED is transferred to the functional layer 30 by mass transfer. For example, a second pad 52 is provided on the side of the functional layer 30 away from the substrate 1, and there are two second pads 52; the micro LED includes a third electrode 42 and a fourth electrode 43, and the third electrode 42 and the fourth electrode 43 are both located on the side of the micro LED close to the second pad 52, and are respectively located on one of the two second pads 52. At this time, the second trace 3 includes an anode layer 31 and a cathode layer 44 provided in the functional layer 30, and the third electrode 42 is electrically connected to the anode layer 31 through one of the second pads 52, and the fourth electrode 43 is electrically connected to the cathode layer 44 through another second pad 52.

[0059] The pixel driving circuit 2 further includes a second metal layer 302 which is a single-layer or multi-layer film layer. The second metal layer 302 includes film layers disposed at the same layer as the second source electrode S2 and the second gate electrode 213, respectively, and adjacent film layers are electrically connected through vias; or, the second metal layer 302 includes a single-layer film layer disposed at the same layer as the second source electrode S2 or the second gate electrode 213.

[0060] Figure 3A for Figure 1 The first cross-sectional view of the panel along line BB is shown in FIG.

[0061] like Figure 3A As shown, a structured light projector is provided in the laser area 10, and the structured light projector includes a plurality of laser emitting units to emit array structured light. The laser emitting unit includes an electrical connection component, a first wiring 6 and a laser 8, the electrical connection component and the first wiring 6 are located in the functional layer 30, the laser 8 is located on the side of the functional layer 30 away from the substrate 1, and the first driving signal is transmitted to the laser 8 through the electrical connection component and the first wiring 6, so that the laser 8 emits a laser. For example, the first wiring 6 is arranged in the same layer as the anode layer 31. For example, the laser 8 is a vertical cavity surface emitting laser.

[0062] For example, a first pad 51 is provided on a side of the functional layer 30 away from the substrate 1, and the laser 8 is located on the first pad 51. The laser 8 is electrically connected to the first trace 6 in the functional layer 30 through the first pad 51 by flip-chip bonding.

[0063] In some examples, such as Figure 3A As shown, the electrical connection component includes a first metal layer 301 located in the functional layer 30, the first metal layer 301 is a single-layer or multi-layer film layer, and the first wiring 6 is electrically connected to the first metal layer 301 through a via. For example, the first metal layer 301 includes a film layer disposed at the same layer as the second source S2 and the second gate 213, and adjacent film layers are electrically connected through a via; or, the first metal layer 301 is a film layer disposed at the same layer as the second source S2 or the second gate 213.

[0064] For example, the non-display area NA of the display panel includes a bonding area BA, in which a first driving chip and a second driving chip which are independent of each other are arranged. The first driving chip provides a first driving signal to the first wiring 6 through the metal film layer to drive the laser 8 to emit laser light; the second driving chip provides a second driving signal to the second wiring 3 through the pixel driving circuit 2 to drive the light emitting diode 4 to emit light.

[0065] For example, Figure 3A As shown, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode flip-chip structure. The laser 8 includes a first electrode 81 and a second electrode 82, and the first electrode 81 and the second electrode 82 are both located on the side of the laser 8 close to the first pad 51. There are two first pads 51, and the first electrode 81 and the second electrode 82 are respectively located on one of the two first pads 51. That is, one of the first pads 51 is electrically connected to the first electrode 81, and the other first pad 51 is electrically connected to the second electrode 82. The first wiring 6 includes a cathode wiring 61 and an anode wiring 62, and the first driver chip provides a positive voltage power supply signal (such as a VDD signal) to the anode wiring 62 through an independent first metal layer 301, and provides a negative voltage power supply signal (such as a VSS signal) to the cathode wiring 61 through an independent first metal layer 301.

[0066] Figure 3B for Figure 1 The second cross-sectional view of the panel along line BB is shown in FIG.

[0067] For example, Figure 3BAs shown, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode upright structure. The laser 8 includes a first electrode 81 and a second electrode 82. The first electrode 81 is located on a side of the laser 8 close to the first pad 51, and the second electrode 82 is located on a side of the laser 8 away from the first pad 51. There is one first pad 51, and the first electrode 81 is located on the first pad 51. The first driver chip provides a positive voltage power supply signal (such as a VDD signal) to the first trace 6 through the first metal layer 301.

[0068] Figure 3C for Figure 1 The third cross-sectional view of the panel along line BB is shown in FIG.

[0069] In other examples, such as Figure 3C As shown, the electrical connection component includes a laser driving circuit 7 located in the functional layer 30, and the laser driving circuit 7 includes a first thin film transistor 71 and a first storage capacitor 72. The first thin film transistor 71 includes a first active layer 711 located on the substrate 1, a first gate insulating layer 712, a first gate electrode 713 and a first interlayer insulating layer 714 located on the side of the first active layer 711 away from the substrate 1, and a first source electrode S1 and a first drain electrode D1 located on the side of the first interlayer insulating layer 714 away from the substrate 1, and the first source electrode S1 and the first drain electrode D1 are respectively electrically connected to the two ends of the first active layer 711 through vias. The first storage capacitor 72 includes a first electrode plate 721 and a second electrode plate 722, the first electrode plate 721 and the first gate electrode 713 are arranged in the same layer, and the second electrode plate 722 and the first source electrode S1 are arranged in the same layer. For example, the first active layer 711 and the second active layer 211 are arranged on the same layer, the first gate insulating layer 712 and the second gate insulating layer 212 are arranged on the same layer, the first gate 713 and the second gate 213 are arranged on the same layer, the first interlayer insulating layer 714 and the second interlayer insulating layer 214 are arranged on the same layer, and the first source S1 and the second source S2 are arranged on the same layer.

[0070] In addition, the structures of the laser driving circuit 7 and the pixel driving circuit 2 are similar, which also facilitates wiring of the laser driving circuit 7 and the pixel driving circuit 2 in the functional layer 30 .

[0071] The functional layer 30 further includes a first planar layer 73 located on a side of the first source S1 away from the substrate 1 , and the first trace 6 is located on a side of the first planar layer 73 away from the substrate 1 .

[0072] For example, a driver chip is arranged in the bonding area BA, and the driver chip can provide a first driving signal to the first wiring 6 through the laser driving circuit 7 to drive the laser 8 to emit laser light, and the driver chip can also provide a second driving signal to the second wiring 3 through the pixel driving circuit 2 to drive the light emitting diode 4 to emit light. In this way, the same driver chip can provide the first driving signal and the second driving signal simultaneously or separately according to the needs, which can reduce the number of driver chips to be arranged.

[0073] Of course, in some other possible examples, a separate driving chip may be arranged in the bonding area BA to provide the first driving signal to the first trace 6 through the laser driving circuit 7 .

[0074] For example, Figure 3C As shown, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode upright structure. The laser 8 includes a first electrode 81 and a second electrode 82, the first electrode 81 is located on the side of the laser 8 close to the first pad 51, and the second electrode 82 is located on the side of the laser 8 away from the first pad 51. There is one first pad 51, and the first electrode 81 is located on the first pad 51. For example, the driver chip provides a positive voltage power supply signal (such as a VDD signal) to the first trace 6 through the laser driver circuit 7.

[0075] Figure 3D for Figure 1 The fourth cross-sectional view of the panel along line BB is shown in FIG.

[0076] For example, Figure 3D As shown, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode upright structure. The electrical connection components include a laser driving circuit 7 and a first metal layer 301. The laser 8 includes a first electrode 81 and a second electrode 82, and the first electrode 81 and the second electrode 82 are both located on a side of the laser 8 close to the first pad 51. There are two first pads 51, and the first electrode 81 and the second electrode 82 are respectively located on one of the two first pads 51. That is, one of the first pads 51 is electrically connected to the first electrode 81, and the other first pad 51 is electrically connected to the second electrode 82. The first wiring 6 includes a cathode wiring 61 and an anode wiring 62, and the first driver chip provides a positive voltage power supply signal (such as a VDD signal) to the anode wiring 62 through the laser driving circuit 7, and provides a negative voltage power supply signal (such as a VSS signal) to the cathode wiring 61 through the first metal layer 301.

[0077] In summary, the embodiments of the present disclosure include the following specific methods:

[0078] (1) In the display area AA, the light emitting diode 4 is an OLED; in the laser area 10, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode upright structure;

[0079] (2) In the display area AA, the light emitting diode 4 is an OLED; in the laser area 10, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode upright structure;

[0080] (3) In the display area AA, the light-emitting diode 4 is a micro LED; in the laser area 10, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode upright structure;

[0081] (4) In the display area AA, the light-emitting diode 4 is a micro LED; in the laser area 10, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode front-mounted structure.

[0082] In the example disclosed herein, the space occupied by the structured light projector can be reduced by integrating the electrical connection components (such as the laser drive circuit 7 and / or the first metal layer 301) in the structured light projector into the functional layer 30 of the display panel. In addition, the laser 8 in the structured light projector is connected to the functional layer 30 of the display panel by mass transfer and is packaged together with the display panel, so that the structured light projector does not need to be packaged separately, thereby reducing the area occupied by the structured light projector.

[0083] Embodiment 2 - Display panel based on silicon substrate

[0084] Figure 4A for Figure 1 The third cross-sectional view of the panel along line AA is shown in the middle; Figure 4B for Figure 1 The fifth cross-sectional view of the panel along line BB is shown in FIG.

[0085] like Figure 4A and Figure 4B As shown, the substrate 1 of the embodiment of the present disclosure is a silicon-based substrate, on which a functional layer 30 is disposed. The functional layer 30 includes an epitaxial layer 11 and other film layers located on the substrate 1.

[0086] like Figure 4B As shown, a structured light projector is provided in the laser area 10, and the structured light projector includes a plurality of laser emitting units to emit array structured light. The laser emitting unit includes an electrical connection component, a first wiring 6 and a laser 8, wherein the first wiring 6 is located in the functional layer 30, and the laser 8 is located on a side of the functional layer 30 away from the substrate 1. The first driving signal is transmitted to the laser 8 through the electrical connection component and the first wiring 6, so that the laser 8 emits laser light.

[0087] For example, a first pad 51 is provided on a side of the functional layer 30 away from the substrate 1, and the laser 8 is located on the first pad 51. The laser 8 is electrically connected to the first trace 6 in the functional layer 30 through the first pad 51 by flip-chip bonding.

[0088] A pixel array is provided in the display area AA, and the pixel array includes a plurality of sub-pixels. The sub-pixels include a second wiring 3 and a light-emitting diode 4, the second wiring 3 is located in the functional layer 30, and the light-emitting diode 4 is located on a side of the functional layer 30 away from the substrate 1, and the second driving signal is transmitted to the light-emitting diode 4 through the second wiring 3, so that the light-emitting diode 4 emits light.

[0089] The display panel also includes a driver chip and a CMOS (Complementary Metal Oxide Semiconductor) driver circuit. The CMOS driver circuit includes a first CMOS device 91 and a second CMOS device 92, wherein the first CMOS device 91 is at least a part of the electrical connection component. The driver chip can provide a first drive signal to the first wiring 6 through the first CMOS device 91, and the driver chip can also provide a second drive signal to the second wiring 3 through the second CMOS device 92.

[0090] For example, Figure 4B As shown, the first CMOS device 91 is a planar gate field effect transistor, including a first well region 910 of a first doping type located in the epitaxial layer 11, a first source S1 and a first drain D1 of a second doping type located in the first well region 910, and a first gate insulating layer 712 and a first gate 713 located on the epitaxial layer 11. For example, the first well region 910 is N-type doped, and the first source S1 and the first drain D1 are P-type doped.

[0091] For example, Figure 4A As shown, the second CMOS device 92 is a planar gate field effect transistor, including a second well region 920 of a first doping type located in the epitaxial layer 11, a second source S2 and a second drain D2 of a second doping type located in the second well region 920, and a second gate insulating layer 212 and a second gate 213 located on the epitaxial layer 11. The first gate 713 and the second gate 213 are arranged in the same layer, and the first gate insulating layer 712 and the second gate insulating layer 212 are arranged in the same layer. For example, the second well region 920 is N-type doped, and the second source S2 and the second drain D2 are P-type doped.

[0092] Of course, the first CMOS device 91 and the second CMOS device 92 may also be other types of field effect transistors, such as trench gate field effect transistors.

[0093] For example, Figure 4BAs shown, the electrical connection component further includes a first metal layer 301. The first source S1 is electrically connected to the driver chip through the first metal layer 301 disposed in the functional layer 30, and the first wiring 6 is electrically connected to the first drain D1 through the first metal layer 301, so that the driver chip can provide a first driving signal to the first wiring 6 through the first CMOS device 91.

[0094] The second source S2 is electrically connected to the driver chip through the second metal layer 302 arranged in the functional layer 30 , and the second wiring 3 is electrically connected to the second drain D2 through the second metal layer 302 , so that the driver chip can provide a second driving signal to the second wiring 3 through the second CMOS device 92 .

[0095] For example, Figure 4A As shown, the light emitting diode 4 is a WOLED, comprising a light emitting layer 41, a cathode layer 44 and a color filter layer 45 sequentially located on the functional layer 30. The transmitted light of the color filter layer 45 in different sub-pixels is different, for example, the transmitted light of the color filter layer 45 in the three-color sub-pixel is red light, green light and blue light respectively.

[0096] For example, Figure 4B As shown, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode upright structure. The laser 8 includes a first electrode 81 and a second electrode 82, and the first electrode 81 and the second electrode 82 are both located on the side of the laser 8 close to the first pad 51. There are two first pads 51, and the first electrode 81 and the second electrode 82 are respectively located on one of the two first pads 51. That is, one of the first pads 51 is electrically connected to the first electrode 81, and the other first pad 51 is electrically connected to the second electrode 82. The first wiring 6 includes an anode wiring 62 and a cathode wiring 61. The driver chip provides a positive voltage power supply signal (such as a VDD signal) to the anode wiring 62 through the first CMOS device 91, and provides a negative voltage power supply signal (such as a VSS signal) to the cathode wiring 61 through the first metal layer 301.

[0097] Figure 4C for Figure 1 The sixth cross-sectional view of the panel along line BB is shown in FIG.

[0098] For example, Figure 4C As shown, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode upright structure. The laser 8 includes a first electrode 81 and a second electrode 82, the first electrode 81 is located on the side of the laser 8 close to the first pad 51, and the second electrode 82 is located on the side of the laser 8 away from the first pad 51. There is one first pad 51, and the first electrode 81 is located on the first pad 51. For example, the driver chip provides a positive voltage power supply signal (such as a VDD signal) to the first trace 6 through the laser driver circuit 7.

[0099] Figure 4D for Figure 1 The cross-section of the panel along line CC is shown in FIG.

[0100] In some embodiments, Figure 4D As shown, the functional layer 30 also includes a photodiode 40. The reflected light of the laser emitted from the structured light projector after being reflected by the object can be received by the photodiode 40, and the electrical signal generated by the photodiode 40 receiving the reflected light can be processed to form a three-dimensional light pattern, and the surface data of the measured object can be obtained after further processing.

[0101] For example, the photodiode 40 is an APD (Avalanche Photodiode), including a first doping region 401 and a second doping region 402 located in the epitaxial layer 11, the doping types of the first doping region 401 and the second doping region 402 are opposite, and the second doping region 402 is located on the side of the first doping region 401 away from the substrate 1. The doping type of the substrate 1 and the epitaxial layer 11 is the same as the doping type of the first doping region 401, and the doping concentration of the substrate 1 is greater than the doping concentration of the epitaxial layer 11. A third metal layer 303 is provided in the functional layer 30, and the third metal layer 303 includes a single layer or a multi-layer metal film layer, and different metal film layers are electrically connected through metal electrodes (such as tungsten electrodes). The second doping region 402 is electrically connected to the third metal layer 303.

[0102] For example, a guard ring 403 is formed in the epitaxial layer 11, and the first doping region 401 and the second doping region 402 are located in the guard ring 403. The doping type of the guard ring 403 is the same as the doping type of the second doping region 402. For example, the doping type of the substrate 1 is P+ type, the doping type of the epitaxial layer 11 is P type (specifically, low doping close to the intrinsic state), the doping type of the first doping region 401 is P type, the doping type of the second doping region 402 is N+ type, and the doping type of the guard ring 403 is N type.

[0103] like Figure 1 As shown, the display area AA includes a laser receiving area 20, and the photodiode is integrated in a functional layer 30 in the laser receiving area 20. For example, the laser receiving area 20 is arranged around the laser area 10.

[0104] At least one embodiment of the present disclosure also provides a method for preparing a display panel, comprising: forming a functional layer on a substrate, the functional layer comprising a first routing line, a second routing line and an electrical connection component; forming a first soldering pad on a side of the functional layer away from the substrate; forming a light-emitting diode on a side of the functional layer away from the substrate; installing a laser on the first soldering pad; wherein a first driving signal is transmitted to the laser through the electrical connection component, the first routing line and the first soldering pad to cause the laser to emit light; and a second driving signal is transmitted to the light-emitting diode through the second routing line to cause the light-emitting diode to emit light.

[0105] The following is a method for preparing a display panel based on a glass-based substrate or a flexible substrate disclosed in at least one embodiment of the present disclosure.

[0106] Figure 5A for Figure 2A A cross-sectional view of the panel during the preparation process is shown in FIG.

[0107] First, if Figure 5A As shown, a substrate 1 is provided. For example, when the display panel is a flexible display panel, the provided substrate 1 may be a flexible substrate such as polyimide (PI), and when the display panel is a rigid display panel, the substrate 1 may be a rigid substrate such as glass or quartz.

[0108] A pixel driving circuit 2 is formed in the display area AA, that is, a second thin film transistor 21 and a second storage capacitor 22 are formed.

[0109] For example, in the display area AA, a second active layer 211 is formed on the substrate 1 by a patterning process, a second gate insulating layer 212 is formed on the second active layer 211 by deposition or the like, and a second gate 213 and a third electrode 221 are simultaneously formed on the second gate insulating layer 212 by a patterning process; another second gate insulating layer 212 is formed on the second gate 213 and the third electrode 221 by deposition or the like, and the two second gate insulating layers 212 wrap the second gate 213 to ensure that the second gate 213 is insulated from the remaining film layers; a fourth electrode 222 is formed by a patterning process, a second interlayer insulating layer 214 is formed on the fourth electrode 222 by deposition, and then the second gate insulating layer 212 and the second interlayer insulating layer 214 are etched to form a via hole exposing the second active layer 211. For example, a patterning process includes processes such as formation of photoresist, exposure, development, and etching.

[0110] For example, the material of the second gate 213 and the third electrode 221 includes metal or alloy materials such as aluminum, titanium, and cobalt. During preparation, a layer of the second gate 213 material layer is first formed by sputtering or evaporation, and then the second gate 213 material layer is patterned to form a patterned second gate 213 and third electrode 221. The formation method of other structures formed in the same layer is similar to this, so it is not repeated here.

[0111] For example, the second active layer 211 may be made of materials such as polysilicon and metal oxide, the second gate insulating layer 212 may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, the fourth electrode 222 may be made of metal or alloy materials such as aluminum, titanium, cobalt, etc., and the second interlayer insulating layer 214 may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The embodiments of the present disclosure do not limit the materials of each functional layer 30, and the materials of each functional layer 30 are not limited to the above examples.

[0112] After the via hole in the second interlayer insulating layer 214 is formed, a second source electrode and a second drain electrode are formed.

[0113] For example, the second source S2 and the second drain D2 may be formed into a multi-layer metal structure, such as a three-layer metal structure. For example, in one example, a titanium material layer, an aluminum material layer, and a titanium material layer may be formed in sequence by sputtering or evaporation, and then the three material layers may be patterned by the same patterning process, thereby forming a titanium / aluminum / titanium three-layer metal structure constituting the second source S2 and the second drain D2.

[0114] After the film layers of the second thin film transistor 21 and the second storage capacitor 22 are formed, the second planarization layer 23 is formed.

[0115] For example, the second planar layer 23 is formed by a patterning process. For example, the material of the second planar layer 23 can be an organic insulating material such as polyimide, epoxy resin, etc. The formed second planar layer 23 has a via hole, so that the anode layer 31 formed later is electrically connected to the second drain electrode D2 through the via hole.

[0116] For example, Figure 2A As shown, the light emitting diode 4 is an OLED, and after forming the second planar layer 23, an anode layer 31, a pixel defining layer 46 and a spacer 47 are sequentially formed. The anode layer 31 serves as the second wiring 3. The anode layer 31 is electrically connected to the second drain electrode D2 through a via hole.

[0117] For example, a patterning process is used to form an anode layer 31 on the second planar layer 23 of the display area AA. The anode layer 31 is electrically connected to the second drain electrode D2 through a via hole in the second planar layer 23. For example, the material of the anode layer 31 includes metal oxides such as ITO and IZO or metals such as Ag, Al, Mo or their alloys.

[0118] For example, the pixel defining layer 46 is formed by a patterning process. The pixel defining layer 46 has an opening exposing the anode layer 31, so as to form the light emitting layer 41 and the cathode layer 44 of the light emitting diode 4. For example, the material of the pixel defining layer 46 may include organic insulating materials such as polyimide and epoxy resin.

[0119] For example, the spacers 47 are formed by a patterning process. The spacers 47 are made of organic insulating materials such as polyimide and epoxy resin.

[0120] Figure 5B for Figure 2B A cross-sectional view of the panel during the preparation process is shown in FIG.

[0121] For example, Figure 5BAs shown, the light-emitting diode 4 is a micro LED. In the process of forming the second thin film transistor 21 and the second storage capacitor 22, a second metal layer 302 is formed in the display area AA. The second metal layer 302 includes multiple sub-metal film layers, and an insulating film layer is formed between the sub-metal film layers. The sub-metal film layers are electrically connected by vias. For example, one of the sub-metal film layers is formed in the same layer with the second gate 213 using the same composition process, and one of the sub-metal film layers is formed in the same layer with the second source S2 using the same composition process, so as to simplify the manufacturing process of the display panel.

[0122] like Figure 2B As shown, after forming the second planar layer 23, a second wiring 3 including an anode layer 31 and a cathode layer 44 is formed. The anode layer 31 is electrically connected to the second drain electrode D2 through a via, and the cathode layer 44 is electrically connected to the second metal layer 302 through a via.

[0123] A second pad 52 is formed on the second trace 3 , and a light emitting diode 4 is mounted on the second pad 52 .

[0124] For example, the micro LED is transferred to the display area AA by mass transfer, so that the first electrode 81 of the micro LED is electrically connected to the anode layer 31 through a second pad 52, and the second electrode 82 is electrically connected to the base layer through another second pad 52.

[0125] Electrical connections are formed in the laser region 10 .

[0126] Fig. 6A for Figure 3A A cross-sectional view of the panel during the preparation process is shown in FIG.

[0127] For example, Fig. 6A and Figure 3A As shown, the electrical connection component includes a first metal layer 301. The first metal layer 301 includes multiple sub-metal film layers, an insulating film layer is formed between the sub-metal film layers, and the sub-metal film layers are electrically connected by vias. For example, one of the sub-metal film layers is formed in the same layer with the second gate 213 using the same patterning process, and one of the sub-metal film layers is formed in the same layer with the second source S2 using the same patterning process.

[0128] A first flat layer 73 is formed, and the first flat layer 73 and the second flat layer 23 can be formed in the same process step and in the same layer. A first wiring 6 is formed on the first flat layer 73, and the first wiring 6 is electrically connected to the first metal layer 301 through a via. A first pad 51 is formed on the first wiring 6, and a laser 8 is mounted on the first pad 51.

[0129] An insulating layer 83 is formed on the first wiring 6, and the insulating layer 83 has an opening that exposes the first wiring 6. For example, the insulating layer 83 and the pixel defining layer 46 are formed in the same layer by using the same patterning process.

[0130] For example, the laser 8 is transferred to the laser region 10 by mass transfer, so that the electrode of the laser 8 is located on the first pad 51 .

[0131] For example, Fig. 6A and Figure 3A As shown, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode upright structure, the first trace 6 includes a cathode trace 61 and an anode trace 62, the cathode trace 61 is electrically connected to a separate first metal layer 301 through a via, and the anode trace 62 is electrically connected to another separate first metal layer 301 through a via. The first electrode 81 of the laser 8 is electrically connected to the anode trace 62 through a first pad 51, and the second electrode 82 is electrically connected to the cathode trace 61 through another first pad 51.

[0132] Figure 6B for Figure 3B A cross-sectional view of the panel during the preparation process is shown in FIG.

[0133] For example, Figure 6B and Figure 3B As shown, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode upright structure, and the first electrode 81 of the laser 8 is electrically connected to the first trace 6 through the first pad 51 .

[0134] Figure 6C for Figure 3C A cross-sectional view of the panel during the preparation process is shown in FIG.

[0135] For example, Figure 6C and Figure 3C As shown, the electrical connection component includes a laser driving circuit 7. The formation of the electrical connection component includes: in the laser region 10, a first active layer 711 is formed on the substrate 1 by a patterning process, a first gate insulating layer 712 is formed on the first active layer 711 by deposition or the like, and a first gate 713 and a first electrode plate 721 are simultaneously formed on the first gate insulating layer 712 by a patterning process; another first gate insulating layer 712 is formed on the first gate 713 and the first electrode plate 721 by deposition or the like, and the two first gate insulating layers 712 wrap the first gate 713 to ensure that the first gate 713 is insulated from the remaining film layers; a second electrode plate 722 is formed by a patterning process, a first interlayer insulating layer 714 is formed on the second electrode plate 722 by deposition, and then the first gate insulating layer 712 and the first interlayer insulating layer 714 are etched to form a via hole exposing the first active layer 711.

[0136] A first flat layer 73 is formed, and the first flat layer 73 and the second flat layer 23 can be formed in the same process step and in the same layer. A first wiring 6 is formed on the first flat layer 73, and the first wiring 6 is electrically connected to the first metal layer 301 through a via. A first pad 51 is formed on the first wiring 6, and then the laser 8 is transferred to the laser area 10, so that the electrode of the laser 8 is located on the first pad 51.

[0137] For example, the laser 8 is a vertical cavity surface emitting laser with a vertical electrode upright structure, and the first electrode 81 of the laser 8 is electrically connected to the first trace 6 through the first pad 51 .

[0138] Fig.6D for Figure 3D A cross-sectional view of the panel during the preparation process is shown in FIG.

[0139] For example, Fig.6D and Figure 3D As shown, the laser 8 is a vertical cavity surface emitting laser with a horizontal electrode upright structure, the first trace 6 includes a cathode trace 61 and an anode trace 62, and the electrical connection components include a laser driving circuit 7 and a first metal layer 301. The cathode trace 61 is electrically connected to the first metal layer 301 through a via, and the anode trace 62 is electrically connected to the first drain D1 through a via. The first electrode 81 of the laser 8 is electrically connected to the anode trace 62 through a first pad 51, and the second electrode 82 is electrically connected to the cathode trace 61 through another first pad 51.

[0140] The following is a method for preparing a display panel based on a silicon-based substrate disclosed in at least one embodiment of the present disclosure.

[0141] Fig. 7A for Figure 4A The middle shows a cross-section of the panel during the preparation process; Figure 7B for Figure 4B A cross-sectional view of the panel during the preparation process is shown in FIG.

[0142] First, a substrate 1 is provided. For example, the substrate 1 is a silicon-based substrate. For example, an epitaxial layer 11 is formed on the substrate 1 .

[0143] like Fig. 7A and Figure 7B As shown, a CMOS driving circuit is formed on the epitaxial layer 11, wherein the CMOS driving circuit includes a first CMOS device 91 located in the laser area 10 and a second CMOS device 92 located in the display area AA. The first CMOS device 91 serves as at least a part of the electrical connection component.

[0144] The first CMOS device 91 and the second CMOS device 92 are both field effect transistors, including but not limited to trench field effect transistors and planar field effect transistors, such as Trench VDMOS (Trench Vertical Double Diffused Metal Oxide Semiconductor), Planar VDMOS (Planar Vertical Double Diffused Metal Oxide Semiconductor), IGBT (Insulated Gate Bipolar Transistor), Trench LDMOS (Trench Laterally Diffused Metal Oxide Semiconductor), Planar LDMOS (Planar Laterally Diffused Metal Oxide Semiconductor). This embodiment is described by taking the first CMOS device 91 and the second CMOS device 92 as Planar VDMOS (Planar Vertical Double Diffused Metal Oxide Semiconductor) as an example.

[0145] For example, Figure 7B As shown, doping and high-temperature annealing are performed on the surface of the epitaxial layer 11 to form a first well region 910 of a first doping type; doping and high-temperature annealing are performed on the surface of the first well region 910 to form a first source S1 and a first drain D1 of a second doping type. For example, the doping type of the first well region 910 is N-type doping, and the doping type of the first source S1 and the first drain D1 is P-type doping.

[0146] For example, a first gate insulating layer 712, a first gate electrode 713 and a first dielectric layer are sequentially formed on the epitaxial layer 11. A via hole exposing the first source electrode S1 and the first drain electrode D1 is formed on the first dielectric layer, and a metal electrode (such as a tungsten electrode) is filled in the via hole.

[0147] For example, multiple layers of metal film layers and dielectric film layers are alternately formed on the first dielectric layer, vias are formed in the dielectric film layers between adjacent metal film layers, metal electrodes are filled in the vias, and adjacent metal film layers are electrically connected through the metal electrodes filled in the vias. The single or multiple metal film layers formed on the first dielectric layer together constitute the first metal layer 301.

[0148] Then, a patterning process is used to form the first wiring 6 . The first wiring 6 includes an anode wiring 62 and a cathode wiring 61 . The anode wiring 62 is electrically connected to the first drain electrode D1 through the first metal layer 301 , and the cathode wiring 61 is electrically connected to the separate first metal layer 301 .

[0149] like Figure 4B As shown, a first pad 51 is formed on the first trace 6, and a laser 8 is mounted on the first pad 51, so that a first electrode 81 of the laser 8 is electrically connected to the anode trace 62 through one of the first pads 51, and a second electrode 82 is electrically connected to the cathode trace 61 through another first pad 51.

[0150] For example, Fig. 7AAs shown, doping and high-temperature annealing are performed on the surface of the epitaxial layer 11 to form a second well region 920 of the first doping type, and doping and high-temperature annealing are performed on the surface of the second well region 920 to form a second source S2 and a second drain D2 of the second doping type. For example, the doping type of the second well region 920 is N-type doping, and the second well region 920 and the first well region 910 are formed in the same process step; the doping type of the second source S2 and the second drain D2 is P-type doping, and the second source S2, the second drain D2, the first source S1 and the first drain D1 are formed in the same process step to simplify the manufacturing process of the display panel.

[0151] For example, a second gate insulating layer 212, a second gate electrode 213, and a second dielectric layer are sequentially formed on the epitaxial layer 11. A via hole exposing the second source electrode S2 and the second drain electrode D2 is formed on the second dielectric layer, and a metal electrode (such as a tungsten electrode) is filled in the via hole. For example, the second gate insulating layer 212 and the first gate insulating layer 712 are formed in the same layer using the same patterning process, the second gate electrode 213 and the second gate electrode 213 are formed in the same layer using the same patterning process, and the second dielectric layer and the first dielectric layer are formed in the same layer using the same patterning process, so as to simplify the manufacturing process of the display panel.

[0152] For example, multiple layers of metal film layers and dielectric film layers are alternately formed on the second dielectric layer, vias are formed in the dielectric layers between adjacent metal film layers, metal electrodes are filled in the vias, and adjacent metal film layers are electrically connected through the metal electrodes filled in the vias. The single or multiple metal film layers on the second dielectric layer together constitute the second metal layer 302.

[0153] For example, the single-layer metal film layer located in the display area AA and the single-layer metal film layer located in the laser area 10 are formed in the same layer using the same composition process, and the single-layer dielectric film layer located in the display area AA and the single-layer dielectric film layer located in the laser area 10 are formed in the same layer using the same composition process.

[0154] Then, a patterning process is used to form the second wiring 3. The second wiring 3 is electrically connected to the second drain electrode D2 through the second metal layer 302.

[0155] For example, Figure 4A As shown, the light emitting diode 4 is a WOLED. A pixel defining layer 46 is formed on the second wiring 3 by a patterning process. The pixel defining layer 46 has an opening exposing the second wiring 3 so as to form the light emitting layer 41, cathode layer 44 and color filter layer 45 of the light emitting diode 4 later.

[0156] For example, the method for manufacturing a display panel provided by at least one embodiment of the present disclosure further includes: forming a photodiode 40 in the functional layer 30 of the laser receiving area 20. For example, the photodiode 40 is an avalanche photodiode.

[0157] For example, Figure 4D As shown, doping and high-temperature annealing are performed on the surface of the epitaxial layer 11 to form a first doping region 401 of a first doping type, and then a second doping and high-temperature annealing are performed on the surface of the epitaxial layer 11 to form a second doping region 402 of a second doping type. For example, a third doping is performed on the surface of the epitaxial layer 11 to form a guard ring 403 of a second doping type, and both the first doping region 401 and the second doping region 402 are located in the guard ring 403.

[0158] For example, a third metal layer 303 is formed in the functional layer 30 , wherein the third metal layer 303 includes multiple metal film layers, a dielectric layer is formed between adjacent metal film layers, and adjacent metal film layers are electrically connected through metal electrodes filled in vias. The third metal layer 303 is electrically connected to the second doped region 402 .

[0159] At least one embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel or the display panel obtained by the preparation method provided in the embodiment of the present disclosure. The display device can be applied to any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, etc., and the embodiments of the present disclosure do not define this.

[0160] There are a few points to note:

[0161] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0162] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0163] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0164] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: substrate; a functional layer disposed on a substrate; A light emitting diode, located on a side of the functional layer away from the substrate; A first pad is located on a side of the functional layer away from the substrate; A laser, located on the first pad; A first wiring and an electrical connection component are both located in the functional layer, and a first driving signal is transmitted to the laser through the electrical connection component, the first wiring and the first pad, so that the laser emits light; The second wiring is located in the functional layer, and the second driving signal is transmitted to the light-emitting diode through the second wiring, so that the light-emitting diode emits light.

2. The display panel according to claim 1, characterized in that: The substrate is a glass substrate or a flexible substrate; A pixel driving circuit is arranged in the functional layer; The display panel further includes: A first driving chip is disposed in a bonding area of ​​the display panel and provides the first driving signal to the first wiring; The second driving chip is disposed in the bonding area and provides the second driving signal to the second wiring through the pixel driving circuit.

3. The display panel according to claim 1, characterized in that: The substrate is a glass substrate or a flexible substrate; The functional layer is provided with a laser driving circuit and a pixel driving circuit, and the laser driving circuit serves as the electrical connection component; The display panel further includes: The driving chip provides a first driving signal to the first wiring through the laser driving circuit, and provides a second driving signal to the second wiring through the pixel driving circuit.

4. The display panel according to claim 2 or 3, characterized in that: The light emitting diode is an OLED formed on a side of the functional layer away from the substrate.

5. The display panel according to claim 4, characterized in that: The laser comprises a first electrode and a second electrode, both of which are located on a side of the laser close to the first pad; There are two first pads, and the first electrode and the second electrode are respectively located on one of the two first pads.

6. The display panel according to claim 4, characterized in that: The laser comprises a first electrode and a second electrode, which are respectively located on a side of the laser close to the first pad and a side of the laser far from the first pad; There is one first pad, and the first electrode is located on the first pad.

7. The display panel according to claim 2 or 3, characterized in that: The light emitting diode is a micro LED located on a side of the functional layer away from the substrate.

8. The display panel according to claim 7, characterized in that: The laser comprises a first electrode and a second electrode, both of which are located on a side of the laser close to the first pad; There are two first pads, and the first electrode and the second electrode are respectively located on one of the two first pads; The display panel further comprises a second pad located on a side of the functional layer away from the substrate; The micro LED includes a third electrode and a fourth electrode, both of which are located on a side of the micro LED close to the second pad; There are two second pads, and the third electrode and the fourth electrode are respectively located on one of the two second pads.

9. The display panel according to claim 7, characterized in that: The laser comprises a first electrode and a second electrode, which are respectively located on a side of the laser close to the pad and a side of the laser far from the pad; The first pad comprises one, and the first electrode is located on the first pad; The display panel further comprises a second pad located on a side of the functional layer away from the substrate; The micro LED includes a third electrode and a fourth electrode, both of which are located on a side of the micro LED close to the second pad; There are two second pads, and the third electrode and the fourth electrode are respectively located on one of the two second pads.

10. The display panel according to claim 1, characterized in that: The substrate is a silicon-based substrate; The display panel further comprises a CMOS driving circuit located in the functional layer, wherein the CMOS driving circuit comprises a first CMOS device and a second CMOS device; The light emitting diode is WOLED; The first CMOS device serves as at least a part of the electrical connection component, the first CMOS device provides the first drive signal to the first wiring, and the second CMOS device provides the second drive signal to the second wiring.

11. The display panel according to claim 10, characterized in that: The functional layer also includes a photodiode.

12. The display panel according to claim 1, characterized in that: The laser is a vertical cavity surface emitting laser.

13. The display panel according to claim 1, characterized in that: The display panel includes a display area and a laser area located in the display area, wherein the lasers are formed in the laser area in an array arrangement manner.

14. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 13.

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