Pixel module and display device

Abstract

The utility model provides a pixel module and a display device. The pixel module comprises a plurality of rows and columns of sub-pixels, a plurality of rows of scanning lines and a plurality of columns of data lines; two sub-pixels located in the nth row are arranged among the (2n-1) th row of scanning line, the (2n) th row of scanning line, the mth column of scanning line and the (m + 1) th column of scanning line; n and m are positive integers; the sub-pixels receive the data voltage under the control of the scanning signal; in the sub-pixels electrically connected with the (2n-1) th row of scanning lines and the sub-pixels electrically connected with the (2n + 1) th row of scanning lines, the sub-pixels electrically connected with the same column of data lines have the same color; among the sub-pixels electrically connected with the 2n row of scanning lines and the sub-pixels electrically connected with the 2n + 2 row of scanning lines, the sub-pixels electrically connected with the same column of data lines have the same color. When the pixel module provided by the embodiment of the utility model is in the double-gate mode, display color errors cannot occur when monochromatic pictures are displayed.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a pixel module and a display device. Background Art

[0002] When the existing pixel module is in DLG (Dual Gate) mode and displays a monochrome image, a display color error may occur. Utility Model Content

[0003] The main purpose of the utility model is to provide a pixel module and a display device to solve the problem that when the existing pixel module is in DLG (Dual Gate) mode and displays a monochrome picture, the display color error may occur.

[0004] In one aspect, an embodiment of the utility model provides a pixel module, including multiple rows and columns of sub-pixels, multiple rows of scan lines and multiple columns of data lines;

[0005] Two sub-pixels located in the nth row are arranged between the 2n-1th row scan line, the 2nth row scan line, the mth column scan line and the m+1th column scan line; n and m are positive integers;

[0006] The sub-pixels are electrically connected to a row of scan lines and a column of data lines respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0007] Among the sub-pixels electrically connected to the 2n-1th row of scan lines and the sub-pixels electrically connected to the 2n+1th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color;

[0008] Among the sub-pixels electrically connected to the 2n-th row of scan lines and the sub-pixels electrically connected to the 2n+2-th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color.

[0009] Optionally, the sub-pixels in the 4a-3th row and the 6b-5th column are electrically connected to the 8a-7th row scan lines and the 3b-2nd column data lines, respectively, and are used to receive the data voltage provided by the 3b-2nd column data lines under the control of the scan signals provided by the 8a-7th row scan lines;

[0010] The sub-pixels in the 4a-3 row and the 6b-4 column are electrically connected to the 8a-6 row scan lines and the 3b-2 column data lines, respectively, and are used to receive data voltages provided by the 3b-2 column data lines under the control of scan signals provided by the 8a-6 row scan lines;

[0011] The sub-pixels in the 4a-3 row and the 6b-3 column are electrically connected to the 8a-6 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-6 row scan line;

[0012] The sub-pixels in the 4a-3 row and the 6b-2 column are electrically connected to the 8a-7 row scan lines and the 3b-1 data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-7 row scan lines;

[0013] The sub-pixels in the 4a-3th row and the 6b-1th column are electrically connected to the 8a-6th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-6th row scan lines;

[0014] The sub-pixels in the 4a-3 rows and the 6b columns are electrically connected to the 8a-7 rows of scan lines and the 3b column of data lines, respectively, and are used to receive data voltages provided by the 3b column of data lines under the control of scan signals provided by the 8a-7 rows of scan lines;

[0015] a and b are positive integers.

[0016] Optionally, the sub-pixels in the 4a-2th row and the 6b-5th column are electrically connected to the 8a-5th row scan line and the 3b-2th column data line, respectively, and are used to receive the data voltage provided by the 3b-2th column data line under the control of the scan signal provided by the 8a-5th row scan line;

[0017] The sub-pixels in the 4a-2 row and the 6b-4 column are electrically connected to the 8a-4 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0018] The sub-pixels in the 4a-2 row and the 6b-3 column are electrically connected to the 8a-4 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0019] The sub-pixels in the 4a-2 row and the 6b-2 column are electrically connected to the 8a-5 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-5 row scan line;

[0020] The sub-pixels in the 4a-2th row and the 6b-1th column are electrically connected to the 8a-4th row scan line and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-4th row scan line;

[0021] The sub-pixels in the 4a-2th row and the 6bth column are electrically connected to the 8a-5th row scan lines and the 3bth column data lines respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-5th row scan lines.

[0022] Optionally, the sub-pixels in the 4a-1th row and the 6b-5th column are electrically connected to the 8a-3th row scan line and the 3b-1th column data line, respectively, and are used to receive a data voltage provided by the 3b-1th column data line under the control of a scan signal provided by the 8a-3th row scan line;

[0023] The sub-pixels in the 4a-1 row and the 6b-4 column are electrically connected to the 8a-2 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0024] The sub-pixels in the 4a-1 row and the 6b-3 column are electrically connected to the 8a-2 row scan line and the 3b column data line, respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0025] The sub-pixels in the 4a-1 row and the 6b-2 column are electrically connected to the 8a-3 row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-3 row scan line;

[0026] The sub-pixel in the 4a-1 row and the 6b-1 column is electrically connected to the 8a-2 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0027] The sub-pixel in the 4a-1 row and the 6b column is electrically connected to the 8a-3 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-3 row scan line.

[0028] Optionally, the sub-pixels in the 4a row and the 6b-5 columns are electrically connected to the 8a-1 row scan line and the 3b-1 column data line, respectively, and are configured to receive a data voltage provided by the 3b-1 column data line under the control of a scan signal provided by the 8a-1 row scan line;

[0029] The sub-pixels in the 4a row and the 6b-4 column are electrically connected to the 8a row scan line and the 3b-1 column data line respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a row scan line;

[0030] The sub-pixels in the 4a row and the 6b-3 columns are electrically connected to the 8a row scan line and the 3b column data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a row scan line;

[0031] The sub-pixels in the 4a row and the 6b-2 column are electrically connected to the 8a-1 row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0032] The sub-pixels in the 4a row and the 6b-1 column are electrically connected to the 8a row scan line and the 3b+1 column data line respectively, and are used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a row scan line;

[0033] The sub-pixel in the 4a row and 6b column is electrically connected to the 8a-1 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-1 row scan line.

[0034] Optionally, the sub-pixels in the 4a-3th row and the 6b-5th column are electrically connected to the 8a-7th row scan lines and the 3b-2nd column data lines, respectively, and are used to receive the data voltage provided by the 3b-2nd column data lines under the control of the scan signals provided by the 8a-7th row scan lines;

[0035] The sub-pixels in the 4a-3 row and the 6b-4 column are electrically connected to the 8a-6 row scan lines and the 3b-2 column data lines, respectively, and are used to receive data voltages provided by the 3b-2 column data lines under the control of scan signals provided by the 8a-6 row scan lines;

[0036] The sub-pixels in the 4a-3 row and the 6b-3 column are electrically connected to the 8a-7 row scan lines and the 3b-1 column data lines, respectively, and are used to receive data voltages provided by the 3b-1 column data lines under the control of scan signals provided by the 8a-7 row scan lines;

[0037] The sub-pixels in the 4a-3 row and the 6b-2 column are electrically connected to the 8a-6 row scan lines and the 3b-1 data lines, respectively, and are used to receive data voltages provided by the 3b-1 column data lines under the control of scan signals provided by the 8a-6 row scan lines;

[0038] The sub-pixels in the 4a-3th row and the 6b-1th column are electrically connected to the 8a-7th row scan lines and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-7th row scan lines;

[0039] The sub-pixels in the 4a-3rd row and the 6bth column are electrically connected to the 8a-6th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-6th row scan lines;

[0040] a and b are positive integers.

[0041] Optionally, the sub-pixels in the 4a-2th row and the 6b-5th column are electrically connected to the 8a-5th row scan line and the 3b-2th column data line, respectively, and are used to receive the data voltage provided by the 3b-2th column data line under the control of the scan signal provided by the 8a-5th row scan line;

[0042] The sub-pixels in the 4a-2 row and the 6b-4 column are electrically connected to the 8a-4 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0043] The sub-pixels in the 4a-2 row and the 6b-3 column are electrically connected to the 8a-5 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-5 row scan line;

[0044] The sub-pixels in the 4a-2 row and the 6b-2 column are electrically connected to the 8a-4 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0045] The sub-pixels in the 4a-2th row and the 6b-1th column are electrically connected to the 8a-5th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-5th row scan lines;

[0046] The sub-pixels in the 4a-2 row and the 6b column are electrically connected to the 8a-4 row scan line and the 3b column data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-4 row scan line.

[0047] Optionally, the sub-pixels in the 4a-1th row and the 6b-5th column are electrically connected to the 8a-3th row scan line and the 3b-1th column data line, respectively, and are used to receive a data voltage provided by the 3b-1th column data line under the control of a scan signal provided by the 8a-3th row scan line;

[0048] The sub-pixels in the 4a-1 row and the 6b-4 column are electrically connected to the 8a-2 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0049] The sub-pixels in the 4a-1th row and the 6b-3th column are electrically connected to the 8a-3th row scan line and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-3th row scan line;

[0050] The sub-pixels in the 4a-1th row and the 6b-2th column are electrically connected to the 8a-2th row scan line and the 3bth data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-2th row scan line;

[0051] The sub-pixel in the 4a-1 row and the 6b-1 column is electrically connected to the 8a-3 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-3 row scan line;

[0052] The sub-pixel in the 4a-1 row and the 6b column is electrically connected to the 8a-2 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-2 row scan line.

[0053] Optionally, the sub-pixels in the 4a row and the 6b-5 columns are electrically connected to the 8a-1 row scan line and the 3b-1 column data line, respectively, and are configured to receive a data voltage provided by the 3b-1 column data line under the control of a scan signal provided by the 8a-1 row scan line;

[0054] The sub-pixels in the 4a row and the 6b-4 column are electrically connected to the 8a row scan line and the 3b-1 column data line respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a row scan line;

[0055] The sub-pixels in the 4a row and the 6b-3 column are electrically connected to the 8a-1 row scan line and the 3b column data line, respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0056] The sub-pixels in the 4a row and the 6b-2 column are electrically connected to the 8a row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a row scan line;

[0057] The sub-pixel in the 4a row and the 6b-1 column is electrically connected to the 8a-1 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0058] The sub-pixel in row 4a and column 6b is electrically connected to the scan line in row 8a and the data line in column 3b+1 respectively, and is used to receive the data voltage provided by the data line in column 3b+1 under the control of the scan signal provided by the scan line in row 8a.

[0059] Optionally, the sub-pixels located in the 3b-2 column have a first color, the sub-pixels located in the 3b-1 column have a second color, and the sub-pixels located in the 3b column have a second color.

[0060] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned pixel module.

[0061] Optionally, the display device described in at least one embodiment of the present utility model further includes a driving module; the driving module includes eight clock signal lines and a multi-stage driving circuit;

[0062] The 8d-7th level driving circuit is electrically connected to the first clock signal line, the 8d-6th level driving circuit is electrically connected to the second clock signal line, the 8d-5th level driving circuit is electrically connected to the third clock signal line, the 8d-4th level driving circuit is electrically connected to the fourth clock signal line, the 8d-3th level driving circuit is electrically connected to the fifth clock signal line, the 8d-2th level driving circuit is electrically connected to the sixth clock signal line, the 8d-1th level driving circuit is electrically connected to the seventh clock signal line, and the 8d-level driving circuit is electrically connected to the eighth clock signal line; d is a positive integer;

[0063] The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+4-th driving circuit, and the driving signal output terminal of the e+4-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

[0064] Optionally, the display device described in at least one embodiment of the present utility model further includes a driving module; the driving module includes twelve clock signal lines and a multi-stage driving circuit;

[0065] The 12d-11th level driving circuit is electrically connected to the first clock signal line, the 12d-10th level driving circuit is electrically connected to the second clock signal line, the 12d-9th level driving circuit is electrically connected to the third clock signal line, the 12d-8th level driving circuit is electrically connected to the fourth clock signal line, the 12d-7th level driving circuit is electrically connected to the fifth clock signal line, the 12d-6th level driving circuit is electrically connected to the sixth clock signal line, the 12d-5th level driving circuit is electrically connected to the seventh clock signal line, the 12d-4th level driving circuit is electrically connected to the eighth clock signal line, the 12d-3th level driving circuit is electrically connected to the ninth clock signal line, the 12d-2th level driving circuit is electrically connected to the tenth clock signal line, the 12d-1th level driving circuit is electrically connected to the eleventh clock signal line, and the 12d-1th level driving circuit is electrically connected to the twelfth clock signal line; d is a positive integer;

[0066] The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+4-th driving circuit, and the driving signal output terminal of the e+4-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

[0067] Optionally, the display device described in at least one embodiment of the present utility model further includes a driving module; the driving module includes sixteen clock signal lines and a multi-stage driving circuit;

[0068] The 16d-15th level driving circuit is electrically connected to the first clock signal line, the 16d-14th level driving circuit is electrically connected to the second clock signal line, the 16d-13th level driving circuit is electrically connected to the third clock signal line, the 16d-12th level driving circuit is electrically connected to the fourth clock signal line, the 16d-11th level driving circuit is electrically connected to the fifth clock signal line, the 16d-19th level driving circuit is electrically connected to the sixth clock signal line, the 16d-9th level driving circuit is electrically connected to the seventh clock signal line, the 16d-8th level driving circuit is electrically connected to the eighth clock signal line, and the 16d-10th level driving circuit is electrically connected to the eighth clock signal line. The 6d-7 level driving circuit is electrically connected to the ninth clock signal line, the 16d-6 level driving circuit is electrically connected to the tenth clock signal line, the 16d-5 level driving circuit is electrically connected to the eleventh clock signal line, the 16d-4 level driving circuit is electrically connected to the twelfth clock signal line, the 16d-3 level driving circuit is electrically connected to the thirteenth clock signal line, the 16d-2 level driving circuit is electrically connected to the fourteenth clock signal line, the 16d-1 level driving circuit is electrically connected to the fifteenth clock signal line, and the 16d level driving circuit is electrically connected to the sixteenth clock signal line; d is a positive integer;

[0069] The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+8-th driving circuit, and the driving signal output terminal of the e+8-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

[0070] In the pixel module described in the embodiment of the present invention, among the sub-pixels electrically connected to the 2n-1th row of scan lines and the sub-pixels electrically connected to the 2n+1th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color, so that when the 2n-1th row of scan lines and the 2n+1th row of scan lines are turned on at the same time, the same column of data lines provides corresponding data voltages to the sub-pixels with the same color, so that when the pixel module is in DLG (Dual Gate) mode, when displaying a monochrome picture, no display color error will occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1A and Figure 1B is a structural diagram of a pixel module according to at least one embodiment of the present utility model;

[0072] Figure 2 yes Figure 1A A working timing diagram of at least one embodiment of the pixel module shown;

[0073] Figure 3 yes Figure 1A A schematic diagram of at least one embodiment of the pixel module shown when displaying a red image;

[0074] Figure 4 yes Figure 1A A schematic diagram of at least one embodiment of the pixel module when displaying a green image;

[0075] Figure 5 yes Figure 1A A schematic diagram of at least one embodiment of the pixel module when displaying a blue image;

[0076] Figure 6 yes Figure 1A A schematic diagram of polarity display of at least one embodiment of the pixel module shown;

[0077] Fig. 7A and Figure 7B is a structural diagram of a pixel module according to at least one embodiment of the present utility model;

[0078] Figure 8 yes Fig. 7A A working timing diagram of at least one embodiment of the pixel module shown;

[0079] Fig. 9 It is a structural diagram of at least one embodiment of a driving module in a display device according to the utility model;

[0080] Fig.10 It is a structural diagram of at least one embodiment of a driving module in a display device according to the utility model;

[0081] Fig.11It is a structural diagram of at least one embodiment of a driving module in a display device described in the utility model. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0083] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.

[0084] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0085] The pixel module described in the embodiment of the utility model includes multiple rows and columns of sub-pixels, multiple rows of scan lines and multiple columns of data lines;

[0086] Two sub-pixels located in the nth row are arranged between the 2n-1th row scan line, the 2nth row scan line, the mth column scan line and the m+1th column scan line; n and m are positive integers;

[0087] The sub-pixels are electrically connected to a row of scan lines and a column of data lines respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0088] Among the sub-pixels electrically connected to the 2n-1th row of scan lines and the sub-pixels electrically connected to the 2n+1th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color;

[0089] Among the sub-pixels electrically connected to the 2n-th row of scan lines and the sub-pixels electrically connected to the 2n+2-th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color.

[0090] In the pixel module described in the embodiment of the present invention, among the sub-pixels electrically connected to the 2n-1th row of scan lines and the sub-pixels electrically connected to the 2n+1th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color, so that when the 2n-1th row of scan lines and the 2n+1th row of scan lines are turned on at the same time, the same column of data lines provides corresponding data voltages to the sub-pixels with the same color, so that when the pixel module is in DLG (Dual Gate) mode, when displaying a monochrome picture, no display color error will occur.

[0091] According to a specific embodiment, the sub-pixels in the 4a-3 rows and the 6b-5 columns are electrically connected to the 8a-7 rows of scan lines and the 3b-2 columns of data lines, respectively, and are used to receive the data voltage provided by the 3b-2 columns of data lines under the control of the scan signals provided by the 8a-7 rows of scan lines;

[0092] The sub-pixels in the 4a-3 row and the 6b-4 column are electrically connected to the 8a-6 row scan lines and the 3b-2 column data lines, respectively, and are used to receive data voltages provided by the 3b-2 column data lines under the control of scan signals provided by the 8a-6 row scan lines;

[0093] The sub-pixels in the 4a-3 row and the 6b-3 column are electrically connected to the 8a-6 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-6 row scan line;

[0094] The sub-pixels in the 4a-3 row and the 6b-2 column are electrically connected to the 8a-7 row scan lines and the 3b-1 data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-7 row scan lines;

[0095] The sub-pixels in the 4a-3th row and the 6b-1th column are electrically connected to the 8a-6th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-6th row scan lines;

[0096] The sub-pixels in the 4a-3 rows and the 6b columns are electrically connected to the 8a-7 rows of scan lines and the 3b column of data lines, respectively, and are used to receive data voltages provided by the 3b column of data lines under the control of scan signals provided by the 8a-7 rows of scan lines;

[0097] a and b are positive integers.

[0098] In at least one embodiment of the present invention, the sub-pixels in the 4a-2th row and the 6b-5th column are electrically connected to the 8a-5th row scan line and the 3b-2th column data line, respectively, and are used to receive the data voltage provided by the 3b-2th column data line under the control of the scan signal provided by the 8a-5th row scan line;

[0099] The sub-pixels in the 4a-2 row and the 6b-4 column are electrically connected to the 8a-4 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0100] The sub-pixels in the 4a-2 row and the 6b-3 column are electrically connected to the 8a-4 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0101] The sub-pixels in the 4a-2 row and the 6b-2 column are electrically connected to the 8a-5 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-5 row scan line;

[0102] The sub-pixels in the 4a-2th row and the 6b-1th column are electrically connected to the 8a-4th row scan line and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-4th row scan line;

[0103] The sub-pixels in the 4a-2th row and the 6bth column are electrically connected to the 8a-5th row scan lines and the 3bth column data lines respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-5th row scan lines.

[0104] In at least one embodiment of the present invention, the sub-pixels in the 4a-1th row and the 6b-5th column are electrically connected to the 8a-3th row scan line and the 3b-1th column data line, respectively, and are used to receive the data voltage provided by the 3b-1th column data line under the control of the scan signal provided by the 8a-3th row scan line;

[0105] The sub-pixels in the 4a-1 row and the 6b-4 column are electrically connected to the 8a-2 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0106] The sub-pixels in the 4a-1 row and the 6b-3 column are electrically connected to the 8a-2 row scan line and the 3b column data line, respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0107] The sub-pixels in the 4a-1 row and the 6b-2 column are electrically connected to the 8a-3 row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-3 row scan line;

[0108] The sub-pixel in the 4a-1 row and the 6b-1 column is electrically connected to the 8a-2 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0109] The sub-pixel in the 4a-1 row and the 6b column is electrically connected to the 8a-3 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-3 row scan line.

[0110] In at least one embodiment of the present invention, the sub-pixels in the 4a row and the 6b-5 columns are electrically connected to the 8a-1 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0111] The sub-pixels in the 4a row and the 6b-4 column are electrically connected to the 8a row scan line and the 3b-1 column data line respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a row scan line;

[0112] The sub-pixels in the 4a row and the 6b-3 columns are electrically connected to the 8a row scan line and the 3b column data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a row scan line;

[0113] The sub-pixels in the 4a row and the 6b-2 column are electrically connected to the 8a-1 row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0114] The sub-pixels in the 4a row and the 6b-1 column are electrically connected to the 8a row scan line and the 3b+1 column data line respectively, and are used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a row scan line;

[0115] The sub-pixel in the 4a row and 6b column is electrically connected to the 8a-1 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-1 row scan line.

[0116] Figure 1A The figure shows four rows and twelve columns of sub-pixels included in the pixel module according to at least one embodiment of the present utility model;

[0117] like Figure 1A As shown, the first row and first column sub-pixel P11 is electrically connected to the first row scan line G1 and the first column data line DL1 respectively, and is used to receive the data voltage provided by the first column data line DL1 under the control of the scan signal provided by the first row scan line G1;

[0118] The first row and second column sub-pixel P12 is electrically connected to the second row scan line G2 and the first column data line DL1 respectively, and is used to receive the data voltage provided by the first column data line DL1 under the control of the scan signal provided by the second row scan line G2;

[0119] The sub-pixel P13 in the first row and the third column is electrically connected to the second row scan line G2 and the second column data line DL2 respectively, and is used to receive a data voltage provided by the second column data line DL2 under the control of a scan signal provided by the second row scan line G2;

[0120] The first row and fourth column sub-pixel P14 is electrically connected to the first row scan line G1 and the second column data line DL2 respectively, and is used to receive a data voltage provided by the second column data line DL2 under the control of the scan signal provided by the first row scan line G1;

[0121] The sub-pixel P15 in the first row and the fifth column is electrically connected to the second row scan line G2 and the third column data line DL3 respectively, and is used to receive a data voltage provided by the third column data line DL3 under the control of the scan signal provided by the second row scan line G2;

[0122] The sub-pixel in the first row and the sixth column is electrically connected to the first row scan line G1 and the third column data line DL3 respectively, and is used to receive a data voltage provided by the third column data line DL3 under the control of the scan signal provided by the first row scan line G1;

[0123] The sub-pixel P17 in the first row and the seventh column is electrically connected to the first row scan line G1 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the first row scan line G1;

[0124] The sub-pixel P18 in the first row and the eighth column is electrically connected to the second row scan line G2 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the second row scan line G2;

[0125] The sub-pixel P19 in the first row and the ninth column is electrically connected to the scan line G2 in the second row and the data line DL5 in the fifth column, respectively, and is used to receive a data voltage provided by the data line DL5 in the fifth column under the control of the scan signal provided by the scan line G2 in the second row;

[0126] The sub-pixel P110 of the first row and the tenth column is electrically connected to the first row scan line G1 and the fifth column data line DL5 respectively, and is used to receive the data voltage provided by the fifth column data line DL5 under the control of the scan signal provided by the first row scan line G1;

[0127] The sub-pixel P111 in the first row and the eleventh column is electrically connected to the second row scan line G2 and the sixth column data line DL6 respectively, and is used to receive a data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the second row scan line G2;

[0128] The sub-pixels in the first row and the twelfth column are electrically connected to the first row scan line G1 and the sixth column data line DL6 respectively, and are used to receive the data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the first row scan line G1;

[0129] The sub-pixel P21 in the second row and the first column is electrically connected to the scan line G3 in the third row and the data line DL1 in the first column, respectively, and is used to receive the data voltage provided by the data line DL1 in the first column under the control of the scan signal provided by the scan line G3 in the third row;

[0130] The sub-pixel P22 in the second row and the second column is electrically connected to the scan line G4 in the fourth row and the data line DL1 in the first column, respectively, and is used to receive the data voltage provided by the data line DL1 in the first column under the control of the scan signal provided by the scan line G4 in the fourth row;

[0131] The sub-pixel P23 in the second row and the fourth column is electrically connected to the scan line G4 in the fourth row and the data line DL2 in the second column, respectively, and is used for receiving a data voltage provided by the data line DL2 in the second column under the control of a scan signal provided by the scan line G4 in the fourth row;

[0132] The sub-pixel P24 in the second row and the fourth column is electrically connected to the scan line G3 in the third row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G3 in the third row;

[0133] The sub-pixel P25 in the second row and the fifth column is electrically connected to the scan line G4 in the fourth row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G4 in the fourth row;

[0134] The sub-pixel P26 in the second row and the sixth column is electrically connected to the scan line G3 in the third row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G3 in the third row;

[0135] The sub-pixel P27 in the second row and the seventh column is electrically connected to the scan line G3 in the third row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G3 in the third row;

[0136] The sub-pixel P28 in the second row and the eighth column is electrically connected to the scan line G4 in the fourth row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G4 in the fourth row;

[0137] The sub-pixel P29 in the second row and the ninth column is electrically connected to the scan line G4 in the fourth row and the data line DL5 in the fifth column, respectively, and is used to receive a data voltage provided by the data line DL5 in the fifth column under the control of a scan signal provided by the scan line G4 in the fourth row;

[0138] The sub-pixel P210 in the second row and the tenth column is electrically connected to the third row scan line G3 and the fifth column data line DL5 respectively, and is used to receive a data voltage provided by the fifth column data line DL5 under the control of a scan signal provided by the third row scan line G3;

[0139] The sub-pixel P211 in the second row and the eleventh column is electrically connected to the fourth row scan line G4 and the sixth column data line DL6 respectively, and is used to receive the data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the fourth row scan line G4;

[0140] The sub-pixel P212 in the second row and the twelfth column is electrically connected to the scan line G3 in the third row and the data line DL6 in the sixth column, respectively, and is used to receive a data voltage provided by the data line DL6 in the sixth column under the control of a scan signal provided by the scan line G3 in the third row;

[0141] The sub-pixel P31 in the third row and the first column is electrically connected to the scan line G5 in the fifth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G5 in the fifth row;

[0142] The sub-pixel P32 in the third row and the second column is electrically connected to the scan line G6 in the sixth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G6 in the sixth row;

[0143] The sub-pixel P33 in the third row and the third column is electrically connected to the scan line G6 in the sixth row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0144] The sub-pixel P34 in the third row and the fourth column is electrically connected to the scan line G5 in the fifth row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G5 in the fifth row;

[0145] The sub-pixel P35 in the third row and the fifth column is electrically connected to the scan line G6 in the sixth row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0146] The sub-pixels in the third row and the sixth column are electrically connected to the fifth row scan line G5 and the fourth column data line DL4 respectively, and are used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the fifth row scan line G5;

[0147] The sub-pixel P37 in the third row and the seventh column is electrically connected to the fifth row scan line G5 and the fifth column data line DL5 respectively, and is used to receive a data voltage provided by the fifth column data line DL5 under the control of a scan signal provided by the fifth row scan line G5;

[0148] The sub-pixel P38 in the third row and the eighth column is electrically connected to the scan line G6 in the sixth row and the data line DL5 in the fifth column, respectively, and is used to receive a data voltage provided by the data line DL5 in the fifth column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0149] The sub-pixel P39 in the third row and the ninth column is electrically connected to the scan line G6 in the sixth row and the data line DL6 in the sixth column, respectively, and is used to receive a data voltage provided by the data line DL6 in the sixth column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0150] The sub-pixel P310 in the third row and the tenth column is electrically connected to the fifth row scan line G5 and the sixth column data line DL6 respectively, and is used to receive a data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the fifth row scan line G5;

[0151] The sub-pixel P311 in the third row and the eleventh column is electrically connected to the sixth row scan line G6 and the seventh column data line DL7 respectively, and is used to receive a data voltage provided by the seventh column data line DL7 under the control of a scan signal provided by the sixth row scan line G6;

[0152] The sub-pixels in the third row and twelfth column are electrically connected to the fifth row scan line G5 and the seventh column data line DL7 respectively, and are used to receive the data voltage provided by the seventh column data line DL7 under the control of the scan signal provided by the fifth row scan line G5;

[0153] The sub-pixel P41 in the first column of the fourth row is electrically connected to the scan line G7 in the seventh row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the second data line DL2 under the control of a scan signal provided by the scan line G7 in the seventh row;

[0154] The sub-pixel P42 in the fourth row and the second column is electrically connected to the scan line G8 in the eighth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G8 in the eighth row;

[0155] The sub-pixel P43 in the fourth row and the third column is electrically connected to the eighth row scan line G8 and the third column data line DL3 respectively, and is used to receive the data voltage provided by the third column data line DL3 under the control of the scan signal provided by the eighth row scan line G8;

[0156] The sub-pixel P44 in the fourth row and the fourth column is electrically connected to the scan line G7 in the seventh row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0157] The sub-pixel P45 in the fourth row and the fifth column is electrically connected to the eighth row scan line G8 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the eighth row scan line G8;

[0158] The sub-pixel P46 in the fourth row and the sixth column is electrically connected to the scan line G7 in the seventh row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0159] The sub-pixel P47 in the fourth row and the seventh column is electrically connected to the scan line G7 in the seventh row and the data line DL3 in the fifth column, and is used to receive the data voltage provided by the data line DL5 in the fifth column under the control of the scan signal provided by the scan line G7 in the seventh row;

[0160] The sub-pixel P48 in the fourth row and the eighth column is electrically connected to the eighth row scan line G8 and the fifth column data line DL5 respectively, and is used to receive the data voltage provided by the fifth column data line DL5 under the control of the scan signal provided by the eighth row scan line G8;

[0161] The sub-pixel P49 in the fourth row and the ninth column is electrically connected to the eighth row scan line G8 and the sixth column data line DL6 respectively, and is used to receive the data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the eighth row scan line G8;

[0162] The sub-pixel P410 in the fourth row and the tenth column is electrically connected to the seventh row scan line G7 and the sixth column data line DL6 respectively, and is used to receive the data voltage provided by the third column data line DL3 under the control of the scan signal provided by the seventh row scan line G7;

[0163] The sub-pixel P411 in the fourth row and the eleventh column is electrically connected to the eighth row scan line G8 and the seventh column data line DL7 respectively, and is used to receive the data voltage provided by the seventh column data line DL11 under the control of the scan signal provided by the eighth row scan line G8;

[0164] The sub-pixel P412 in the fourth row and the twelfth column is electrically connected to the seventh row scan line G7 and the seventh column data line DL7 respectively, and is used to receive a data voltage provided by the seventh column data line DL7 under the control of a scan signal provided by the seventh row scan line G7.

[0165] exist Figure 1A In at least one embodiment shown, P11, P21, P31 and P41 are all red sub-pixels, P12, P22, P32 and P42 are all green sub-pixels, P13, P23, P33 and P43 are all blue sub-pixels; P14, P24, P34 and P44 are all red sub-pixels, P15, P25, P35 and P45 are all green sub-pixels, and P16, P26, P36 and P46 are all blue sub-pixels; P17, P27, P37 and P47 are all red sub-pixels, P18, P28, P38 and P48 are all green sub-pixels, P19, P29, P39 and P49 are all blue sub-pixels; P110, P210, P310 and P410 are all red sub-pixels, P111, P211, P311 and P411 are all green sub-pixels, P112, P212, P312 and P412 are all blue sub-pixels.

[0166] exist Figure 1AIn at least one embodiment shown, P11 and P12 are disposed between G1, G2, DL1, and DL2, P13 and P14 are disposed between G1, G2, DL2, and DL3, P15 and P16 are disposed between G1, G2, DL3, and DL4, P17 and P18 are disposed between G1, G2, DL4, and DL5, P19 and P110 are disposed between G1, G2, DL5, and DL6, and P111 and P112 are disposed between G1, G2, DL6, and DL7;

[0167] P21 and P22 are arranged between G3, G4, DL1 and DL2, P23 and P24 are arranged between G3, G4, DL2 and DL3, P25 and P26 are arranged between G3, G4, DL3 and DL4, P27 and P28 are arranged between G3, G4, DL4 and DL5, P29 and P210 are arranged between G3, G4, DL5 and DL6, P211 and P212 are arranged between G3, G4, DL6 and DL7;

[0168] P31 and P32 are arranged between G5, G6, DL1 and DL2, P33 and P34 are arranged between G5, G6, DL2 and DL3, P35 and P36 are arranged between G5, G6, DL3 and DL4, P37 and P38 are arranged between G5, G6, DL4 and DL5, P39 and P310 are arranged between G5, G6, DL5 and DL6, P311 and P312 are arranged between G5, G6, DL6 and DL7;

[0169] P41 and P42 are arranged between G7, G8, DL1 and DL2, P43 and P44 are arranged between G7, G8, DL2 and DL3, P45 and P46 are arranged between G7, G8, DL3 and DL4, P47 and P48 are arranged between G7, G8, DL4 and DL5, P49 and P410 are arranged between G7, G8, DL5 and DL6, and P411 and P412 are arranged between G7, G8, DL6 and DL7.

[0170] like Figure 1B As shown, in Figure 1ABased on at least one embodiment of the pixel module shown, the first row and the first column sub-pixel includes the first row and the first column pixel electrode PJ11 and the first row and the first column thin film transistor T11; the first row and the second column sub-pixel includes the first row and the second column pixel electrode PJ12 and the first row and the second column thin film transistor T12; the first row and the third column sub-pixel includes the first row and the third column pixel electrode PJ13 and the first row and the third column thin film transistor T13; the first row and the fourth column sub-pixel includes the first row and the fourth column pixel electrode PJ14 and the first row and the fourth column thin film transistor T14; the first row and the fifth column sub-pixel includes the first row and the fifth column pixel electrode PJ15 and the first row and the fifth column thin film transistor T15; the first row and the sixth column sub-pixel includes the first row and the sixth column pixel electrode PJ16 and the first row and the sixth column thin film transistor T16; the first row and the seventh column sub-pixel includes the first row and the seventh column pixel electrode PJ17 and the first row and the seventh column thin film transistor T17; the first row and the eighth column sub-pixel includes the first row and the eighth column pixel electrode PJ18 and the first row and the eighth column thin film transistor T18; the first row and the ninth column sub-pixel includes the first row and the ninth column pixel electrode PJ19 and the first row and the ninth column thin film transistor T19; the first row and the tenth column sub-pixel includes the first row and the tenth column pixel electrode PJ110 and the first row and the tenth column thin film transistor T110; the first row and the eleventh column sub-pixel includes the first row and the eleventh column pixel electrode PJ111 and the first row and the eleventh column thin film transistor T111; the first row and the twelfth column sub-pixel includes the first row and the twelfth column pixel electrode PJ112 and the first row and the twelfth column thin film transistor T112;

[0171] The second row and first column sub-pixel includes a second row and first column pixel electrode PJ21 and a second row and first column thin film transistor T21; the second row and second column sub-pixel includes a second row and second column pixel electrode PJ22 and a second row and second column thin film transistor T22; the second row and third column sub-pixel includes a second row and third column pixel electrode PJ23 and a second row and third column thin film transistor T23; the second row and fourth column sub-pixel includes a second row and fourth column pixel electrode PJ24 and a second row and fourth column thin film transistor T24; the second row and fifth column sub-pixel includes a second row and fifth column pixel electrode PJ25 and a second row and fifth column thin film transistor T25; the second row and sixth column sub-pixel includes a second row and sixth column pixel electrode PJ26 and a second row and sixth column thin film transistor T26; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ27 and a second row and sixth column thin film transistor T28; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ28 and a second row and sixth column thin film transistor T29; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ29 and a second row and sixth column thin film transistor T21; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ21 and a second row and sixth column thin film transistor T22; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ23 and a second row and third column thin film transistor T23; the second row and fourth column sub-pixel includes a second row and fourth column pixel electrode PJ24 and a second row and fourth column thin film transistor T24; the second row and fifth column sub-pixel includes a second row and fifth column pixel electrode PJ25 and a second row and fifth column thin film transistor T25; the second row and sixth column sub-pixel includes a second row and sixth The sub-pixel includes a pixel electrode PJ27 in the second row and the seventh column and a thin film transistor T27 in the second row and the seventh column; the sub-pixel in the second row and the eighth column includes a pixel electrode PJ28 in the second row and the eighth column and a thin film transistor T28 in the second row and the eighth column; the sub-pixel in the second row and the ninth column includes a pixel electrode PJ29 in the second row and the ninth column and a thin film transistor T29 in the second row and the ninth column; the sub-pixel in the second row and the tenth column includes a pixel electrode PJ210 in the second row and the tenth column and a thin film transistor T210 in the second row and the tenth column; the sub-pixel in the second row and the eleventh column includes a pixel electrode PJ211 in the second row and the eleventh column and a thin film transistor T211 in the second row and the eleventh column; the sub-pixel in the second row and the twelfth column includes a pixel electrode PJ212 in the second row and the twelfth column and a thin film transistor T212 in the second row and the twelfth column;

[0172] The third row and first column sub-pixel includes a third row and first column pixel electrode PJ31 and a third row and first column thin film transistor T31; the third row and second column sub-pixel includes a third row and second column pixel electrode PJ32 and a third row and second column thin film transistor T32; the third row and third column sub-pixel includes a third row and third column pixel electrode PJ33 and a third row and third column thin film transistor T33; the third row and fourth column sub-pixel includes a third row and fourth column pixel electrode PJ34 and a third row and fourth column thin film transistor T34; the third row and fifth column sub-pixel includes a third row and fifth column pixel electrode PJ35 and a third row and fifth column thin film transistor T35; the third row and sixth column sub-pixel includes a third row and sixth column pixel electrode PJ36 and a third row and sixth column thin film transistor T36; the third row and seventh column sub-pixel includes a third row and sixth column pixel electrode PJ37 and a third row and sixth column thin film transistor T37; the third row and seventh column sub-pixel includes a third row and sixth column pixel electrode PJ38 and a third row and sixth column thin film transistor T39; the third row and seventh column sub-pixel includes a third row and seventh column pixel electrode PJ39 and a third row and sixth column thin film transistor T31; the third row and seventh column sub-pixel includes a third row and seventh column pixel electrode PJ31 and a third row and sixth column thin film transistor T33; the third row and seventh column sub-pixel includes a third row and seventh column pixel electrode PJ34 and a third row and fourth column thin film transistor T34; the third row and fifth column sub-pixel includes a third row and fifth column pixel electrode PJ35 and a third row and fifth column thin film transistor T35; the third row and sixth column sub-pixel includes a third row and sixth column pixel electrode PJ36 and a third row and sixth column thin film transistor T36; the third row and seventh column sub-pixel includes a third row and sixth The sub-pixel includes the pixel electrode PJ37 in the third row and the seventh column and the thin film transistor T37 in the third row and the seventh column; the sub-pixel in the third row and the eighth column includes the pixel electrode PJ38 in the third row and the eighth column and the thin film transistor T38 in the third row and the eighth column; the sub-pixel in the third row and the ninth column includes the pixel electrode PJ39 in the third row and the ninth column and the thin film transistor T39 in the third row and the ninth column; the sub-pixel in the third row and the tenth column includes the pixel electrode PJ310 in the third row and the tenth column and the thin film transistor T310 in the third row and the tenth column; the sub-pixel in the third row and the eleventh column includes the pixel electrode PJ311 in the third row and the eleventh column and the thin film transistor T311 in the third row and the eleventh column; the sub-pixel in the third row and the twelfth column includes the pixel electrode PJ312 in the third row and the twelfth column and the thin film transistor T312 in the third row and the twelfth column;

[0173] The fourth row and the first column sub-pixel includes the fourth row and the first column pixel electrode PJ41 and the fourth row and the first column thin film transistor T41; the fourth row and the second column sub-pixel includes the fourth row and the second column pixel electrode PJ42 and the fourth row and the second column thin film transistor T42; the fourth row and the third column sub-pixel includes the fourth row and the third column pixel electrode PJ43 and the fourth row and the third column thin film transistor T43; the fourth row and the fourth column sub-pixel includes the fourth row and the fourth column pixel electrode PJ44 and the fourth row and the fourth column thin film transistor T44; the fourth row and the fifth column sub-pixel includes the fourth row and the fifth column pixel electrode PJ45 and the fourth row and the fifth column thin film transistor T45; the fourth row and the sixth column sub-pixel includes the fourth row and the sixth column pixel electrode PJ46 and the fourth row and the sixth column thin film transistor T46; the fourth row and the seventh column sub-pixel includes the fourth row and the sixth column pixel electrode PJ47 and the fourth row and the sixth column thin film transistor T47; The subpixel includes the pixel electrode PJ47 in the fourth row and the seventh column and the thin film transistor T47 in the fourth row and the seventh column; the subpixel in the fourth row and the eighth column includes the pixel electrode PJ48 in the fourth row and the eighth column and the thin film transistor T48 in the fourth row and the eighth column; the subpixel in the fourth row and the ninth column includes the pixel electrode PJ49 in the fourth row and the ninth column and the thin film transistor T49 in the fourth row and the ninth column; the subpixel in the fourth row and the tenth column includes the pixel electrode PJ410 in the fourth row and the tenth column and the thin film transistor T410 in the fourth row and the tenth column; the subpixel in the fourth row and the eleventh column includes the pixel electrode PJ411 in the fourth row and the eleventh column and the thin film transistor T411 in the fourth row and the twelfth column; the subpixel in the fourth row and the twelfth column includes the pixel electrode PJ412 in the fourth row and the twelfth column and the thin film transistor T412 in the fourth row and the twelfth column.

[0174] In at least one embodiment of the present invention, in a sub-pixel, a gate of the thin film transistor is electrically connected to a corresponding row gate line, a first electrode of the thin film transistor is electrically connected to a corresponding pixel electrode, and a second electrode of the thin film transistor is electrically connected to a corresponding column data line.

[0175] like Figure 2 As shown, the utility model Figure 1A When at least one embodiment of the pixel module shown is in operation, a display cycle may include a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4 which are arranged in sequence;

[0176] In the first stage S1, G1 and G3 both provide high voltage signals, P11 is connected to the data voltage on DL1, P14 is connected to the data voltage on DL2, P16 is connected to the data voltage on DL3, P17 is connected to the data voltage on DL4, P110 is connected to the data voltage on DL5, and P112 is connected to the data voltage on DL6;

[0177] P21 is connected to the data voltage on DL1, P24 is connected to the data voltage on DL2, P26 is connected to the data voltage on DL3, P27 is connected to the data voltage on DL4, P210 is connected to the data voltage on DL5, and P212 is connected to the data voltage on DL6;

[0178] P11 and P21 are both red sub-pixels, P14 and P24 are both red sub-pixels, P16 and P26 are both blue sub-pixels, P17 and P27 are both red sub-pixels, P110 and P210 are both red sub-pixels, and P112 and P212 are both blue sub-pixels, so that there is no color confusion when displaying a monochrome picture;

[0179] In the first stage S1, G2 and G4 both provide high voltage signals, and precharge the data voltages P12 and P22 on DL1, P13 and P23 on DL2, P15 and P25 on DL3, P18 and P28 on DL4, P19 and P29 on DL5, P111 and P112 on DL6. 211 performs pre-charging so that when polarity flipping is performed between adjacent frames, P12, P22, P13, P23, P15, P25, P18, P28, P19, P29, P111 and P211 can be pre-charged with data voltages of corresponding polarities, so that in the second stage S2, P12, P22, P13, P23, P15, P25, P18, P28, P19, P29, P111 and P211 can be quickly charged with the data voltages of the polarity;

[0180] In the second stage S2, G2 and G4 provide high voltage signals, P12 receives the data voltage on DL1, P13 receives the data voltage on DL2, P15 receives the data voltage on DL3, P18 receives the data voltage on DL4, P19 receives the data voltage on DL5, and P111 receives the data voltage on DL6; P22 receives the data voltage on DL1, P23 receives the data voltage on DL2, P25 receives the data voltage on DL3, P28 receives the data voltage on DL4, P29 receives the data voltage on DL5, and P2111 receives the data voltage on DL3;

[0181] In the second stage S2, G5 and G7 provide high voltage signals, and precharge P31 and P41 through the data voltage on DL2, precharge P34 and P44 through the data voltage on DL3, precharge P36 and P46 through the data voltage on DL4, precharge P37 and P47 through the data voltage on DL5, precharge P310 and P410 through the data voltage on DL6, and precharge P312 and P41 through the data voltage on DL7. 2. Pre-charging is performed so that when polarity is flipped between adjacent frames, P31, P41, P34, P44, P36, P46, P37, P47, P310, P410, P312 and P412 can be pre-charged with data voltages of corresponding polarities, so that in the second stage S2, P31, P41, P34, P44, P36, P46, P37, P47, P310, P410, P312 and P412 can be quickly charged with the data voltages of the polarity;

[0182] In the third stage S3, G5 and G7 provide high voltage signals, P31 and P41 receive the data voltage on DL2, P34 and P44 access the data voltage on DL3, P36 and P45 access the data voltage on DL4, P37 and P47 access the data voltage on DL5, P310 and P410 access the data voltage on DL6, and P312 and P412 access the data voltage on DL7;

[0183] In the third stage S3, G6 and G8 provide high voltage signals, and precharge P32 and P42 through the data voltage on DL2, precharge P33 and P43 through the data voltage on DL3, precharge P35 and P45 through the data voltage on DL4, precharge P38 and P48 through the data voltage on DL5, precharge P39 and P49 through the data voltage on DL6, and precharge P311 and P41 through the data voltage on DL7. 11 performs precharging so that when polarity flipping is performed between adjacent frames, P32, P42, P33, P43, P35, P45, P38, P48, P39, P49, P311 and P411 can be pre-charged with data voltages of corresponding polarities, so that in the second stage S2, P32, P42, P33, P43, P35, P45, P38, P48, P39, P49, P311 and P411 can be quickly charged with the data voltages of the polarity;

[0184] In the fourth stage S4, G6 and G8 provide high voltage signals, P32 and P42 are connected to the data voltage on DL2, P33 and P43 are connected to the data voltage on DL3, P35 and P45 are connected to the data voltage on DL4, P38 and P48 are connected to the data voltage on DL5, P39 and P49 are connected to the data voltage on DL6, and P311 and P411 are connected to the data voltage on DL7.

[0185] like Figure 3 As shown, when Figure 1A At least one embodiment of the pixel module shown in the DLG mode displays a red image.

[0186] First, G1 and G3 provide high voltage signals, DL1 provides a first red data voltage, DL2 provides a second red data voltage, DL4 provides a third red data voltage, DL5 provides a fourth red data voltage, P11 and P21 are connected to the first red data voltage, P14 and P24 are connected to the second red data voltage, P17 and P27 are connected to the third red data voltage, P110 and P210 are connected to the fourth red data voltage, P11, P31, P14, P34, P17, P27, P110 and P210 are all red sub-pixels, and the displayed colors are not disordered;

[0187] Afterwards, G2 and G4 provide high voltage signals, and each data line does not provide data voltage;

[0188] Afterwards, G5 and G7 provide high voltage signals, DL2 provides the fifth red data voltage, DL3 provides the sixth data voltage, DL5 provides the seventh red data voltage, DL6 provides the eighth red data voltage, P31 and P41 are connected to the fifth red data voltage, P34 and P44 are connected to the second red data voltage, P37 and P47 are connected to the third red data voltage, P310 and P410 are connected to the fourth red data voltage, P31, P41, P34, P44, P37, P47, P310 and P410 are all red sub-pixels, and the displayed colors are not disordered;

[0189] Afterwards, G6 and G8 provide high voltage signals, and each data line does not provide a data voltage.

[0190] like Figure 4 As shown, when Figure 1A At least one embodiment of the pixel module shown in the DLG mode displays a green image.

[0191] First, G1 and G3 provide high voltage signals, and each data line does not provide data voltage;

[0192] Afterwards, G2 and G4 provide high voltage signals, DL1 provides a first green data voltage, DL3 provides a second green data voltage, DL4 provides a third green data voltage, DL6 provides a fourth green data voltage, P12 and P22 are connected to the first green data voltage, P15 and P25 are connected to the second green-red data voltage, P18 and P28 are connected to the third green-red data voltage, P111 and P211 are connected to the fourth green data voltage, P12, P22, P15, P25, P18, P28, P111 and P211 are all green sub-pixels, and the displayed colors are not disordered;

[0193] Afterwards, G5 and G7 provide high voltage signals, and each data line does not provide data voltage;

[0194] Afterwards, G6 and G8 provide high voltage signals, DL2 provides the fifth green data voltage, DL4 provides the sixth green data voltage, DL5 provides the seventh green data voltage, DL7 provides the eighth green data voltage, P32 and P42 are connected to the fifth green data voltage, P35 and P45 are connected to the sixth green data voltage, P38 and P48 are connected to the seventh green data voltage, P311 and P411 are connected to the eighth green data voltage, P32, P42, P35, P45, P38, P48, P311 and P411 are all green sub-pixels, and the displayed colors are not disordered.

[0195] like Figure 5 As shown, when Figure 1A At least one embodiment of the pixel module shown in the DLG mode displays a blue image.

[0196] First, G1 and G3 provide high voltage signals, DL3 provides a first blue data voltage, DL6 provides a second blue data voltage, P16 and P26 are connected to the first blue data voltage, and P112 and P212 are connected to the second blue data voltage;

[0197] Afterwards, G2 and G4 provide high voltage signals, DL2 provides a third blue data voltage, DL5 provides a fourth blue data voltage, P13 and P23 are connected to the third blue data voltage, and P19 and P29 are connected to the fourth blue data voltage;

[0198] Afterwards, G5 and G7 provide high voltage signals, DL4 provides a fifth blue data voltage, DL6 provides a sixth blue data voltage, P36 and P46 are connected to the fifth blue data voltage, and P312 and P412 are connected to the sixth blue data voltage;

[0199] Afterwards, G6 and G8 provide high voltage signals, DL3 provides the seventh blue data voltage, DL6 provides the eighth blue data voltage, P33 and P43 are connected to the seventh blue data voltage, and P39 and P49 are connected to the eighth blue data voltage;

[0200] P16, P26, P112, P121, P13, P23, P19, P29, P36, P46, P312, P412, P33, P43, P39 and P49 are all blue sub-pixels and have no problem displaying colors.

[0201] The utility model Figure 1A At least one embodiment of the pixel module shown is in a normal display mode, that is, each row of scanning lines outputs a high voltage signal in sequence, and when a red image is displayed,

[0202] First, G1 provides a high voltage signal, DL1 provides a first red data voltage, DL2 provides a second red data voltage, DL4 provides a third red data voltage, DL5 provides a fourth red data voltage, P11 is connected to the first red data voltage, P14 is connected to the second red data voltage, P17 is connected to the third red data voltage, and P110 is connected to the fourth red data voltage;

[0203] Afterwards, G2 provides a high voltage signal, and each data line does not provide a data voltage;

[0204] Afterwards, G3 provides a high voltage signal, DL1 provides a fifth red data voltage, DL2 provides a sixth red data voltage, DL4 provides a seventh red data voltage, DL5 provides an eighth red data voltage, P21 is connected to the fifth red data voltage, P24 is connected to the sixth red data voltage, P27 is connected to the seventh red data voltage, and P210 is connected to the eighth red data voltage;

[0205] Afterwards, G4 provides a high voltage signal, and each data line does not provide a data voltage;

[0206] Afterwards, G5 provides a high voltage signal, DL2 provides a ninth red data voltage, DL3 provides a tenth red data voltage, DL5 provides an eleventh red data voltage, DL6 provides a twelfth red data voltage, P31 is connected to the ninth red data voltage, P34 is connected to the tenth red data voltage, P37 is connected to the eleventh red data voltage, and P310 is connected to the twelfth red data voltage;

[0207] After that, G6 provides a high voltage signal, and each data line does not provide a data voltage;

[0208] Then G7 provides a high voltage signal, DL2 provides the thirteenth red data voltage, DL3 provides the fourteenth red data voltage, DL5 provides the fifteenth red data voltage, DL6 provides the sixteenth red data voltage, P41 is connected to the thirteenth red data voltage, P44 is connected to the fourteenth red data voltage, P47 is connected to the fifteenth red data voltage, and P410 is connected to the sixteenth red data voltage;

[0209] P11, P14, P17, P110, P21, P24, P27, P210, P31, P34, P37, P310, P41, P44, P47 and P410 are all red data voltages and the display colors are correct.

[0210] The utility model Figure 1A In at least one embodiment of the pixel module shown, when in normal display mode, when displaying a monochrome image, all sub-pixels are not pre-charged, have a consistent charging state, consistent brightness, and very good image quality.

[0211] The utility model Figure 1A At least one embodiment of the pixel module has a display accuracy comparable to that of a related pixel module when displaying a mixed color image in a normal display mode.

[0212] The pixel module described in at least one embodiment of the present invention can realize DLG display, can double the refresh rate of the display panel, and improve the performance and competitiveness of the display panel.

[0213] exist Figure 1A In at least one embodiment of the pixel module shown, the connection method of the first row of sub-pixels is the same as the connection method of the second row of sub-pixels, the connection method of the third row of sub-pixels is the same as the connection method of the fourth row of sub-pixels, and the connection method of the first row of sub-pixels is opposite to the connection method of the third row of sub-pixels.

[0214] In the pixel module described in at least one embodiment of the present utility model, each sub-pixel may include a pixel electrode and a thin film transistor electrically connected to each other;

[0215] The gate electrode of the thin film transistor is electrically connected to the corresponding row gate line, the first electrode of the thin film transistor is electrically connected to the corresponding pixel electrode, and the second electrode of the thin film transistor is electrically connected to the corresponding column data line.

[0216] like Figure 6 As shown, the utility model Figure 1A At least one embodiment of the pixel module shown is in operation, in the DLG display mode, when DL1 provides a positive polarity data voltage, DL2 provides a negative polarity data voltage, DL3 provides a positive polarity data voltage, DL4 provides a negative polarity data voltage, DL5 provides a positive polarity data voltage, DL6 provides a negative polarity data voltage, and DL7 provides a positive polarity data voltage,

[0217] First, G1 and G3 provide high voltage signals, P11 and P21 are connected to positive polarity data voltages, P14 and P24 are connected to negative polarity data voltages, P16 and P26 are connected to positive polarity data voltages, P17 and P27 are connected to negative polarity data voltages, P110 and P210 are connected to positive polarity data voltages, and P112 and P212 are connected to negative polarity data voltages;

[0218] Afterwards, G2 and G4 provide high voltage signals, P12 and P22 are connected to positive polarity data voltages, P13 and P23 are connected to negative polarity data voltages, P15 and P25 are connected to positive polarity data voltages, P18 and P28 are connected to negative polarity data voltages, P19 and P29 are connected to positive polarity data voltages, and P111 and P211 are connected to negative polarity data voltages;

[0219] Afterwards, G5 and G7 provide high voltage signals, P31 and P41 are connected to negative polarity data voltages, P34 and P44 are connected to positive polarity data voltages, P36 and P46 are both connected to negative polarity data voltages, P37 and P47 are both connected to positive polarity data voltages, P310 and P410 are connected to negative polarity data voltages, and P312 and P412 are connected to positive polarity data voltages;

[0220] Afterwards, G6 and G8 provide high voltage signals, P32 and P42 are connected to negative polarity data voltage, P33 and P43 are connected to positive polarity data voltage, P35 and P45 are connected to negative polarity data voltage, P38 and P48 are connected to positive polarity data voltage, P39 and P49 are both connected to negative polarity data voltage, and P311 and P411 are both connected to positive polarity data voltage.

[0221] like Figure 6 As shown, the polarities of four adjacent sub-pixels are the same, and the polarities of the four adjacent sub-pixels are opposite to the polarities of the surrounding adjacent sub-pixels.

[0222] According to another specific embodiment, the sub-pixels in the 4a-3 rows and the 6b-5 columns are electrically connected to the 8a-7 rows of scan lines and the 3b-2 columns of data lines, respectively, and are used to receive the data voltage provided by the 3b-2 columns of data lines under the control of the scan signals provided by the 8a-7 rows of scan lines;

[0223] The sub-pixels in the 4a-3 row and the 6b-4 column are electrically connected to the 8a-6 row scan lines and the 3b-2 column data lines, respectively, and are used to receive data voltages provided by the 3b-2 column data lines under the control of scan signals provided by the 8a-6 row scan lines;

[0224] The sub-pixels in the 4a-3 row and the 6b-3 column are electrically connected to the 8a-7 row scan lines and the 3b-1 column data lines, respectively, and are used to receive data voltages provided by the 3b-1 column data lines under the control of scan signals provided by the 8a-7 row scan lines;

[0225] The sub-pixels in the 4a-3 row and the 6b-2 column are electrically connected to the 8a-6 row scan lines and the 3b-1 data lines, respectively, and are used to receive data voltages provided by the 3b-1 column data lines under the control of scan signals provided by the 8a-6 row scan lines;

[0226] The sub-pixels in the 4a-3th row and the 6b-1th column are electrically connected to the 8a-7th row scan lines and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-7th row scan lines;

[0227] The sub-pixels in the 4a-3rd row and the 6bth column are electrically connected to the 8a-6th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-6th row scan lines;

[0228] a and b are positive integers.

[0229] In at least one embodiment of the present invention, the sub-pixels in the 4a-2th row and the 6b-5th column are electrically connected to the 8a-5th row scan line and the 3b-2th column data line, respectively, and are used to receive the data voltage provided by the 3b-2th column data line under the control of the scan signal provided by the 8a-5th row scan line;

[0230] The sub-pixels in the 4a-2 row and the 6b-4 column are electrically connected to the 8a-4 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0231] The sub-pixels in the 4a-2 row and the 6b-3 column are electrically connected to the 8a-5 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-5 row scan line;

[0232] The sub-pixels in the 4a-2 row and the 6b-2 column are electrically connected to the 8a-4 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-4 row scan line;

[0233] The sub-pixels in the 4a-2th row and the 6b-1th column are electrically connected to the 8a-5th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-5th row scan lines;

[0234] The sub-pixels in the 4a-2 row and the 6b column are electrically connected to the 8a-4 row scan line and the 3b column data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-4 row scan line.

[0235] In at least one embodiment of the present invention, the sub-pixels in the 4a-1th row and the 6b-5th column are electrically connected to the 8a-3th row scan line and the 3b-1th column data line, respectively, and are used to receive the data voltage provided by the 3b-1th column data line under the control of the scan signal provided by the 8a-3th row scan line;

[0236] The sub-pixels in the 4a-1 row and the 6b-4 column are electrically connected to the 8a-2 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-2 row scan line;

[0237] The sub-pixels in the 4a-1th row and the 6b-3th column are electrically connected to the 8a-3th row scan line and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-3th row scan line;

[0238] The sub-pixels in the 4a-1th row and the 6b-2th column are electrically connected to the 8a-2th row scan line and the 3bth data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-2th row scan line;

[0239] The sub-pixel in the 4a-1 row and the 6b-1 column is electrically connected to the 8a-3 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-3 row scan line;

[0240] The sub-pixel in the 4a-1 row and the 6b column is electrically connected to the 8a-2 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-2 row scan line.

[0241] In at least one embodiment of the present invention, the sub-pixels in the 4a row and the 6b-5 columns are electrically connected to the 8a-1 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0242] The sub-pixels in the 4a row and the 6b-4 column are electrically connected to the 8a row scan line and the 3b-1 column data line respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a row scan line;

[0243] The sub-pixels in the 4a row and the 6b-3 column are electrically connected to the 8a-1 row scan line and the 3b column data line, respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0244] The sub-pixels in the 4a row and the 6b-2 column are electrically connected to the 8a row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a row scan line;

[0245] The sub-pixel in the 4a row and the 6b-1 column is electrically connected to the 8a-1 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-1 row scan line;

[0246] The sub-pixel in row 4a and column 6b is electrically connected to the scan line in row 8a and the data line in column 3b+1 respectively, and is used to receive the data voltage provided by the data line in column 3b+1 under the control of the scan signal provided by the scan line in row 8a.

[0247] Optionally, the sub-pixels located in the 3b-2 column have a first color, the sub-pixels located in the 3b-1 column have a second color, and the sub-pixels located in the 3b column have a second color.

[0248] like Fig. 7A As shown, the first row and first column sub-pixel P11 is electrically connected to the first row scan line G1 and the first column data line DL1 respectively, and is used to receive the data voltage provided by the first column data line DL1 under the control of the scan signal provided by the first row scan line G1;

[0249] The first row and second column sub-pixel P12 is electrically connected to the second row scan line G2 and the first column data line DL1 respectively, and is used to receive the data voltage provided by the first column data line DL1 under the control of the scan signal provided by the second row scan line G2;

[0250] The first row and third column sub-pixel P13 is electrically connected to the first row scan line G1 and the second column data line DL2 respectively, and is used to receive a data voltage provided by the second column data line DL2 under the control of the scan signal provided by the first row scan line G1;

[0251] The sub-pixel P14 in the first row and the fourth column is electrically connected to the second row scan line G2 and the second column data line DL2 respectively, and is used to receive the data voltage provided by the second column data line DL2 under the control of the scan signal provided by the second row scan line G2;

[0252] The first row and fifth column sub-pixel P15 is electrically connected to the first row scan line G1 and the third column data line DL3 respectively, and is used to receive a data voltage provided by the third column data line DL3 under the control of the scan signal provided by the first row scan line G1;

[0253] The sub-pixel P16 in the first row and the sixth column is electrically connected to the second row scan line G2 and the third column data line DL3 respectively, and is used to receive a data voltage provided by the third column data line DL3 under the control of the scan signal provided by the second row scan line G2;

[0254] The sub-pixel P17 in the first row and the seventh column is electrically connected to the first row scan line G1 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the first row scan line G1;

[0255] The sub-pixel P18 in the first row and the eighth column is electrically connected to the second row scan line G2 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the second row scan line G2;

[0256] The sub-pixel P19 in the first row and the ninth column is electrically connected to the first row scan line G1 and the fifth column data line DL5 respectively, and is used to receive a data voltage provided by the fifth column data line DL5 under the control of the scan signal provided by the first row scan line G1;

[0257] The sub-pixel P110 of the first row and the tenth column is electrically connected to the second row scan line G2 and the fifth column data line DL5 respectively, and is used to receive the data voltage provided by the fifth column data line DL5 under the control of the scan signal provided by the second row scan line G2;

[0258] The sub-pixel P111 in the first row and the eleventh column is electrically connected to the first row scan line G1 and the sixth column data line DL6 respectively, and is used to receive a data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the first row scan line G1;

[0259] The sub-pixel P112 in the first row and the twelfth column is electrically connected to the second row scan line G2 and the sixth column data line DL6 respectively, and is used to receive the data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the second row scan line G2;

[0260] The sub-pixel P21 in the second row and the first column is electrically connected to the scan line G3 in the third row and the data line DL1 in the first column, respectively, and is used to receive the data voltage provided by the data line DL1 in the first column under the control of the scan signal provided by the scan line in the third row;

[0261] The sub-pixel P22 in the second row and the second column is electrically connected to the fourth row scan line G4 and the first column data line DL1 respectively, and is used to receive the data voltage provided by the first column data line DL1 under the control of the scan signal provided by the fourth row scan line G4;

[0262] The sub-pixel P23 in the second row and the third column is electrically connected to the scan line G3 in the third row and the data line DL2 in the second column, respectively, and is used for receiving a data voltage provided by the data line DL2 in the second column under the control of a scan signal provided by the scan line G3 in the third row;

[0263] The sub-pixel P24 in the second row and the fourth column is electrically connected to the scan line G4 in the fourth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G4 in the fourth row;

[0264] The sub-pixel P25 in the second row and the fifth column is electrically connected to the scan line G3 in the third row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G3 in the third row;

[0265] The sub-pixel P26 in the second row and the sixth column is electrically connected to the scan line G4 in the fourth row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G4 in the fourth row;

[0266] The sub-pixel P27 in the second row and the seventh column is electrically connected to the scan line G3 in the third row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line in the third row;

[0267] The sub-pixel P28 in the second row and the eighth column is electrically connected to the scan line G4 in the fourth row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G4 in the fourth row;

[0268] The sub-pixel P29 in the second row and the ninth column is electrically connected to the scan line G3 in the third row and the data line DL5 in the fifth column, respectively, and is used to receive a data voltage provided by the data line DL5 in the fifth column under the control of a scan signal provided by the scan line G3 in the third row;

[0269] The sub-pixel P210 in the second row and the tenth column is electrically connected to the fourth row scan line G4 and the fifth column data line DL5 respectively, and is used to receive the data voltage provided by the fifth column data line DL5 under the control of the scan signal provided by the fourth row scan line G4;

[0270] The sub-pixel P211 in the second row and the eleventh column is electrically connected to the third row scan line G3 and the sixth column data line DL6 respectively, and is used to receive a data voltage provided by the sixth column data line DL6 under the control of a scan signal provided by the third row scan line G3;

[0271] The sub-pixel P212 in the second row and the twelfth column is electrically connected to the fourth row scan line G4 and the sixth column data line DL6 respectively, and is used to receive the data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the fourth row scan line G4;

[0272] The sub-pixel P31 in the third row and the first column is electrically connected to the scan line G5 in the fifth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G5 in the fifth row;

[0273] The sub-pixel P32 in the third row and the second column is electrically connected to the scan line G6 in the sixth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G6 in the sixth row;

[0274] The sub-pixel P33 in the third row and the third column is electrically connected to the scan line G5 in the fifth row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G5 in the fifth row;

[0275] The sub-pixel P34 in the third row and the fourth column is electrically connected to the scan line G6 in the sixth row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0276] The sub-pixel P35 in the third row and the fifth column is electrically connected to the fifth row scan line G5 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the fifth row scan line G5;

[0277] The sub-pixel P36 in the third row and the sixth column is electrically connected to the scan line G6 in the sixth row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0278] The sub-pixel P37 in the third row and the seventh column is electrically connected to the fifth row scan line G5 and the fifth column data line DL5 respectively, and is used to receive a data voltage provided by the fifth column data line DL5 under the control of a scan signal provided by the fifth row scan line G5;

[0279] The sub-pixel P38 in the third row and the eighth column is electrically connected to the scan line G6 in the sixth row and the data line DL5 in the fifth column, respectively, and is used to receive a data voltage provided by the data line DL5 in the fifth column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0280] The sub-pixel P39 in the third row and the ninth column is electrically connected to the fifth row scan line G5 and the sixth column data line DL6 respectively, and is used to receive a data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the fifth row scan line G5;

[0281] The sub-pixel P310 in the third row and the tenth column is electrically connected to the sixth row scan line G6 and the sixth column data line DL3 respectively, and is used to receive a data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the sixth row scan line G6;

[0282] The sub-pixel P311 in the third row and the eleventh column is electrically connected to the fifth row scan line G5 and the seventh column data line DL7 respectively, and is used to receive a data voltage provided by the seventh column data line DL7 under the control of a scan signal provided by the fifth row scan line G5;

[0283] The sub-pixel P312 in the third row and the twelfth column is electrically connected to the scan line G6 in the sixth row and the data line DL7 in the seventh column, respectively, and is used to receive a data voltage provided by the data line DL7 in the seventh column under the control of a scan signal provided by the scan line G6 in the sixth row;

[0284] The sub-pixel P41 in the first column of the fourth row is electrically connected to the scan line G7 in the seventh row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the second data line DL2 under the control of a scan signal provided by the scan line G7 in the seventh row;

[0285] The sub-pixel P42 in the fourth row and the second column is electrically connected to the scan line G8 in the eighth row and the data line DL2 in the second column, respectively, and is used to receive a data voltage provided by the data line DL2 in the second column under the control of the scan signal provided by the scan line G8 in the eighth row;

[0286] The sub-pixel P43 in the fourth row and the third column is electrically connected to the scan line G7 in the seventh row and the data line DL3 in the third column, respectively, and is used to receive a data voltage provided by the data line DL3 in the third column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0287] The sub-pixel P44 in the fourth row and the fourth column is electrically connected to the eighth row scan line G8 and the third column data line DL3 respectively, and is used to receive the data voltage provided by the third column data line DL4 under the control of the scan signal provided by the eighth row scan line G8;

[0288] The sub-pixel P45 in the fourth row and the fifth column is electrically connected to the scan line G7 in the seventh row and the data line DL4 in the fourth column, respectively, and is used to receive a data voltage provided by the data line DL4 in the fourth column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0289] The sub-pixel P46 in the fourth row and the sixth column is electrically connected to the eighth row scan line G8 and the fourth column data line DL4 respectively, and is used to receive the data voltage provided by the fourth column data line DL4 under the control of the scan signal provided by the eighth row scan line G8;

[0290] The sub-pixel P47 in the fourth row and the seventh column is electrically connected to the scan line G7 in the seventh row and the data line DL5 in the fifth column, respectively, and is used to receive a data voltage provided by the data line DL5 in the fifth column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0291] The sub-pixel P48 in the fourth row and the eighth column is electrically connected to the eighth row scan line G8 and the fifth column data line DL5 respectively, and is used to receive the data voltage provided by the fifth column data line DL5 under the control of the scan signal provided by the eighth row scan line G8;

[0292] The sub-pixel P49 in the fourth row and the ninth column is electrically connected to the scan line G7 in the seventh row and the data line DL6 in the sixth column, respectively, and is used to receive a data voltage provided by the data line DL6 in the sixth column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0293] The sub-pixel P410 in the fourth row and the tenth column is electrically connected to the eighth row scan line G8 and the sixth column data line DL6 respectively, and is used to receive the data voltage provided by the sixth column data line DL6 under the control of the scan signal provided by the eighth row scan line G8;

[0294] The sub-pixel P411 in the fourth row and the eleventh column is electrically connected to the scan line G7 in the seventh row and the data line DL7 in the seventh column, and is used to receive a data voltage provided by the data line DL7 in the seventh column under the control of a scan signal provided by the scan line G7 in the seventh row;

[0295] The sub-pixel P412 in the fourth row and the twelfth column is electrically connected to the eighth row scan line G8 and the seventh column data line DL7 respectively, and is used to receive a data voltage provided by the seventh column data line DL7 under the control of a scan signal provided by the eighth row scan line G8.

[0296] exist Fig. 7AIn at least one embodiment of the pixel module shown, the first row of sub-pixels are red sub-pixels, the second row of sub-pixels are green sub-pixels, and the third row of sub-pixels are blue sub-pixels; the fourth row of sub-pixels are red sub-pixels, the fifth row of sub-pixels are green sub-pixels, and the sixth row of sub-pixels are blue sub-pixels; the seventh row of sub-pixels are red sub-pixels, the eighth row of sub-pixels are green sub-pixels, and the ninth row of sub-pixels are blue sub-pixels; the tenth row of sub-pixels are red sub-pixels, the eleventh row of sub-pixels are green sub-pixels, and the third row of sub-pixels are blue sub-pixels.

[0297] like Figure 7B As shown, in Fig. 7A Based on at least one embodiment of the pixel module shown, the first row and the first column sub-pixel includes the first row and the first column pixel electrode PJ11 and the first row and the first column thin film transistor T11; the first row and the second column sub-pixel includes the first row and the second column pixel electrode PJ12 and the first row and the second column thin film transistor T12; the first row and the third column sub-pixel includes the first row and the third column pixel electrode PJ13 and the first row and the third column thin film transistor T13; the first row and the fourth column sub-pixel includes the first row and the fourth column pixel electrode PJ14 and the first row and the fourth column thin film transistor T14; the first row and the fifth column sub-pixel includes the first row and the fifth column pixel electrode PJ15 and the first row and the fifth column thin film transistor T15; the first row and the sixth column sub-pixel includes the first row and the sixth column pixel electrode PJ16 and the first row and the sixth column thin film transistor T16; the first row and the seventh column sub-pixel includes the first row and the seventh column pixel electrode PJ17 and the first row and the seventh column thin film transistor T17; the first row and the eighth column sub-pixel includes the first row and the eighth column pixel electrode PJ18 and the first row and the eighth column thin film transistor T18; the first row and the ninth column sub-pixel includes the first row and the ninth column pixel electrode PJ19 and the first row and the ninth column thin film transistor T19; the first row and the tenth column sub-pixel includes the first row and the tenth column pixel electrode PJ110 and the first row and the tenth column thin film transistor T110; the first row and the eleventh column sub-pixel includes the first row and the eleventh column pixel electrode PJ111 and the first row and the eleventh column thin film transistor T111; the first row and the twelfth column sub-pixel includes the first row and the twelfth column pixel electrode PJ112 and the first row and the twelfth column thin film transistor T112;

[0298] The second row and first column sub-pixel includes a second row and first column pixel electrode PJ21 and a second row and first column thin film transistor T21; the second row and second column sub-pixel includes a second row and second column pixel electrode PJ22 and a second row and second column thin film transistor T22; the second row and third column sub-pixel includes a second row and third column pixel electrode PJ23 and a second row and third column thin film transistor T23; the second row and fourth column sub-pixel includes a second row and fourth column pixel electrode PJ24 and a second row and fourth column thin film transistor T24; the second row and fifth column sub-pixel includes a second row and fifth column pixel electrode PJ25 and a second row and fifth column thin film transistor T25; the second row and sixth column sub-pixel includes a second row and sixth column pixel electrode PJ26 and a second row and sixth column thin film transistor T26; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ27 and a second row and sixth column thin film transistor T28; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ28 and a second row and sixth column thin film transistor T29; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ29 and a second row and sixth column thin film transistor T21; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ21 and a second row and sixth column thin film transistor T22; the second row and seventh column sub-pixel includes a second row and sixth column pixel electrode PJ23 and a second row and third column thin film transistor T23; the second row and fourth column sub-pixel includes a second row and fourth column pixel electrode PJ24 and a second row and fourth column thin film transistor T24; the second row and fifth column sub-pixel includes a second row and fifth column pixel electrode PJ25 and a second row and fifth column thin film transistor T25; the second row and sixth column sub-pixel includes a second row and sixth The sub-pixel includes a pixel electrode PJ27 in the second row and the seventh column and a thin film transistor T27 in the second row and the seventh column; the sub-pixel in the second row and the eighth column includes a pixel electrode PJ28 in the second row and the eighth column and a thin film transistor T28 in the second row and the eighth column; the sub-pixel in the second row and the ninth column includes a pixel electrode PJ29 in the second row and the ninth column and a thin film transistor T29 in the second row and the ninth column; the sub-pixel in the second row and the tenth column includes a pixel electrode PJ210 in the second row and the tenth column and a thin film transistor T210 in the second row and the tenth column; the sub-pixel in the second row and the eleventh column includes a pixel electrode PJ211 in the second row and the eleventh column and a thin film transistor T211 in the second row and the eleventh column; the sub-pixel in the second row and the twelfth column includes a pixel electrode PJ212 in the second row and the twelfth column and a thin film transistor T212 in the second row and the twelfth column;

[0299] The third row and first column sub-pixel includes a third row and first column pixel electrode PJ31 and a third row and first column thin film transistor T31; the third row and second column sub-pixel includes a third row and second column pixel electrode PJ32 and a third row and second column thin film transistor T32; the third row and third column sub-pixel includes a third row and third column pixel electrode PJ33 and a third row and third column thin film transistor T33; the third row and fourth column sub-pixel includes a third row and fourth column pixel electrode PJ34 and a third row and fourth column thin film transistor T34; the third row and fifth column sub-pixel includes a third row and fifth column pixel electrode PJ35 and a third row and fifth column thin film transistor T35; the third row and sixth column sub-pixel includes a third row and sixth column pixel electrode PJ36 and a third row and sixth column thin film transistor T36; the third row and seventh column sub-pixel includes a third row and sixth column pixel electrode PJ37 and a third row and sixth column thin film transistor T37; the third row and seventh column sub-pixel includes a third row and sixth column pixel electrode PJ38 and a third row and sixth column thin film transistor T39; the third row and seventh column sub-pixel includes a third row and seventh column pixel electrode PJ39 and a third row and sixth column thin film transistor T31; the third row and seventh column sub-pixel includes a third row and seventh column pixel electrode PJ31 and a third row and sixth column thin film transistor T33; the third row and seventh column sub-pixel includes a third row and seventh column pixel electrode PJ34 and a third row and fourth column thin film transistor T34; the third row and fifth column sub-pixel includes a third row and fifth column pixel electrode PJ35 and a third row and fifth column thin film transistor T35; the third row and sixth column sub-pixel includes a third row and sixth column pixel electrode PJ36 and a third row and sixth column thin film transistor T36; the third row and seventh column sub-pixel includes a third row and sixth The sub-pixel includes the pixel electrode PJ37 in the third row and the seventh column and the thin film transistor T37 in the third row and the seventh column; the sub-pixel in the third row and the eighth column includes the pixel electrode PJ38 in the third row and the eighth column and the thin film transistor T38 in the third row and the eighth column; the sub-pixel in the third row and the ninth column includes the pixel electrode PJ39 in the third row and the ninth column and the thin film transistor T39 in the third row and the ninth column; the sub-pixel in the third row and the tenth column includes the pixel electrode PJ310 in the third row and the tenth column and the thin film transistor T310 in the third row and the tenth column; the sub-pixel in the third row and the eleventh column includes the pixel electrode PJ311 in the third row and the eleventh column and the thin film transistor T311 in the third row and the eleventh column; the sub-pixel in the third row and the twelfth column includes the pixel electrode PJ312 in the third row and the twelfth column and the thin film transistor T312 in the third row and the twelfth column;

[0300] The fourth row and the first column sub-pixel includes the fourth row and the first column pixel electrode PJ41 and the fourth row and the first column thin film transistor T41; the fourth row and the second column sub-pixel includes the fourth row and the second column pixel electrode PJ42 and the fourth row and the second column thin film transistor T42; the fourth row and the third column sub-pixel includes the fourth row and the third column pixel electrode PJ43 and the fourth row and the third column thin film transistor T43; the fourth row and the fourth column sub-pixel includes the fourth row and the fourth column pixel electrode PJ44 and the fourth row and the fourth column thin film transistor T44; the fourth row and the fifth column sub-pixel includes the fourth row and the fifth column pixel electrode PJ45 and the fourth row and the fifth column thin film transistor T45; the fourth row and the sixth column sub-pixel includes the fourth row and the sixth column pixel electrode PJ46 and the fourth row and the sixth column thin film transistor T46; the fourth row and the seventh column sub-pixel includes the fourth row and the sixth column pixel electrode PJ47 and the fourth row and the sixth column thin film transistor T47; The subpixel includes the pixel electrode PJ47 in the fourth row and the seventh column and the thin film transistor T47 in the fourth row and the seventh column; the subpixel in the fourth row and the eighth column includes the pixel electrode PJ48 in the fourth row and the eighth column and the thin film transistor T48 in the fourth row and the eighth column; the subpixel in the fourth row and the ninth column includes the pixel electrode PJ49 in the fourth row and the ninth column and the thin film transistor T49 in the fourth row and the ninth column; the subpixel in the fourth row and the tenth column includes the pixel electrode PJ410 in the fourth row and the tenth column and the thin film transistor T410 in the fourth row and the tenth column; the subpixel in the fourth row and the eleventh column includes the pixel electrode PJ411 in the fourth row and the eleventh column and the thin film transistor T411 in the fourth row and the twelfth column; the subpixel in the fourth row and the twelfth column includes the pixel electrode PJ412 in the fourth row and the twelfth column and the thin film transistor T412 in the fourth row and the twelfth column.

[0301] like Figure 8 As shown, the utility model Fig. 7A When at least one embodiment of the pixel module shown is in operation, a display cycle may include a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4 which are arranged in sequence;

[0302] In the first stage S1, G1 and G3 both provide high voltage signals, P11 is connected to the data voltage on DL1, P13 is connected to the data voltage on DL2, P15 is connected to the data voltage on DL3, P17 is connected to the data voltage on DL4, P19 is connected to the data voltage on DL5, and P111 is connected to the data voltage on DL6;

[0303] P21 is connected to the data voltage on DL1, P23 is connected to the data voltage on DL2, P25 is connected to the data voltage on DL3, P27 is connected to the data voltage on DL4, P29 is connected to the data voltage on DL5, and P211 is connected to the data voltage on DL6;

[0304] P11 and P21 are both red sub-pixels, P13 and P23 are both blue sub-pixels, P15 and P25 are both green sub-pixels, P17 and P27 are both red sub-pixels, P19 and P29 are both blue sub-pixels, and P111 and P211 are both green sub-pixels, so that there is no color confusion when displaying a monochrome picture;

[0305] In the first stage S1, G2 and G4 both provide high voltage signals, and precharge P12 and P22 through the data voltage on DL1, precharge P14 and P24 through the data voltage on DL2, precharge P16 and P26 through the data voltage on DL3, precharge P18 and P28 through the data voltage on DL4, precharge P110 and P210 through the data voltage on DL5, and precharge P112 and P210 through the data voltage on DL6. P212 is precharged so that when polarity is flipped between adjacent frames, P12, P22, P14, P24, P16, P26, P18, P28, P19, P29, P112 and P212 can be precharged with data voltages of corresponding polarities, so that in the second stage S2, P12, P22, P14, P24, P16, P26, P18, P28, P19, P29, P112 and P212 can be quickly charged with the data voltages of the polarity;

[0306] In the second stage S2, G2 and G4 provide high voltage signals, P12 receives the data voltage on DL1, P14 receives the data voltage on DL2, P16 receives the data voltage on DL3, P18 receives the data voltage on DL4, P110 receives the data voltage on DL5, and P112 receives the data voltage on DL6; P22 receives the data voltage on DL1, P24 receives the data voltage on DL2, P26 receives the data voltage on DL3, P28 receives the data voltage on DL4, P210 receives the data voltage on DL5, and P212 receives the data voltage on DL3;

[0307] In the second stage S2, G5 and G7 provide high voltage signals, and precharge P31 and P41 through the data voltage on DL2, precharge P33 and P43 through the data voltage on DL3, precharge P35 and P45 through the data voltage on DL4, precharge P37 and P47 through the data voltage on DL5, precharge P39 and P49 through the data voltage on DL6, and precharge P311 and P41 through the data voltage on DL7. 11 performs precharging so that when polarity flipping is performed between adjacent frames, P31, P41, P33, P43, P35, P45, P37, P47, P39, P49, P311 and P411 can be pre-charged with data voltages of corresponding polarities, so that in the second stage S2, P31, P41, P33, P43, P35, P45, P37, P47, P39, P49, P311 and P411 can be quickly charged with the data voltages of the polarity;

[0308] In the third stage S3, G5 and G7 provide high voltage signals, P31 and P41 receive the data voltage on DL2, P33 and P43 access the data voltage on DL3, P35 and P45 access the data voltage on DL4, P37 and P47 access the data voltage on DL5, P39 and P49 access the data voltage on DL6, and P311 and P411 access the data voltage on DL7;

[0309] In the third stage S3, G6 and G8 provide high voltage signals, and precharge P32 and P42 through the data voltage on DL2, precharge P34 and P44 through the data voltage on DL3, precharge P36 and P46 through the data voltage on DL4, precharge P38 and P48 through the data voltage on DL5, precharge P310 and P410 through the data voltage on DL6, and precharge P312 and P41 through the data voltage on DL7. 2 pre-charges so that when polarity is flipped between adjacent frames, P32, P42, P34, P44, P36, P46, P38, P48, P310, P410, P312 and P412 can be pre-charged with data voltages of corresponding polarities, so that in the second stage S2, P32, P42, P34, P44, P36, P46, P38, P48, P310, P410, P312 and P412 can be quickly charged with the data voltages of the polarity;

[0310] In the fourth stage S4, G6 and G8 provide high voltage signals, P32 and P42 are connected to the data voltage on DL2, P34 and P44 are connected to the data voltage on DL3, P36 and P46 are connected to the data voltage on DL4, P38 and P48 are connected to the data voltage on DL5, P310 and P410 are connected to the data voltage on DL6, and P312 and P412 are connected to the data voltage on DL7.

[0311] In at least one embodiment of the present invention, a driving method is applied to the above-mentioned pixel module, and a driving cycle includes a plurality of driving stages arranged in sequence; the driving method includes:

[0312] In the 2c-1 phase, the 4c-3 scan line and the 4c-1 scan line are turned on, and the sub-pixels electrically connected to the 4c-3 scan line and the sub-pixels electrically connected to the 4c-1 scan line are controlled to receive data voltages on corresponding data lines;

[0313] In the 2c phase, the 4c-2 scan line and the 4c ​​scan line are turned on, and the sub-pixels electrically connected to the 4c-2 scan line and the sub-pixels electrically connected to the 4c ​​scan line are controlled to receive data voltages on corresponding data lines;

[0314] c is a positive integer.

[0315] In at least one embodiment of the present invention, the 2c-1 stage is the 2c pre-charging stage; the 2c stage is the 2c+1 pre-charging stage; and the driving method further includes:

[0316] In the 2c-1 stage, the 4c-2 scan line and the 4c ​​scan line are turned on, and the sub-pixels electrically connected to the 4c-2 scan line and the sub-pixels electrically connected to the 4c ​​scan line are controlled to receive data voltages on corresponding data lines, so as to pre-charge the sub-pixels electrically connected to the 4c-2 scan line and the sub-pixels electrically connected to the 4c ​​scan line;

[0317] In the 2c stage, the 4c+1th scan line and the 4c+3th scan line are turned on, and the sub-pixels electrically connected to the 4c-2th scan line and the sub-pixels electrically connected to the 4c+1th scan line are controlled to receive the data voltages on the corresponding data lines to pre-charge the sub-pixels electrically connected to the 4c+3th scan line and the sub-pixels electrically connected to the 4cth scan line.

[0318] The display device described in the embodiment of the present invention includes the above-mentioned pixel module.

[0319] The display device described in at least one embodiment of the present utility model further includes a driving module; the driving module includes eight clock signal lines and a multi-stage driving circuit;

[0320] The 8d-7th level driving circuit is electrically connected to the first clock signal line, the 8d-6th level driving circuit is electrically connected to the second clock signal line, the 8d-5th level driving circuit is electrically connected to the third clock signal line, the 8d-4th level driving circuit is electrically connected to the fourth clock signal line, the 8d-3th level driving circuit is electrically connected to the fifth clock signal line, the 8d-2th level driving circuit is electrically connected to the sixth clock signal line, the 8d-1th level driving circuit is electrically connected to the seventh clock signal line, and the 8d-level driving circuit is electrically connected to the eighth clock signal line; d is a positive integer;

[0321] The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+4-th driving circuit, and the driving signal output terminal of the e+4-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

[0322] like Fig. 9 As shown, in at least one embodiment of the present utility model, the driving module includes a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, a sixth-level driving circuit GA6, a seventh-level driving circuit GA7 and an eighth-level driving circuit GA8;

[0323] GA1 is electrically connected to the first clock signal line CLK1, GA2 is electrically connected to the second clock signal line CLK2, GA3 is electrically connected to the third clock signal line CLK3, GA4 is electrically connected to the fourth clock signal line CLK4, GA5 is electrically connected to the fifth clock signal line CLK5, GA6 is electrically connected to the sixth clock signal line CLK6, GA7 is electrically connected to the seventh clock signal line CLK7, and GA8 is electrically connected to the eighth clock signal line CLK8;

[0324] The drive signal output terminal of GA1 is electrically connected to the input terminal of GA5, the drive signal output terminal of GA2 is electrically connected to the input terminal of GA6, the drive signal output terminal of GA3 is electrically connected to the input terminal of GA7, and the drive signal output terminal of GA4 is electrically connected to the input terminal of GA8;

[0325] The drive signal output terminal of GA5 is electrically connected to the reset terminal of GA1, the drive signal output terminal of GA6 is electrically connected to the reset terminal of GA2, the drive signal output terminal of GA7 is electrically connected to the reset terminal of GA3, and the drive signal output terminal of GA8 is electrically connected to the reset terminal of GA4.

[0326] exist Fig. 9 Among them, the one labeled I1 is the input terminal, the one labeled OT is the drive signal output terminal, the one labeled RST is the reset terminal, and the one labeled CLK is the clock signal terminal.

[0327] The display device described in at least one embodiment of the present utility model further includes a driving module; the driving module includes twelve clock signal lines and a multi-stage driving circuit;

[0328] The 12d-11th level driving circuit is electrically connected to the first clock signal line, the 12d-10th level driving circuit is electrically connected to the second clock signal line, the 12d-9th level driving circuit is electrically connected to the third clock signal line, the 12d-8th level driving circuit is electrically connected to the fourth clock signal line, the 12d-7th level driving circuit is electrically connected to the fifth clock signal line, the 12d-6th level driving circuit is electrically connected to the sixth clock signal line, the 12d-5th level driving circuit is electrically connected to the seventh clock signal line, the 12d-4th level driving circuit is electrically connected to the eighth clock signal line, the 12d-3th level driving circuit is electrically connected to the ninth clock signal line, the 12d-2th level driving circuit is electrically connected to the tenth clock signal line, the 12d-1th level driving circuit is electrically connected to the eleventh clock signal line, and the 12d-1th level driving circuit is electrically connected to the twelfth clock signal line; d is a positive integer;

[0329] The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+4-th driving circuit, and the driving signal output terminal of the e+4-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

[0330] like Fig.10 As shown, in at least one embodiment of the present utility model, the driving module includes a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, a sixth-level driving circuit GA6, a seventh-level driving circuit GA7, an eighth-level driving circuit GA8, a ninth-level driving circuit GA9, a tenth-level driving circuit GA10, an eleventh-level driving circuit GA11 and a twelfth-level driving circuit GA12;

[0331] GA1 is electrically connected to the first clock signal line CLK1, GA2 is electrically connected to the second clock signal line CLK2, GA3 is electrically connected to the third clock signal line CLK3, GA4 is electrically connected to the fourth clock signal line CLK4, GA5 is electrically connected to the fifth clock signal line CLK5, GA6 is electrically connected to the sixth clock signal line CLK6, GA7 is electrically connected to the seventh clock signal line CLK7, GA8 is electrically connected to the eighth clock signal line CLK8; GA9 is electrically connected to the ninth clock signal line CLK9, GA10 is electrically connected to the tenth clock signal line CLK10, GA11 is electrically connected to the eleventh clock signal line CLK11, and GA12 is electrically connected to the twelfth clock signal line CLK12;

[0332] The drive signal output terminal of GA1 is electrically connected to the input terminal of GA5, the drive signal output terminal of GA2 is electrically connected to the input terminal of GA6, the drive signal output terminal of GA3 is electrically connected to the input terminal of GA7, and the drive signal output terminal of GA4 is electrically connected to the input terminal of GA8; the drive signal output terminal of GA5 is electrically connected to the input terminal of GA9, the drive signal output terminal of GA6 is electrically connected to the input terminal of GA10, the drive signal output terminal of GA7 is electrically connected to the input terminal of GA11, and the drive signal output terminal of GA8 is electrically connected to the input terminal of GA12;

[0333] The drive signal output terminal of GA5 is electrically connected to the reset terminal of GA1, the drive signal output terminal of GA6 is electrically connected to the reset terminal of GA2, the drive signal output terminal of GA7 is electrically connected to the reset terminal of GA3, and the drive signal output terminal of GA8 is electrically connected to the reset terminal of GA4; the drive signal output terminal of GA9 is electrically connected to the reset terminal of GA5, the drive signal output terminal of GA10 is electrically connected to the reset terminal of GA6, the drive signal output terminal of GA11 is electrically connected to the reset terminal of GA7, and the drive signal output terminal of GA12 is electrically connected to the reset terminal of GA8.

[0334] exist Fig.10 Among them, the one labeled I1 is the input terminal, the one labeled OT is the drive signal output terminal, the one labeled RST is the reset terminal, and the one labeled CLK is the clock signal terminal.

[0335] The display device described in at least one embodiment of the present utility model further includes a driving module; the driving module includes sixteen clock signal lines and a multi-stage driving circuit;

[0336] The 16d-15th level driving circuit is electrically connected to the first clock signal line, the 16d-14th level driving circuit is electrically connected to the second clock signal line, the 16d-13th level driving circuit is electrically connected to the third clock signal line, the 16d-12th level driving circuit is electrically connected to the fourth clock signal line, the 16d-11th level driving circuit is electrically connected to the fifth clock signal line, the 16d-19th level driving circuit is electrically connected to the sixth clock signal line, the 16d-9th level driving circuit is electrically connected to the seventh clock signal line, the 16d-8th level driving circuit is electrically connected to the eighth clock signal line, and the 16d-10th level driving circuit is electrically connected to the eighth clock signal line. The 6d-7 level driving circuit is electrically connected to the ninth clock signal line, the 16d-6 level driving circuit is electrically connected to the tenth clock signal line, the 16d-5 level driving circuit is electrically connected to the eleventh clock signal line, the 16d-4 level driving circuit is electrically connected to the twelfth clock signal line, the 16d-3 level driving circuit is electrically connected to the thirteenth clock signal line, the 16d-2 level driving circuit is electrically connected to the fourteenth clock signal line, the 16d-1 level driving circuit is electrically connected to the fifteenth clock signal line, and the 16d level driving circuit is electrically connected to the sixteenth clock signal line; d is a positive integer;

[0337] The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+8-th driving circuit, and the driving signal output terminal of the e+8-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

[0338] like Fig.11 As shown, in at least one embodiment of the utility model, the driving module includes a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, a sixth-level driving circuit GA6, a seventh-level driving circuit GA7, an eighth-level driving circuit GA8, a ninth-level driving circuit GA9, a tenth-level driving circuit GA10, an eleventh-level driving circuit GA11, a twelfth-level driving circuit GA12, a thirteenth-level driving circuit GA13, a fourteenth-level driving circuit GA14, a fifteenth-level driving circuit GA15 and a sixteenth-level driving circuit GA16;

[0339] GA1 is electrically connected to the first clock signal line CLK1, GA2 is electrically connected to the second clock signal line CLK2, GA3 is electrically connected to the third clock signal line CLK3, GA4 is electrically connected to the fourth clock signal line CLK4, GA5 is electrically connected to the fifth clock signal line CLK5, GA6 is electrically connected to the sixth clock signal line CLK6, GA7 is electrically connected to the seventh clock signal line CLK7, GA8 is electrically connected to the eighth clock signal line CLK8; GA9 is electrically connected to the ninth clock signal line CLK9, GA10 is electrically connected to the tenth clock signal line CLK10, GA11 is electrically connected to the eleventh clock signal line CLK11, GA12 is electrically connected to the twelfth clock signal line CLK12; GA13 is electrically connected to the thirteenth clock signal line CLK13, GA14 is electrically connected to the fourteenth clock signal line CLK14, GA15 is electrically connected to the fifteenth clock signal line CLK15, and GA16 is electrically connected to the sixteenth clock signal line CLK16;

[0340] The drive signal output terminal of GA1 is electrically connected to the input terminal of GA9, the drive signal output terminal of GA2 is electrically connected to the input terminal of GA10, the drive signal output terminal of GA3 is electrically connected to the input terminal of GA11, and the drive signal output terminal of GA4 is electrically connected to the input terminal of GA12; the drive signal output terminal of GA5 is electrically connected to the input terminal of GA13, the drive signal output terminal of GA6 is electrically connected to the input terminal of GA14, the drive signal output terminal of GA7 is electrically connected to the input terminal of GA15, and the drive signal output terminal of GA8 is electrically connected to the input terminal of GA16;

[0341] The drive signal output terminal of GA9 is electrically connected to the reset terminal of GA1, the drive signal output terminal of GA10 is electrically connected to the reset terminal of GA2, the drive signal output terminal of GA11 is electrically connected to the reset terminal of GA3, and the drive signal output terminal of GA12 is electrically connected to the reset terminal of GA4; the drive signal output terminal of GA13 is electrically connected to the reset terminal of GA5, the drive signal output terminal of GA14 is electrically connected to the reset terminal of GA6, the drive signal output terminal of GA15 is electrically connected to the reset terminal of GA7, and the drive signal output terminal of GA16 is electrically connected to the reset terminal of GA8.

[0342] exist Fig.11 Among them, the one labeled I1 is the input terminal, the one labeled OT is the drive signal output terminal, the one labeled RST is the reset terminal, and the one labeled CLK is the clock signal terminal.

[0343] The above is a preferred embodiment of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A pixel module, characterized in that: It includes multiple rows and columns of sub-pixels, multiple rows of scan lines and multiple columns of data lines; Two sub-pixels located in the nth row are arranged between the 2n-1th row scan line, the 2nth row scan line, the mth column scan line and the m+1th column scan line; n and m are positive integers; The sub-pixels are electrically connected to a row of scan lines and a column of data lines respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines; Among the sub-pixels electrically connected to the 2n-1th row of scan lines and the sub-pixels electrically connected to the 2n+1th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color; Among the sub-pixels electrically connected to the 2n-th row of scan lines and the sub-pixels electrically connected to the 2n+2-th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color.

2. The pixel module according to claim 1, wherein: The sub-pixels in the 4a-3 rows and the 6b-5 columns are electrically connected to the 8a-7 rows of scan lines and the 3b-2 columns of data lines, respectively, and are used to receive data voltages provided by the 3b-2 columns of data lines under the control of scan signals provided by the 8a-7 rows of scan lines; The sub-pixels in the 4a-3 row and the 6b-4 column are electrically connected to the 8a-6 row scan lines and the 3b-2 column data lines, respectively, and are used to receive data voltages provided by the 3b-2 column data lines under the control of scan signals provided by the 8a-6 row scan lines; The sub-pixels in the 4a-3 row and the 6b-3 column are electrically connected to the 8a-6 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-6 row scan line; The sub-pixels in the 4a-3 row and the 6b-2 column are electrically connected to the 8a-7 row scan lines and the 3b-1 data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-7 row scan lines; The sub-pixels in the 4a-3th row and the 6b-1th column are electrically connected to the 8a-6th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-6th row scan lines; The sub-pixels in the 4a-3 rows and the 6b columns are electrically connected to the 8a-7 rows of scan lines and the 3b column of data lines, respectively, and are used to receive data voltages provided by the 3b column of data lines under the control of scan signals provided by the 8a-7 rows of scan lines; a and b are positive integers.

3. The pixel module according to claim 2, wherein: The sub-pixels in the 4a-2 row and the 6b-5 column are electrically connected to the 8a-5 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-5 row scan line; The sub-pixels in the 4a-2 row and the 6b-4 column are electrically connected to the 8a-4 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-4 row scan line; The sub-pixels in the 4a-2 row and the 6b-3 column are electrically connected to the 8a-4 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-4 row scan line; The sub-pixels in the 4a-2 row and the 6b-2 column are electrically connected to the 8a-5 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-5 row scan line; The sub-pixels in the 4a-2th row and the 6b-1th column are electrically connected to the 8a-4th row scan line and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-4th row scan line; The sub-pixels in the 4a-2th row and the 6bth column are electrically connected to the 8a-5th row scan lines and the 3bth column data lines respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-5th row scan lines.

4. The pixel module according to claim 3, wherein: The sub-pixels in the 4a-1 row and the 6b-5 column are electrically connected to the 8a-3 row scan line and the 3b-1 column data line, respectively, and are used to receive a data voltage provided by the 3b-1 column data line under the control of a scan signal provided by the 8a-3 row scan line; The sub-pixels in the 4a-1 row and the 6b-4 column are electrically connected to the 8a-2 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-2 row scan line; The sub-pixels in the 4a-1 row and the 6b-3 column are electrically connected to the 8a-2 row scan line and the 3b column data line, respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-2 row scan line; The sub-pixels in the 4a-1 row and the 6b-2 column are electrically connected to the 8a-3 row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-3 row scan line; The sub-pixel in the 4a-1 row and the 6b-1 column is electrically connected to the 8a-2 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-2 row scan line; The sub-pixel in the 4a-1 row and the 6b column is electrically connected to the 8a-3 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-3 row scan line.

5. The pixel module according to claim 4, characterized in that: The sub-pixels in the 4a row and the 6b-5 columns are electrically connected to the 8a-1 row scan line and the 3b-1 column data line, respectively, and are used to receive a data voltage provided by the 3b-1 column data line under the control of a scan signal provided by the 8a-1 row scan line; The sub-pixels in the 4a row and the 6b-4 column are electrically connected to the 8a row scan line and the 3b-1 column data line respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a row scan line; The sub-pixels in the 4a row and the 6b-3 columns are electrically connected to the 8a row scan line and the 3b column data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a row scan line; The sub-pixels in the 4a row and the 6b-2 column are electrically connected to the 8a-1 row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-1 row scan line; The sub-pixels in the 4a row and the 6b-1 column are electrically connected to the 8a row scan line and the 3b+1 column data line respectively, and are used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a row scan line; The sub-pixel in the 4a row and 6b column is electrically connected to the 8a-1 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-1 row scan line.

6. The pixel module according to claim 1, wherein: The sub-pixels in the 4a-3 rows and the 6b-5 columns are electrically connected to the 8a-7 rows of scan lines and the 3b-2 columns of data lines, respectively, and are used to receive data voltages provided by the 3b-2 columns of data lines under the control of scan signals provided by the 8a-7 rows of scan lines; The sub-pixels in the 4a-3 row and the 6b-4 column are electrically connected to the 8a-6 row scan lines and the 3b-2 column data lines, respectively, and are used to receive data voltages provided by the 3b-2 column data lines under the control of scan signals provided by the 8a-6 row scan lines; The sub-pixels in the 4a-3 row and the 6b-3 column are electrically connected to the 8a-7 row scan lines and the 3b-1 column data lines, respectively, and are used to receive data voltages provided by the 3b-1 column data lines under the control of scan signals provided by the 8a-7 row scan lines; The sub-pixels in the 4a-3 row and the 6b-2 column are electrically connected to the 8a-6 row scan lines and the 3b-1 data lines, respectively, and are used to receive data voltages provided by the 3b-1 column data lines under the control of scan signals provided by the 8a-6 row scan lines; The sub-pixels in the 4a-3th row and the 6b-1th column are electrically connected to the 8a-7th row scan lines and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-7th row scan lines; The sub-pixels in the 4a-3rd row and the 6bth column are electrically connected to the 8a-6th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-6th row scan lines; a and b are positive integers.

7. The pixel module according to claim 6, wherein: The sub-pixels in the 4a-2 row and the 6b-5 column are electrically connected to the 8a-5 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-5 row scan line; The sub-pixels in the 4a-2 row and the 6b-4 column are electrically connected to the 8a-4 row scan line and the 3b-2 column data line, respectively, and are used to receive the data voltage provided by the 3b-2 column data line under the control of the scan signal provided by the 8a-4 row scan line; The sub-pixels in the 4a-2 row and the 6b-3 column are electrically connected to the 8a-5 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-5 row scan line; The sub-pixels in the 4a-2 row and the 6b-2 column are electrically connected to the 8a-4 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-4 row scan line; The sub-pixels in the 4a-2th row and the 6b-1th column are electrically connected to the 8a-5th row scan lines and the 3bth column data lines, respectively, and are used to receive data voltages provided by the 3bth column data lines under the control of scan signals provided by the 8a-5th row scan lines; The sub-pixels in the 4a-2 row and the 6b column are electrically connected to the 8a-4 row scan line and the 3b column data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-4 row scan line.

8. The pixel module according to claim 7, wherein: The sub-pixels in the 4a-1 row and the 6b-5 column are electrically connected to the 8a-3 row scan line and the 3b-1 column data line, respectively, and are used to receive a data voltage provided by the 3b-1 column data line under the control of a scan signal provided by the 8a-3 row scan line; The sub-pixels in the 4a-1 row and the 6b-4 column are electrically connected to the 8a-2 row scan line and the 3b-1 column data line, respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a-2 row scan line; The sub-pixels in the 4a-1th row and the 6b-3th column are electrically connected to the 8a-3th row scan line and the 3bth column data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-3th row scan line; The sub-pixels in the 4a-1th row and the 6b-2th column are electrically connected to the 8a-2th row scan line and the 3bth data line, respectively, and are used to receive the data voltage provided by the 3bth column data line under the control of the scan signal provided by the 8a-2th row scan line; The sub-pixel in the 4a-1 row and the 6b-1 column is electrically connected to the 8a-3 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-3 row scan line; The sub-pixel in the 4a-1 row and the 6b column is electrically connected to the 8a-2 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-2 row scan line.

9. The pixel module according to claim 8, wherein: The sub-pixels in the 4a row and the 6b-5 columns are electrically connected to the 8a-1 row scan line and the 3b-1 column data line, respectively, and are used to receive a data voltage provided by the 3b-1 column data line under the control of a scan signal provided by the 8a-1 row scan line; The sub-pixels in the 4a row and the 6b-4 column are electrically connected to the 8a row scan line and the 3b-1 column data line respectively, and are used to receive the data voltage provided by the 3b-1 column data line under the control of the scan signal provided by the 8a row scan line; The sub-pixels in the 4a row and the 6b-3 column are electrically connected to the 8a-1 row scan line and the 3b column data line, respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a-1 row scan line; The sub-pixels in the 4a row and the 6b-2 column are electrically connected to the 8a row scan line and the 3b data line respectively, and are used to receive the data voltage provided by the 3b column data line under the control of the scan signal provided by the 8a row scan line; The sub-pixel in the 4a row and the 6b-1 column is electrically connected to the 8a-1 row scan line and the 3b+1 column data line respectively, and is used to receive the data voltage provided by the 3b+1 column data line under the control of the scan signal provided by the 8a-1 row scan line; The sub-pixel in row 4a and column 6b is electrically connected to the scan line in row 8a and the data line in column 3b+1 respectively, and is used to receive the data voltage provided by the data line in column 3b+1 under the control of the scan signal provided by the scan line in row 8a.

10. The pixel module according to any one of claims 1 to 9, characterized in that: The sub-pixels located in the 3b-2 column have the first color, the sub-pixels located in the 3b-1 column have the second color, and the sub-pixels located in the 3b column have the second color.

11. A display device, characterized in that: The invention comprises the pixel module as claimed in any one of claims 1 to 10.

12. The display device according to claim 11, wherein: Also includes a driving module; the driving module includes eight clock signal lines and a multi-stage driving circuit; The 8d-7th level driving circuit is electrically connected to the first clock signal line, the 8d-6th level driving circuit is electrically connected to the second clock signal line, the 8d-5th level driving circuit is electrically connected to the third clock signal line, the 8d-4th level driving circuit is electrically connected to the fourth clock signal line, the 8d-3th level driving circuit is electrically connected to the fifth clock signal line, the 8d-2th level driving circuit is electrically connected to the sixth clock signal line, the 8d-1th level driving circuit is electrically connected to the seventh clock signal line, and the 8d-level driving circuit is electrically connected to the eighth clock signal line; d is a positive integer; The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+4-th driving circuit, and the driving signal output terminal of the e+4-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

13. The display device according to claim 11, wherein: Also includes a driving module; the driving module includes twelve clock signal lines and a multi-stage driving circuit; The 12d-11th level driving circuit is electrically connected to the first clock signal line, the 12d-10th level driving circuit is electrically connected to the second clock signal line, the 12d-9th level driving circuit is electrically connected to the third clock signal line, the 12d-8th level driving circuit is electrically connected to the fourth clock signal line, the 12d-7th level driving circuit is electrically connected to the fifth clock signal line, the 12d-6th level driving circuit is electrically connected to the sixth clock signal line, the 12d-5th level driving circuit is electrically connected to the seventh clock signal line, the 12d-4th level driving circuit is electrically connected to the eighth clock signal line, the 12d-3th level driving circuit is electrically connected to the ninth clock signal line, the 12d-2th level driving circuit is electrically connected to the tenth clock signal line, the 12d-1th level driving circuit is electrically connected to the eleventh clock signal line, and the 12d-1th level driving circuit is electrically connected to the twelfth clock signal line; d is a positive integer; The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+4-th driving circuit, and the driving signal output terminal of the e+4-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

14. The display device according to claim 11, wherein: Also includes a driving module; the driving module includes sixteen clock signal lines and a multi-stage driving circuit; The 16d-15th level driving circuit is electrically connected to the first clock signal line, the 16d-14th level driving circuit is electrically connected to the second clock signal line, the 16d-13th level driving circuit is electrically connected to the third clock signal line, the 16d-12th level driving circuit is electrically connected to the fourth clock signal line, the 16d-11th level driving circuit is electrically connected to the fifth clock signal line, the 16d-19th level driving circuit is electrically connected to the sixth clock signal line, the 16d-9th level driving circuit is electrically connected to the seventh clock signal line, the 16d-8th level driving circuit is electrically connected to the eighth clock signal line, and the 16d-10th level driving circuit is electrically connected to the eighth clock signal line. The 6d-7 level driving circuit is electrically connected to the ninth clock signal line, the 16d-6 level driving circuit is electrically connected to the tenth clock signal line, the 16d-5 level driving circuit is electrically connected to the eleventh clock signal line, the 16d-4 level driving circuit is electrically connected to the twelfth clock signal line, the 16d-3 level driving circuit is electrically connected to the thirteenth clock signal line, the 16d-2 level driving circuit is electrically connected to the fourteenth clock signal line, the 16d-1 level driving circuit is electrically connected to the fifteenth clock signal line, and the 16d level driving circuit is electrically connected to the sixteenth clock signal line; d is a positive integer; The driving signal output terminal of the e-th driving circuit is electrically connected to the input terminal of the e+8-th driving circuit, and the driving signal output terminal of the e+8-th driving circuit is electrically connected to the reset terminal of the e-th driving circuit; e is a positive integer.

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