BCD device

Abstract

The utility model discloses a BCD device. The BCD device comprises a substrate of a first doping type; the epitaxial layer of the first doping type is located on the substrate, and a first LDMOS structure, a low-voltage NMOS structure, a low-voltage PMOS structure and an NPN structure are formed in the epitaxial layer; the first field oxide and the second field oxide are located on the surface of the epitaxial layer, and the thickness of the first field oxide is larger than that of the second field oxide; wherein in the first LDMOS structure, the first field oxide and the second field oxide are located between a source ohmic contact region and a drain ohmic contact region of the first LDMOS structure, the first field oxide and the second field oxide are in contact with each other, and the second field oxide is close to one side of the source ohmic contact region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a BCD device. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic IC manufacturing process that combines Bipolar (bipolar junction transistor) devices, CMOS (Complementary Metal Oxide Semiconductor) devices and DMOS (Double-diffused Metal Oxide Semiconductor) devices. According to industry standards, BCD technology is generally divided into high-voltage BCD, high-density BCD and high-power BCD. Different BCD processes can be further subdivided according to different voltage specifications. Among them, the BCD process with a voltage specification of 25V to 120V is widely used in the development and manufacture of DC-DC power supplies and motor drive products.

[0003] In the BCD process, low-voltage CMOS (Complementary Metal Oxide Semiconductor) devices are used to implement logic signal processing, Bipolar (bipolar junction transistor) devices provide signal gain and power amplification, and DMOS (Double-diffused Metal Oxide Semiconductor) devices need to bear very high reverse voltage and output large current, and often occupy a larger chip area. Improving the efficiency of DMOS devices can reduce costs, but the accompanying reliability issues need to be paid special attention.

[0004] In the BCD process, the LDMOS (Lateral Double-diffused MOSFET) device is a power device with electrodes on the surface of the silicon wafer. It has good compatibility with the Bipolar process and CMOS process, and has both high voltage resistance and large current output capabilities. It is a very important type of device in the BCD process.

[0005] Since the BCD process is a universal process that includes devices of various voltage levels, when designing high-voltage devices, the setting of some process conditions often sacrifices the performance of low-voltage devices. Utility Model Content

[0006] In view of the above problems, the purpose of this application is to provide a BCD device that can effectively solve the above technical problems based on the demand for high-performance and high-reliability devices and processes.

[0007] According to one aspect of the present invention, a BCD device is provided, comprising: a substrate of a first doping type; an epitaxial layer of the first doping type, located on the substrate, a first LDMOS structure, a low-voltage NMOS structure, a low-voltage PMOS structure and an NPN structure formed in the epitaxial layer; and a first field oxygen and a second field oxygen, located on the surface of the epitaxial layer, the thickness of the first field oxygen being greater than the thickness of the second field oxygen; wherein, in the first LDMOS structure, the first field oxygen and the second field oxygen are located between a source ohmic contact region and a drain ohmic contact region of the first LDMOS structure, the first field oxygen and the second field oxygen are in contact with each other, the second field oxygen is close to one side of the source ohmic contact region and is not in contact with the source ohmic contact region of the first LDMOS structure, and the first field oxygen is close to one side of the drain ohmic contact region of the first LDMOS structure and is adjacent to the drain ohmic contact region of the first LDMOS structure.

[0008] Optionally, the low-voltage NMOS structure, the low-voltage PMOS structure, and the NPN structure all include the first field oxygen and the second field oxygen.

[0009] Optionally, the low-voltage NMOS structure, the low-voltage PMOS structure and the NPN structure include the first field oxygen or the second field oxygen.

[0010] Optionally, in the low-voltage NMOS structure, the second field oxygen is located between the source ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, and is adjacent to the source ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, respectively; the second field oxygen is also located between the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, and is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, respectively.

[0011] Optionally, in the low-voltage PMOS structure, the second field oxygen is located between the source ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, and is adjacent to the source ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, respectively; the second field oxygen is also located between the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, and is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, respectively.

[0012] Optionally, in the NPN structure, the first field oxygen is located between the base ohmic contact region and the collector ohmic contact region of the NPN structure, and is adjacent to the base ohmic contact region and the collector ohmic contact region of the NPN structure, respectively; the second field oxygen is located between the emitter ohmic contact region and the base ohmic contact region of the NPN structure, and is adjacent to the emitter ohmic contact region and the base ohmic contact region of the NPN structure, respectively; or, the second field oxygen is located between the base ohmic contact region and the collector ohmic contact region of the NPN structure, and is adjacent to the base ohmic contact region and the collector ohmic contact region of the NPN structure, respectively, and the second field oxygen is also located between the emitter ohmic contact region and the base ohmic contact region of the NPN structure, and is adjacent to the emitter ohmic contact region and the base ohmic contact region of the NPN structure, respectively.

[0013] Optionally, the first LDMOS structure includes: a buried layer of a second doping type, located on the substrate, the second doping type is opposite to the first doping type; an epitaxial layer of a first doping type, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a drift region of a second doping type, located in the epitaxial layer and both sides of the drift region extend laterally into the high-voltage well; a second low-voltage well of a second doping type, located in the high-voltage well of the first LDMOS structure; a body region of a first doping type, located in the drift region of the first LDMOS structure; a source ohmic contact region of a second doping type, located in the first LDMOS structure In the body region, a drain ohmic contact region of the second doping type is located in the second low-voltage well of the first LDMOS structure; a body electrode ohmic contact region of the first doping type is located in the body region of the first LDMOS structure and is adjacent to the source ohmic contact region; a gate stack structure is located between the source ohmic contact region and the drain ohmic contact region of the first LDMOS structure; the gate stack structure includes: a gate oxide layer, located between the source ohmic contact region and the second field oxygen of the first LDMOS structure and adjacent to the source ohmic contact region and the second field oxygen of the first LDMOS structure; and a gate polycrystalline, covering the gate oxide layer, the second field oxygen and a portion of the first field oxygen of the first LDMOS structure.

[0014] Optionally, the low-voltage NMOS structure includes: an epitaxial layer of a first doping type, located on the substrate; a first low-voltage well of the first doping type, located in the epitaxial layer; a source ohmic contact region, a drain ohmic contact region and a body electrode ohmic contact region of a second doping type, located in the first low-voltage well of the low-voltage NMOS structure.

[0015] Optionally, the low-voltage PMOS structure includes: an epitaxial layer of a first doping type, located on the substrate; a second low-voltage well of a second doping type, located in the epitaxial layer; a first low-voltage well of a first doping type, located in the epitaxial layer, and the first low-voltage well is located on both sides of the second low-voltage well and separated from the second low-voltage well; a source ohmic contact region, a drain ohmic contact region and a body electrode ohmic contact region of a first doping type, located in the second low-voltage well of the low-voltage PMOS structure; a substrate electrode ohmic contact region of a first doping type, located in the first low-voltage well of the low-voltage PMOS structure; a first field oxygen or a second field oxygen, located between the substrate electrode ohmic contact region of the low-voltage PMOS structure and the body electrode ohmic contact region of the low-voltage PMOS structure, and adjacent to the substrate electrode ohmic contact region of the low-voltage PMOS structure and the body electrode ohmic contact region of the low-voltage PMOS structure, respectively.

[0016] Optionally, the NPN structure includes: a buried layer of a second doping type, located on the substrate; an epitaxial layer, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and a bottom of which is in contact with the buried layer; a first low-voltage well of a first doping type and a second low-voltage well of a second doping type, located in the high-voltage well of the NPN structure, and the second low-voltage well is located on both sides of the first low-voltage well and separated from each other; a collector ohmic contact region of a second doping type, located in the second low-voltage well of the NPN structure; a base ohmic contact region of a first doping type and an emitter ohmic contact region of a second doping type, located in the first low-voltage well of the NPN structure.

[0017] Optionally, a second LDMOS structure is also included, wherein the second LDMOS structure includes: the buried layer of the second doping type, located on the substrate, the second doping type is opposite to the first doping type; the epitaxial layer of the first doping type, located on the buried layer; a high-voltage well of the second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a drift region of the second doping type, located in the epitaxial layer and both sides of the drift region extend laterally into the high-voltage well; a second low-voltage well of the second doping type, located in the high-voltage well of the second LDMOS structure; a body region of the first doping type, located in the drift region of the second LDMOS structure; a source ohmic contact region of the second doping type, located in the body region of the second LDMOS structure, and a drain ohmic contact region of the second doping type, located in the second LDMO The invention relates to a second low voltage well of an S structure; a body electrode ohmic contact region of a first doping type, located in the body region of the second LDMOS structure and adjacent to the source ohmic contact region; a gate stack structure, located between the source ohmic contact region and the drain ohmic contact region of the second LDMOS structure; and a second field oxide with a second thickness, located between the source ohmic contact region and the drain ohmic contact region of the second LDMOS structure and adjacent to the drain ohmic contact region of the second LDMOS structure; the gate stack structure comprises a gate oxide layer and a gate polycrystalline, the gate oxide layer is located between the source ohmic contact region and the second field oxide of the second LDMOS structure and adjacent to the source ohmic contact region and the second field oxide of the second LDMOS structure, and the gate polycrystalline covers the gate oxide layer and a portion of the second field oxide of the second LDMOS structure.

[0018] Optionally, a first DENMOS structure is also included, wherein the first DENMOS structure includes: an epitaxial layer of a first doping type, located on the substrate; a first low-voltage well of the first doping type and a second low-voltage well of the second doping type, located in the epitaxial layer and separated from each other; a drain ohmic contact region of the second doping type, located in the second low-voltage well of the first DENMOS structure; a body electrode ohmic contact region of the first doping type and a source ohmic contact region of the second doping type, located in the first low-voltage well of the first DENMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the first DENMOS structure; a first field oxide having a first thickness, located between the source ohmic contact region and the drain ohmic contact region of the first DENMOS structure, wherein the first DENMOS structure The first field oxide has one side adjacent to the drain ohmic contact region of the first DENMOS structure and the other side not in contact with the source ohmic contact region of the first DENMOS structure; and a second field oxide with a second thickness is located between the body electrode ohmic contact region and the source ohmic contact region of the first DENMOS structure, and the second field oxide of the first DENMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the first DENMOS structure respectively; the gate stack structure includes a gate oxide layer and a gate polycrystalline, the gate oxide layer is located between the source ohmic contact region of the first DENMOS structure and the first field oxide and is adjacent to the source ohmic contact region and the first field oxide of the first DENMOS structure, and the gate polycrystalline covers the gate oxide layer and a portion of the first field oxide of the first DENMOS structure.

[0019] Optionally, a second DENMOS structure is also included, wherein the second DENMOS structure includes: an epitaxial layer of a first doping type, located on the substrate; a first low-voltage well of the first doping type and a second low-voltage well of the second doping type, located in the epitaxial layer and separated from each other; a drain ohmic contact region of the second doping type, located in the second low-voltage well of the second DENMOS structure; a body electrode ohmic contact region of the first doping type and a source ohmic contact region of the second doping type, located in the first low-voltage well of the second DENMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the second DENMOS structure, the gate stack structure including a gate oxide layer and a gate polycrystalline; and a second field oxide having a second thickness, located in the second DENMOS The second field oxygen between the source ohmic contact region and the drain ohmic contact region of the second DENMOS structure and between the body electrode ohmic contact region and the source ohmic contact region of the second DENMOS structure; one side of the second field oxygen between the source ohmic contact region and the drain ohmic contact region of the second DENMOS structure is adjacent to the drain ohmic contact region of the second DENMOS structure, and the other side is adjacent to the gate oxide layer, and the gate polycrystalline covers the gate oxide layer of the second DENMOS structure and part of the second field oxygen between the source ohmic contact region and the drain ohmic contact region of the second DENMOS structure; the second field oxygen between the body electrode ohmic contact region and the source ohmic contact region of the second DENMOS structure are adjacent to the body electrode ohmic contact region and the source ohmic contact region of the second DENMOS structure respectively.

[0020] Optionally, it also includes a first DEPMOS structure, which includes: a buried layer of a second doping type, located on the substrate, the second doping type is opposite to the first doping type; an epitaxial layer of a first doping type, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a first low-voltage well of the first doping type and a second low-voltage well of the second doping type, located in the high-voltage well of the first DEPMOS structure, the second low-voltage well being located on both sides of the first low-voltage well and separated from each other; a drain ohmic contact region of the first doping type, located in the first low-voltage well of the first DEPMOS structure; a body electrode ohmic contact region of the second doping type and a source ohmic contact region of the first doping type, located in the second low-voltage well of the first DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the first DEPMOS structure, the gate stack structure including a gate oxide layer and a gate polycrystalline; and a first field oxide having a first thickness, located in the The first DEPMOS structure is provided with a first field oxide between the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure and between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure, one side of the first field oxide between the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure is adjacent to the drain ohmic contact region of the first DEPMOS structure, and the other side is adjacent to the gate oxide layer, the gate polycrystalline covers the gate oxide layer of the first DEPMOS structure and a part of the first field oxide between the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure, the first field oxide between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure respectively; and a second field oxide with a second thickness is located between the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure, and is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure respectively.

[0021] Optionally, it also includes a first DEPMOS structure, which includes: a buried layer of a second doping type, located on the substrate, the second doping type is opposite to the first doping type; an epitaxial layer of a first doping type, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a first low-voltage well of the first doping type and a second low-voltage well of the second doping type, located in the high-voltage well of the first DEPMOS structure, the second low-voltage well being located on both sides of the first low-voltage well and separated from each other; a drain ohmic contact region of the first doping type, located in the first low-voltage well of the first DEPMOS structure; a body electrode ohmic contact region of the second doping type and a source ohmic contact region of the first doping type, located in the second low-voltage well of the first DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the first DEPMOS structure, the gate stack structure including a gate oxide layer and a gate polycrystalline; a first A field oxygen is located between the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure, one side of the first field oxygen of the first DEPMOS structure is adjacent to the drain ohmic contact region of the first DEPMOS structure, and the other side is adjacent to the gate oxide layer, and the gate polycrystalline covers the gate oxide layer of the first DEPMOS structure and part of the first field oxygen; and a second field oxygen with a second thickness is located between the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure and between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure, the second field oxygen between the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure respectively, and the second field oxygen between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure respectively.

[0022] Optionally, a second DEPMOS structure is also included, wherein the second DEPMOS structure includes: a buried layer of a second doping type, located on the substrate, the second doping type is opposite to the first doping type; an epitaxial layer of a first doping type, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a first low-voltage well of the first doping type and a second low-voltage well of the second doping type, located in the high-voltage well of the second DEPMOS structure, the second low-voltage well being located on both sides of the first low-voltage well and separated from each other; a drain ohmic contact region of the first doping type, located in the first low-voltage well of the second DEPMOS structure; a body electrode ohmic contact region of the second doping type and a source ohmic contact region of the first doping type, located in the second low-voltage well of the second DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure, the gate stack structure comprising a gate oxide layer and a gate polycrystalline; and a second field oxide having a second thickness, located at the second DEPMOS junction The second field oxide between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure, between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure, and between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure; one side of the second field oxide between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the drain ohmic contact region of the second DEPMOS structure, and the other side is adjacent to the gate oxide layer, and the gate polycrystalline covers the gate oxide layer of the second DEPMOS structure and part of the second field oxide between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure; the second field oxide between the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure respectively; the second field oxide between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure respectively.

[0023] Optionally, a second DEPMOS structure is also included, wherein the second DEPMOS structure includes: a buried layer of a second doping type, located on the substrate, the second doping type is opposite to the first doping type; an epitaxial layer of a first doping type, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a first low-voltage well of the first doping type and a second low-voltage well of the second doping type, located in the high-voltage well of the second DEPMOS structure, the second low-voltage well being located on both sides of the first low-voltage well and separated from each other; a drain ohmic contact region of the first doping type, located in the first low-voltage well of the second DEPMOS structure; a body electrode ohmic contact region of the second doping type and a source ohmic contact region of the first doping type, located in the second low-voltage well of the second DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure, the gate stack structure including a gate oxide layer and a gate polycrystalline; and a first field oxide having a first thickness, located The second field oxygen having a second thickness is located between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure and between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure; the second field oxygen between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the drain ohmic contact region of the second DEPMOS structure on one side and adjacent to the gate oxide layer on the other side, and the gate polycrystalline covers the gate oxide layer of the second DEPMOS structure and part of the second field oxygen between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure; the second field oxygen between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure, respectively.

[0024] Optionally, a PNP structure is also included, wherein the PNP structure includes: a buried layer of a second doping type, located on the substrate; an epitaxial layer, located on the buried layer; a high-voltage well of a second doping type, located in the epitaxial layer, and its bottom is in contact with the buried layer; a first low-voltage well of a first doping type, located in the high-voltage well of the PNP structure and in the epitaxial layer outside the high-voltage well of the PNP structure; a base ohmic contact region of a second doping type, located in the high-voltage well of the PNP structure; an emitter ohmic contact region of a first doping type, located in the first low-voltage well within the high-voltage well in the PNP structure; and a collector ohmic contact region of a first doping type. , located in the first low-voltage well in the epitaxial layer in the PNP structure; a second field oxygen with a second thickness is located between the base ohmic contact region and the collector ohmic contact region of the PNP structure, and between the emitter ohmic contact region and the base ohmic contact region of the PNP structure; the second field oxygen between the base ohmic contact region and the collector ohmic contact region of the PNP structure is respectively adjacent to the base ohmic contact region and the collector ohmic contact region of the PNP structure; the second field oxygen between the emitter ohmic contact region and the base ohmic contact region of the PNP structure is respectively adjacent to the emitter ohmic contact region and the base ohmic contact region of the PNP structure.

[0025] Optionally, the thickness of the first field oxygen is 4000 angstroms to 5000 angstroms, and the thickness of the second field oxygen is 2000 angstroms to 3000 angstroms.

[0026] Optionally, the first LDMOS structure, the low-voltage NMOS structure, the low-voltage PMOS structure and the NPN structure are separated by an isolation structure, and the isolation structure includes a DTI isolation structure and / or a LOCOS isolation structure.

[0027] In the BCD device of the embodiment of the present application, the source ohmic contact region and the drain ohmic contact region of the high-voltage LDMOS structure are isolated by thin field oxygen (second field oxygen) and thick field oxygen (first field oxygen), and the second field oxygen is close to one side of the source ohmic contact region, and the first field oxygen is added on the side close to the drain ohmic contact region, so that the performance and reliability of the high-voltage LDMOS structure are guaranteed.

[0028] In the BCD device of the embodiment of the present application, the source ohmic contact region and the drain ohmic contact region of the high-voltage LDMOS structure are isolated by thin field oxygen (second field oxygen) and thick field oxygen (first field oxygen), and the second field oxygen is close to one side of the source ohmic contact region, the gate conductor completely covers the thin field oxygen (second field oxygen), and the end of the gate conductor away from the source ohmic contact region is located on the thick field oxygen (first field oxygen); when the high-voltage LDMOS structure is reversely withstand voltage, the field plate auxiliary depletion effect at the thin field oxygen (second field oxygen) is stronger, and the end of the field plate away from the source ohmic contact region will not introduce an excessively high electric field inside the drift region, taking into account both the performance and reliability of the high-voltage LDMOS structure.

[0029] In the BCD device of the embodiment of the present application, two thicknesses of field oxygen can be selectively set. Thin field oxygen (second field oxygen) is used inside the low-voltage structure. The thin field oxygen (second field oxygen) can significantly reduce the rules of the low-voltage structure and reduce the layout area. Thick field oxygen (first field oxygen) is used in areas where high-voltage cross-lines exist to meet field-on design requirements.

[0030] All first field oxygens in the BCD device of the embodiment of the present application are formed simultaneously, and all second field oxygens are formed simultaneously. Only one more photolithography and etching step is required to form field oxygens of two different thicknesses. The method is simple.

[0031] The high-voltage structure of the embodiment of the present application uses thick field oxygen, which can effectively reduce the surface electric field of the structure and improve reliability; the low-voltage structure uses thin field oxygen, the depletion effect of the polycrystalline field plate is stronger, and the on-resistance is smaller under the same withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0033] Figure 1a to Figure 1d A cross-sectional schematic diagram of a BCD device according to a first embodiment of the present application is shown;

[0034] Figure 2 Shows Figure 1a An enlarged structural diagram of the first LDMOS structure;

[0035] Figure 3 Shows Figure 1a An enlarged structural diagram of the second LDMOS structure;

[0036] Figure 4 Shows Figure 1b A magnified schematic diagram of the low and medium voltage NMOS structure;

[0037] Figure 5 Shows Figure 1b A magnified schematic diagram of the low and medium voltage PMOS structure;

[0038] Figure 6 Shows Figure 1b A schematic diagram of the enlarged structure of the first DENMOS structure;

[0039] Figure 7 Shows Figure 1c A schematic diagram of the enlarged structure of the second DENMOS structure;

[0040] Figure 8 Shows Figure 1c A schematic diagram of the enlarged structure of the first DEPMOS structure;

[0041] Fig. 9 Shows Figure 1c A schematic diagram of the enlarged structure of the second DEPMOS structure;

[0042] Fig.10 Shows Figure 1d A schematic diagram of the enlarged structure of the NPN structure;

[0043] Fig.11 Shows Figure 1d A schematic diagram of the enlarged structure of the PNP structure;

[0044] Figures 12a to 12d A cross-sectional schematic diagram of a BCD device according to a second embodiment of the present application is shown;

[0045] Fig.13 Shows Figure 12b A magnified schematic diagram of the low and medium voltage PMOS structure;

[0046] Fig.14 Shows Fig.12c A schematic diagram of the enlarged structure of the first DEPMOS structure;

[0047] Fig.15 Shows Fig.12c A schematic diagram of the enlarged structure of the second DEPMOS structure;

[0048] Fig.16 Shows Fig.12d A schematic diagram of the enlarged structure of the NPN structure;

[0049] Fig.17 A schematic diagram of the circuit principle of a pre-voltage stabilization circuit is shown. DETAILED DESCRIPTION

[0050] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0051] This application may be presented in a variety of forms, some examples of which are described below.

[0052] In the BCD process, LDMOS structures with different withstand voltages are set to meet the needs of products with different voltage levels. When two LDMOS structures with different withstand voltages exist in a product, in order to save costs, the high-voltage and low-voltage LDMOS structures usually differ only in the length of the drift region; in order to meet the withstand voltage and reliability of the high-voltage LDMOS structure, the performance of the low-voltage LDMOS structure is often sacrificed; when the voltage span is large, such sacrifice is more obvious.

[0053] In view of the above problems, an embodiment of the present application provides a BCD device, in which a thin field oxygen (second field oxygen) and a thick field oxygen (first field oxygen) are arranged inside the drift region of the high-voltage LDMOS structure, and a thin field oxygen (second field oxygen) is arranged inside the drift region of the low-voltage LDMOS structure, so that the performance and reliability of the BCD device are guaranteed.

[0054] Figure 1a to Figure 1d FIG. 4 is a cross-sectional schematic diagram showing a BCD device according to a first embodiment of the present application. Figure 1a to Figure 1d FIG. 4 shows a partial structure of a BCD device according to a first embodiment of the present application; Figure 1a to Figure 1d As shown, the BCD device includes a substrate 101 of a first doping type, a buried layer 102 of a second doping type, an epitaxial layer 103 of a first doping type, and an isolation structure. The first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping.

[0055] The buried layer 102 is located on the substrate 101, covering part of the surface of the substrate 101, and the epitaxial layer 103 is located on the substrate 101 and the buried layer 102, covering the surface of the substrate 101 and the surface of the buried layer 102. The isolation structure includes a DTI (Deep Trench Isolation) isolation structure and / or a LOCOS (Local Oxidation of Silicon) isolation structure. The DTI isolation structure extends from the surface of the epitaxial layer 103 toward the substrate 101, penetrates the epitaxial layer 103 or the epitaxial layer 103 and the buried layer 102, and extends to the inside of the substrate 101. The isolation structure isolates the epitaxial layer 103 into multiple regions to form a corresponding semiconductor structure in each region.

[0056] In this embodiment, the isolation structure includes a DTI isolation structure and a LOCOS isolation structure, and each semiconductor structure is isolated by the DTI isolation structure and the LOCOS isolation structure, and the LOCOS isolation structure is located on both sides of the DTI isolation structure. The DTI isolation structure includes a trench extending from the surface of the epitaxial layer 103 to the substrate 101, an oxide layer located inside the trench, and a polysilicon layer 107. The LOCOS isolation structure is, for example, a first field oxide 108a.

[0057] The BCD device at least includes a first LDMOS structure, a low voltage NMOS structure, a low voltage PMOS structure, and an NPN structure located on the same substrate 101. In this embodiment, the BCD device includes a first LDMOS structure, a second LDMOS structure, a first DENMOS (Drain Extended NMOS, drain extended N-type field effect transistor) structure, a second DENMOS structure, a first DEPMOS (Drain Extended PMOS, drain extended P-type field effect transistor) structure, a second DEPMOS structure, a low voltage NMOS structure, a low voltage PMOS structure, an NPN structure, and a PNP structure located on the same substrate 101. Among them, the first LDMOS structure is, for example, a high-voltage NLDMOS structure (HV NLDMOS), the second LDMOS structure is, for example, a low-voltage NLDMOS structure (LV NLDMOS), the first DENMOS structure is, for example, a high-voltage DENMOS structure (HV DENMOS), the second DENMOS structure is, for example, a low-voltage DENMOS structure (LV DENMOS), the first DEPMOS structure is, for example, a high-voltage DEPMOS structure (HV DEPMOS), and the second DEPMOS structure is, for example, a low-voltage DEPMOS (LV DEPMOS) structure.

[0058] Figure 2 Shows Figure 1a FIG. 1 is a schematic diagram of an enlarged structure of the first LDMOS structure; FIG. Figure 1a and Figure 2 As shown, the first LDMOS structure includes a substrate 101 of a first doping type, a buried layer 102 of a second doping type, an epitaxial layer 103 of a first doping type, a high-voltage well 104 of a second doping type, and a drift region.

[0059] The buried layer 102 is located on the substrate 101 and covers the surface of the substrate 101. The epitaxial layer 103 is located on the buried layer 102 and covers the surface of the buried layer 102. The high-voltage well 104 extends from the surface of the epitaxial layer 103 to the inside thereof, and the bottom is in contact with the buried layer 102. The adjacent high-voltage wells 104 and the buried layer 102 form a U-shaped isolation structure. The drift region includes a first drift region 110 of a first doping type and a second drift region 111 of a second doping type. The drift region is located in the epitaxial layer 103 defined by the adjacent high-voltage wells 104 and the buried layer 102, and both sides of the drift region extend laterally into the high-voltage well 104, and both sides of the drift region contact the second low-voltage well 113 in the high-voltage well 104. Specifically, the first drift region 110 is located in the epitaxial layer 103 defined by the adjacent high-voltage wells 104 and the buried layer 102, and the first drift region 110 extends laterally into the high-voltage wells 104 on both sides thereof. The second drift region 111 is located on the first drift region 110 , and its bottom contacts the first drift region 110 . The second drift region 111 extends laterally into the high pressure well 104 on both sides thereof, and its two sides contact the second low pressure well 113 located in the high pressure well 104 .

[0060] The first LDMOS structure includes a second low voltage well 113 of the second doping type and a body region 116 of the first doping type. The second low voltage well 113 is located in the high voltage well 104 , and the body region 116 is located in the drift region, specifically in the second drift region 111 .

[0061] The first LDMOS structure includes a second ohmic contact region 118 of a first doping type and a first ohmic contact region 117 of a second doping type, wherein the first ohmic contact region 117 of a second doping type is located in the second low voltage well 113 and the body region 116, and the second ohmic contact region 118 of a first doping type is located in the body region 116 and is adjacent to the first ohmic contact region 117 located in the body region 116. The first ohmic contact region 117 located in the second low voltage well 113 constitutes a drain ohmic contact region of the first LDMOS structure, the first ohmic contact region 117 located in the body region 116 constitutes a source ohmic contact region of the first LDMOS structure, and the second ohmic contact region 118 located in the body region 116 constitutes a body electrode ohmic contact region of the first LDMOS structure. The source ohmic contact region of the first LDMOS structure is isolated from the substrate 101 via an isolation structure formed by the high voltage well 104 and the buried layer 102.

[0062] The first LDMOS structure includes a field oxide layer located on the surface of the epitaxial layer 103, the field oxide layer includes a first field oxide 108 having a first thickness and a second field oxide 109 having a second thickness, wherein the first thickness is greater than the second thickness. In one embodiment, the first thickness is 4000 angstroms to 5000 angstroms, and the second thickness is 2000 angstroms to 3000 angstroms. The first field oxygen 108 and the second field oxygen 109 are located between the first ohmic contact region 117 (source ohmic contact region) in the body region 116 and the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113. The first field oxygen 108 and the second field oxygen 109 are in contact with each other on the sides close to each other. The second field oxygen 109 is close to the first ohmic contact region 117 (source ohmic contact region) in the body region 116 and is not in contact with the first ohmic contact region 117 (source ohmic contact region) in the body region 116. The first field oxygen 108 is close to the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 and is adjacent to the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113.

[0063] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 and the DTI isolation structure.

[0064] The first LDMOS structure includes a gate oxide layer 114 and a gate polycrystalline 115, and the gate oxide layer 114 and the gate polycrystalline 115 constitute a gate stack structure. The gate oxide layer 114 is located on the epitaxial layer 103 between the first ohmic contact region 117 (source ohmic contact region) in the body region 116 and the second field oxygen 109, and one side of the gate oxide layer 114 is adjacent to the first ohmic contact region 117 (source ohmic contact region) in the body region 116, and the other side is in contact with the second field oxygen 109. The gate polycrystalline 115 covers the gate oxide layer 114, the second field oxygen 109 and part of the first field oxygen 108. In other words, one end of the gate polycrystalline 115 is tangent to the first ohmic contact region 117 (source ohmic contact region) in the body region 116, and the other end extends to the top of the first field oxygen 108.

[0065] The first LDMOS structure includes a dielectric layer 120, a source electrode 122, a drain electrode 121 and a body electrode 123. The dielectric layer 120 at least covers the field oxide layer, the gate polycrystalline 115, the first ohmic contact region 117 and the second ohmic contact region 118. The drain electrode 121 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113; the source electrode 122 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (source ohmic contact region) in the body region 116; the body electrode 123 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (body electrode ohmic contact region) in the body region 116. In this embodiment, the source electrode 122 and the body electrode 123 are connected together.

[0066] Figure 3 Shows Figure 1a FIG. 1 is a schematic diagram of an enlarged structure of the second LDMOS structure; Figure 1a and Figure 3 As shown, the second LDMOS structure is substantially the same as the first LDMOS structure, and is different from the first LDMOS structure in that, in the second LDMOS structure, the length of the drift region is shorter, and the field oxide layer in the drift region only includes the second field oxide 109. The second field oxide 109 is located between the first ohmic contact region 117 (source ohmic contact region) in the body region 116 and the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113, and the first ohmic contact region 117 (source ohmic contact region) in the body region 116 and the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113 are isolated from each other via the second field oxide 109. The second field oxygen 109 between the first ohmic contact region 117 (source ohmic contact region) in the body region 116 and the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 is adjacent to the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 on one side and not in contact with the first ohmic contact region 117 (source ohmic contact region) in the body region 116 on the other side.

[0067] The gate oxide layer 114 is located between the second field oxide 109 and the first ohmic contact region 117 (source ohmic contact region) in the body region 116. One side of the gate oxide layer 114 is adjacent to the first ohmic contact region 117 (source ohmic contact region) in the body region 116, and the other side is in contact with the second field oxide 109. One end of the gate polycrystalline 115 is tangent to the first ohmic contact region 117 (source ohmic contact region) in the body region 116, and the other end extends to above the second field oxide 109.

[0068] Figure 4 Shows Figure 1bA schematic diagram of the enlarged structure of the medium and low voltage NMOS structure; Figure 1b and Figure 4 As shown, the low voltage NMOS structure includes a substrate 101 of a first doping type, an epitaxial layer 103 of a first doping type, and a first low voltage well 112 of a first doping type. The epitaxial layer 103 is located on the substrate 101 and covers the surface of the substrate 101. The first low voltage well 112 is located in the epitaxial layer 103.

[0069] The low voltage NMOS structure includes a second ohmic contact region 118 of the first doping type and a first ohmic contact region 117 of the second doping type in the first low voltage well 112. The second ohmic contact region 118 in the first low voltage well 112 constitutes the body electrode ohmic contact region of the NMOS structure; the first ohmic contact region 117 in the first low voltage well 112 respectively constitutes the source and drain ohmic contact regions of the NMOS structure.

[0070] The low-voltage NMOS structure includes a second field oxygen 109 located on the surface of the first low-voltage well 112. The second field oxygen 109 is located between the second ohmic contact region 118 (body electrode ohmic contact region) and the source ohmic contact region in the first low-voltage well 112 and between the second ohmic contact region 118 (body electrode ohmic contact region) and the drain ohmic contact region, isolating the second ohmic contact region 118 (body electrode ohmic contact region) and the first ohmic contact region 117 (source and drain ohmic contact regions) in the first low-voltage well 112. Among them, the second field oxygen 109 between the second ohmic contact region 118 (body electrode ohmic contact region) and the source ohmic contact region in the first low voltage well 112 is respectively adjacent to the second ohmic contact region 118 (body electrode ohmic contact region) and the source ohmic contact region in the first low voltage well 112, and the second field oxygen 109 between the second ohmic contact region 118 (body electrode ohmic contact region) and the drain ohmic contact region is respectively adjacent to the second ohmic contact region 118 (body electrode ohmic contact region) and the drain ohmic contact region.

[0071] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the second ohmic contact region 118 and the DTI isolation structure.

[0072] The low voltage NMOS structure includes a gate oxide layer 114 and a gate polycrystalline 115, which form a gate stack structure. The gate oxide layer 114 is located on the surface of the first low voltage well 112 between adjacent first ohmic contact regions 117 (source ohmic contact region and drain ohmic contact region), and the gate polycrystalline 115 is located on the surface of the gate oxide layer 114.

[0073] The low voltage NMOS structure includes a dielectric layer 120, a source electrode 122, a drain electrode 121 and a body electrode 123, wherein the dielectric layer 120 covers at least the first field oxide 108a, the second field oxide 109, the gate polycrystalline 115, and the second ohmic contact region 118 (body electrode ohmic contact region) and the first ohmic contact region 117 (source and drain ohmic contact regions) in the first low voltage well 112. The drain electrode 121 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (drain ohmic contact region) in the first low-voltage well 112; the source electrode 122 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112; the body electrode 123 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (body electrode ohmic contact region) in the first low-voltage well 112.

[0074] Figure 5 Shows Figure 1b A schematic diagram of the enlarged structure of the medium and low voltage PMOS structure; Figure 1b and Figure 5 As shown, the low-voltage PMOS structure includes a substrate 101 of a first doping type, an epitaxial layer 103 of a first doping type, and a second low-voltage well 113 of a second doping type. The epitaxial layer 103 is located on the substrate 101 and covers the surface of the substrate 101 . The second low-voltage well 113 is located in the epitaxial layer 103 .

[0075] The low voltage PMOS structure includes a second ohmic contact region 118 of the first doping type and a first ohmic contact region 117 of the second doping type located in the second low voltage well 113. The first ohmic contact region 117 in the second low voltage well 113 constitutes a body electrode ohmic contact region of the low voltage PMOS structure; the second ohmic contact region 118 in the second low voltage well 113 respectively constitutes a source and a drain ohmic contact region of the low voltage PMOS structure.

[0076] The low-voltage PMOS structure includes a first low-voltage well 112 of a first doping type located in the epitaxial layer 103 and a second ohmic contact region 118 of a first doping type located in the first low-voltage well 112. The first low-voltage well 112 is located on both sides of the second low-voltage well 113 and is separated from the second low-voltage well 113. The second ohmic contact region 118 in the first low-voltage well 112 constitutes a substrate electrode ohmic contact region of the low-voltage PMOS structure.

[0077] The low-voltage PMOS structure includes a first field oxygen 108 and a second field oxygen 109 located on the surface of the epitaxial layer 103. The second field oxygen 109 is located between the first ohmic contact region 117 (body electrode ohmic contact region) and the source ohmic contact region in the second low-voltage well 113 and between the first ohmic contact region 117 (body electrode ohmic contact region) and the drain ohmic contact region, isolating the first ohmic contact region 117 (body electrode ohmic contact region) and the second ohmic contact region 118 (source and drain ohmic contact regions) in the second low-voltage well 113. Among them, the second field oxygen 109 between the first ohmic contact region 117 (body electrode ohmic contact region) and the source ohmic contact region in the second low voltage well 113 is adjacent to the first ohmic contact region 117 (body electrode ohmic contact region) and the source ohmic contact region in the second low voltage well 113, respectively, and the second field oxygen 109 between the first ohmic contact region 117 (body electrode ohmic contact region) and the drain ohmic contact region is adjacent to the first ohmic contact region 117 (body electrode ohmic contact region) and the drain ohmic contact region, respectively. The first field oxygen 108 is located between the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low voltage well 112, and is adjacent to the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low voltage well 112, respectively.

[0078] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low voltage well 112 and the DTI isolation structure.

[0079] The low voltage PMOS structure includes a gate oxide layer 114 and a gate polycrystalline 115, which form a gate stack structure. The gate oxide layer 114 is located on the surface of the second low voltage well 113 between adjacent second ohmic contact regions 118 (source ohmic contact region and drain ohmic contact region), and the gate polycrystalline 115 is located on the surface of the gate oxide layer 114.

[0080] The low-voltage PMOS structure includes a dielectric layer 120, a source electrode 122, a drain electrode 121, a body electrode 123 and a substrate electrode 124. The dielectric layer 120 covers at least the first field oxide 108, the second field oxide 109, the gate polycrystalline 115, the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low-voltage well 112, the first ohmic contact region 117 (body electrode ohmic contact region) and the second ohmic contact region 118 (source and drain ohmic contact region) in the second low-voltage well 113. The drain electrode 121 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (drain ohmic contact region) in the second low-voltage well 113; the source electrode 122 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113; the body electrode 123 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113; the substrate electrode 124 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low-voltage well 112.

[0081] Figure 6 Shows Figure 1b The enlarged structural diagram of the first DENMOS structure in FIG. Figure 1b and Figure 6 As shown, the first DENMOS structure includes a substrate 101 of a first doping type, an epitaxial layer 103 of a first doping type, a first low-voltage well 112 of a first doping type, and a second low-voltage well 113 of a second doping type. The epitaxial layer 103 is located on the substrate 101 and covers the surface of the substrate 101. The first low-voltage well 112 and the second low-voltage well 113 are located in the epitaxial layer 103 and are separated from each other. The second low-voltage well 113 constitutes a drift region of the first DENMOS structure.

[0082] The first DENMOS structure includes a second ohmic contact region 118 of a first doping type and a first ohmic contact region 117 of a second doping type, wherein the second ohmic contact region 118 of the first doping type is located in the first low voltage well 112, and the first ohmic contact region 117 of the second doping type is located in the first low voltage well 112 and the second low voltage well 113. The first ohmic contact region 117 of the second doping type in the second low voltage well 113 constitutes a drain ohmic contact region of the DENMOS structure; the first ohmic contact region 117 of the second doping type in the first low voltage well 112 and the second ohmic contact region 118 of the first doping type respectively constitute a source ohmic contact region and a body electrode ohmic contact region of the DENMOS structure.

[0083] The first DENMOS structure includes a field oxide layer located on the surface of the epitaxial layer 103, wherein the field oxide layer includes a first field oxide 108 having a first thickness and a second field oxide 109 having a second thickness. The second field oxide 109 is located on the surface of the first low voltage well 112, and is further located between the first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112, and is adjacent to the first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112, respectively. The first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112 are isolated by the second field oxide 109. The first field oxygen 108 is located on the surface of the second low-voltage well 113, and is further located between the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113. The first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113 are isolated by the first field oxygen 108. One side of the first field oxygen 108 is adjacent to the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113, and the other side is not in contact with the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112.

[0084] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 and the DTI isolation structure, and between the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112 and the DTI isolation structure.

[0085] The first DENMOS structure includes a gate oxide layer 114 and a gate polycrystalline 115, and the gate oxide layer 114 and the gate polycrystalline 115 constitute a gate stack structure. The gate oxide layer 114 is located on the epitaxial layer 103 between the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112 and the first field oxygen 108. One side of the gate oxide layer 114 is adjacent to the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112, and the other side is in contact with the first field oxygen 108. The gate polycrystalline 115 covers the gate oxide layer 114 and part of the first field oxygen 108. One end of the gate polycrystalline 115 is tangent to the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112, and the other end extends to above the first field oxygen 108.

[0086] The first DENMOS structure includes a dielectric layer 120, a source electrode 122, a drain electrode 121 and a body electrode 123, wherein the dielectric layer 120 covers at least the first field oxide 108, the second field oxide 109, the gate polycrystalline 115, the first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low-voltage well 112, and the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113. The drain electrode 121 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (drain ohmic contact region) in the second low-voltage well 113; the source electrode 122 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112; the body electrode 123 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (body electrode ohmic contact region) in the first low-voltage well 112.

[0087] Figure 7 Shows Figure 1c The enlarged structural diagram of the second DENMOS structure in FIG. Figure 1c and Figure 7As shown, the structure of the second DENMOS structure is substantially the same as that of the first DENMOS structure. The difference from the first DENMOS structure is that in the second DENMOS structure, the second field oxygen 109 is located between the first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112 and between the first ohmic contact region 117 (source ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113. The first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 are isolated by the second field oxygen 109. Among them, the second field oxygen 109 between the first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112 is adjacent to the first ohmic contact region 117 (source ohmic contact region) and the second ohmic contact region 118 (body electrode ohmic contact region) in the first low voltage well 112, respectively, and one side of the second field oxygen 109 between the first ohmic contact region 117 (source ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113 is adjacent to the first ohmic contact region 117 (drain ohmic contact region) in the second low voltage well 113, and the other side is not in contact with the first ohmic contact region 117 (source ohmic contact region) in the first low voltage well 112.

[0088] The gate oxide layer 114 is located on the epitaxial layer 103 between the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112 and the second field oxygen 109 on the surface of the second low-voltage well 113. One side of the gate oxide layer 114 is adjacent to the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112, and the other side is in contact with the second field oxygen 109 on the surface of the second low-voltage well 113. The gate polycrystalline 115 covers the gate oxide layer 114 and part of the surface of the second field oxygen 109 in the second low-voltage well 113. One end of the gate polycrystalline 115 is tangent to the first ohmic contact region 117 (source ohmic contact region) in the first low-voltage well 112, and the other end extends to above the second field oxygen 109 in the second low-voltage well 113.

[0089] Figure 8 Shows Figure 1c The enlarged structural diagram of the first DEPMOS structure in FIG. Figure 1c and Figure 8As shown, the first DEPMOS structure includes a substrate 101 of a first doping type, a buried layer 102 of a second doping type, an epitaxial layer 103 of a first doping type, and a high-voltage well 104 of a second doping type, wherein the buried layer 102 is located on the surface of the substrate 101, and the epitaxial layer 103 is located on the buried layer 102, covering the surface of the buried layer 102. The high-voltage well 104 is located in the epitaxial layer 103, and the bottom is in contact with the buried layer 102. The buried layer 102 and the high-voltage well 104 are used to separate the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure from the substrate 101.

[0090] The first DEPMOS structure includes a first low-pressure well 112 of a first doping type, a second low-pressure well 113 of a second doping type, a second ohmic contact region 118 of a first doping type, and a first ohmic contact region 117 of a second doping type. The first low-pressure well 112 and the second low-pressure well 113 are located in the high-pressure well 104 and are separated from each other. The second low-pressure well 113 is located on both sides of the first low-pressure well 112, for example. The first low-pressure well 112 constitutes a drift region of the first DEPMOS structure. The second ohmic contact region 118 of a first doping type is located in the first low-pressure well 112 and the second low-pressure well 113, and the first ohmic contact region 117 of a second doping type is located in the second low-pressure well 113. The second ohmic contact region 118 in the first low voltage well 112 constitutes the drain ohmic contact region of the first DEPMOS structure; the second ohmic contact region 118 in the second low voltage well 113 constitutes the source ohmic contact region of the first DEPMOS structure, and the first ohmic contact region 117 in the second low voltage well 113 constitutes the body electrode ohmic contact region of the first DEPMOS structure.

[0091] The first DEPMOS structure includes a field oxide layer located on the surface of the epitaxial layer 103, the field oxide layer includes a first field oxide 108 having a first thickness and a second field oxide 109 having a second thickness, wherein the first thickness is greater than the second thickness. The second field oxide 109 is located on the surface of the second low-voltage well 113, further located between the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113, and is adjacent to the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113, respectively, and the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 are isolated from each other via the second field oxide 109. The first field oxygen 108 is located on the surface of the first low-voltage well 112 and part of the surface of the second low-voltage well 113 , and is further located between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113 , and between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 , that is, between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113 , and the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 are isolated by the first field oxygen 108 . Among them, one side of the first field oxygen 108 between the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the second ohmic contact region 118 (source ohmic contact region) in the second low voltage well 113 is adjacent to the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112, and the other side is not in contact with the second ohmic contact region 118 (source ohmic contact region) in the second low voltage well 113, and the first field oxygen 108 between the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 is adjacent to the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 respectively.

[0092] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the first ohmic contact region 117 in the second low voltage well 113 and the DTI isolation structure.

[0093] The first DEPMOS structure includes a gate oxide layer 114 and a gate polycrystalline 115, and the gate oxide layer 114 and the gate polycrystalline 115 constitute a gate stack structure. The gate oxide layer 114 is located between the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113 and the first field oxygen 108, one side of the gate oxide layer 114 is adjacent to the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113, and the other side is in contact with the first field oxygen 108. The gate polycrystalline 115 covers the gate oxide layer 114 and part of the first field oxygen 108, one end of the gate polycrystalline 115 is tangent to the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113, and the other end extends to above the first field oxygen 108.

[0094] The first DEPMOS structure includes a dielectric layer 120, a source electrode 122, a drain electrode 121 and a body electrode 123. The dielectric layer 120 covers at least the first field oxygen 108, the second field oxygen 109, the gate polycrystalline 115, the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112, and the first ohmic contact region 117 (body electrode ohmic contact region) and the second ohmic contact region 118 (source ohmic contact region) located in the second low-voltage well 113. The drain electrode 121 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112; the source electrode 122 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113; the body electrode 123 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113.

[0095] Fig. 9 Shows Figure 1c The enlarged structural diagram of the second DEPMOS structure in FIG. Figure 1c and Fig. 9As shown, the structure of the second DEPMOS structure is substantially the same as that of the first DEPMOS structure. The difference from the first DEPMOS structure is that in the second DEPMOS structure, the second field oxygen 109 is located between the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113, between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113, and between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the second low-voltage well 113. The first ohmic contact region 117 (body electrode ohmic contact region) in the low voltage well 113, that is, between the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113, between the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the second ohmic contact region 118 (source ohmic contact region) in the second low voltage well 113, and between the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (substrate electrode ohmic contact region) in the second low voltage well 113 are isolated by the second field oxide 109. The second field oxygen 109 between the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 is adjacent to the second ohmic contact region 118 (source ohmic contact region) and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113, respectively; the second field oxygen 109 between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 is adjacent to the first low-voltage well 113, respectively. The second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 is adjacent to the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113; one side of the second field oxygen 109 between the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113 is adjacent to the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112, and the other side is not in contact with the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113.

[0096] The gate oxide layer 114 is located between the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113 and the second field oxygen 109 on the surface of the first low-voltage well 112. One side of the gate oxide layer 114 is adjacent to the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113, and the other side is in contact with the second field oxygen 109 on the surface of the first low-voltage well 112. The gate polycrystalline 115 covers the gate oxide layer 114 and part of the surface of the second field oxygen 109 in the first low-voltage well 112. One end of the gate polycrystalline 115 is tangent to the second ohmic contact region 118 (source ohmic contact region) in the second low-voltage well 113, and the other end extends to above the second field oxygen 109 in the first low-voltage well 112.

[0097] Fig.10 Shows Figure 1d The enlarged structural diagram of the NPN structure in FIG. Figure 1d and Fig.10 As shown, the NPN structure includes a substrate 101 of a first doping type, a buried layer 102 of a second doping type, an epitaxial layer 103 of a first doping type, a high-voltage well 104 of a second doping type, a first low-voltage well 112 of a first doping type, a second low-voltage well 113 of a second doping type, a second ohmic contact region 118 of a first doping type, and a first ohmic contact region 117 of a second doping type. The buried layer 102 is located on the surface of the substrate 101, and the epitaxial layer 103 is located on the buried layer 102 and covers the surface of the buried layer 102. The high-voltage well 104 is located in the epitaxial layer 103, and the bottom is in contact with the buried layer 102. The first low-voltage well 112 and the second low-voltage well 113 are located in the high-voltage well 104 and are separated from each other, and the second low-voltage well 113 is located on both sides of the first low-voltage well 112. The second ohmic contact region 118 of the first doping type is located in the first low-voltage well 112, and the first ohmic contact region 117 of the second doping type is located in the first low-voltage well 112 and the second low-voltage well 113.

[0098] The high-voltage well 104 and the buried layer 102 thereunder constitute the collector region of the NPN structure, the first ohmic contact region 117 in the second low-voltage well 113 constitutes the collector ohmic contact region of the NPN structure, and the collector region is led out from the surface of the second low-voltage well 113 through the first ohmic contact region 117 in the second low-voltage well 113. The first low-voltage well 112 serves as the base region of the NPN structure, and the second ohmic contact region 118 in the first low-voltage well 112 constitutes the base ohmic contact region of the NPN structure, and the base region is led out from the surface of the first low-voltage well 112 through the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112. The first ohmic contact region 117 in the first low-voltage well 112 constitutes the emitter ohmic contact region of the NPN structure.

[0099] The NPN structure includes a field oxide layer located on the surface of the high-voltage well 104, the field oxide layer includes a first field oxide 108 having a first thickness and a second field oxide 109 having a second thickness, the first thickness being greater than the second thickness. The second field oxide 109 is located between the first ohmic contact region 117 (emitter ohmic contact region) and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112, and is adjacent to the first ohmic contact region 117 (emitter ohmic contact region) and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112, respectively, to isolate the first ohmic contact region 117 (emitter ohmic contact region) and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112. The first field oxygen 108 is located between the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112, and is adjacent to the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112, respectively, isolating the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112.

[0100] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the first ohmic contact region 117 in the second low voltage well 113 and the DTI isolation structure.

[0101] The NPN structure includes a dielectric layer 120, a collector 125, a base 126 and an emitter 127. The dielectric layer 120 covers at least the first field oxygen 108, the second field oxygen 109, the first ohmic contact region 117 (emitter ohmic contact region) and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112, and the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113. The collector 125 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113; the base 126 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112; the emitter 127 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (emitter ohmic contact region) in the first low-voltage well 112.

[0102] Fig.11 Shows Figure 1d Schematic diagram of the enlarged structure of the PNP structure; Figure 1d and Fig.11As shown, the PNP structure includes a substrate 101 of a first doping type, a buried layer 102 of a second doping type, an epitaxial layer 103 of a first doping type, a high-voltage well 104 of a second doping type, a first low-voltage well 112 of a first doping type, a second ohmic contact region 118 of a first doping type, and a first ohmic contact region 117 of a second doping type. The buried layer 102 is located on the surface of the substrate 101, and the epitaxial layer 103 is located on the buried layer 102, covering the surface of the buried layer 102. The high-voltage well 104 is located in the epitaxial layer 103, and the bottom is in contact with the buried layer 102. The first low-voltage well 112 is located in the high-voltage well 104, and in the epitaxial layer 103 outside the high-voltage well 104. The first ohmic contact region 117 is located in the high-voltage well 104. The second ohmic contact region 118 is located in the first low-voltage well 112 in the epitaxial layer 103 and in the first low-voltage well 112 in the high-voltage well 104.

[0103] The high-voltage well 104 and the buried layer 102 thereunder constitute the base region of the PNP structure, the first ohmic contact region 117 in the high-voltage well 104 constitutes the base ohmic contact region of the PNP structure, and the base region is led out from the surface of the high-voltage well 104 through the first ohmic contact region 117 (base ohmic contact region) in the high-voltage well 104. The first low-voltage well 112 in the high-voltage well 104 constitutes the emitter region of the PNP structure, and the second ohmic contact region 118 in the first low-voltage well 112 in the high-voltage well 104 constitutes the emitter ohmic contact region of the PNP structure. The first low-voltage well 112 in the epitaxial layer 103 located outside the high-voltage well 104 constitutes the collector region of the PNP structure, and the second ohmic contact region 118 in the first low-voltage well 112 in the epitaxial layer 103 constitutes the collector ohmic contact region of the PNP structure.

[0104] The second field oxygen 109 is located between the collector ohmic contact region and the base ohmic contact region, and between the base ohmic contact region and the emitter ohmic contact region, isolating the collector ohmic contact region and the base ohmic contact region, and the base ohmic contact region and the emitter ohmic contact region. The second field oxygen 109 between the collector ohmic contact region and the base ohmic contact region is adjacent to the collector ohmic contact region and the base ohmic contact region, respectively, and the second field oxygen 109 between the base ohmic contact region and the emitter ohmic contact region is adjacent to the base ohmic contact region and the emitter ohmic contact region, respectively.

[0105] Furthermore, there is a LOCOS isolation structure (first field oxygen 108 a ) between the collector ohmic contact region and the DTI isolation structure.

[0106] The PNP structure includes a dielectric layer 120, a collector 125, a base 126 and an emitter 127, wherein the dielectric layer 120 covers at least the first field oxygen 108, the second field oxygen 109, the first ohmic contact region 117 in the high-voltage well 104, the second ohmic contact region 118 in the first low-voltage well 112 in the high-voltage well 104, and the second ohmic contact region 118 in the first low-voltage well 112 in the epitaxial layer 103. The collector 125 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (collector ohmic contact region) in the first low-voltage well 112 in the epitaxial layer 103; the base 126 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the first ohmic contact region 117 (base ohmic contact region) in the high-voltage well 104; the emitter 127 is located on the dielectric layer 120 and penetrates the dielectric layer 120 to contact the second ohmic contact region 118 (emitter ohmic contact region) in the first low-voltage well 112 in the high-voltage well 104.

[0107] Figures 12a to 12d FIG. 4 is a schematic cross-sectional view of a BCD device according to a second embodiment of the present application. Figures 12a to 12d The device structures shown are structures of different parts of the same device; Figures 12a to 12d As shown, the BCD device includes a substrate 101 of a first doping type, a buried layer 102 of a second doping type, an epitaxial layer 103 of a first doping type, and a DTI (Deep Trench Isolation) isolation structure, wherein the first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping.

[0108] The buried layer 102 is located on the substrate 101, covering a portion of the surface of the substrate 101, and the epitaxial layer 103 is located on the substrate 101 and the buried layer 102, covering the surface of the substrate 101 and the surface of the buried layer 102. The DTI isolation structure extends from the surface of the epitaxial layer 103 toward the substrate 101, penetrates the epitaxial layer 103 or the epitaxial layer 103 and the buried layer 102, and extends to the inside of the substrate 101. The DTI isolation structure isolates the epitaxial layer 103 into multiple regions to form a corresponding semiconductor structure in each region. The DTI isolation structure includes a trench extending from the surface of the epitaxial layer 103 to the substrate 101, an oxide layer located inside the trench, and a polysilicon layer 107.

[0109] The BCD device includes a first LDMOS structure, a second LDMOS structure, a first DENMOS (Drain Extended NMOS, drain extended N-type field effect transistor) structure, a second DENMOS structure, a first DEPMOS (Drain Extended PMOS, drain extended P-type field effect transistor) structure, a second DEPMOS structure, a low voltage NMOS structure, a low voltage PMOS structure, an NPN structure and a PNP structure located on the same substrate 101. Among them, the first LDMOS structure is, for example, a high voltage NLDMOS structure (HVNLDMOS), the second LDMOS structure is, for example, a low voltage NLDMOS structure (LV NLDMOS), the first DENMOS structure is, for example, a high voltage DENMOS structure (HV DENMOS), the second DENMOS structure is, for example, a low voltage DENMOS structure (LV DENMOS), the first DEPMOS structure is, for example, a high voltage DEPMOS structure (HV DEPMOS), and the second DEPMOS structure is, for example, a low voltage DEPMOS (LVDEPMOS) structure.

[0110] The first LDMOS structure, the second LDMOS structure, the first DENMOS (Drain Extended NMOS, drain extended N-type field effect transistor) structure, the second DENMOS structure, the low-voltage NMOS structure, and the PNP structure in this embodiment are the same as the first LDMOS structure, the second LDMOS structure, the first DENMOS (Drain Extended NMOS, drain extended N-type field effect transistor) structure, the second DENMOS structure, the low-voltage NMOS structure, and the PNP structure in the first embodiment, and are not repeated in this embodiment.

[0111] like Fig.13As shown, the low-voltage PMOS structure of this embodiment is substantially the same as the low-voltage PMOS structure of the first embodiment, except that, in the first embodiment, the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low-voltage well 112 are isolated via the first field oxide 108, while in this embodiment, the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low-voltage well 112 are isolated via the first field oxide 108. The ohmic contact regions 118 (substrate electrode ohmic contact regions) are isolated from each other by the second field oxygen 109, and the second field oxygen 109 between the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low voltage well 112 is adjacent to the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (substrate electrode ohmic contact region) in the first low voltage well 112, respectively.

[0112] like Fig.14 As shown, the first DEPMOS structure of this embodiment is substantially the same as the first DEPMOS structure of the first embodiment, except that, in the first embodiment, the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 are isolated via the first field oxide 108; in this embodiment, the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 are isolated via the first field oxide 108. The first ohmic contact regions 117 (body electrode ohmic contact regions) are isolated by the second field oxygen 109, and the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 are adjacent to the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113, respectively.

[0113] like Fig.15As shown, the second DEPMOS structure of this embodiment is substantially the same as the second DEPMOS structure of the first embodiment, except that, in the first embodiment, the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 are isolated via the second field oxide 109; in this embodiment, the second ohmic contact region 118 (drain ohmic contact region) in the first low-voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low-voltage well 113 are isolated via the second field oxide 109. The first ohmic contact regions 117 (body electrode ohmic contact regions) are isolated by the first field oxygen 108, and the first field oxygen 108 between the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113 are adjacent to the second ohmic contact region 118 (drain ohmic contact region) in the first low voltage well 112 and the first ohmic contact region 117 (body electrode ohmic contact region) in the second low voltage well 113, respectively.

[0114] like Fig.16 As shown, the NPN structure of this embodiment is substantially the same as the NPN structure of the first embodiment, except that, in the first embodiment, the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112 are isolated via the first field oxide 108; in this embodiment, the first ohmic contact region 117 (collector ohmic contact region) in the second low-voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low-voltage well 112 are isolated via the first field oxide 108. The first ohmic contact regions 117 (collector ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low voltage well 112 are isolated from each other by the second field oxygen 109, and the second field oxygen 109 between the first ohmic contact region 117 (collector ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low voltage well 112 are adjacent to the first ohmic contact region 117 (collector ohmic contact region) in the second low voltage well 113 and the second ohmic contact region 118 (base ohmic contact region) in the first low voltage well 112, respectively.

[0115] It is worth noting that, in the first embodiment, the low voltage NMOS structure, the low voltage PMOS structure and the NPN structure all include the first field oxygen 108 and the second field oxygen 109; in the second embodiment, the low voltage NMOS structure, the low voltage PMOS structure and the NPN structure all include only the second field oxygen 109; in other embodiments, the low voltage NMOS structure, the low voltage PMOS structure and the NPN structure may also include only the first field oxygen 108.

[0116] Fig.17 A schematic diagram of the circuit principle of a pre-stabilization circuit is shown; Fig.17As shown, the pre-stabilization circuit includes an input terminal VIN, a first output terminal VOUT and a second output terminal IOUT, the input terminal VIN inputs a high voltage power supply, the first output terminal VOUT outputs a low voltage power supply VDD, and the second output terminal IOUT outputs a current source I.

[0117] Specifically, the pre-regulator circuit includes a first LDMOS structure (LDMOS), a first PMOS structure (PMOS1 and PMOS2), a first NMOS structure (NMOS1 and NMOS2), an NPN structure (NPN), resistors R1 to R3, and a voltage regulator Z1.

[0118] The resistor R1, the resistor R2, the first LDMOS structure, and the voltage regulator Z1 constitute a voltage source whose output end is the first output end VOUT, wherein the resistor R1 and the resistor R2 are current limiting protection resistors of the voltage regulator Z1 and the first LDMOS structure respectively. The NPN structure, the first PMOS structure, the second PMOS structure, the first NMOS structure, the second NMOS structure, and the resistor R3 constitute a current source whose output end is the second output end IOUT.

[0119] The voltage V output by the first output terminal DD for:

[0120] V DD =V Z1 -V TH

[0121] Among them, V Z1 is the voltage of the Zener tube, V TH is the threshold voltage of the first LDMOS structure.

[0122] The current I output by the second output terminal is:

[0123] I=(V DD -V BE ) / R3

[0124] Among them, V DD is the voltage output from the first output terminal, V BE It is the base-emitter conduction voltage drop of the NPN structure.

[0125] In the BCD device of the embodiment of the present application, the source ohmic contact region and the drain ohmic contact region of the high-voltage LDMOS structure are isolated by thin field oxygen (second field oxygen) and thick field oxygen (first field oxygen), and the second field oxygen is close to one side of the source ohmic contact region, and the first field oxygen is added on the side close to the drain ohmic contact region, so that the performance and reliability of the high-voltage LDMOS structure are guaranteed.

[0126] In the BCD device of the embodiment of the present application, the source ohmic contact region and the drain ohmic contact region of the high-voltage LDMOS structure are isolated by thin field oxygen (second field oxygen) and thick field oxygen (first field oxygen), and the second field oxygen is close to one side of the source ohmic contact region, the gate conductor completely covers the thin field oxygen (second field oxygen), and the end of the gate conductor away from the source ohmic contact region is located on the thick field oxygen (first field oxygen); when the high-voltage LDMOS structure is reversely withstand voltage, the field plate auxiliary depletion effect at the thin field oxygen (second field oxygen) is stronger, and the end of the field plate away from the source ohmic contact region will not introduce an excessively high electric field inside the drift region, taking into account both the performance and reliability of the high-voltage LDMOS structure.

[0127] In the BCD device of the embodiment of the present application, two thicknesses of field oxygen can be selectively set. Thin field oxygen (second field oxygen) is used inside the low-voltage structure. The thin field oxygen (second field oxygen) can significantly reduce the rules of the low-voltage structure and reduce the layout area. Thick field oxygen (first field oxygen) is used in areas where high-voltage cross-lines exist to meet field-on design requirements.

[0128] All first field oxygens in the BCD device of the embodiment of the present application are formed simultaneously, and all second field oxygens are formed simultaneously. Only one more photolithography and etching step is required to form field oxygens of two different thicknesses. The method is simple.

[0129] The high-voltage structure of the embodiment of the present application uses thick field oxygen, which can effectively reduce the surface electric field of the structure and improve reliability; the low-voltage structure uses thin field oxygen, the depletion effect of the polycrystalline field plate is stronger, and the on-resistance is smaller under the same withstand voltage.

[0130] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A BCD device, characterized in that: include: a substrate of a first doping type; An epitaxial layer of a first doping type, located on the substrate, wherein a first LDMOS structure, a low-voltage NMOS structure, a low-voltage PMOS structure, and an NPN structure are formed in the epitaxial layer; as well as A first field oxygen and a second field oxygen are located on a surface of the epitaxial layer, and a thickness of the first field oxygen is greater than a thickness of the second field oxygen; Among them, in the first LDMOS structure, the first field oxygen and the second field oxygen are located between the source ohmic contact region and the drain ohmic contact region of the first LDMOS structure, the first field oxygen and the second field oxygen are in contact with each other, the second field oxygen is close to one side of the source ohmic contact region and is not in contact with the source ohmic contact region of the first LDMOS structure, and the first field oxygen is close to one side of the drain ohmic contact region of the first LDMOS structure and is adjacent to the drain ohmic contact region of the first LDMOS structure.

2. The BCD device according to claim 1, characterized in that: The low-voltage NMOS structure, the low-voltage PMOS structure, and the NPN structure all include the first field oxygen and the second field oxygen.

3. The BCD device according to claim 1, characterized in that: The low-voltage NMOS structure, the low-voltage PMOS structure, and the NPN structure include the first field oxygen or the second field oxygen.

4. The BCD device according to claim 1, characterized in that: In the low-voltage NMOS structure, the second field oxygen is located between the source ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, and is adjacent to the source ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, respectively; the second field oxygen is also located between the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, and is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage NMOS structure, respectively.

5. The BCD device according to claim 1, characterized in that: In the low-voltage PMOS structure, the second field oxygen is located between the source ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, and is adjacent to the source ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, respectively; the second field oxygen is also located between the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, and is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the low-voltage PMOS structure, respectively.

6. The BCD device according to claim 1, characterized in that: In the NPN structure, the first field oxygen is located between the base ohmic contact region and the collector ohmic contact region of the NPN structure, and is adjacent to the base ohmic contact region and the collector ohmic contact region of the NPN structure respectively; the second field oxygen is located between the emitter ohmic contact region and the base ohmic contact region of the NPN structure, and is adjacent to the emitter ohmic contact region and the base ohmic contact region of the NPN structure respectively; or, The second field oxygen is located between the base ohmic contact region and the collector ohmic contact region of the NPN structure, and is adjacent to the base ohmic contact region and the collector ohmic contact region of the NPN structure respectively. The second field oxygen is also located between the emitter ohmic contact region and the base ohmic contact region of the NPN structure, and is adjacent to the emitter ohmic contact region and the base ohmic contact region of the NPN structure respectively.

7. The BCD device according to claim 1, characterized in that: The first LDMOS structure comprises: a buried layer of a second doping type, located on the substrate, wherein the second doping type is opposite to the first doping type; An epitaxial layer of a first doping type, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A drift region of a second doping type is located in the epitaxial layer and both sides of the drift region extend laterally into the high-voltage well; a second low voltage well of a second doping type, located in the high voltage well of the first LDMOS structure; A body region of a first doping type, located in a drift region of the first LDMOS structure; A source ohmic contact region of a second doping type is located in the body region of the first LDMOS structure, A drain ohmic contact region of a second doping type, located in a second low voltage well of the first LDMOS structure; A body electrode ohmic contact region of a first doping type, located in the body region of the first LDMOS structure and adjacent to the source ohmic contact region; A gate stack structure, located between the source ohmic contact region and the drain ohmic contact region of the first LDMOS structure; The gate stack structure comprises: a gate oxide layer located between the source ohmic contact region and the second field oxide of the first LDMOS structure and adjacent to the source ohmic contact region and the second field oxide of the first LDMOS structure; and The gate polycrystalline covers the gate oxide layer, the second field oxide and a part of the first field oxide of the first LDMOS structure.

8. The BCD device according to claim 4, characterized in that: The low voltage NMOS structure comprises: An epitaxial layer of a first doping type, located on the substrate; a first low voltage well of a first doping type, located in the epitaxial layer; A source ohmic contact region of the second doping type, a drain ohmic contact region, and a body electrode ohmic contact region of the first doping type are located in a first low-voltage well of the low-voltage NMOS structure.

9. The BCD device according to claim 5, characterized in that: The low voltage PMOS structure comprises: An epitaxial layer of a first doping type, located on the substrate; a second low voltage well of a second doping type, located in the epitaxial layer; A first low-pressure well of a first doping type is located in the epitaxial layer, and the first low-pressure well is located on both sides of the second low-pressure well and is separated from the second low-pressure well; A source ohmic contact region of a first doping type, a drain ohmic contact region, and a body electrode ohmic contact region of a second doping type, located in a second low-voltage well of the low-voltage PMOS structure; A substrate electrode ohmic contact region of a first doping type, located in a first low-voltage well of the low-voltage PMOS structure; The first field oxygen or the second field oxygen is located between the substrate electrode ohmic contact region of the low voltage PMOS structure and the body electrode ohmic contact region of the low voltage PMOS structure, and is adjacent to the substrate electrode ohmic contact region of the low voltage PMOS structure and the body electrode ohmic contact region of the low voltage PMOS structure respectively.

10. The BCD device according to claim 6, characterized in that: The NPN structure includes: A buried layer of a second doping type, located on the substrate; an epitaxial layer, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type are located in the high-voltage well of the NPN structure, and the second low-voltage well is located on both sides of the first low-voltage well and separated from each other; A collector ohmic contact region of a second doping type, located in a second low voltage well of the NPN structure; A base ohmic contact region of a first doping type and an emitter ohmic contact region of a second doping type are located in a first low voltage well of the NPN structure.

11. The BCD device according to claim 1, characterized in that: Also included is a second LDMOS structure, wherein the second LDMOS structure includes: a buried layer of a second doping type, located on the substrate, wherein the second doping type is opposite to the first doping type; An epitaxial layer of a first doping type, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A drift region of a second doping type is located in the epitaxial layer and both sides of the drift region extend laterally into the high-voltage well; a second low voltage well of a second doping type, located in the high voltage well of the second LDMOS structure; A body region of a first doping type, located in a drift region of the second LDMOS structure; A source ohmic contact region of a second doping type is located in the body region of the second LDMOS structure, A drain ohmic contact region of a second doping type, located in a second low voltage well of the second LDMOS structure; A body electrode ohmic contact region of a first doping type, located in the body region of the second LDMOS structure and adjacent to the source ohmic contact region; a gate stack structure, located between the source ohmic contact region and the drain ohmic contact region of the second LDMOS structure; and A second field oxide having a second thickness is located between the source ohmic contact region and the drain ohmic contact region of the second LDMOS structure and is adjacent to the drain ohmic contact region of the second LDMOS structure; The gate stack structure includes a gate oxide layer and a gate polycrystalline. The gate oxide layer is located between the source ohmic contact region and the second field oxygen of the second LDMOS structure and is adjacent to the source ohmic contact region and the second field oxygen of the second LDMOS structure. The gate polycrystalline covers the gate oxide layer and a portion of the second field oxygen of the second LDMOS structure.

12. The BCD device according to claim 1, characterized in that: Also included is a first DENMOS structure, wherein the first DENMOS structure includes: An epitaxial layer of a first doping type, located on the substrate; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type, located in the epitaxial layer and separated from each other; A drain ohmic contact region of a second doping type, located in a second low voltage well of the first DENMOS structure; A body electrode ohmic contact region of a first doping type and a source ohmic contact region of a second doping type, located in a first low voltage well of the first DENMOS structure; A gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the first DENMOS structure; a first field oxygen having a first thickness, located between a source ohmic contact region and a drain ohmic contact region of the first DENMOS structure, wherein one side of the first field oxygen of the first DENMOS structure is adjacent to the drain ohmic contact region of the first DENMOS structure, and the other side of the first field oxygen of the first DENMOS structure is not in contact with the source ohmic contact region of the first DENMOS structure; and A second field oxygen having a second thickness is located between the body electrode ohmic contact region and the source ohmic contact region of the first DENMOS structure, and the second field oxygen of the first DENMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the first DENMOS structure respectively; The gate stack structure includes a gate oxide layer and a gate polycrystalline. The gate oxide layer is located between the source ohmic contact region and the first field oxygen of the first DENMOS structure and is adjacent to the source ohmic contact region and the first field oxygen of the first DENMOS structure. The gate polycrystalline covers the gate oxide layer and a portion of the first field oxygen of the first DENMOS structure.

13. The BCD device according to claim 1, characterized in that: Also included is a second DENMOS structure, wherein the second DENMOS structure includes: An epitaxial layer of a first doping type, located on the substrate; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type, located in the epitaxial layer and separated from each other; A drain ohmic contact region of a second doping type, located in a second low voltage well of the second DENMOS structure; A body electrode ohmic contact region of a first doping type and a source ohmic contact region of a second doping type, located in a first low voltage well of the second DENMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the second DENMOS structure, the gate stack structure comprising a gate oxide layer and a gate polycrystalline; and A second field oxide having a second thickness is located between the source ohmic contact region and the drain ohmic contact region of the second DENMOS structure, and between the body electrode ohmic contact region and the source ohmic contact region of the second DENMOS structure; One side of the second field oxide between the source ohmic contact region and the drain ohmic contact region of the second DENMOS structure is adjacent to the drain ohmic contact region of the second DENMOS structure, and the other side is adjacent to the gate oxide layer, and the gate poly covers the gate oxide layer of the second DENMOS structure and a portion of the second field oxide between the source ohmic contact region and the drain ohmic contact region of the second DENMOS structure; The second field oxide between the body electrode ohmic contact region and the source ohmic contact region of the second DENMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the second DENMOS structure, respectively.

14. The BCD device according to claim 1, characterized in that: Also included is a first DEPMOS structure, wherein the first DEPMOS structure includes: a buried layer of a second doping type, located on the substrate, wherein the second doping type is opposite to the first doping type; An epitaxial layer of a first doping type, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type are located in the high-voltage well of the first DEPMOS structure, and the second low-voltage well is located on both sides of the first low-voltage well and is separated from each other; A drain ohmic contact region of a first doping type, located in a first low voltage well of the first DEPMOS structure; A second doping type body electrode ohmic contact region and a first doping type source electrode ohmic contact region are located in a second low voltage well of the first DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the first DEPMOS structure, the gate stack structure comprising a gate oxide layer and a gate polycrystalline; and a first field oxygen having a first thickness, located between a source ohmic contact region and a drain ohmic contact region of the first DEPMOS structure and between the drain ohmic contact region and a body electrode ohmic contact region of the first DEPMOS structure, one side of the first field oxygen between the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure is adjacent to the drain ohmic contact region of the first DEPMOS structure, and the other side is adjacent to the gate oxide layer, the gate poly covers the gate oxide layer of the first DEPMOS structure and a portion of the first field oxygen between the source ohmic contact region and the drain ohmic contact region of the first DEPMOS structure, and the first field oxygen between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure respectively; and The second field oxide with a second thickness is located between the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure, and is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure respectively.

15. The BCD device according to claim 1, characterized in that: Also included is a first DEPMOS structure, wherein the first DEPMOS structure includes: a buried layer of a second doping type, located on the substrate, wherein the second doping type is opposite to the first doping type; An epitaxial layer of a first doping type, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type are located in the high-voltage well of the first DEPMOS structure, and the second low-voltage well is located on both sides of the first low-voltage well and is separated from each other; A drain ohmic contact region of a first doping type, located in a first low voltage well of the first DEPMOS structure; A second doping type body electrode ohmic contact region and a first doping type source electrode ohmic contact region are located in a second low voltage well of the first DEPMOS structure; A gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the first DEPMOS structure, the gate stack structure comprising a gate oxide layer and a gate polycrystalline; a first field oxide having a first thickness, located between a source ohmic contact region and a drain ohmic contact region of the first DEPMOS structure, wherein one side of the first field oxide of the first DEPMOS structure is adjacent to the drain ohmic contact region of the first DEPMOS structure, and the other side is adjacent to the gate oxide layer, and the gate poly covers the gate oxide layer of the first DEPMOS structure and a portion of the first field oxide; and A second field oxygen having a second thickness is located between the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure and between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure, the second field oxygen between the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure are respectively adjacent to the body electrode ohmic contact region and the source ohmic contact region of the first DEPMOS structure, and the second field oxygen between the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure are respectively adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the first DEPMOS structure.

16. The BCD device according to claim 1, characterized in that: Also included is a second DEPMOS structure, wherein the second DEPMOS structure includes: a buried layer of a second doping type, located on the substrate, wherein the second doping type is opposite to the first doping type; An epitaxial layer of a first doping type, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type are located in the high-voltage well of the second DEPMOS structure, and the second low-voltage well is located on both sides of the first low-voltage well and is separated from each other; A drain ohmic contact region of a first doping type, located in a first low voltage well of the second DEPMOS structure; A second doping type body electrode ohmic contact region and a first doping type source electrode ohmic contact region are located in a second low voltage well of the second DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure, the gate stack structure comprising a gate oxide layer and a gate polycrystalline; and A second field oxide having a second thickness is located between the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure, between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure, and between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure; One side of the second field oxygen between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the drain ohmic contact region of the second DEPMOS structure, and the other side is adjacent to the gate oxide layer, and the gate poly covers the gate oxide layer of the second DEPMOS structure and part of the second field oxygen between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure; The second field oxygen between the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure is adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure respectively; The second field oxide between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure, respectively.

17. The BCD device according to claim 1, characterized in that: Also included is a second DEPMOS structure, wherein the second DEPMOS structure includes: a buried layer of a second doping type, located on the substrate, wherein the second doping type is opposite to the first doping type; An epitaxial layer of a first doping type, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A first low-voltage well of a first doping type and a second low-voltage well of a second doping type are located in the high-voltage well of the second DEPMOS structure, and the second low-voltage well is located on both sides of the first low-voltage well and is separated from each other; A drain ohmic contact region of a first doping type, located in a first low voltage well of the second DEPMOS structure; A second doping type body electrode ohmic contact region and a first doping type source electrode ohmic contact region are located in a second low voltage well of the second DEPMOS structure; a gate stack structure, located between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure, the gate stack structure comprising a gate oxide layer and a gate polycrystalline; and a first field oxide having a first thickness, located between the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure, and adjacent to the drain ohmic contact region and the body electrode ohmic contact region of the second DEPMOS structure respectively; A second field oxide having a second thickness is located between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure and between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure; The second field oxygen between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the drain ohmic contact region of the second DEPMOS structure on one side and adjacent to the gate oxide layer on the other side, and the gate poly covers the gate oxide layer of the second DEPMOS structure and part of the second field oxygen between the drain ohmic contact region and the source ohmic contact region of the second DEPMOS structure; The second field oxide between the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure is adjacent to the body electrode ohmic contact region and the source ohmic contact region of the second DEPMOS structure, respectively.

18. The BCD device according to claim 1, characterized in that: Also included is a PNP structure, the PNP structure comprising: A buried layer of a second doping type, located on the substrate; an epitaxial layer, located on the buried layer; A high-voltage well of a second doping type, located in the epitaxial layer, and having a bottom in contact with the buried layer; A first low-voltage well of a first doping type is located in the high-voltage well of the PNP structure and in an epitaxial layer outside the high-voltage well of the PNP structure; A base ohmic contact region of a second doping type, located in the high-voltage well of the PNP structure; An emitter ohmic contact region of a first doping type is located in a first low-voltage well within a high-voltage well in the PNP structure; A collector ohmic contact region of a first doping type, located in a first low voltage well in the epitaxial layer in the PNP structure; A second field oxide having a second thickness is located between the base ohmic contact region and the collector ohmic contact region of the PNP structure, and between the emitter ohmic contact region and the base ohmic contact region of the PNP structure; The second field oxygen between the base ohmic contact region and the collector ohmic contact region of the PNP structure is adjacent to the base ohmic contact region and the collector ohmic contact region of the PNP structure respectively; the second field oxygen between the emitter ohmic contact region and the base ohmic contact region of the PNP structure is adjacent to the emitter ohmic contact region and the base ohmic contact region of the PNP structure respectively.

19. The BCD device according to claim 1, characterized in that: The thickness of the first field oxygen is 4000 angstroms to 5000 angstroms, and the thickness of the second field oxygen is 2000 angstroms to 3000 angstroms.

20. The BCD device according to claim 1, characterized in that: The first LDMOS structure, the low-voltage NMOS structure, the low-voltage PMOS structure, and the NPN structure are separated by an isolation structure, and the isolation structure includes a DTI isolation structure and / or a LOCOS isolation structure.

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