A SPI display screen display system

Abstract

The utility model provides a SPI display screen display system, including: an SPI FLASH chip, the SPI FLASH chip having a MOSI port and a MISO port; an MCU having two MOSI ports and one MISO port; the SPI display screen having a MOSI port; the MCU is connected to the MOSI port of the SPI FLASH chip through a first MOSI port, the MCU is connected to the MOSI port of the SPI display screen through a second MOSI port, the MCU is connected to the MISO port of the SPI FLASH chip through a MISO port, and the MISO port of the SPI FLASH chip is also connected to the MOSI port of the SPI display screen, so that when the SPI reception is controlled to be enabled, the second MOSI port of the MCU is configured as an input function, a read data instruction is sent to the SPI FLASH chip, and the SPI transmission is controlled to be prohibited, the data to be displayed is directly written from the SPI FLASH chip to the SPI display screen for display. The solution can realize that the display resources stored in the SPI FLASH are directly written to the SPI display screen for display without consuming the internal RAM cache space of the MCU.

Description

Technical Field

[0001] The utility model relates to the technical field of SPI interface display screens, in particular to a SPI display screen display system. Background Art

[0002] Small-size display screens have been increasingly widely used in products with human-computer interaction functions, such as smart bracelets, floor scrubbers, coffee machines, and so on. For 32-bit MCUs, SPI interface peripherals are used as a standard resource to provide support for driving SPI LCD displays. When you want to display the display resources stored in the SPI FLASH memory chip on the SPI LCD display, the most common way is to use the MCU as a transfer medium between the SPI FLASH memory chip and the SPI LCD display, first read the display resource data stored in the SPI FLASH memory chip to the MCU, temporarily store it in the RAM cache space inside the MCU, and then write the display resource data in the RAM cache space to the SPI LCD display for display. However, this method will consume a certain amount of MCU RAM cache resources, and if you want to increase the refresh frame rate of the SPI display, the larger the MCU RAM resources required, the higher the corresponding MCU cost. Utility Model Content

[0003] The purpose of the utility model is to provide a SPI display screen display system, which can display the display resources stored in the SPI FLASH on the SPI display screen without consuming the internal RAM cache space of the MCU, and can improve the refresh frame rate of the SPI display screen, so that the display switching of the SPI display screen is smoother.

[0004] The technical solution provided by the utility model is as follows:

[0005] The utility model provides a SPI display screen display system, comprising:

[0006] An SPI FLASH chip stores data to be displayed, wherein the SPI FLASH chip has a MOSI port and a MISO port;

[0007] The MCU has two MOSI ports and one MISO port; the SPI display has one MOSI port;

[0008] The MCU is connected to the MOSI port of the SPI FLASH chip through the first MOSI port, the MCU is connected to the MOSI port of the SPI display screen through the second MOSI port, and the MCU is connected to the MISO port of the SPI FLASH chip through the MISO port.

[0009] The MISO port of the SPI FLASH chip is also connected to the MOSI port of the SPI display screen, so that when the SPI reception is controlled to be enabled, the second MOSI port of the MCU is configured as an input function, a read data instruction is sent to the SPI FLASH chip, and the SPI transmission is controlled to be disabled, the data to be displayed can be directly written from the SPI FLASH chip to the SPI display screen for display.

[0010] The present application sets the MCU to have two MOSI ports, and respectively connects with the MOSI port of the SPI FLASH chip and the MOSI port of the SPI display screen, and sets the MISO port of the MCU to be connected with the MISO port of the SPI FLASH chip, and the MISO port of the SPI FLASH chip to be connected with the MOSI port of the SPI display screen, so that when the SPI reception is controlled to be enabled, the second MOSI port of the MCU is configured as a normal input function, a read data instruction is sent to the SPI FLASH chip, and the SPI transmission is controlled to be prohibited, the data to be displayed can be directly written from the SPI FLASH chip to the SPI display screen for display, so that the display resources stored in the SPI FLASH can be displayed on the SPI display screen without consuming the internal RAM cache space of the MCU, and the refresh frame rate of the SPI display screen can be improved, so that the display switching of the SPI display screen is smoother.

[0011] In some implementations, the SPI FLASH chip and the SPI display screen each have a chip select port, and the MCU has two chip select ports.

[0012] The first chip select port of the MCU is connected to the chip select port of the SPI FLASH chip, and the second chip select port of the MCU is connected to the chip select port of the SPI display screen.

[0013] In some implementations, the chip select port of the SPI display screen is initially pulled down to a low level, and is set to a high level after the SPI display screen receives the data to be displayed.

[0014] In some implementations, the chip select port of the SPI FLASH chip is pulled down to a low level when SPI reception is enabled and the second MOSI port of the MCU is configured as an input function, and is set to a high level when SPI reception is disabled and the second MOSI port of the MCU is configured as a multiplexing function.

[0015] In some implementations, the SPI display screen sets an operation area corresponding to the data to be displayed when a chip select port of the SPI display screen is pulled down to a low level.

[0016] In some implementations, both the MCU and the SPI FLASH chip have a clock port, and the clock port of the MCU is connected to the clock port of the SPI FLASH chip.

[0017] In some implementations, the SPI display screen also has a clock port, and the clock port of the SPI FLASH chip is connected to the clock port of the SPI display screen.

[0018] In some implementations, after the MCU sends a data read instruction to the SPI FLASH chip and configures the received data number register to set the number of received data, it controls the SPI to prohibit sending, so that the SPI triggers the receive-only mode, thereby causing the MCU to automatically generate a clock signal.

[0019] The MCU stops generating the clock signal after the reception of the data to be displayed is completed.

[0020] In some implementations, the MCU determines whether the data reception is completed through a reception completion flag bit of the received data number register.

[0021] In some embodiments, the MCU and the SPI display screen both have a backlight port, a command port, and a reset port, and the backlight port, command port, and reset port of the MCU are respectively connected to the backlight port, command port, and reset port corresponding to the SPI display screen.

[0022] According to a SPI display screen display system provided by the utility model, display resources stored in SPI FLASH can be displayed on the SPI display screen without consuming the internal RAM cache space of the MCU, and the refresh frame rate of the SPI display screen can be improved, so that the display switching of the SPI display screen is smoother. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present solution.

[0024] Figure 1 It is a schematic diagram of the overall structure of an embodiment of the utility model;

[0025] Figure 2 It is a structural schematic diagram of a prior art of the utility model;

[0026] Figure 3 It is a structural schematic diagram of another prior art of the utility model;

[0027] Figure 4It is a schematic diagram of the overall process of an embodiment of the utility model. DETAILED DESCRIPTION

[0028] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the specific implementation methods of the utility model will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0029] In order to simplify the drawings, only the parts related to the utility model are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0030] Small-size displays are increasingly being used in products with human-computer interaction functions, such as smart bracelets, floor scrubbers, coffee machines, and so on. For 32-bit MCUs, SPI interface peripherals are used as a standard resource to support driving SPI displays (e.g., SPI LCD displays). When you want to display the display resources stored in the SPI FLASH memory chip on the SPI LCD display, the most common way is to use the MCU as a transfer medium between the SPI FLASH memory chip and the SPI LCD display, first read the display resource data stored in the SPI FLASH memory chip to the MCU, temporarily store it in the RAM cache space inside the MCU, and then write the display resource data in the RAM cache space to the SPI LCD display for display.

[0031] A solution adopted by the prior art is to set up two different SPI interfaces for control, such as Figure 2As shown, different SPI interfaces are connected to the SPI FLASH storage chip and the SPI display screen respectively. Specifically, the MCU is connected to the SPI FLASH and the SPI display screen through the FLASH chip select (CS) port and the LCD chip select (CS) port respectively, and the MCU is connected to the SPIFLASH through one SPI interface, specifically through the clock (SCK) port, the host output slave input (MOSI) port, and the host input slave output (MISO) port; the MCU is connected to the SPI display screen through another SPI interface, specifically through the clock (SCK) port and the host output slave input (MOSI) port. The MCU and the SPI display screen are also connected through the conventional backlight (BL) port, command / data (RS) port, and reset (RESET) port. This solution requires two SPI interface resources, and different software design methods (such as interrupt, DMA, DMA+double buffering) can be used to operate these two peripherals at the same time, thereby improving the refresh frame rate of the SPI LCD; but it is not applicable to the MCU with only one SPI interface resource; and when the number of SPI interface resources is large, the cost of the corresponding MCU will also increase.

[0032] Another solution adopted by the prior art is to share the SPI interface, such as Figure 3 As shown, by sharing the two signal lines SCK and MOSI of the SPI interface, the connection method of other ports remains unchanged, and the SPI FLASH or SPI LCD display is operated through the CS chip selection in different time periods. This hardware design solution only requires one SPI interface resource, but can only operate one peripheral at the same time, which is less efficient than the first solution. However, no matter which of the above solutions is used, the MCU is required to implement the data transfer operation between the SPI FLASH storage chip and the SPI LCD display; in terms of MCU resources, a certain amount of RAM is required as a transfer cache space, and the larger the RAM cache space that can be allocated, the fewer the number of MCU transfers, the less software overhead for implementing the transfer function, and the refresh frame rate of the SPI LCD display will increase accordingly; and the larger the MCU's RAM resources, the higher the corresponding MCU cost. Therefore, if you want to increase the refresh frame rate of the SPI display, the larger the MCU's RAM resources are required, and the higher the corresponding MCU cost is. The purpose of this application is to enable the MCU, which realizes data transfer between the SPI FLASH storage chip and the SPI LCD display, to reduce software overhead as much as possible, improve the refresh frame rate of the SPI LCD display without consuming the internal RAM cache space, and make the display switching of the SPI LCD display smoother. Below, this solution will be described in detail with reference to the accompanying drawings:

[0033] In one embodiment, the reference specification Figure 1 The utility model provides a SPI display screen display system, including: SPI FLASH chip and MCU. The SPI FLASH chip is used to store data to be displayed, and the MCU is a microprocessor. In other embodiments, other control terminals can also be selected, and this application does not limit them.

[0034] The SPI FLASH chip has one MOSI port and one MISO port; the MCU has two MOSI ports and one MISO port; the SPI display has one MOSI port.

[0035] The MCU is connected to the MOSI port of the SPI FLASH chip through the first MOSI port, the MCU is connected to the MOSI port of the SPI display screen through the second MOSI port, and the MCU is connected to the MISO port of the SPI FLASH chip through the MISO port. This application shares the MOSI signal line of the SPI interface, and sets the two MOSI ports of the MCU to be connected to the SPI FLASH chip and the SPI display screen respectively, and sets the MISO port of the SPI FLASH chip to be connected to the MOSI port of the SPI display screen. Since the MCU port function multiplexing always finds the same multiplexing function corresponding to one or more different port pins, the above design enables the SPI reception to be enabled, configures the second MOSI port of the MCU as an input function, sends a read data instruction to the SPI FLASH chip, and controls the SPI transmission prohibition. When the data to be displayed can be written directly from the SPI FLASH chip to the SPI display screen for display. This method uses only one SPI interface resource and two MOSI pins to realize the operation of the SPI FLASH chip and the SPI LCD display screen, and can also display the display resource data in the SPI FLASH storage chip on the SPI LCD display screen without consuming any MCU resources. Through hardware connection, the MISO of the SPI FLASH chip is connected to the MOSI of the SPI LCD display. The disadvantages of hardware transmission are eliminated through software configuration, so that a display frame rate close to the theoretical display frame rate calculated according to the SPI communication rate can be achieved.

[0036] According to the description in the SPI serial peripheral interface of the MM32 chip user manual, "When only receiving data, after receiving the number of bytes defined by the SPI_I2S_RXDNR (receive data number register), the hardware will set the SPI_I2S_INTEN.RXMATCH_INTF flag (receive completion flag), and the master device will no longer send a clock signal, and the SCK output will remain in the state configured by the CPOL bit (fixed high or low level)". It can be concluded that after enabling the SPI receive function and disabling the SPI send function, it is in a data-only state. At this time, the MCU will automatically generate the SPI_SCK signal, and set the number of received data by configuring the SPI_I2S_RXDNR register. After receiving the configured amount of data, the MCU will stop generating the SPI_SCK signal and stop receiving data, and the corresponding receive completion flag will be set. The valid value range of the SPI_I2S_RXDNR register is between 1 and 65535, and the default value is 1. The SPI receive buffer has only 4 bytes of valid space, so when the SPI read-only working mode is used and the SPI_I2S_RXDNR (configuration receive data number register) register is set to be greater than 4 to receive data greater than 4 bytes, the SPI receive buffer will inevitably overflow / overwrite. Therefore, if we want to use the SPI read-only working mode, we still need to make some improvements in the hardware.

[0037] The present application sets the MCU to have two MOSI ports, and respectively connects with the MOSI port of the SPI FLASH chip and the MOSI port of the SPI display screen, and sets the MISO port of the MCU to be connected with the MISO port of the SPI FLASH chip, and the MISO port of the SPI FLASH chip to be connected with the MOSI port of the SPI display screen, so that when the SPI reception is controlled to be enabled, the second MOSI port of the MCU is configured as a normal input function, a read data instruction is sent to the SPI FLASH chip, and the SPI transmission is controlled to be prohibited, the data to be displayed can be directly written from the SPI FLASH chip to the SPI display screen for display, so that the display resources stored in the SPI FLASH can be displayed on the SPI display screen without consuming the internal RAM cache space of the MCU, and the refresh frame rate of the SPI display screen can be improved, so that the display switching of the SPI display screen is smoother.

[0038] In one embodiment, Figure 1 As shown, the SPI FLASH chip and the SPI display screen each have a chip select port, the MCU has two chip select ports, the first chip select port of the MCU is connected to the chip select port of the SPI FLASH chip, and the second chip select port of the MCU is connected to the chip select port of the SPI display screen.

[0039] The chip select port of the SPI display screen is pulled down to a low level at the beginning (i.e., the first step of the entire process of this display system), and is set to a high level after the SPI display screen receives the data to be displayed.

[0040] The chip select port of the SPI FLASH chip is pulled down to a low level when SPI reception is enabled and the second MOSI port of the MCU is configured as an input function, and is set to a high level when SPI reception is disabled and the second MOSI port of the MCU is configured as a multiplexing function.

[0041] Preferably, the SPI display screen sets an operation area corresponding to the data to be displayed when the chip select port of the SPI display screen is pulled down to a low level.

[0042] When implementing the direct transmission of data from the SPI FLASH chip to the SPI LCD display, first pull down LCD_CS and configure the LCD area to be operated, then configure the starting address of the SPI FLASH to read data, then enter the SPI receive-only mode, wait for the transmission to be completed, and finally restore each control pin to the default state.

[0043] In one embodiment, Figure 1 As shown, both the MCU and the SPI FLASH chip have clock ports, and the clock port of the MCU is connected to the clock port of the SPI FLASH chip.

[0044] The SPI display screen also has a clock port, and the clock port of the SPI FLASH chip is connected to the clock port of the SPI display screen.

[0045] After the MCU sends a data read instruction to the SPI FLASH chip and configures the register for the number of received data, and sets the number of received data, it controls the SPI to prohibit sending, so that the SPI triggers the receive-only mode, and then the MCU automatically generates a clock signal (i.e., SPI_SCK signal); the MCU stops generating the clock signal after the reception of the data to be displayed is completed. In addition, the system may also generate the SPI_SCK signal at other stages, but they are all generated by the MCU control needs, and are not automatically generated by the MCU when the SPI triggers the receive-only mode in this application.

[0046] Preferably, the MCU determines whether the data reception is completed through the reception completion flag bit of the received data number register.

[0047] After setting the update area for the SPI LCD display and the starting address for reading the display resource for the SPI FLASH chip, the MISO of the SPI FLASH is triggered by the SPI_SCK signal to continuously send out the display resource data. The SPI_SCK signal is essentially a rectangular pulse signal with a fixed frequency and a fixed duty cycle. In other embodiments, other control methods can also be used for control, and this application does not limit it.

[0048] In one embodiment, Figure 1 As shown, both the MCU and the SPI display screen have a backlight port, a command port and a reset port, and the backlight port, command port and reset port of the MCU are respectively connected to the backlight port, command port and reset port corresponding to the SPI display screen.

[0049] In one embodiment, Figure 4 As shown, on the basis of the above embodiment, the operation steps of directly transmitting the resource data stored in the SPI FLASH chip to the SPI display screen in the present application are as follows: pull down the chip select port of the SPI display screen to a low level at the initial time (i.e., the first step of the entire process of the present display system); set an operation area corresponding to the data to be displayed on the SPI display screen; control SPI reception enable, configure the second MOSI port of the MCU as an input function, and pull down the chip select port of the SPI FLASH chip to a low level; the MCU sends a read data instruction to the SPI FLASH chip; the MCU configures the number of received data registers and sets the number of received data; controls SPI transmission prohibition to make the SPI enter a receive-only working mode, thereby making the MCU automatically generate a clock signal; by judging the reception completion flag bit of the receive data number register, judge whether the received data is completed, and wait for the data reception to be completed; control SPI transmission enable to turn off the receive-only working mode of SPI; set the chip select port of the SPI FLASH chip to a high level, control SPI to prohibit reception, and configure the second MOSI port of the MCU as a multiplexing function; set the chip select port of the SPI display screen to a high level after receiving the data to be displayed. This operation step can realize the display resources stored in SPI FLASH on the SPI display without consuming the internal RAM cache space of MCU, and can improve the refresh frame rate of the SPI display, making the display switching of the SPI display smoother.

[0050] There are three control points that need attention: First, when operating SPI FLASH, SPI reception needs to be enabled, and after operating the SPI FLASH chip, SPI reception needs to be disabled; Second, when operating the SPI FLASH chip, the second MOSI port SPI1_MOSI-2 needs to be configured as input, and after operating the SPI FLASH chip, the second MOSI port SPI1_MOSI-2 needs to be restored to the SPI MOSI multiplexing function, because the MISO of the SPI FLASH chip is connected to the MOSI of the SPI LCD display. For the MCU, MISO is the input pin and MOSI is the output pin. These two pins are connected together in hardware. If the pin mode is not switched, the data output by the MISO of the SPI FLASH chip will be incorrect; Third, the SPI receive-only mode is controlled by disabling / enabling SPI transmission when SPI reception is enabled.

[0051] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred implementation of the utility model. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the utility model, and these improvements and modifications should also be regarded as the protection scope of the utility model.

Claims

1. A SPI display screen display system, characterized in that: include: A SPIFLASH chip, storing data to be displayed, wherein the SPIFLASH chip has a MOSI port and a MISO port; The MCU has two MOSI ports and one MISO port; the SPI display has one MOSI port; The MCU is connected to the MOSI port of the SPI FLASH chip through the first MOSI port, the MCU is connected to the MOSI port of the SPI display screen through the second MOSI port, and the MCU is connected to the MISO port of the SPI FLASH chip through the MISO port. The MISO port of the SPI FLASH chip is also connected to the MOSI port of the SPI display screen, so that when the SPI reception is controlled to be enabled, the second MOSI port of the MCU is configured as an input function, a read data instruction is sent to the SPIFLASH chip, and the SPI transmission is controlled to be disabled, the data to be displayed can be directly written from the SPI FLASH chip to the SPI display screen for display.

2. The SPI display screen display system according to claim 1, characterized in that: The SPI FLASH chip and the SPI display screen each have a chip select port, and the MCU has two chip select ports. The first chip select port of the MCU is connected to the chip select port of the SPI FLASH chip, and the second chip select port of the MCU is connected to the chip select port of the SPI display screen.

3. The SPI display screen display system according to claim 2, characterized in that: The chip select port of the SPI display screen is initially pulled down to a low level, and is set to a high level after the SPI display screen receives the data to be displayed.

4. The SPI display screen display system according to claim 2, characterized in that: The chip select port of the SPI FLASH chip is pulled down to a low level when SPI reception is enabled and the second MOSI port of the MCU is configured as an input function, and is set to a high level when SPI reception is disabled and the second MOSI port of the MCU is configured as a multiplexing function.

5. The SPI display screen display system according to claim 2, characterized in that: The SPI display screen sets a to-be-operated area corresponding to the to-be-displayed data when the chip select port of the SPI display screen is pulled down to a low level.

6. The SPI display screen display system according to any one of claims 1 to 5, characterized in that: The MCU and the SPI FLASH chip both have a clock port, and the clock port of the MCU is connected to the clock port of the SPI FLASH chip.

7. The SPI display screen display system according to claim 6, characterized in that: The SPI display screen also has a clock port, and the clock port of the SPI FLASH chip is connected to the clock port of the SPI display screen.

8. The SPI display screen display system according to claim 7, characterized in that: The MCU sends a data read instruction to the SPIFLASH chip, configures the received data number register, sets the number of received data, controls the SPI to prohibit sending, triggers the SPI to receive only mode, and then automatically generates a clock signal by the MCU. The MCU stops generating the clock signal after the reception of the data to be displayed is completed.

9. The SPI display screen display system according to claim 8, characterized in that: The MCU determines whether the received data is completed through the receiving completion flag bit of the received data number register.

10. The SPI display screen display system according to claim 1, characterized in that: The MCU and the SPI display screen both have a backlight port, a command port and a reset port, and the backlight port, command port and reset port of the MCU are respectively connected to the backlight port, command port and reset port corresponding to the SPI display screen.

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