Stacked semiconductor structure

Abstract

A stacked semiconductor structure includes a bottom circuit structure having one or more first semiconductor devices, a first interconnect structure, a first redistribution via, and a first bond pad; the top die circuit structure has a second semiconductor device, a second interconnect structure, an interconnect via, a second redistribution via, and a second bonding pad. The integrated circuit top metal line is arranged on the top crystal grain circuit structure and falls on the interconnection guide hole; the passivation layer is arranged on the top metal line of the integrated circuit; the metal-insulator-metal capacitor structure is arranged in the passivation layer; the integrated circuit redistribution guide hole penetrates through the metal-insulator-metal capacitor structure and the passivation layer to fall on the integrated circuit top metal wire; the integrated circuit aluminum pad is arranged on the integrated circuit redistribution guide hole; the integrated circuit bonding pad is on the integrated circuit aluminum pad.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor structure, and more particularly to a stacked semiconductor structure. Background Art

[0002] The electronics industry continues to have a growing demand for smaller, faster electronic devices that are simultaneously capable of supporting a multitude of increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry continues to develop low-cost, high-performance, and low-power ICs. To date, these goals have been achieved in large part by reducing IC size (e.g., minimum IC feature size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of IC manufacturing processes. Therefore, to achieve continued advancements in IC devices and their performance, similar advancements in IC manufacturing processes and technologies are required.

[0003] Many technological advances have occurred in the field of three-dimensional integrated circuit (3D IC) packaging, which is about stacking and bonding multiple chips together. Each chip includes at least one functional IC, such as an IC configured to perform logic functions, memory functions, digital functions, analog functions, mixed signal functions, radio frequency (RF) functions, I / O functions, communication functions (e.g., by implementing the required communication protocols, such as 5G (i.e., 5th generation) wireless communication protocols, Ethernet communication protocols, IB communication protocols, etc., to provide support for wired communication and / or wireless communication), power management functions, other functions or combinations thereof.

[0004] As 3D IC stacking technology continues to advance, integrated chips are becoming more versatile and highly heterogeneous. These highly integrated devices may experience large current spikes during some circuit operations, such as during simultaneous switching, which may cause noise, voltage bias fluctuations, and resistance-capacitance delays (RC delays) in the power supply network. Specifically, when the transition time of the transient current is particularly short or when the parasitic inductance or parasitic resistance of the line is large, the voltage on the power supply line may fluctuate. Therefore, passive devices, such as capacitors, can be used as part of the 3D IC for signal conditioning. Specifically, filtering or decoupling capacitors can be used as temporary charge reservoirs to prevent instantaneous fluctuations in the power supply voltage. In order to increase the capacitance density in the 3D IC stacking structure, ultra-high density metal-insulator-metal (MIM) capacitors can be used.

[0005] However, as 3D IC multi-chip devices become more dense and more interconnected, decoupling capacitors (e.g., MIM capacitors) may not be effectively utilized. For example, depending on the signal path, some signals of the stacked device remain unfiltered or minimally filtered. That is, because some signal lines bypass the decoupling capacitors, the decoupling capacitors cannot be effectively coupled to the power signal lines to optimize noise filtering.

[0006] Thus, while existing methods and structures for decoupling capacitors in 3D IC devices are generally adequate for their intended purposes, they are not satisfactory in all respects. Utility Model Content

[0007] The purpose of the present invention is to provide a stacked semiconductor structure to solve at least one of the above problems.

[0008] Some embodiments of the utility model provide a stacked semiconductor structure, including: a bottom circuit structure, having one or more first semiconductor devices in a first transistor region; a first interconnect structure on the first transistor region; a first redistribution via on a top metal line of the first interconnect structure; and a first bonding pad on the first redistribution via and electrically connected to the first redistribution via; a top die circuit structure, having a second semiconductor device in a second transistor region; a second interconnect structure under the second transistor region; an interconnect via passing through the second transistor region and a portion of the second interconnect structure to contact the bottom metal line of the second interconnect structure; and a second redistribution via on the second interconnect structure. The invention relates to a method for manufacturing a semiconductor device for manufacturing a semiconductor device for manufacturing a semiconductor device of the present invention, wherein the semiconductor device comprises a bottom metal line, a second bonding pad, a top metal line, a metal-insulator-metal (MIM) capacitor structure, and a metal-insulator-metal capacitor structure. The method comprises: providing a semiconductor device for manufacturing a semiconductor device for manufacturing a semiconductor device of the present invention, wherein the top metal line is provided on the top metal line of the integrated circuit, and the semiconductor device comprises a metal-insulator-metal capacitor structure, a metal-insulator-metal capacitor structure, and a metal-insulator-metal capacitor structure. The method comprises: providing a semiconductor device for manufacturing ...

[0009] According to one embodiment of the present invention, it further includes: a plurality of protection ring structures in the first interconnection structure and surrounding the interconnection guide hole.

[0010] According to one embodiment of the utility model, it also includes: a third bonding pad in the bottom circuit structure; a dielectric filling layer adjacent to the top grain circuit structure and on the third bonding pad; a bypass via passing through the dielectric filling layer and landing on the third bonding pad; a second integrated circuit top metal line on the bypass via; a second metal-insulator-metal capacitor structure in the passivation layer and on the second integrated circuit top metal line; a second integrated circuit redistribution via passing through the second metal-insulator-metal capacitor structure and the passivation layer to land on the second integrated circuit top metal line; a second integrated circuit aluminum pad on the second integrated circuit redistribution via; and a second integrated circuit bonding pad on the second integrated circuit aluminum pad.

[0011] According to one embodiment of the present invention, it also includes: a third redistribution via on a second top metal line of the first interconnect structure, wherein the third bonding pad is on the third redistribution via and electrically connected to the third redistribution via, wherein the first redistribution via is electrically connected to a first bottom device of the plurality of the first semiconductor devices, and the third redistribution via is electrically connected to a second bottom device of the plurality of the first semiconductor devices.

[0012] According to one embodiment of the present invention, the one or more first semiconductor devices are memory devices, and the second semiconductor device is a logic device.

[0013] According to one embodiment of the present invention, the integrated circuit redistribution via has a first width along a first direction, the first redistribution via and the second redistribution via have a second width along the first direction, and the first width is greater than the second width.

[0014] Some other embodiments of the present invention provide a stacked semiconductor structure, including: a bottom circuit structure, having one or more first semiconductor devices in a first transistor region; a first interconnect structure on the first transistor region; a first redistribution via on a top metal line of the first interconnect structure; and a first bonding pad on the first redistribution via and electrically connected to the first redistribution via; a top die circuit structure, having a second semiconductor device in a second transistor region; a second interconnect structure under the second transistor region; an interconnect via passing through the second transistor region and a portion of the second interconnect structure to contact a bottom metal line of the second interconnect structure; a second redistribution via under the bottom metal line of the second interconnect structure; and a second bonding pad, under the second redistribution via and electrically connected to the second redistribution via, wherein the first bonding pad of the bottom circuit structure is bonded to the second bonding pad of the top die circuit structure; an interlayer dielectric (ILD) layer, on the interconnection via; a metal-insulator-metal (MIM) capacitor structure, in the interlayer dielectric layer; an integrated circuit (IC) bonding pad via, passing through the metal-insulator-metal capacitor structure and the interlayer dielectric layer to land on the interconnection via; an integrated circuit top metal line, on the integrated circuit bonding pad via; an integrated circuit redistribution via, on the integrated circuit top metal line; an integrated circuit aluminum pad, on the integrated circuit redistribution via; and an integrated circuit bonding pad, on the integrated circuit aluminum pad.

[0015] According to one embodiment of the present invention, the integrated circuit bonding pad via has a first width along a first direction, the first redistribution via and the second redistribution via have a second width along the first direction, and the first width is greater than the second width.

[0016] According to one embodiment of the present invention, the integrated circuit bonding pad via has a first width along a first direction, the interconnection via has a second width along the first direction, and the first width is greater than the second width.

[0017] According to one embodiment of the utility model, it also includes: a third bonding pad in the bottom circuit structure; a dielectric filling layer adjacent to the top grain circuit structure and on the third bonding pad; a bypass via passing through the dielectric filling layer and falling on the third bonding pad; a second metal-insulator-metal capacitor structure in the interlayer dielectric layer and on the bypass via; a second integrated circuit bonding pad via passing through the second metal-insulator-metal capacitor structure and the interlayer dielectric layer to fall on the bypass via; a second integrated circuit top metal line on the second integrated circuit bonding pad via; a second integrated circuit redistribution via on the second integrated circuit top metal line; a second integrated circuit aluminum pad on the second integrated circuit redistribution via; and a second integrated circuit bonding pad on the second integrated circuit aluminum pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following will be detailed with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the unit may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure. It should also be noted that the drawings only illustrate some embodiments of the present disclosure and therefore should not be considered to limit the scope of the present disclosure, which may also apply to other embodiments.

[0019] According to one embodiment of the present disclosure, Figure 1A-1B A flow chart illustrating a method of forming a stacked semiconductor structure having one or more MIM capacitors.

[0020] According to one embodiment of the present disclosure, Figure 2-Figure 15 Show according to Figure 1A-1B Methods for the formation of stacked semiconductor structures at intermediate stages of fabrication and processing.

[0021] According to one embodiment of the present disclosure, Fig.16 A stacked semiconductor structure is shown with one or more integrated MIM capacitors to filter a received power signal.

[0022] According to another embodiment of the present disclosure, Fig.17 A stacked semiconductor structure is shown with one or more integrated MIM capacitors to filter a received power signal.

[0023] According to another embodiment of the present disclosure, Figure 18A-18B A flow chart illustrating a method of forming a stacked semiconductor structure having one or more MIM capacitors.

[0024] According to one embodiment of the present disclosure, Figure 19-Figure 23 Show according to Figure 18A-18B Methods for the formation of stacked semiconductor structures at intermediate stages of fabrication and processing.

[0025] According to another embodiment of the present disclosure, Fig.24 A stacked semiconductor structure is shown with one or more integrated MIM capacitors to filter a received power signal.

[0026] According to other embodiments of the present disclosure, Figure 25-27 A stacked semiconductor structure is shown with one or more integrated MIM capacitors to filter a received power signal.

[0027] The reference numerals are as follows:

[0028] 100:Semiconductor structure / IC structure / structure

[0029] 108: Guide hole

[0030] 200: Circuit structure

[0031] 201:Substrate

[0032] 202:Semiconductor device / device

[0033] 204: Protection ring structure

[0034] 205: Interconnection structure

[0035] 206: Guide hole

[0036] 207:ILD layer

[0037] 208:Metal Wire

[0038] 209: Passivation layer

[0039] 210: Guide hole

[0040] 212: Aluminum pad

[0041] 214: Guide hole

[0042] 216: Bonding pad

[0043] 250: Grain

[0044] 300: Circuit structure

[0045] 301:Substrate

[0046] 302:Semiconductor device / device

[0047] 305: Interconnection structure

[0048] 307:ILD layer

[0049] 308:Metal Wire

[0050] 309: passivation layer

[0051] 310: Guide hole

[0052] 312: Aluminum pad

[0053] 314: Guide hole

[0054] 316: Bonding pad

[0055] 406: Guide hole

[0056] 409: Filling layer

[0057] 507:ILD layer

[0058] 508:Metal wire

[0059] 509: passivation layer

[0060] 510: Guide hole

[0061] 512: Aluminum pad

[0062] 516: Bonding pad

[0063] 612: Capacitor structure

[0064] 616: Guide hole

[0065] 712: Capacitor structure

[0066] 812: Capacitor structure / capacitor

[0067] 912: Capacitor structure

[0068] 1000:Method

[0069] 1002: Operation

[0070] 1004: Operation

[0071] 1006: Operation

[0072] 1008: Operation

[0073] 1010: Operation

[0074] 1012: Operation

[0075] 1014: Operation

[0076] 1016: Operation

[0077] 1018: Operation

[0078] 1020: Operation

[0079] 1022: Operation

[0080] 1024: Operation

[0081] 1026: Operation

[0082] 1028: Operation

[0083] 1030: Operation

[0084] 1032: Operation

[0085] 1034: Operation

[0086] 2000: Methods

[0087] 2026: Operation

[0088] 2028: Operation

[0089] 2030: Operation

[0090] 2032: Operation

[0091] 2034: Operation

[0092] 2036: Operation

[0093] 201a: Insulator layer

[0094] 301a: Insulator layer

[0095] 812A: Conductor plate

[0096] 812B: Conductor plate

[0097] A: Electrode

[0098] B: Electrode DETAILED DESCRIPTION

[0099] The following content provides many different embodiments or examples to implement different parts of the embodiments of the present disclosure. The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that a first component is formed above or on a second component, which may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0100] Spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0101] Furthermore, when the terms "about", "approximately" and the like are used to describe a number or a range of numbers, the terms are intended to cover values ​​that include the described number within a reasonable range, such as within + / -10% of the described number, or other values ​​understood by a person skilled in the art. For example, the term "about 5 nanometers" may cover a size range from 4.5 nanometers to 5.5 nanometers.

[0102] The present disclosure relates to methods and structures for forming a 3D integrated circuit (IC) structure with filtering or decoupling capacitors. A 3D IC structure is a stacked structure with heterogeneous integration, such as a logic device stacked on a memory device, or vice versa. The filtering or decoupling capacitors include multilayer MIM capacitors that can filter noise in various signal paths. These signal paths can include power signals traveling from a top IC bonding pad to various devices in a 3D IC structure, or they can include signal paths between devices in a 3D IC structure. In order to ensure that the signal does not bypass the MIM capacitors, some MIM capacitors are formed at a position closer to the top of the 3D IC structure. This allows coupling between the input power signal and the MIM capacitor before the power signal is transmitted to the device in the 3D IC structure. For example, the MIM capacitor is formed on a transistor region of a bottom device (e.g., a memory device) and a transistor region of a top device (e.g., a logic device), and the power signal from the top of the 3D IC structure passes through the MIM capacitor before reaching the top and / or bottom device. Forming the MIM capacitor closer to the input power signal ensures that the MIM capacitor is formed along the power signal path before the power signal reaches its destination device. These MIM capacitors may be referred to as IC-level MIM capacitors. The present disclosure also covers other MIM capacitors with more regional characteristics. These MIM capacitors may regulate signals transmitted only to the bottom device, the top device, or between the top device and the bottom device.

[0103] Figure 1A-1B Flow chart of a method 1000 for forming a stacked semiconductor structure 100 having one or more MIM capacitors. Figure 2-Figure 15 Describing method 1000, Figure 2-Figure 15 The formation of a stacked semiconductor structure 100 is shown at an intermediate stage of fabrication and processing according to method 1000. Additional operations may be provided before, during, and after method 1000, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 1000.

[0104] refer to Figure 2, method 1000 receives or provides a first circuit structure 200 in operation 1002, the first circuit structure 200 having a substrate 201, a semiconductor device 202 formed on or in the substrate 201, and an interconnect structure 205 formed on the semiconductor device 202. The first circuit structure 200 may be a portion of a first wafer having the first semiconductor device 202. The semiconductor device 202 may be formed in a transistor region of the substrate 201. The first semiconductor device 202 may be a logic device for operation, logic, control, and I / O operations. The substrate 201 may be a silicon (Si) substrate, or a substrate having other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. In one embodiment, the substrate may include an insulator layer 201a located below the top of the substrate 201. The insulator layer 201a may include a dielectric material such as silicon oxide. In another embodiment, the insulator layer 201a is not present. The semiconductor device 202 may include a device layer structure forming the semiconductor device 202. These structures may include semiconductor features, such as a semiconductor channel, a gate structure on the semiconductor channel, and source / drain features adjacent to the semiconductor channel.

[0105] Continue to refer Figure 2 , an interconnect structure 205 is formed on the semiconductor device 202. The interconnect structure 205 includes components that electrically couple various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain components of the semiconductor device 202) so that the various devices and / or components can operate according to design requirements. The interconnect structure 205 includes a combination of a dielectric layer (e.g., an interlayer dielectric (ILD) layer) and a conductive layer. The conductive layer is configured to form vertical interconnect components, such as metal vias, and / or horizontal interconnect components, such as conductive metal lines. The vertical interconnect components generally connect horizontal interconnect components in different layers (or different planes) of the interconnect structure 205. During operation, the interconnect structure 205 is configured to route signals between the device 202 and / or components of the device 202 and / or distribute signals (e.g., time signals, voltage signals, and / or ground signals) to the device 202 and / or components of the device 202. The interconnect structure 205 may further include a guard ring structure 204. The guard ring structure 204 is a metal component (eg, copper wire) that is formed in a feedthrough via 206 (see Figure 3 ) is used to protect the device 202 and other structures in the substrate 201. The guard ring structure may include a metal via layer and a metal line layer surrounded by an ILD layer.

[0106] Reference now Figure 3, method 1000 forms a first feedthrough via 206 in operation 1004, the first feedthrough via 206 passing through the interconnect structure 205 and a portion of the substrate 201. For example, as shown, the first feedthrough via 206 passes through the top of the substrate 201 and lands on the insulator layer 201a. As shown, the first feedthrough via 206 can pass through a portion of the insulator layer 201a. The first feedthrough via 206 (also referred to as an interconnect via) can be formed by first depositing a dielectric layer (e.g., ILD layer 207) on the first circuit structure 200, performing patterning and photolithography processes to form a first feedthrough via trench, which passes through the dielectric layer, the interconnect structure 205 and a portion of the substrate 201, and then filling the first feedthrough via trench with a metal component. As previously described, when the feedthrough via 206 is formed, the guard ring structure 204 provides protection for the device 202 and other structures in the substrate 201. For example, the guard ring structure 204 provides structural integrity when forming feedthrough via trenches and blocks unwanted moisture, etchants, and chemicals from reaching device layer structures in the substrate 201 during photolithography processes and field applications.

[0107] Reference now Figure 4 , the method 1000 forms other parts of the interconnect structure 205 in operation 1006, including the top metal line 208 above the first feedthrough via 206. As shown, the top metal line 208 can include several metal line layers connected by the metal vias 108. These top metal lines 208 are still part of the interconnect structure 205 and are metal lines in the top metal layer of the interconnect structure 205. As shown, the metal line layer of the top metal line 208 can fall on the first feedthrough via 206 or other vias 108 in the interconnect structure 205.

[0108] Reference now Figure 5 , the method 1000 forms a passivation layer 209 having a dielectric material on the top metal line 208 in operation 1008. Figure 5 In operation 1010 , the method 1000 forms a redistribution via 210 in the passivation layer 209 and on the top metal line 208 . The redistribution via 210 includes a metal material, such as copper, and is located on the top metal layer of the top metal line 208 .

[0109] Reference now Figure 6 , the method 1000 forms an aluminum pad 212 on the redistribution via 210 in operation 1012. The aluminum pad 212 falls on the redistribution via 210 and is formed in the passivation layer 209. The passivation layer 209 may be multi-layered (not shown for simplicity), wherein the passivation layer has each metal sub-layer formed in the passivation layer 209 sub-layer. Figure 6, method 1000 forms bonding pad 216 on aluminum pad 212 in operation 1014 and is electrically connected to aluminum pad 212. For example, as shown in the figure, method 1000 forms bonding pad via 214 on aluminum pad 212 and falls on aluminum pad 212, and forms bonding pad 216 on bonding pad via 214 and falls on bonding pad via 214. Each of these components can be formed in a different sublayer of passivation layer 209. Redistribution via 210, aluminum pad 212 and bonding pad via 214 are different parts of the redistribution layer (RDL) structure. The RDL structure may include additional redistribution routing lines. Redistribution via 210 is a via that connects the RDL structure to the top metal line 208, and bonding pad via 214 is a via that connects the RDL structure to bonding pad 216.

[0110] Reference now Figure 7 , method 1000 dices first circuit structure 200 in operation 1016 to form top die 250 having top semiconductor device 202 and first bonding pad 216. As part of operation 1016 or before operation 1016, method 1000 may probe top die 250 to determine whether it is suitable for subsequent processing and integration.

[0111] Reference now Figure 8 , the method 1000 forms the stacked IC structure 100 in operation 1018 by bonding the top die 250 to the second circuit structure 300. The second circuit structure 300 can be a portion of a second wafer having a second semiconductor device 302. The second semiconductor device 302 can be formed in a transistor region of the second substrate 301. The second semiconductor device 302 can be a memory device, such as an SRAM device for storage and read / write operations. The second circuit structure 300 can be similar to the first circuit structure 200 (refer to Figure 6 ), except that no feedthrough via is formed therein. As shown in the figure, the second circuit structure 300 includes a second substrate 301, a second semiconductor device 302 formed on or in the second substrate 301, a second interconnect structure 305 formed on the second semiconductor device 302, a second redistribution via 310 on the second interconnect structure 305, a second aluminum pad 312 on the second redistribution via 310, a second bonding pad via 314 on the second aluminum pad 312, and a second bonding pad 316 on the second bonding pad via 314.

[0112] The second substrate 310 may include a second insulator layer 301a similar to the insulator layer 201a. The second interconnect structure 305 may include a second top metal line 308 and a via 108 formed between a metal line layer in a dielectric layer (e.g., an ILD layer 307). A second redistribution via 310, an aluminum pad 312, a second bonding pad via 314, and a second bonding pad 316 are formed in the passivation layer 309. The second redistribution via 310, the second aluminum pad 312, and the second bonding pad via 314 are different parts of the second RDL structure. The second RDL structure may include additional redistribution routing lines. The second redistribution via 310 is a via that connects the second RDL structure to the second top metal line 308, and the second bonding pad via 314 is a via that connects the second RDL structure to the second bonding pad 316. It should be noted that the second circuit structure 300 is not a die and may include one or more semiconductor devices 302. As such, the second circuit structure 300 may include more devices than the top die 250. In an illustrative example, the second circuit structure 300 may include two memory devices, while the top die 250 includes one logic device.

[0113] Continue to refer Figure 8 , the top die 250 is bonded to the second circuit structure 300 by a flip chip process, wherein the front side of the top die 250 is bonded to the front side of the second circuit structure 300. Specifically, the bonding pad 216 of the top die 250 is bonded to the bonding pad 316 of the second bonding pad 316. In this way, one or more devices 202 can be vertically stacked on one or more devices 302.

[0114] Reference now Fig. 9 In operation 1020, the method 1000 performs a gap filling process on the stacked IC structure 100, the gap filling process using the dielectric filling layer 409 to fill the gap adjacent to the top die 250. The gap filling process can be any suitable deposition process. The dielectric filling layer 409 can be deposited on the substrate 201, the passivation layer 309, and the other bonding pad 316.

[0115] Reference now Fig.10 , method 1000 forms a second feedthrough via 406 (also referred to as a bypass via) in operation 1022, which passes through dielectric fill layer 409 and lands on bonding pad 316 of second circuit structure 300. Second feedthrough via 406 is a bypass via that bypasses top die 250 to connect second circuit structure 300 to IC top metal line (formed later). It should be noted that second feedthrough via 406 has a greater height in the vertical direction than first feedthrough via 206. Formation of second feedthrough via 406 is similar to formation of first feedthrough via 206, and includes patterning and deposition.

[0116] Reference now Fig.11 The method 1000 performs a planarization process (eg, a CMP process) in operation 1024 to expose the top surface of the first feedthrough via 206 and the top surface of the second feedthrough via 406 .

[0117] Reference now Fig.12 , method 1000 forms an interconnect structure on the back side of top die 250 in operation 1026, thus referred to as a backside interconnect structure. The backside interconnect structure may include metal lines and vias distributed in one or more metal layers. The backside interconnect structure includes an IC top metal line 508 on the first feedthrough via 206 and the second feedthrough via 406. The IC top metal line 508 may include several metal line layers connected by metal vias 108. The IC top metal line 508 is electrically connected and may fall on the first feedthrough via 206 and / or the second feedthrough via 406. The IC top metal line 508 is formed in another ILD layer 507.

[0118] Reference now Fig.13 , method 1000 forms MIM capacitor structure 812 on IC top metal line 508 in operation 1028. MIM capacitor structure 812 includes multiple conductor plate layers separated from each other by insulator layers (e.g., high-k (dielectric constant) dielectric layers). MIM capacitor structure 812 can be formed by multiple processes, including processes for forming and patterning bottom conductor plates, intermediate conductor plates, top conductor plates or additional conductor plates. Multiple processes also include processes for forming and patterning bottom insulator layers, intermediate insulator layers, top insulator layers or additional insulator layers. In other words, MIM capacitor structure 812 may include multiple metal conductor plate layers intertwined with multiple insulator layers. Multilayer MIM capacitor structure 812 allows capacitors to be tightly packaged together in the vertical direction and in the lateral direction, thereby reducing the lateral space required for implementing capacitors. Therefore, MIM capacitor structure 812 can accommodate ultra-high density capacitors.

[0119] Continue to refer Fig.13 , the MIM capacitor structure 812 is formed in the IC passivation layer 509. For example, the IC passivation layer 509 is first deposited on the workpiece, and then the MIM capacitor structure 812 is formed in the IC passivation layer 509 through appropriate patterning and photolithography processes.

[0120] Reference now Fig.14 In operation 1030, the method 1000 forms an IC redistribution via 510 on the IC top metal line 508 and through the MIM capacitor structure 812. The IC redistribution via 510 is located on the IC top metal line 508 and through a portion of the MIM capacitor structure 812 (i.e., a portion connected to one end of the capacitor electrode, e.g., Fig.14ACapacitor electrode A or B in the circuit). Fig.14A A MIM capacitor structure 812 is shown, which has a first conductor plate 812A connected to capacitor electrode A and a second conductor plate 812B connected to capacitor electrode B. The IC redistribution via 510 can be electrically coupled to capacitor electrode A by passing through and contacting the first conductor plate 812A of the MIM capacitor structure 812. In this case, electrode B can be connected to a ground power line (not shown). Alternatively, the IC redistribution via 510 can be electrically coupled to capacitor electrode B by passing through and contacting the second conductor plate 812B of the MIM capacitor structure 812. In this case, electrode A can be connected to a ground power line (not shown).

[0121] Reference now Fig.15 In operation 1032, the method 1000 forms an IC aluminum pad 512 on the IC redistribution via 510. Fig.15 , method 1000 forms an IC bonding pad 516 on the IC aluminum pad 512 in operation 1034. The aluminum pad 512 and the IC bonding pad 516 can be formed in the IC passivation layer 509. Similar to the passivation layers 209 and 309, the IC passivation layer 509 can be multi-layered, wherein the passivation layer has sub-layers that are formed separately and surround different metal components (e.g., IC redistribution vias 510, IC aluminum pads 512, and IC bonding pads 516). The IC redistribution vias 510 and the IC aluminum pads 512 are different parts of the IC RDL structure. The IC RDL structure may include additional redistribution routing lines or vias. The IC redistribution vias 510 are vias that connect the IC RDL structure to the IC top metal line 508. In one embodiment, the IC bonding pads 516 are where the input power signal is received.

[0122] Fig.16 Show Fig.15 The stacked semiconductor structure 100. In addition, Fig.16Solid and dotted arrows representing input power signals are shown. According to an embodiment of the present disclosure, arrows show how one or more integrated MIM capacitors 812 filter received input power signals. As shown, the stacked semiconductor structure 100 receives the input power signal through the IC bonding pad 516. The input power signal may include a desired power signal (solid arrow) and undesirable noise, such as a frequency spike (dotted arrow). The input power signal travels through various metal components (bonding pads, aluminum pads, redistribution layers, metal lines, interconnects, vias, etc.) to power the corresponding semiconductor devices 202 and 302. As shown, due to the MIM capacitor structure 812 in the signal path, undesirable noise is filtered and does not reach the corresponding semiconductor devices 202 and 302. Specifically, the MIM capacitor structure 812 is coupled to the IC redistribution vias 510 in the top IC layer portion of the stacked semiconductor structure 100. The MIM capacitor structure 812 shorts the undesired noise (dashed arrow) to the ground power line (not shown), so that only the desired power signal (solid arrow) travels through the IC redistribution via 510 and along the IC top metal line 508 to reach the corresponding semiconductor devices 202 and 302. For example, the undesired noise propagates to the ground through the first capacitor plate 812A, and the desired power signal propagates through the second capacitor plate 812B and through the IC redistribution via 510 (refer to FIG. Fig.14A ) propagates. One path may pass through the first feedthrough via 206 (or interconnect via) to reach the first semiconductor device 202. It should be noted that if there are more devices 202 in the top die 250, the above path may reach multiple first semiconductor devices 202. Another path may reach the second semiconductor device 302 through the second feedthrough via 406 (or bypass via). In this path, the power signal skips the metal wiring in the top die 250 and directly reaches the second circuit structure 300. In yet another path, the power signal may pass through the top die 250 and enter the second circuit structure 300 through the bonding pads 216 and 316. In this longer path, the power signal may also reach the second semiconductor device 302. In all possible paths, because the decoupling MIM capacitor 812 filters the input power signal early in the path (e.g., at the IC redistribution via 510 on the top die 250 and the second circuit structure 300), the current spikes, voltage bias fluctuations and / or current resistance drops are decoupled before reaching the corresponding semiconductor devices 202 and 302.

[0123] Fig.17 Shown with Fig.16 Another embodiment of a similar stacked semiconductor structure 100 . Fig.17The power signal path of the example is also shown. The difference here is the integration of the additional MIM capacitor structure 712 located in the lower layer and the top die 250. These structures are not in the IC layer but are specific to the top die 250. For example, they are located in the passivation layer 209 and coupled to the redistribution vias 210. The MIM capacitor structure 712 does not filter or decouple the undesirable noise from the IC bonding pad 516 and go to the semiconductor device 202. This is because they are not along the signal path before arriving at the semiconductor device 202. However, the MIM capacitor structure 712 can be included to filter the undesirable crosstalk and coupling between the semiconductor device 202 and the semiconductor device 302. For example, as shown in the figure, the signal path starting from the semiconductor device 202 passes through the MIM capacitor structure 712 before arriving at the semiconductor device 302.

[0124] According to another embodiment of the present disclosure, Figure 18A-18B Flow chart of a method 2000 for forming a stacked semiconductor structure 100 having one or more MIM capacitors 812. Figure 19-Figure 23 Describe Method 2000, Figure 19-Figure 23 The formation of the stacked semiconductor structure 100 is shown at an intermediate stage of fabrication and processing according to the method 2000. Additional operations may be provided before, during, and after the method 2000, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 2000.

[0125] Method 2000 is similar to method 1000 described above. Specifically, operations 1002-1024 in method 2000 may be the same as operations 1002-1024 in method 1000. Therefore, for the sake of brevity, similar operation steps will not be described again. The difference in method 2000 is operations 2026-2036, which indicate the position difference when forming the MIM capacitor structure 812. Operations 2026-2036 are described in more detail below.

[0126] Fig.19 The stacked semiconductor structure 100 is shown at the end of operation 1024 of the method 2000. Fig.11 The stacked semiconductor structure 100 in FIG. 1 shows that the first feedthrough via 206 and the second feedthrough via 406 are exposed.

[0127] Reference now Fig. 20 In operation 2026, method 2000 forms a MIM capacitor structure 812 on the first feedthrough via 206 and the second feedthrough via 406 (similar to that described with respect to method 1000). The MIM capacitor structure 812 is formed on the ILD layer 507. For example, the ILD layer 507 is first deposited on the workpiece, and the MIM capacitor structure 812 is formed in the ILD layer 507 by a suitable patterning and photolithography process.

[0128] Reference now Fig.21 In operation 2028, method 2000 forms an IC bonding pad via 616 on the first feedthrough via 206 and the second feedthrough via 406 through MIM capacitor structure 812. IC bonding pad via 616 falls on the first feedthrough via 206 and the second feedthrough via 406, and passes through a portion of MIM capacitor structure 812 (i.e., a portion connected to one end of a capacitor electrode, e.g., Fig.14A The IC bonding pad guide hole 616 can be electrically coupled to the capacitor electrode A by passing through and contacting the first conductor plate 812A of the MIM capacitor structure 812. In this case, the electrode B can be connected to a ground power line (not shown). Alternatively, the IC bonding pad guide hole 616 can be electrically coupled to the capacitor electrode B by passing through and contacting the second conductor plate 812B of the MIM capacitor structure 812. In this case, the electrode A can be connected to a ground power line (not shown).

[0129] Reference now Fig. 22 , method 2000 forms IC top metal line 508 on IC bonding pad via 616 in operation 2030. IC top metal line 508 may include several metal line layers connected by metal via 108. IC top metal line 508 is electrically connected to IC bonding pad via 616 and may fall on IC bonding pad via 616. IC top metal line 508 is formed in ILD layer 507, which may be multiple layers to surround IC bonding pad via 616, MIM capacitor structure 812, and IC top metal line 508.

[0130] Reference now Fig.23 , method 2000 forms IC redistribution vias 510 on IC top metal lines 508 in operation 2032. IC redistribution vias 510 are formed in IC passivation layer 509, which may be first deposited on the workpiece. It should be noted that in this embodiment, unlike the embodiment of method 1000, no MIM capacitor structures 812 are formed at this level (i.e., in IC passivation layer 509), and IC redistribution vias 510 do not pass through any MIM capacitor structures 812.

[0131] Continue to refer Fig.23 In operation 2034, the method 2000 forms an IC aluminum pad 512 on the IC redistribution via 510. Fig.23, method 2000 forms IC bonding pad 516 on IC aluminum pad 512 in operation 2036. Aluminum pad 512 and IC bonding pad 516 can be formed in IC passivation layer 509. Similar to passivation layers 209 and 309, IC passivation layer 509 can be multi-layered, wherein the passivation layer has sub-layers formed separately and surrounding different metal components (e.g., IC redistribution via 510, IC aluminum pad 512, and IC bonding pad 516). IC redistribution via 510 and IC aluminum pad 512 are different parts of the IC RDL structure. The IC RDL structure can include additional redistribution routing lines or vias. IC redistribution via 510 is a via that connects the IC RDL structure to the IC top metal line 508. In one embodiment, IC bonding pad 516 is where the input power signal is received.

[0132] It should be noted that for method 2000, the MIM capacitor structure 812 is formed in an additional layer (i.e., a sublayer of the ILD layer 507) located directly between the first and second feedthrough vias 206 and 406 and the IC top metal line 508. This has an additional process step compared to method 1000, in which the MIM capacitor structure is formed in the IC passivation layer 509 closer to the IC bonding pad 516. It should be noted that in the example Fig.17 In another embodiment (not shown here), the MIM capacitor structure 712 may also exist in the stacked semiconductor structure 100 as shown in FIG. 23 .

[0133] Fig.24 Show Fig.23 The stacked semiconductor structure 100. In addition, Fig.24Solid and dotted arrows representing input power signals are shown. According to an embodiment of the present disclosure, arrows show how one or more integrated MIM capacitors 812 filter received input power signals. As shown, stacked semiconductor structure 100 receives input power signals through IC bonding pads 516. The input power signal may include a desired power signal (solid arrow) and undesirable noise, such as a frequency spike (dotted arrow). The input power signal travels through various metal components (bonding pads, aluminum pads, redistribution layers, metal lines, interconnects, guide holes, etc.) to power corresponding semiconductor devices 202 and 302. As shown, due to the MIM capacitor structure 812 in the signal path, undesirable noise is filtered and does not reach the corresponding semiconductor devices 202 and 302. Specifically, the MIM capacitor structure 812 is coupled to the IC bonding pad guide holes 616 in the top IC layer portion of the stacked semiconductor structure 100. The MIM capacitor structure 812 shorts the undesired noise (dashed arrow) to the ground power line (not shown), so that only the desired power signal (solid arrow) travels through the IC bonding pad via 616 along the first and second feedthrough vias 206 and 406 to reach the corresponding semiconductor devices 202 and 302. For example, the undesired noise propagates to the ground through the first capacitor plate 812A, and the desired power signal propagates through the second capacitor plate 812B and through the IC bonding pad via 616 (refer to FIG. Fig.14A ) propagates. One path may pass through the first feedthrough via 206 (or interconnect via) to reach the first semiconductor device 202. It should be noted that if there are more devices 202 in the top die 250, the above path may reach multiple first semiconductor devices 202. Another path may reach the second semiconductor device 302 through the second feedthrough via 406 (or bypass via). In this path, the power signal skips the metal wiring in the top die 250 and directly reaches the second circuit structure 300. In yet another path, the power signal may pass through the top die 250 and enter the second circuit structure 300 through the bonding pads 216 and 316. In this longer path, the power signal may also reach the second semiconductor device 302. In all possible paths, because the decoupling MIM capacitor 812 filters the input power signal early in the path (e.g., at the IC bonding pad via 616 on the top die 250 and the second circuit structure 300), current spikes, voltage bias fluctuations and / or current resistance reduction are decoupled before reaching the corresponding semiconductor devices 202 and 302.

[0134] According to other embodiments of the present disclosure, Figure 25-27 A stacked semiconductor structure 100 is shown having one or more integrated MIM capacitors.

[0135] Fig.25An embodiment with a MIM capacitor structure 612 located in a lower layer and in the second circuit structure 300 is shown. These structures are not in the IC layer but are specific to the second circuit structure 300. For example, they are located in the passivation layer 309 and coupled to the second bonding pad via 314. Similar to the MIM capacitor structure 712, the MIM capacitor structure 612 does not filter or decouple the undesirable noise from the IC bonding pad 516 and go to the semiconductor device 202. This is because they do not pass through the MIM capacitor structure 612 along the signal path before reaching the semiconductor device 202. However, here, the MIM capacitor structure 612 can filter or decouple the undesirable noise from the IC bonding pad 516 and go to the semiconductor device 302. For example, in the signal path that bypasses the top die 250 and passes through the second feedthrough via 406, the MIM capacitor structure 612 filters the noise before the noise reaches the semiconductor device 302. Therefore, for the power signal not passing through the top die 250 and going directly to the second circuit structure 300 , the MIM capacitor does not need to be formed in the IC top layer of the stacked semiconductor structure 100 .

[0136] Fig.26 A combined embodiment of a MIM capacitor structure 812 located on the top IC layer and coupled to IC redistribution vias 510 and / or coupled to IC bonding pad vias 616 (described in methods 1000 and 2000, respectively) is shown. In addition, this embodiment also shows coupling to Fig.25 The MIM capacitor structure 612 of the second bond pad via 314 is depicted. Thus, the signal path can pass through multiple MIM capacitor structures for optimized noise filtering.

[0137] Fig. 27 An embodiment with a MIM capacitor structure 912 located in a lower layer and located in the top die 250 is shown. These structures are not in the IC layer but are specific to the top die 250. For example, they are located in the substrate 201 (or the insulator layer 201a of the substrate 201) and directly coupled to the first feedthrough via 206. Unlike the MIM capacitor structure 712, the MIM capacitor structure 912 filters or decouples the undesirable noise from the IC bonding pad 516 and goes to the semiconductor device 202. This is because they pass through the MIM capacitor structure 912 along the signal path before reaching the semiconductor device 202. However, here, the MIM capacitor structure 912 does not filter or decouple the undesirable noise from the IC bonding pad 516 and bypassing the top die 250 and going to the semiconductor device 302. For example, in the signal path that bypasses the top die 250 and travels through the second feedthrough via 406, the MIM capacitor structure 912 does not filter the noise along the signal path before the noise reaches the semiconductor device 302.

[0138] The MIM capacitor structure 812 can be referred to as an IC layer MIM capacitor structure. These MIM capacitor structures are placed closer to the position where the input power is received. Before the input power signal reaches the semiconductor devices 202 and 302, they capture and filter the input power signal at the same layer of the stacked semiconductor structure 100 of each embodiment. It should be noted that other region-specific MIM capacitor structures, such as the MIM capacitor structures 612, 712 and 912 described above, can also be integrated. For example, the MIM capacitor structure 612 is integrated to filter the input power signal that powers the semiconductor device 302 in the second circuit structure 300. The MIM capacitor structure 712 is integrated to filter the crosstalk between the top die 250 and the semiconductor devices 202 and 302 in the second circuit structure 300. The MIM capacitor structure 912 is integrated to filter the input power signal that powers the semiconductor device 202 in the top die 250.

[0139] Now return to reference Fig.23 , the widths of different redistribution vias and / or bonding pad vias coupled to different MIM capacitor structures are described in more detail below. In one embodiment, the IC redistribution via 510 has a greater width than the top die redistribution via 210 and the second circuit structure redistribution via 310. This is because forming a larger IC layer redistribution layer on top of the structure 100 can have greater freedom, especially being able to better couple with the IC layer MIM capacitor structure 812. In one embodiment, the top die redistribution via 210 and the second circuit structure redistribution via 310 each have a width of 1 to 2.7 microns, and the width of the IC redistribution via 510 is 3 microns. Similarly, in one embodiment, the IC bonding pad via 616 can have a greater width than the top die redistribution via 210 and the second circuit structure redistribution via 310. In one embodiment, the IC bonding pad via 616 has a width of 2.5 to 3.5 microns. In one embodiment, the IC bonding pad via 616 has a greater width than the first feedthrough via 206 and the second feedthrough via 406.

[0140] In addition to the different aluminum pads described in the present disclosure (which include aluminum materials), the different metal wirings and interconnects described in the present disclosure (e.g., redistribution vias, redistribution layers, bonding pads, feedthrough vias, metal lines, etc.) may include copper materials. The ILD layer described in the present disclosure may include silicon oxide, a material containing silicon oxide, or a low-K (dielectric constant) dielectric layer, such as TEOS oxide, undoped silicate glass (undoped silicate glass, USG) or doped silicon oxide, such as BPSG, FSG, PSG, BSG and / or other suitable low-K dielectric materials. The passivation layer described in the present disclosure may include silicon oxide, silicon nitride or a suitable dielectric material. For the sake of simplicity, the ILD layer and the passivation layer surrounding multiple metal layers in the same area may be referred to as the same ILD layer and / or passivation layer with multiple sublayers. In various examples, the ILD layer and the passivation layer may be deposited by chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD) or a combination thereof.

[0141] Some embodiments described in the present disclosure refer to the second circuit structure 300 as a bottom structure and having a memory device, and the top die 250 is from the first circuit structure 200 having a logic device. However, in other embodiments, the bottom structure may be the first circuit structure having a logic device, and the top die may be from the second circuit structure having a memory device. It should be noted that the naming of the first or second circuit structure, semiconductor device, passivation layer, etc. may be reversed without departing from the spirit and scope of the present disclosure.

[0142] While not intended to limit the present disclosure, the present disclosure provides benefits to stacked 3D IC semiconductor structures by integrating filtering or decoupling capacitors. One example benefit is utilizing ultra-high density MIM capacitors and integrating them closer to the top of the stacked semiconductor structure so that they filter power signals to the top and bottom stacked semiconductor devices. Another example benefit is integrating additional area-specific MIM capacitors that filter signals that propagate only to the bottom device, the top device, or between the top and bottom devices. Another example benefit is forming MIM capacitors to couple to larger redistribution vias and / or bond pad vias to better couple with IC layer MIM capacitor structures.

[0143] In one exemplary aspect, the present disclosure provides a method for forming a stacked semiconductor structure, comprising: receiving a first circuit structure, the first circuit structure having a semiconductor device formed on a first substrate; an interconnect structure formed on the semiconductor device; a first feedthrough via passing through the interconnect structure and a portion of the first substrate; a top metal line on the first feedthrough via; a redistribution via on the top metal line; and a bonding pad on the redistribution via; cutting the first circuit structure to form a top die, the top die having a top semiconductor device and the first bonding pad; forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having a second semiconductor device formed on a second substrate; and a second interconnect structure formed on the second semiconductor device. a first bonding pad on the second redistribution via, wherein the first bonding pad of the top die is bonded to the first bonding pad of the second bonding pad; a planarization process is performed to expose the top surface of the first feedthrough via; an integrated circuit top metal line is formed on the first feedthrough via; an integrated circuit passivation layer is formed on the integrated circuit top metal line; a metal-insulator-metal (MIM) capacitor structure is formed in the integrated circuit passivation layer; an integrated circuit redistribution via is formed, passing through the metal-insulator-metal capacitor structure and the integrated circuit passivation layer to land on the integrated circuit top metal line; an integrated circuit aluminum pad is formed on the integrated circuit redistribution via; and an integrated circuit bonding pad is formed on the integrated circuit aluminum pad.

[0144] In some embodiments, one of the metal-insulator-metal capacitor structures is a first metal-insulator-metal capacitor formed along a power signal path between an integrated circuit bonding pad and a top semiconductor device, the first metal-insulator-metal capacitor having an electrode electrically connected to the power signal path and another electrode electrically connected to a ground power line.

[0145] In some embodiments, it also includes: performing a gap filling process on the stacked integrated circuit structure, the gap filling process filling the gap between adjacent top grains with a dielectric filling layer; and forming a second feedthrough via, passing through the dielectric filling layer to fall on a second bonding pad in the second bonding pad, wherein the formation of the integrated circuit top metal line also forms the integrated circuit top metal line on the second feedthrough via.

[0146] In some embodiments, the other of the metal-insulator-metal capacitor structures is a second metal-insulator-metal capacitor formed along a power signal path between an integrated circuit bonding pad and a bottom semiconductor device of the second semiconductor device, the second metal-insulator-metal capacitor having an electrode electrically connected to the power signal path and another electrode electrically connected to a ground power line.

[0147] In some embodiments, it also includes: forming a top grain metal-insulator-metal capacitor structure in the first circuit structure, wherein the top grain metal-insulator-metal capacitor structure is arranged between the top metal line of the first circuit structure and the bonding pad of the first circuit structure, and the redistribution via of the first circuit structure is formed to pass through the top grain metal-insulator-metal capacitor structure.

[0148] In some embodiments, the top grain metal-insulator-metal capacitor structure is a top grain metal-insulator-metal capacitor formed along a signal path between a top semiconductor device and a bottom semiconductor device of a second semiconductor device, the top grain metal-insulator-metal capacitor having an electrode electrically connected to the signal path and another electrode electrically connected to a ground power line.

[0149] In some embodiments, the top semiconductor device is a logic device and the second semiconductor device is a memory device.

[0150] In some embodiments, the integrated circuit redistribution via has a first width along the first direction, the redistribution via of the first circuit structure has a second width along the first direction, and the first width is greater than the second width.

[0151] In another exemplary aspect, the present disclosure provides a stacked semiconductor structure, including: a bottom circuit structure having one or more first semiconductor devices in a first transistor region; a first interconnect structure on the first transistor region; a first redistribution via on a top metal line of the first interconnect structure; and a first bonding pad on the first redistribution via and electrically connected to the first redistribution via; a top die circuit structure having a second semiconductor device in a second transistor region; a second interconnect structure under the second transistor region; an interconnect via passing through the second transistor region and a portion of the second interconnect structure to contact the bottom metal line of the second interconnect structure; and a second redistribution via on the second interconnect structure. a bottom metal line; and a second bonding pad, under the second redistribution via and electrically connected to the second redistribution via, wherein the first bonding pad of the bottom circuit structure is bonded to the second bonding pad of the top grain circuit structure; an integrated circuit (IC) top metal line, on the top grain circuit structure and landing on the interconnection via; a passivation layer, on the top metal line of the integrated circuit; a metal-insulator-metal (MIM) capacitor structure, in the passivation layer; an integrated circuit redistribution via, passing through the metal-insulator-metal capacitor structure and the passivation layer to land on the top metal line of the integrated circuit; an integrated circuit aluminum pad, on the integrated circuit redistribution via; and an integrated circuit bonding pad, on the integrated circuit aluminum pad.

[0152] In some other embodiments, the method further includes: a guard ring structure in the first interconnect structure and surrounding the interconnect via.

[0153] In other embodiments, it also includes: a third bonding pad in the bottom circuit structure; a dielectric filling layer, adjacent to the top die circuit structure and on the third bonding pad; a bypass via, passing through the dielectric filling layer and landing on the third bonding pad; a second integrated circuit top metal line, on the bypass via; a second metal-insulator-metal capacitor structure, in the passivation layer and on the second integrated circuit top metal line; a second integrated circuit redistribution via, passing through the second metal-insulator-metal capacitor structure and the passivation layer to land on the second integrated circuit top metal line; a second integrated circuit aluminum pad, on the second integrated circuit redistribution via; and a second integrated circuit bonding pad, on the second integrated circuit aluminum pad.

[0154] In other embodiments, it also includes: a third redistribution via on the second top metal line of the first interconnect structure, wherein the third bonding pad is on the third redistribution via and electrically connected to the third redistribution via, wherein the first redistribution via is electrically connected to the first bottom device of the first semiconductor device, and the third redistribution via is electrically connected to the second bottom device of the first semiconductor device.

[0155] In some other embodiments, the first semiconductor device is a memory device, and the second semiconductor device is a logic device.

[0156] In some other embodiments, the integrated circuit redistribution via has a first width along the first direction, the first redistribution via and the second redistribution via have a second width along the first direction, and the first width is greater than the second width.

[0157] In yet another example aspect, the present disclosure provides a stacked semiconductor structure, including: a bottom circuit structure having one or more first semiconductor devices in a first transistor region; a first interconnect structure on the first transistor region; a first redistribution via on a top metal line of the first interconnect structure; and a first bonding pad on the first redistribution via and electrically connected to the first redistribution via; a top die circuit structure having a second semiconductor device in a second transistor region; a second interconnect structure under the second transistor region; an interconnect via passing through the second transistor region and a portion of the second interconnect structure to contact a bottom metal line of the second interconnect structure; a second redistribution via under the bottom metal line of the second interconnect structure; and a second bonding pad, under the second redistribution via and electrically connected to the second redistribution via, wherein the first bonding pad of the bottom circuit structure is bonded to the second bonding pad of the top die circuit structure; an interlayer dielectric (ILD) layer, on the interconnection via; a metal-insulator-metal (MIM) capacitor structure, in the interlayer dielectric layer; an integrated circuit (IC) bonding pad via, passing through the metal-insulator-metal capacitor structure and the interlayer dielectric layer to land on the interconnection via; an integrated circuit top metal line, on the integrated circuit bonding pad via; an integrated circuit redistribution via, on the integrated circuit top metal line; an integrated circuit aluminum pad, on the integrated circuit redistribution via; and an integrated circuit bonding pad, on the integrated circuit aluminum pad.

[0158] In some further embodiments, the integrated circuit bonding pad via has a first width along a first direction, the first redistribution via and the second redistribution via have a second width along the first direction, and the first width is greater than the second width.

[0159] In some further embodiments, the integrated circuit bonding pad via has a first width along a first direction, the interconnection via has a second width along the first direction, and the first width is greater than the second width.

[0160] In some other embodiments, it also includes: a third bonding pad, in the bottom circuit structure; a dielectric filling layer, adjacent to the top die circuit structure, and on the third bonding pad; a bypass via, passing through the dielectric filling layer and landing on the third bonding pad; a second metal-insulator-metal capacitor structure, in the interlayer dielectric layer and on the bypass via; a second integrated circuit bonding pad via, passing through the second metal-insulator-metal capacitor structure and the interlayer dielectric layer to land on the bypass via; a second integrated circuit top metal line, on the second integrated circuit bonding pad via; a second integrated circuit redistribution via, on the second integrated circuit top metal line; a second integrated circuit aluminum pad, on the second integrated circuit redistribution via; and a second integrated circuit bonding pad, on the second integrated circuit aluminum pad.

[0161] In some further embodiments, it also includes: a third redistribution via on the second top metal line of the first interconnect structure, wherein the third bonding pad is on the third redistribution via and electrically connected to the third redistribution via, wherein the first redistribution via is electrically connected to the first bottom device of the first semiconductor device, and the third redistribution via is electrically connected to the second bottom device of the first semiconductor device.

[0162] In some further embodiments, the integrated circuit bonding pad via has a first width along a first direction, the bypass via has a second width along the first direction, and the first width is greater than the second width.

[0163] The features of several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the utility model to achieve the same purpose and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the utility model, and various changes, substitutions and replacements can be made without violating the spirit and scope of the embodiments of the utility model. Therefore, the scope of protection of the utility model shall be defined by the attached claims.

Claims

1. A stacked semiconductor structure, characterized in that: include: a bottom circuit structure having one or more first semiconductor devices in a first transistor region; a first interconnect structure on the first transistor region; a first redistribution via on a top metal line of the first interconnect structure; and a first bonding pad on the first redistribution via and electrically connected to the first redistribution via; a top die circuit structure having a second semiconductor device in a second transistor region; a second interconnect structure under the second transistor region; an interconnect via passing through the second transistor region and a portion of the second interconnect structure to contact a bottom metal line of the second interconnect structure; a second redistribution via under the bottom metal line of the second interconnect structure; and a second bonding pad under the second redistribution via and electrically connected to the second redistribution via, wherein the first bonding pad of the bottom circuit structure is bonded to the second bonding pad of the top die circuit structure; an integrated circuit top metal line on the top die circuit structure and landing on the interconnect via; a passivation layer on the top metal lines of the integrated circuit; a metal-insulator-metal capacitor structure in the passivation layer; an integrated circuit redistribution via, passing through the metal-insulator-metal capacitor structure and the passivation layer to land on the top metal line of the integrated circuit; An integrated circuit aluminum pad on the integrated circuit redistribution via; as well as An integrated circuit bonding pad is on the integrated circuit aluminum pad.

2. The stacked semiconductor structure according to claim 1, wherein: Also includes: A plurality of guard ring structures are provided in the first interconnect structure and surround the interconnect via.

3. The stacked semiconductor structure according to claim 1, wherein: Also includes: a third bonding pad in the bottom circuit structure; a dielectric fill layer adjacent to the top die circuit structure and on the third bonding pad; A bypass via passes through the dielectric filling layer and lands on the third bonding pad; a second integrated circuit top metal line on the bypass via; a second metal-insulator-metal capacitor structure in the passivation layer and on the second integrated circuit top metal line; a second integrated circuit redistribution via, passing through the second metal-insulator-metal capacitor structure and the passivation layer to land on the second integrated circuit top metal line; a second integrated circuit aluminum pad on the second integrated circuit redistribution via; as well as A second integrated circuit bonding pad is on the second integrated circuit aluminum pad.

4. The stacked semiconductor structure according to claim 3, wherein: Also includes: a third redistribution via on a second top metal line of the first interconnect structure, wherein the third bonding pad is on the third redistribution via and is electrically connected to the third redistribution via, The first redistribution via is electrically connected to a first bottom device of the first semiconductor devices, and the third redistribution via is electrically connected to a second bottom device of the first semiconductor devices.

5. The stacked semiconductor structure according to claim 1, wherein: The one or more first semiconductor devices are memory devices, and the second semiconductor device is a logic device.

6. The stacked semiconductor structure according to any one of claims 1 to 5, characterized in that: The integrated circuit redistribution via has a first width along a first direction. The first redistribution via and the second redistribution via have a second width along the first direction, and the first width is greater than the second width.

7. A stacked semiconductor structure, characterized in that: include: a bottom circuit structure having one or more first semiconductor devices in a first transistor region; a first interconnect structure on the first transistor region; a first redistribution via on a top metal line of the first interconnect structure; and a first bonding pad on the first redistribution via and electrically connected to the first redistribution via; a top die circuit structure having a second semiconductor device in a second transistor region; a second interconnect structure under the second transistor region; an interconnect via passing through the second transistor region and a portion of the second interconnect structure to contact a bottom metal line of the second interconnect structure; a second redistribution via under the bottom metal line of the second interconnect structure; and a second bonding pad under the second redistribution via and electrically connected to the second redistribution via, wherein the first bonding pad of the bottom circuit structure is bonded to the second bonding pad of the top die circuit structure; an interlayer dielectric layer on the interconnect via; a metal-insulator-metal capacitor structure in the interlayer dielectric layer; an integrated circuit bonding pad via, passing through the metal-insulator-metal capacitor structure and the interlayer dielectric layer to land on the interconnect via; An integrated circuit top metal line on the integrated circuit bonding pad via; An integrated circuit redistribution via on a top metal line of the integrated circuit; An integrated circuit aluminum pad on the integrated circuit redistribution via; as well as An integrated circuit bonding pad is on the integrated circuit aluminum pad.

8. The stacked semiconductor structure according to claim 7, wherein: The integrated circuit bonding pad via has a first width along a first direction. The first redistribution via and the second redistribution via have a second width along the first direction, and the first width is greater than the second width.

9. The stacked semiconductor structure according to claim 7, wherein: The integrated circuit bonding pad via has a first width along a first direction. The interconnection via has a second width along the first direction, and the first width is greater than the second width.

10. The stacked semiconductor structure according to any one of claims 7 to 9, characterized in that: Also includes: a third bonding pad in the bottom circuit structure; a dielectric fill layer adjacent to the top die circuit structure and on the third bonding pad; A bypass via passes through the dielectric filling layer and lands on the third bonding pad; a second metal-insulator-metal capacitor structure in the interlayer dielectric layer and on the bypass via; a second integrated circuit bonding pad via, passing through the second metal-insulator-metal capacitor structure and the interlayer dielectric layer to land on the bypass via; a second integrated circuit top metal line on the second integrated circuit bonding pad via; a second integrated circuit redistribution via on the second integrated circuit top metal line; a second integrated circuit aluminum pad on the second integrated circuit redistribution via; as well as A second integrated circuit bonding pad is on the second integrated circuit aluminum pad.

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