Hybrid quad flat no-lead QFN and quad flat package QFP integrated circuit package
By adopting a hybrid QFN and QFP lead frame in semiconductor packages, using multiple QFN conductive pads and QFP conductive leads, the problems of bonding difficulties and insufficient input/output complexity in existing packages when supporting multiple integrated circuit dies are solved, achieving more efficient package connections.
Patent Information
- Application Number
- CN202420400965.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-14
- Filing Date
- 2024-03-01
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2034-03-01
AI Technical Summary
Existing semiconductor packages, when supporting multiple integrated circuit dies, have difficulty clamping the lead frame, resulting in unsuccessful bonding and failing to provide sufficient device contacts to handle the increased input/output complexity.
An integrated circuit package with a hybrid quad flat leadless (QFN) and quad flat packages (QFP) provides more complex input/output connections through multiple QFN conductive pads and QFP conductive leads in the lead frame.
It realizes effective support and connection of multiple integrated circuit dies, solves the problems of bonding difficulties and insufficient input/output complexity, and provides a more efficient packaging solution.
Smart Images
Figure CN222720429U_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 449,366, filed on March 2, 2023, the disclosure of which is incorporated herein by reference. Technical Field
[0003] The present disclosure relates generally to semiconductor packaging, and more particularly to quad flat no-lead (QFN) and quad flat package (QFP) semiconductor packages that support the combination of multiple integrated circuit dies. Background Art
[0004] Various packages for semiconductor devices are known in the art. Figure 1 A known quad flat no-lead (QFN) package type shown in FIG. 1 is based on the use of a lead frame 10 including a die pad 12 supporting an integrated circuit die 14. Exposed device contacts of the package are provided in the form of conductive pads 16 flush with the bottom and side edges of a package body 18, which are electrically connected to the integrated circuit die 14 by bonding wires. Figure 2 The known quad flat package (QFP) package type shown in FIG. 1 is also based on the use of a lead frame 20 including a die pad 22 supporting an integrated circuit die 24. However, here the exposed device contacts of the package are provided in the form of conductive leads 26 protruding from the sides of a package body 28 and electrically connected to the integrated circuit die 24 by bonding wires.
[0005] It is recognized that some applications require the use of multiple integrated circuit dies within a single package. In such cases, the lead frame is provided with a corresponding number of die pads and typically a larger number of device contacts. Increasing the number of die pads introduces a number of problems, such as difficulty in clamping the lead frame in order to flatten the die pads to ensure successful bonding of the integrated circuit die, and an inability to provide a sufficient number of device contacts to handle the increased input / output complexity of supporting multiple integrated circuit dies in a single package.
[0006] Thus, there is a need in the art to address the aforementioned problems.It would be advantageous to have a semiconductor package that supports multiple integrated circuit dies and uses a combination of QFN conductive pads and QFP conductive leads to provide increased input / output complexity. Utility Model Content
[0007] In an embodiment, a hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package includes: a lead frame including a first die pad, a second die pad, a plurality of first QFN conductive pads and a plurality of QFP conductive leads; a first integrated circuit mounted to the first die pad; a second integrated circuit mounted to the second die pad; and a package shell encapsulating the first die pad, the first integrated circuit mounted thereon, the second die pad, the second integrated circuit mounted thereon, the plurality of first QFN conductive pads, and proximal ends of the plurality of QFP conductive leads; wherein distal ends of the plurality of QFP conductive leads extend away from side edges of the package shell; wherein bottom surfaces of the plurality of first QFN conductive pads are exposed at the bottom surface of the package shell; and wherein the plurality of first QFN conductive pads are located between the first die pad and the second die pad.
[0008] In some embodiments, the lead frame further includes a plurality of second QFN conductive pads, wherein the package shell further encapsulates the plurality of second QFN conductive pads, and wherein the plurality of second QFN conductive pads are exposed at a bottom surface and at least one side edge of the package shell.
[0009] In some embodiments, the lead frame also includes a third die pad and a third integrated circuit mounted to the third die pad, wherein the packaging shell also encapsulates the third die pad and the third integrated circuit mounted thereon, and wherein the plurality of first QFN conductive pads are also located between the first die pad and the third die pad and between the second die pad and the third die pad.
[0010] In some embodiments, the hybrid QFN and QFP integrated circuit package further includes wire bonds between each of the first integrated circuit and the second integrated circuit and proximal ends of the plurality of QFP conductive leads.
[0011] In some embodiments, the hybrid QFN and QFP integrated circuit package further comprises a solder layer at upper surfaces of the plurality of first QFP conductive leads at proximal ends thereof; wherein the wire bonds are connected to the solder layer.
[0012] In some embodiments, the hybrid QFN and QFP integrated circuit package further includes wire bonds between each of the first integrated circuit and the second integrated circuit and an upper surface of the plurality of first QFN conductive pads.
[0013] In some embodiments, the hybrid QFN and QFP integrated circuit package further comprises a solder layer at an upper surface of the plurality of first QFN conductive pads; wherein the wire bonds are connected to the solder layer.
[0014] In some embodiments, the hybrid QFN and QFP integrated circuit package further includes wire bonds between the first integrated circuit and the second integrated circuit, the wire bonds crossing one or more of the plurality of first QFN conductive pads between the first die pad and the second die pad.
[0015] In some embodiments, the hybrid QFN and QFP integrated circuit package further includes a solder layer at surfaces of the first die pad and the second die pad; wherein the first integrated circuit and the second integrated circuit are mounted to the solder layer.
[0016] In an embodiment, a method for manufacturing a hybrid QFN and QFP integrated circuit package includes: processing a metal plate to provide a prototype lead frame structure, which includes a base plate and a plurality of lead structures; forming a first die pad opening, a second die pad opening, and a recess surrounding the pad structure positioned between the first die pad opening and the second die pad opening in an upper surface of the base plate; mounting a first integrated circuit at the first die pad opening; mounting a second integrated circuit at the second die pad opening; encapsulating the base plate, the first integrated circuit mounted at the first die pad opening, the second integrated circuit mounted at the second die pad opening, and the proximal ends of the plurality of lead structures; thinning the base plate from the back side of the base plate to remove material of the base plate until reaching the recess surrounding the pad structure and producing a plurality of QFN conductive pads; and processing the distal ends of the lead structures to produce a plurality of QFP conductive leads.
[0017] In an embodiment, a hybrid QFN and QFP lead frame includes: a substrate and a plurality of lead structures; a first die pad opening formed in an upper surface of the substrate; a second die pad opening formed in an upper surface of the substrate; and a recess formed in the upper surface of the substrate, which surrounds a pad structure positioned between the first die pad opening and the second die pad opening. The first and second die pad openings have a first depth from a front surface of the substrate. The recess has a second depth from the front surface of the substrate. Wherein, the second depth is deeper than the first depth.
[0018] In some embodiments, the first and second die pad openings have a first depth from the front surface of the substrate, and wherein the recess has a second depth from the front surface of the substrate, the second depth being deeper than the first depth.
[0019] In some embodiments, the hybrid QFN and QFP lead frame further includes a solder layer at upper surfaces of the plurality of lead structures at proximal ends thereof.
[0020] In some embodiments, the hybrid QFN and QFP lead frame further includes a solder layer at an upper surface of the pad structure.
[0021] In some embodiments, the hybrid QFN and QFP lead frame further includes a solder layer at the bottom of the first die pad opening and the second die pad opening.
[0022] In some embodiments, the hybrid QFN and QFP lead frame further includes an insulating layer at the bottom of the recess surrounding the pad structure.
[0023] In some embodiments, the plurality of lead structures include QFP leads and QFN pads.
[0024] In some embodiments, the pad structure is configured to form a QFN pad. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:
[0026] Figure 1 shows a cross-sectional view of a quad flat no-lead (QFN) package;
[0027] Figure 2 shows a cross-sectional view of a quad flat package (QFP) package;
[0028] Figure 3A , Figure 3B and Figure 3C shows a plan view of a hybrid QFN-QFP lead frame supporting multiple integrated circuit dies;
[0029] Figure 4 and Figure 5 Shows the use of Figure 3A , Figure 3B and Figure 3C A cross-sectional view of a hybrid multi-die QFP-QFN package of the lead frame shown in FIG.
[0030] Figures 6A-6G Steps in a method for manufacturing a hybrid multi-die QFP-QFN package are shown. DETAILED DESCRIPTION
[0031] refer to Figure 3A , Figure 3B and Figure 3C , these figures show a plan view (top view) of a hybrid quad flat no-lead (QFN)-quad flat package (QFP) lead frame 100 supporting multiple integrated circuit dies. The lead frame 100 includes tie bar structures 101a extending from corners of a central region 101b. Figure 3A and3C The lead frame 100 in FIG. 1 includes two die pads 102 a and 102 b , a plurality of QFN conductive pads 104 , and a plurality of QFP conductive leads 106 . Figure 3B The lead frame 100 in the embodiment includes three die pads 102a, 102b, 102c, a plurality of QFN conductive pads 104, and a plurality of QFP conductive leads 106. Each QFP conductive lead 106 includes a proximal end 106p located within the boundary of the package specified by the perimeter dot line 110 and a distal end 106d located outside the boundary of the package. The upper surface at the proximal end 106p of the QFP conductive lead 106 is wire-bonded to the integrated circuit die. The upper surface of the QFN conductive pad 104 is further wire-bonded to the integrated circuit die.
[0032] It should be noted that in the central region 101b for the lead frame 100, a plurality of QFN conductive pads 104 are positioned between adjacent die pads 102. For example, Figure 3A Between the die pads 102a and 102b in Figure 3B Between the die pads 102a and 102b, between the die pads 102a and 102c, and between the die pads 102b and 102c. Figure 3A and 3B The embodiment of the present invention does not illustrate the use of QFN conductive pads 104 at the boundary of the package specified by the perimeter dotted line 110. However, it should be understood that in addition to the placement between the die pads 102a and 102b in the central area 101b, such placement of QFN conductive pads 104 at the package boundary can also be supported, such as Figure 3C as shown in .
[0033] Reference now Figure 4 , Figure 4 A cross-sectional view of a hybrid multi-die QFP-QFN package 200 is shown. Figure 4 The cross-section is along Figure 3A 112 in FIG. The lead frame 100 includes a first die pad 102a supporting a first integrated circuit die 224a and a second die pad 102b supporting a second integrated circuit die 224b. Exposed device contacts for the package 200 include: a QFN conductive pad 104 flush with the bottom of the package body 218, which is connected to the integrated circuit die 224a, 224b by a bonding wire; and a QFP conductive lead 106 protruding from the side of the package body 228, which is electrically connected to the integrated circuit die 224a, 224b by a bonding wire. It should also be noted that the bottom surfaces of the first and second die pads 102a and 102b are exposed flush with the bottom of the package body 218 to support electrical and / or thermal contact.
[0034] Reference now Figure 5 , Figure 5 A cross-sectional view of a hybrid multi-die QFP-QFN package 300 is shown. Figure 5 The cross-section is along Figure 3C 113 in FIG. The lead frame 100 includes a first die pad 102a supporting a first integrated circuit die 224a and a second die pad 102b supporting a second integrated circuit die 224b. The exposed device contacts for the package 200 include: a QFN conductive pad 104a flush with the bottom of the package body 218 and a QFN conductive pad 104b flush with the bottom and side edges of the package body 218; wherein the pads 104a, 104b are electrically connected to the integrated circuit dies 224a, 224b through bonding wires. The exposed device contacts of the package 200 also include: a QFP conductive lead 106 protruding from the side of the package body 228; wherein the lead 106 is electrically connected to the integrated circuit dies 224a, 224b through bonding wires. It should also be noted that the bottom surfaces of the first and second die pads 102a and 102b are exposed flush with the bottom of the package housing 218 to enable electrical and / or thermal contact to be made.
[0035] Figures 6A-6G Steps in a method for manufacturing a hybrid multi-die QFP-QFN package are shown.
[0036] Fig. 6A A metal plate, for example made of copper, is processed using etching, stamping, patterning, etc. techniques known in the art to provide a prototype lead frame structure 400 including a substrate 402 and a plurality of lead structures 404. A stamping or patterning process may be used to define the peripheral shape of the substrate 402 and the lead structures 404. An etching process is used to form a first die pad opening 406a, a second die pad opening 406b, and a recess 408 surrounding the pad structure 410 in the upper surface of the substrate 402. It should be noted that the stamping process may also introduce a vertical offset of the lead structure 404 relative to the substrate 402. Figures 3A-3C The top view of the lead frame 100 shown in illustrative figures illustrates the lead frame configuration at this step of the process.
[0037] Figure 6B A solder layer 412 is applied to the bottom of the first die pad opening 406a, the bottom of the second die pad opening 406b, the upper surface of the pad structure 410 and the upper surface of the lead structure 404 at its end close to the substrate 402. An insulating layer 414 is applied at the bottom of the recess 408.
[0038] Figure 6CA die attach process is then performed to mount the first and second integrated circuit dies 224a, 224b onto the substrate 402 within the first die pad opening 406a and the second die pad opening 406b, respectively.
[0039] Fig.6D Wire bonding is then performed to electrically connect the pads of the first and second integrated circuit dies 224a, 224b to each other via bonding wires 416, to the solder layer 412 at the proximal end of the lead structure 404, and to the solder layer 412 at the upper surface of the pad structure 410. It should be noted that the bonding wires 416 between the first and second integrated circuit dies 224a, 224b pass over one or more of the pad structures 410.
[0040] Fig. 6E - The prototype lead frame structure 400 with the mounted and wire-bonded first and second integrated circuit dies 224a, 224b is then placed in a molding cavity, and an encapsulation material (such as a curable resin) is injected into the molding cavity to produce a package shell 228. Such transfer molding processes are well known in the art. The distal ends 420 of the lead structures 404 are clamped by the molding device and are therefore not encapsulated, so that they will extend from the peripheral side of the package shell 228. The substrate 402 of the prototype lead frame structure 400 is only partially encapsulated in the package shell 228; wherein the bottom portion of the substrate 402 is exposed from the package shell 228.
[0041] Fig. 6F - An etching and / or grinding process is then applied to the back side of the substrate 402 of the prototype lead frame structure 400 (and, if desired, to the bottom portion of the package housing 228 as well) to reduce the thickness of the substrate 402. This backside etching / grinding process performed on the substrate 402 continues to remove material of the substrate 402 until the encapsulant material-filled recess 408 surrounding the pad structure 410 is reached. In particular, the backside etching / grinding process is continued until the insulating layer 414 present at the bottom of the recess 408 is reached and removed. At this point, the pad structure 410 becomes individually isolated to form a plurality of QFN conductive pads 104, and portions of the substrate 403 become individually isolated to form the first and second die pads 102a and 102b.
[0042] Figure 6G - A trimming and forming process is then performed at the distal ends 420 of the lead structures 404 to individually isolate and shape the lead structures 404 to form a plurality of QFP conductive leads 106. At this stage, the exposed ends of the tie bars 101a are also cut off.
[0043] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, the illustration and description are considered to be illustrative or exemplary rather than restrictive; the present disclosure is not limited to the disclosed embodiments. Those skilled in the art can understand and implement other changes to the disclosed embodiments by studying the drawings, the disclosure, and the appended claims when practicing the claimed technical solutions.
Claims
1. A hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package, characterized in that: include: a lead frame including a first die pad, a second die pad, a plurality of first QFN conductive pads, and a plurality of QFP conductive leads; a first integrated circuit mounted to a first die pad; a second integrated circuit mounted to a second die pad; as well as a package housing encapsulating a first die pad, a first integrated circuit mounted thereon, a second die pad, a second integrated circuit mounted thereon, the plurality of first QFN conductive pads, and proximal ends of the plurality of QFP conductive leads; wherein the distal ends of the plurality of QFP conductive leads extend away from the side edge of the package housing; wherein bottom surfaces of the plurality of first QFN conductive pads are exposed at a bottom surface of the package housing; and The plurality of first QFN conductive pads are located between the first die pad and the second die pad.
2. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 1, wherein: The lead frame further comprises a plurality of second QFN conductive pads, the package shell further encapsulates the plurality of second QFN conductive pads, and the plurality of second QFN conductive pads are exposed at a bottom surface and at least one side edge of the package shell.
3. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 1, wherein: The lead frame further includes a third die pad and a third integrated circuit mounted on the third die pad, the package shell further encapsulates the third die pad and the third integrated circuit mounted thereon, and the plurality of first QFN conductive pads are further located between the first die pad and the third die pad and between the second die pad and the third die pad.
4. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 1, wherein: Also included is wire bonding between each of the first integrated circuit and the second integrated circuit and proximal ends of the plurality of QFP conductive leads.
5. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 4, wherein: Also included is a solder layer located at upper surfaces of the plurality of QFP conductive leads at proximal ends thereof; wherein the wire bonds are connected to the solder layer.
6. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 1, wherein: Also included is wire bonding between each of the first integrated circuit and the second integrated circuit and an upper surface of the plurality of first QFN conductive pads.
7. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 6, wherein: Also included is a solder layer at an upper surface of the plurality of first QFN conductive pads; wherein the wire bonds are connected to the solder layer.
8. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 1, wherein: Also included is a wire bond between the first integrated circuit and the second integrated circuit, the wire bond crossing one or more of the plurality of first QFN conductive pads between the first die pad and the second die pad.
9. The hybrid quad flat no-lead (QFN) and quad flat package (QFP) integrated circuit package of claim 1, wherein: Also included is a solder layer located at surfaces of the first die pad and the second die pad; wherein the first integrated circuit and the second integrated circuit are mounted to the solder layer.