A MOS driving circuit capable of eliminating current competition

Abstract

A MOS drive circuit capable of eliminating current competition belongs to the technical field of electronic circuits. It is composed of a MOS push-pull output circuit and its pre-amplifier circuit, and the level drive transfer of VAA driving VCC is completed on the amplifier circuit; the MOS push-pull output circuit is a conventional push-pull circuit composed of a PMOS tube Q5 and an NMOS tube Q6; the pre-amplifier circuit can be a common base amplifier circuit composed of an NPN transistor Q1 and a PNP transistor Q2, or a common gate amplifier circuit composed of an NMOS tube Q3 and a PMOS tube Q4. The beneficial effects of the utility model: it can eliminate the current competition of the MOS drive circuit in the prior art.

Description

Technical Field

[0001] The utility model belongs to the technical field of electronic circuits, in particular to a MOS driving circuit capable of eliminating current competition. Background Art

[0002] Push-pull output is an important output mode in electronic circuits, which is used to drive loads. Push-pull output has low output resistance and high output current capabilities, which can ensure fast conversion and stability of output levels.

[0003] The common MOS push-pull output structure is shown in Figure 1 It uses PMOS and NMOS to complement each other. Under the control of the input digital signal, one of the two MOS tubes is turned on and the other is cut off.

[0004] The biggest feature of MOS push-pull output is that it can truly output high and low levels, and has the ability to drive output current at both levels. However, MOS push-pull output has a disadvantage, that is, there will be current competition between the upper and lower MOS tubes. Specifically, when the input is low (static), the upper MOS tube is turned on, the lower MOS tube is turned off, and the output end = VCC. When the input low level is dynamically switched to high level, the upper MOS tube has not been completely turned off, and the lower MOS tube has been turned on, and the current flows directly from the upper MOS tube to GND through the lower MOS tube. When the input is high (static), the upper MOS tube is turned off, the lower MOS tube is turned on, and the output end = GND. When the input high level is dynamically switched to low, that is, the lower MOS tube has not been completely turned off, and the upper MOS tube has been turned on, the current will flow directly from the upper MOS tube to GND through the lower MOS tube. As a result, the resistance of the entire path is very small in dynamic state, close to a short circuit, power consumption increases sharply, heat is serious, and even the drive circuit is burned, causing damage to the output end. Therefore, in circuits driven by MOS tubes, such as motor drive circuits and pulse sending circuits, it is necessary to prevent current competition between the upper and lower tubes when the output rises or falls. The measure is generally to add a necessary delay to the conduction tube. Utility Model Content

[0005] The utility model aims to provide a MOS driving circuit capable of eliminating current competition.

[0006] The utility model is a MOS driving circuit capable of eliminating current competition, which is composed of a MOS push-pull output circuit and a pre-amplifier circuit thereof, and the level driving transfer of VAA driving VCC is completed on the amplifier circuit;

[0007] The MOS push-pull output circuit is a conventional push-pull circuit composed of a PMOS tube Q5 and an NMOS tube Q6;

[0008] The pre-amplifier circuit may be a common base amplifier circuit composed of an NPN transistor Q1 and a PNP transistor Q2, or a common gate amplifier circuit composed of an NMOS transistor Q3 and a PMOS transistor Q4;

[0009] (1) If the front stage is a common base amplifier circuit composed of an NPN transistor Q1 and a PNP transistor Q2, the emitters of Q1 and Q2 are connected as input terminal A; resistor R1 = resistor R2, resistor R1 and resistor R2 are connected in series, and their series terminals are connected to the bases of Q1 and Q2, the other end of R1 is connected to VAA and the other end of R2 is grounded; resistor R3 = resistor R4, one end of R3 is connected to VCC and the other end is connected to the collector of Q1, one end of R4 is grounded and the other end is connected to the collector of Q2; the collector of Q1 is connected to the gate of Q5, the collector of Q2 is connected to the gate of Q6, the drain of Q5 is connected to the drain of Q6 as the power output point B, the source of Q5 is connected to VCC and the source of Q6 is grounded;

[0010] (2) If the pre-stage driving circuit is a common gate amplifier circuit composed of an NMOS transistor Q3 and a PMOS transistor Q4, the sources of Q3 and Q4 are connected as the input terminal A; the resistor R1 = resistor R2, the resistor R1 and the resistor R2 are connected in series, and the series terminal is connected to the gates of Q3 and Q4, the other end of R1 is connected to VAA and the other end of R2 is grounded; the resistor R3 = resistor R4, one end of R3 is connected to VCC and the other end is connected to the drain of Q3, one end of R4 is grounded and the other end is connected to the drain of Q4; the drain of Q3 is connected to the gate of Q5, the drain of Q4 is connected to the gate of Q6, and the drain of Q5 is connected to the drain of Q6 as the power output point B, the source of Q5 is connected to VCC and the source of Q6 is grounded.

[0011] The working principle of the utility model circuit:

[0012] The first case see Figure 2 ; Q1 = NPN tube, Q2 = PNP tube; R1 = R2, R3 = R4, the voltage dividing point of R1 and R2 is connected to the base of Q1 and Q2 tubes (b). The input point A of the microprocessor is connected to the emitter of Q1 and Q2 tubes (e), forming a common base amplifier circuit. The collector of Q1 (c) is connected to the gate of Q5 (G) and one end of R3, and the other end of R3 is connected to VCC. The collector of Q2 (c) is connected to the gate of Q6 (G) and one end of R4, and the other end of R4 is connected to GND. MOS tubes Q5 and Q6 form a conventional push-pull output circuit, and point B is the power output point.

[0013] When input point A = high level (3.3V), the base voltages of Q1 and Q2 tubes are floated to 2.6V, Q2 tube is saturated and turned on, and the no-load measured gate voltages of R4 and Q5 are 3.1V (AO3400; VGS = 2.5V, ID = 4A), Q1 tube is turned off and Q2 tube is turned on, Q5 tube is turned off and Q6 tube is turned on, and point B is a low level.

[0014] When the input point A dynamically drops to 1 / 2VAA, Q1 and Q2 tubes are cut off, and Q5 and Q6 tubes are turned off.

[0015] When input point A = 0V, the base voltages of Q1 and Q2 tubes are floated to 0.7V, Q1 tube is saturated and turned on, the no-load measured voltage of R3 and Q5 gate is less than 0.2V, Q1 tube is turned on and Q2 tube is turned off, Q5 tube is turned on and Q6 tube is turned off, and point B is a high level.

[0016] When the input point A rises dynamically to 1 / 2VAA, Q1 and Q2 tubes are cut off, and Q5 and Q6 tubes are turned off.

[0017] When input point A = high level (3.3V), Q1 tube is turned off and Q2 tube is turned on, Q5 tube is turned off and Q6 tube is turned on, and point B is a low level.

[0018] This circuit fails to detect current competition conflicts during pulse square wave transmission (rated load).

[0019] The second case see Figure 3 , that is, replace with corresponding MOS tubes Q3 and Q4 Figure 2 Q1 and Q2 in .

[0020] Q3 = NMOS tube, Q4 = PMOS tube; R1 = R2, R3 = R4, the voltage dividing point of R1 and R2 is connected to the gate (G) of Q3 and Q4 tubes, and the input point A of the microprocessor is connected to the source (S) of Q1 and Q2 tubes, forming a common gate amplifier circuit. The drain (D) of Q3 is connected to the gate (G) of Q5 and one end of R3, and the other end of R3 is connected to VCC, the drain (D) of Q4 is connected to the gate (G) of Q6 and one end of R4, and the other end of R4 is connected to GND. MOS tubes Q5 and Q6 form a conventional push-pull output circuit, and point B is the power output point.

[0021] When input point A = high level (3.3V), the gate voltage of Q3 and Q4 tubes = 1 / 2VAA = 1.65V, Q4 tube is turned on, and the no-load measured voltage between R4 and Q4 gate is close to 3.3V (AO3400; VGS = 2.5V, ID = 4A), Q3 tube is turned off and Q4 tube is turned on, Q5 tube is turned off and Q6 tube is turned on, and point B is a low level.

[0022] When the input point A dynamically drops to 1 / 2VAA, Q3 and Q4 tubes are cut off, and Q5 and Q6 tubes are turned off.

[0023] When input point A = 0V, the gate voltage of Q3 and Q4 tubes = 1 / 2VAA = 1.65V, Q5 tube is turned on, and the no-load measured voltage of R3 and Q3 gate is close to 0V, Q3 tube is turned on and Q4 tube is turned off, Q5 tube is turned on and Q6 tube is turned off, and point B is a high level.

[0024] When the A input point dynamically rises to 1 / 2VAA, Q3 and Q4 tubes are cut off, and Q5 and Q6 tubes are closed.

[0025] When input point A = high level (3.3V), Q3 tube is turned off and Q4 tube is turned on, Q5 tube is turned off and Q6 tube is turned on, and point B is a low level.

[0026] No current contention conflict was detected during pulse square wave transmission (rated load).

[0027] The beneficial effects of the utility model are as follows: a MOS driving circuit capable of eliminating current competition is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The electrical schematic diagram of the prior art.

[0029] Figure 2 This is the electrical schematic diagram of Example 1.

[0030] Figure 3 The electrical schematic diagram of Example 2. DETAILED DESCRIPTION

[0031] Example 1: See Figure 2 , used in electronic detonator initiators.

[0032] ⅤAA=3.3V,

[0033] VCC=18V,

[0034] Q1 = CS9013,

[0035] Q2 = CS9012,

[0036] Q5=SL2309,

[0037] Q6=AO3400,

[0038] R1=R2=10K,

[0039] R3=R4=3.3K.

[0040] This circuit fails to detect current competition conflicts during pulse square wave transmission (rated load).

[0041] Example 2: Figure 3 , used for electronic detonator initiators.

[0042] ⅤAA=3.3V,

[0043] VCC=18V,

[0044] Q3=AO3400,

[0045] Q4=AO3401,

[0046] Q5=SL2309,

[0047] Q6=AO3400,

[0048] R1=R2=10K,

[0049] R3=R4=3.3K.

[0050] This circuit fails to detect current competition conflicts during pulse square wave transmission (rated load).

Claims

1. A MOS drive circuit capable of eliminating current competition, characterized in that: It consists of a MOS push-pull output circuit and its pre-amplifier circuit; The MOS push-pull output circuit is a push-pull circuit composed of a PMOS transistor Q5 and an NMOS transistor Q6; The pre-amplifier circuit may be a common base amplifier circuit composed of an NPN transistor Q1 and a PNP transistor Q2, or a common gate amplifier circuit composed of an NMOS transistor Q3 and a PMOS transistor Q4. (1) If the pre-amplifier circuit is a common base amplifier circuit composed of an NPN transistor Q1 and a PNP transistor Q2, then the emitters of Q1 and Q2 are connected as input terminal A; resistor R1 = resistor R2, resistor R1 and resistor R2 are connected in series, and their series terminals are connected to the bases of Q1 and Q2, the other terminal of R1 is connected to VAA, and the other terminal of R2 is grounded; resistor R3 = resistor R4, one terminal of R3 is connected to VCC and the other terminal is connected to the collector of Q1, one terminal of R4 is grounded and the other terminal is connected to the collector of Q2; the collector of Q1 is connected to the gate of Q5, the collector of Q2 is connected to the gate of Q6, and the drain of Q5 is connected to the drain of Q6 as the power output point B, the source of Q5 is connected to VCC, and the source of Q6 is grounded; (2) If the pre-amplifier circuit is a common-gate amplifier circuit consisting of an NMOS transistor Q3 and a PMOS transistor Q4, the sources of Q3 and Q4 are connected as input terminal A; resistor R1 = resistor R2, resistor R1 and resistor R2 are connected in series, and their series terminals are connected to the gates of Q3 and Q4, the other terminal of R1 is connected to VAA, and the other terminal of R2 is grounded; resistor R3 = resistor R4, one terminal of R3 is connected to VCC and the other terminal to the drain of Q3, one terminal of R4 is grounded and the other terminal to the drain of Q4; the drain of Q3 is connected to the gate of Q5, the drain of Q4 is connected to the gate of Q6, and the drain of Q5 is connected to the drain of Q6 as power output point B, the source of Q5 is connected to VCC, and the source of Q6 is grounded.

2. The MOS driving circuit capable of eliminating current competition according to claim 1, wherein: The pre-amplifier circuit is a common base amplifier circuit composed of an NPN transistor Q1 and a PNP transistor Q2. VAA=3.3V, VCC=18V, Q1 = CS9013, Q2 = CS9012, Q5=SL2309, Q6=AO3400, R1=R2=10K, R3=R4=3.3K.

3. The MOS driving circuit capable of eliminating current competition according to claim 1, wherein: The pre-amplifier circuit is a common gate amplifier circuit composed of an NMOS transistor Q3 and a PMOS transistor Q4. VAA=3.3V, ⅤCC=18V, Q3=AO3400, Q4=AO3401, Q5=SL2309, Q6=AO3400, R1=R2=10K, R3=R4=3.3K.

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