SiC MOSFET with high short circuit tolerance

Abstract

The utility model discloses a SiC MOSFET with high short circuit tolerance, and relates to the technical field of semiconductors. Comprising an N + substrate layer; a P-Well region extending downwards is arranged on the top surface of the N-drift layer; an N + region which extends downwards is arranged in the P-Well region; a P + region extending downwards is arranged on the top surface of the N + region; the middle part of the N-drift layer is provided with a trench region which extends downwards from the top surface of the N + region to the lower part of the P-Well region. A gate oxide layer and a Poly layer which are connected in sequence are arranged in the trench region; a gap is formed between the gate oxide layer and the side part of the P + region; according to the utility model, the JFET is integrated in the SiC MOSFET device, and the JFET is integrated in the P-Well region of the device, so that when the device is short-circuited, the current can be limited by the internal JFET after flowing through a channel, thereby achieving the purpose of reducing the short-circuit current, and improving the short-circuit endurance capability of the device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC MOSFET with high short-circuit tolerance. Background Art

[0002] At present, under the social environment of energy conservation and emission reduction, carbon peak and carbon neutrality have become the goals of countries around the world. Compared with traditional fossil energy, the conversion and transmission of electric energy are more convenient and more in line with the current development trend. The performance of power semiconductor devices directly determines the key performance of power electronic devices such as conversion efficiency, power density and operating frequency. At present, with the continuous development and maturity of technology, the performance of traditional Si-based devices has been close to the theoretical limit of materials, and it is difficult to meet the use conditions under more stringent working conditions. Compared with traditional Si materials, 4H-SiC materials have a series of characteristic advantages such as large bandgap width, high critical breakdown electric field, small intrinsic carrier concentration, fast saturation drift velocity, high melting point, and high thermal conductivity, which makes it have great advantages in high voltage, high temperature, high frequency and other application fields.

[0003] SiC MOSFET devices have outstanding device performance due to the advantages of their own material characteristics. Compared with Si MOSFET and Si IGBT devices of the same voltage and current capacity, SiCMOSFET has a smaller chip size and thinner chip thickness, and also has the advantages of conduction and switching characteristics of both Si MOSFET and Si IGBT. However, while bringing higher power density, it also brings obvious disadvantages. SiC MOSFET has poor short-circuit tolerance. The short-circuit tolerance time of Si IGBT devices can reach about 10us, while SiC MOSFET is generally less than 5us, which makes its application in harsh working conditions challenging. Therefore, how to improve the short-circuit robustness of SiC MOSFET devices is an urgent issue.

[0004] In response to the above problems, there are existing patent documents, such as "A Silicon Carbide MOSFET Device and Preparation Method" published on July 7, 2022, with an international publication number of WO 2022 / 142435 A1; it includes a substrate substrate, a buffer layer, and a drift layer stacked in sequence from bottom to top, and also includes multiple P-well regions, located inside the drift layer and attached to the upper surface of the drift layer; a P-type control region, located between two adjacent P-well regions in the drift layer and attached to the upper surface of the drift layer; a p+-type base region and an n+-type source region are both located in the P-well region; a gate oxide layer, located on the upper surface of part of the drift layer; a sub-electrode, located on the oxide layer, and one end is located on the n+-type source region, and the other end is located above the area between the P-type control region and the P-well region; a passivation dielectric layer; a source electrode layer, located on the upper surfaces of the P-type control region, the p+-type base region and part of the n+-type source region; a Schottky electrode, located between two adjacent P-type control regions of the drift layer and on the upper surface of the domain, and connected to the source electrode layer: and an electrode layer. Although this case can improve the short-circuit tolerance of the device as mentioned, since the P-type control area for reducing the short-circuit current is produced by sacrificing a portion of the chip area, the source cell size of the device is significantly increased, the power density of the device is reduced, and the cost of the device is directly increased. Utility Model Content

[0005] In view of the above problems, the utility model provides a high short-circuit tolerance SiC MOSFET with high area utilization and improved short-circuit tolerance of the device.

[0006] The technical solution of the utility model is:

[0007] The high short-circuit withstand SiC MOSFET includes the following components arranged from bottom to top:

[0008] N+ substrate layer;

[0009] An N-drift layer, with a P-Well region extending downward on the top surface; an N+ region extending downward is provided in the P-Well region; a P+ region extending downward is provided on the top surface of the N+ region; a groove region extending downward from the top surface of the N+ region to below the P-Well region is provided in the middle of the N-drift layer; a gate oxide layer and a Poly layer connected in sequence are provided in the groove region; a gap is provided between the gate oxide layer and the side of the P+ region;

[0010] The front electrode metal has an ohmic contact alloy layer at the bottom which is respectively connected to the N+ region, the gate oxide layer and the Poly layer; a dielectric layer is provided between the front electrode metal and the P+ region and the N+ region, and the dielectric layer is connected to the side wall of the ohmic contact alloy layer.

[0011] Specifically, the thickness of the gate oxide layer is 60-70 nm.

[0012] Specifically, the thickness ratio between the P-Well region, the N+ region and the P+ region is 1:2:4.

[0013] Specifically, the top surface of the ohmic contact alloy layer is located above the top surface of the dielectric layer.

[0014] Specifically, the top surface of the N+ region is connected to the dielectric layer and the ohmic contact alloy layer respectively.

[0015] The utility model integrates a JFET inside a SiC MOSFET device, and integrates the JFET in a P-Well region of the device, so that when the device is short-circuited, the current flowing through the channel will be limited by the internal JFET, thereby achieving the purpose of reducing the short-circuit current and improving the short-circuit tolerance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0017] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0018] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0019] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0020] Figure 5 It is a structural schematic diagram of step S500 of the utility model;

[0021] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0022] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0023] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0024] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0025] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0026] In the figure, 1 is the N+ substrate layer, 2 is the N-drift layer, 3 is the P-Well region, 4 is the N+ region, 5 is the P+ region, 6 is the gate oxide layer, 7 is the Poly layer, 8 is the dielectric layer, 9 is the ohmic contact alloy layer, and 10 is the front electrode metal. DETAILED DESCRIPTION

[0027] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0028] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] The SiC MOSFET with high short-circuit withstand capability includes the following steps:

[0031] S100, refer to Figure 1 As shown, a lightly doped N- drift layer 2 is epitaxially grown on a heavily doped N+ substrate layer 1;

[0032] The doping ions of the N+ substrate layer 1 in step S100 are N ions with a concentration of 1E19 cm -2 ; The doping ions of N-drift layer 2 are N ions with a concentration of 5E15cm -2 -5E16cm -2 .

[0033] S200, refer to Figure 2 As shown, a shallowly doped P-Well region 3 is formed on the upper surface of the N-drift layer 2 by ion implantation;

[0034] The P-Well region 3 in step S200 is doped with Al ions at a concentration of 1E17 cm -2 -1E18cm -2 .

[0035] S300, refer to Figure 3As shown, a heavily doped N+ region 4 is formed on the upper surface of the P-Well region 3 by ion implantation;

[0036] The doping ions of the N+ region 4 in step S300 are N ions with a concentration of 1E18 cm -2 -5E18cm -2 .

[0037] S400, refer to Figure 4 As shown, a heavily doped P+ region 5 is formed on the upper surface of the N+ region 4 by ion implantation, so that the P-Well region 3, the N+ region 4 and the P+ region 5 form a JFET structure;

[0038] The doping ions of the P+ region 5 in step S400 are Al ions with a concentration of 5E18cm -2 -1E19cm -2 .

[0039] S500, refer to Figure 5 As shown, etching is performed downward on the top surface of the N+ region 4 to form a trench region extending to below the P-Well region 3;

[0040] The bottom surface of the trench region is lower than the P-Well region 3 to ensure that a channel region is formed in the P-Well region 3 when the gate electrode of the device is pressurized.

[0041] S600, refer to Figure 6 As shown, a gate oxide layer 6 is grown in the trench region by dry oxygen oxidation;

[0042] The thickness of the gate oxide layer 6 in step S600 is 60-70 nm to improve the robustness of the gate oxide layer.

[0043] S700, reference Figure 7 As shown, a Poly layer 7 is formed in the trench region by depositing polysilicon to lead out the gate electrode of the MOS device;

[0044] S800, reference Figure 8 As shown, a dielectric layer 8 is formed on the top surface of the N+ region 4 and the trench region by depositing oxide, serving as an isolation layer for isolating the gate electrode of the trench region and the source electrode of the device;

[0045] S900, refer to Fig. 9 As shown, a nickel metal layer connected to the side of the dielectric layer 8 is formed on the top surface of the P+ region 5 by nickel metal sputtering, and then the nickel metal layer and the P+ region 5 are alloyed by annealing to form an ohmic contact alloy layer 9;

[0046] S1000, refer to Fig.10As shown, a front electrode metal 10 is formed on the top surface of the dielectric layer 8 and the ohmic contact alloy layer 9 by titanium / aluminum-copper metal sputtering, which is used as the source electrode of the MOS device;

[0047] A SiC MOS device with improved short-circuit withstand capability includes:

[0048] N+ substrate layer 1;

[0049] The N-drift layer 2 has a P-Well region 3 extending downward on its top surface; an N+ region 4 extending downward is provided in the P-Well region 3; a P+ region 5 extending downward is provided on the top surface of the N+ region 4; a trench region extending downward from the top surface of the N+ region 4 to below the P-Well region 3 is provided in the middle of the N-drift layer 2; a gate oxide layer 6 and a Poly layer 7 connected in sequence are provided in the trench region;

[0050] The front electrode metal 10 has an ohmic contact alloy layer 8 at the bottom which is respectively connected to the N+ region 4, the gate oxide layer 6 and the Poly layer 7; a dielectric layer 9 is provided between the front electrode metal 10 and the P+ region 5 and the N+ region 4, and the dielectric layer 9 is connected to the side wall of the ohmic contact alloy layer 8.

[0051] The thickness ratio between the P-Well region 3, the N+ region 4 and the P+ region 5 is set to 1:2:4, so as to reduce the short-circuit current of the device without excessively affecting the current carrying capacity of the device, and at the same time ensure the reverse voltage withstand performance of the device.

[0052] The utility model improves the short-circuit tolerance of the device:

[0053] Under the same device specifications, SiC MOSFET has a higher power density than Si IGBT and other devices due to its smaller chip size and thinner chip thickness. However, while SiC MOSFET brings excellent performance, it also has disadvantages. Its short-circuit tolerance is worse than that of Si IGBT. Usually, the short-circuit tolerance time of SiC MOSFET is less than 5us. Fig.10 As shown in the figure, the dotted line part is the JFET region integrated inside the structure, which is composed of the P-Well region, the N+ region and the P+ region. The utility model integrates the JFET in the P-Well region of the SiC MOSFET, so that when the device is short-circuited, the short-circuit current flows through the inversion layer channel and is limited by the internally integrated JFET, thereby achieving the purpose of reducing the short-circuit current, improving the short-circuit tolerance of the SiCMOSFET device, and meeting the use requirements under more stringent working conditions.

Claims

1. High short-circuit withstand SiC MOSFET, characterized by: Including setting from bottom to top: N+ substrate layer (1); An N-drift layer (2) is provided with a P-Well region (3) extending downward on its top surface; an N+ region (4) extending downward is provided in the P-Well region (3); a P+ region (5) extending downward is provided on the top surface of the N+ region (4); a groove region extending downward from the top surface of the N+ region (4) to below the P-Well region (3) is provided in the middle of the N-drift layer (2); a gate oxide layer (6) and a Poly layer (7) connected in sequence are provided in the groove region; a spacing is provided between the gate oxide layer (6) and the side of the P+ region (5); A front electrode metal (10) has an ohmic contact alloy layer (8) at the bottom thereof which is respectively connected to an N+ region (4), a gate oxide layer (6) and a Poly layer (7); a dielectric layer (9) is provided between the front electrode metal (10) and the P+ region (5) and the N+ region (4); the dielectric layer (9) is connected to the side wall of the ohmic contact alloy layer (8).

2. The SiC MOSFET with high short-circuit withstand capability according to claim 1, characterized in that: The thickness of the gate oxide layer (6) is 60-70 nm.

3. The SiC MOSFET with high short-circuit withstand capability according to claim 1, wherein: The thickness ratio between the P-Well region (3), the N+ region (4) and the P+ region (5) is 1:2:

4.

4. The SiC MOSFET with high short-circuit withstand capability according to claim 1, wherein: The top surface of the ohmic contact alloy layer (8) is located above the top surface of the dielectric layer (9).

5. The SiC MOSFET with high short-circuit withstand capability according to claim 1, characterized in that: The top surface of the N+ region (4) is connected to the dielectric layer (9) and the ohmic contact alloy layer (8) respectively.

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