SiC field effect transistor with reduced conduction loss

Abstract

The utility model discloses a SiC field effect transistor capable of reducing conduction loss, and relates to the technical field of semiconductors. The SBD structure is integrated in the SiC MOSFET device, the original mode that only a PN junction body diode serves as a discharge path in the follow current process is changed into the mode that the SBD and the PN junction body diode serve as paths at the same time while the source cell through-current capacity of the device is not affected, the conduction loss of the device in the follow current process is reduced, the bipolar degeneration effect of the device is reduced, and the reliability of the device is improved. And the device can be stably used for a long time.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC field effect transistor with reduced conduction loss. Background Art

[0002] In Si-based power devices, the higher the voltage used, the greater the on-resistance per unit area of ​​the device. Therefore, Si IGBT devices are mainly used for voltages above 600V. Due to the conductivity modulation effect of Si IGBT devices, the on-resistance can be smaller than that of MOSFET at high voltages, but due to the accumulation of minority carriers, it will also cause large switching losses during the switching process. Compared with Si devices, SiC devices have lower drift layer impedance, and can achieve high voltage resistance and low impedance with MOSFET of high-frequency device structure without conductivity modulation. In principle, there is no tail current in MOSFET devices. Therefore, when SiC MOSFET is used to replace IGBT, switching losses can be significantly reduced, and the heat dissipation components can be miniaturized. Therefore, SiC MOSFET is considered to be a device that can completely replace Si IGBT in the future, especially in high voltage, high temperature, high frequency and other application fields.

[0003] Due to the internal parasitic PN junction body diode, SiC MOSFET does not need an additional anti-parallel freewheeling diode in the bypass for protection compared to SiIGBT, which not only reduces the number of devices used in the system, but also reduces costs. However, since SiC materials have more defects than Si materials, during the freewheeling process of SiC MOSFET, the conduction of the parasitic PN junction body diode will cause the holes in the P region to enter the drift layer and recombine with the electrons, thereby causing the lattice defects in the drift layer to spread and cause a bipolar degradation effect, which reduces the performance of the device, which greatly affects the long-term stable use of the device. Therefore, how to realize the internal parasitic body diode in SiC MOSFET and improve the bipolar degradation effect caused by the body diode at the same time is of great benefit to the long-term application of the device. Utility Model Content

[0004] In view of the above problems, the utility model provides a SiC field effect transistor with reduced conduction loss, which reduces the conduction loss of the device during the freewheeling process without affecting the current flow capacity of the source cell of the device, reduces the occurrence of bipolar degradation effect of the device, and enables the device to be used stably for a longer period of time.

[0005] The technical solution of the utility model is:

[0006] A SiC field effect transistor with reduced conduction loss, characterized in that it includes a Sub layer, a Drift layer, a Schottky contact alloy layer and a source metal layer arranged in sequence from bottom to top;

[0007] The Drift layer has:

[0008] An N-region extending downward from the top surface of the Drift layer;

[0009] A P-body region extending downward from the top surface of the N-region to the bottom surface of the N-region;

[0010] An NP region extending downward from the top surface of the P-body region and having a gap with the bottom surface of the P-body region;

[0011] A PP region, located in the middle of the P-body region, extending downward from the top surface of the P-body region, and connected to the NP region;

[0012] The bottom of the Schottky contact alloy layer is provided with an ohmic contact alloy layer connected to the NP region and the PP region respectively;

[0013] The end of the Schottky contact alloy layer is provided with a gate oxide layer connected to the N-region, the P-body region and the NP region respectively; the top surface of the gate oxide layer is provided with a Poly layer; the top surface of the Poly layer is provided with a dielectric layer for isolating the gate electrode and the source electrode of the device, and the dielectric layer extends downward from the side of the Poly layer and is connected to the NP region;

[0014] The source-level metal layer is respectively arranged on the dielectric layer and the Schottky contact alloy layer.

[0015] Specifically, the bottom surface of the PP region is lower than the bottom surface of the NP region.

[0016] Specifically, the implantation depth of the N-region is 1 um-1.2 um.

[0017] Specifically, the implantation depth of the P-body region is 1 um.

[0018] Specifically, the implantation depth of the NP region is 0.4 um.

[0019] Specifically, the implantation depth of the PP region is 0.5 um.

[0020] The utility model integrates an SBD structure in a SiC MOSFET device. Without affecting the current flow capacity of the source cell of the device, the utility model also transforms the original PN junction body diode as the leakage path in the freewheeling process into a path with both SBD and PN junction body diodes as paths. This not only reduces the conduction loss of the device in the freewheeling process, but also reduces the occurrence of the bipolar degradation effect of the device, so that the device can be used more stably for a longer period of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a top view of the utility model;

[0022] Figure 2 yes Figure 1 The structural diagram of the AA section in the X direction;

[0023] Figure 3 yes Figure 1 Structural diagram of the BB section in the X direction;

[0024] Figure 4 It is a structural schematic diagram of step S100 of the utility model;

[0025] Figure 5 It is a structural schematic diagram of step S200 of the utility model;

[0026] Figure 6 It is a structural schematic diagram of step S300 of the utility model;

[0027] Figure 7 It is a structural schematic diagram of step S400 of the utility model;

[0028] Figure 8 It is a schematic diagram of the structure of step S500 of the utility model;

[0029] Fig. 9 It is a structural schematic diagram of step S600 of the utility model;

[0030] Fig.10 It is a structural schematic diagram of step S700 of the utility model;

[0031] Fig.11 It is a structural schematic diagram of step S800 of the utility model;

[0032] Fig.12 It is a structural schematic diagram of step S900 of the utility model;

[0033] Fig.13 It is a structural schematic diagram of step S1000 of the utility model;

[0034] Fig.14 It is a structural schematic diagram of step S1100 of the utility model;

[0035] In the figure, 1 is the Sub layer, 2 is the Drift layer, 3 is the N-region, 4 is the P-body region, 5 is the NP region, 6 is the PP region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the dielectric layer, 10 is the Ohmic contact alloy layer, 11 is the Schottky contact alloy layer, and 12 is the source metal layer. DETAILED DESCRIPTION

[0036] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0037] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0038] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] A method for preparing a SiC field effect transistor with reduced conduction loss comprises the following steps:

[0040] S100, refer to Figure 4 As shown, a Drift layer 2 is epitaxially grown on the Sub layer 1;

[0041] The conductivity types of Sub layer 1 and Drift layer 2 in step S100 are both N-type, and the doping concentration of Sub layer 1 is 1E19cm -2 , the doping concentration of Drift layer 2 is 5E15-1E16cm -2 .

[0042] S200, refer to Figure 5 As shown, an N-region 3 is initially formed on the upper surface of the Drift layer 2 by ion implantation to reduce the resistance of the Drift layer 2;

[0043] The ions implanted into the N-region 3 in step S200 are N ions with a doping concentration of 5E16-1E17cm -2 .

[0044] The implantation depth of the N-region 3 is 1 um-1.2 um, which reduces the device resistance and allows the subsequent P-body region 4 to be located in the N-region 3 .

[0045] S300, refer to Figure 6 As shown, a P-body region 4 is initially formed on the N-region 3 by ion implantation;

[0046] The ions implanted into the P-body region 4 in step S300 are Al ions with a doping concentration of 1E17-3E18cm -2 .

[0047] The implantation depth of the P-body region 4 is 1 um to ensure the reverse withstand voltage performance of the device.

[0048] S400, refer to Figure 7 As shown, a NP region 5 is initially formed on the P-body region 4 by ion implantation;

[0049] The ions implanted into the NP region 5 in step S400 are N ions with a doping concentration of 1E18-1E19 cm -2 .

[0050] The implantation depth of the NP region 5 is 0.4 μm to ensure that the depletion layer space inside the P-body region 4 is sufficient when the device withstands reverse voltage.

[0051] S500, refer to Figure 8 As shown, a PP region 6 connected to the NP region 5 is initially formed on the P-body region 4 by ion implantation, and then the implantation region is completely formed by high temperature activation annealing;

[0052] The ions implanted into the PP region 6 in step S500 are Al ions with a doping concentration of 1E18-1E19 cm -2 , the high temperature activation annealing temperature is between 1600℃-1900℃.

[0053] The implantation depth of the PP region 6 is 0.5 um, and it is located in the P-body region 4 and is lower than the depth of the NP region 5, so as to improve the reverse withstand voltage performance of the device.

[0054] S600, refer to Fig. 9 As shown, a gate oxide layer 7 is grown on the top surface of the N-region 3 by dry oxygen oxidation;

[0055] S700, reference Fig.10 As shown, a Poly layer 8 is formed on the top surface of the gate oxide layer 7 by polysilicon deposition to serve as the gate electrode of the device;

[0056] S800, reference Fig.11 As shown, a dielectric layer 9 is formed on the top surface of the NP region 5 and the Poly layer 8 by oxide deposition to isolate the gate electrode and the source electrode of the device;

[0057] S900, refer to Fig.12As shown, an ohmic contact alloy layer 10 is formed on the top surface of the NP region 5 and the PP region 6 by Ni metal sputtering and thermal annealing;

[0058] S1000, refer to Fig.13 As shown, a Schottky contact alloy layer 11 is formed on the top surface of the Drift layer 2 and the Ohmic contact alloy layer 10 by sputtering Ti metal and then thermally annealing;

[0059] S1100, reference Fig.14 As shown, a source-level metal layer 12 is formed on the top of the device by AlCu metal sputtering to serve as the source electrode of the device.

[0060] A SiC field effect transistor with reduced conduction loss comprises a Sub layer 1, a Drift layer 2, a Schottky contact alloy layer 11 and a source metal layer 12 arranged in sequence from bottom to top;

[0061] The Drift layer 2 has:

[0062] N-region 3, extending downward from the top surface of the Drift layer 2;

[0063] A P-body region 4 extends downward from the top surface of the N-region 3 to the bottom surface of the N-region 3;

[0064] The NP region 5 extends downward from the top surface of the P-body region 4 and is spaced apart from the bottom surface of the P-body region 4;

[0065] The PP region 6 is located in the middle of the P-body region 4 and extends downward from the top surface of the P-body region 4 to connect with the NP region 5; the bottom surface of the PP region 6 is lower than the bottom surface of the NP region 5;

[0066] The bottom of the Schottky contact alloy layer 11 is provided with an ohmic contact alloy layer 10 connected to the NP region 5 and the PP region 6 respectively; in this case, the bottom of the Schottky contact alloy layer 11 is connected to the top surface of the N-region 3;

[0067] The end of the Schottky contact alloy layer 11 is provided with a gate oxide layer 7 connected to the N-region 3, the P-body region 4 and the NP region 5 respectively; the top surface of the gate oxide layer 7 is provided with a Poly layer 8; the top surface of the Poly layer 8 is provided with a dielectric layer 9 for isolating the device gate electrode and the source electrode, and the dielectric layer 9 extends downward from the side of the Poly layer 8 and is connected to the NP region 5;

[0068] The source-level metal layer 12 is disposed on the dielectric layer 9 and the Schottky contact alloy layer 11 , respectively.

[0069] Beneficial effects of the utility model:

[0070] Reduce device freewheeling loss and reduce bipolar degradation effect: The integrated PN junction diode inside SiC MOSFET easily causes the recombination of P-region holes and drift layer electrons during freewheeling, resulting in bipolar degradation effect, which affects the use of the device. In order to improve this problem, the industry usually adopts the method of integrating SBD inside MOSFET, but the design of integrating SBD generally increases the chip area, thereby reducing the device power density and increasing the device cost.

[0071] The utility model adopts a unique design layout in SiC MOSFET, integrates SBD inside without increasing the chip area, and does not affect the power density of the device. Although the area of ​​the SBD integrated in the device is limited, the utility model also transforms the original PN junction diode as the freewheeling path into a freewheeling path by SBD and PN junction diode at the same time, and the conduction voltage drop of SBD is lower than that of PN junction, so it not only reduces the freewheeling loss of SiC MOSFET device, but also reduces the occurrence of bipolar degradation effect of the device, and improves the stable use of the device.

Claims

1. A SiC field effect transistor with reduced conduction loss, characterized in that: It includes a sub layer (1), a drift layer (2), a Schottky contact alloy layer (11) and a source metal layer (12) which are arranged in sequence from bottom to top; The Drift layer (2) includes: An N-region (3) extending downward from the top surface of the Drift layer (2); A P-body region (4) extending downward from the top surface of the N-region (3) to the bottom surface of the N-region (3); An NP region (5) extending downward from the top surface of the P-body region (4) and having a gap with the bottom surface of the P-body region (4); A PP region (6), located in the middle of the P-body region (4), extending downward from the top surface of the P-body region (4), and connected to the NP region (5); An ohmic contact alloy layer (10) connected to the NP region (5) and the PP region (6) is provided at the bottom of the Schottky contact alloy layer (11); The end of the Schottky contact alloy layer (11) is provided with a gate oxide layer (7) connected to the N-region (3), the P-body region (4) and the NP region (5) respectively; the top surface of the gate oxide layer (7) is provided with a Poly layer (8); the top surface of the Poly layer (8) is provided with a dielectric layer (9) for isolating the gate electrode and the source electrode of the device, and the dielectric layer (9) extends downward from the side of the Poly layer (8) and is connected to the NP region (5); The source-level metal layer (12) is respectively arranged on the dielectric layer (9) and the Schottky contact alloy layer (11).

2. The SiC field effect transistor with reduced conduction loss according to claim 1, characterized in that: The bottom surface of the PP region (6) is lower than the bottom surface of the NP region (5).

3. The SiC field effect transistor with reduced conduction loss according to claim 1, characterized in that: The implantation depth of the N-region (3) is 1 um-1.2 um.

4. The SiC field effect transistor with reduced conduction loss according to claim 1, characterized in that: The implantation depth of the P-body region (4) is 1 um.

5. The SiC field effect transistor with reduced conduction loss according to claim 1, characterized in that: The implantation depth of the NP region (5) is 0.4 um.

6. The SiC field effect transistor with reduced conduction loss according to claim 1, characterized in that: The injection depth of the PP region (6) is 0.5 um.

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