Semiconductor device

Abstract

A semiconductor device includes a first region and a second region. The first region includes a first section of the first active region and a metal-containing gate structure. A metal-containing gate structure is disposed in a vertical direction over a first section of the active region in a cross-sectional side view. The second region includes a second section of the active region and a dielectric structure. The dielectric structure is disposed in a vertical direction over a second section of the active region in a cross-sectional side view, where the second section of the active region is thicker than the first section of the active region in a planar top view.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices having trimmed active regions. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. In the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This process of shrinking generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing integrated circuits.

[0003] For example, as the size of transistor components continues to decrease, it may be more difficult for an active region (e.g., a fin structure of a FinFET) to maintain a relatively linear top view profile. In some cases, the active region may have a curved top view profile, which may cause various manufacturing problems that may adversely affect the performance and / or yield of the integrated circuit.

[0004] Thus, while existing semiconductor devices are generally suitable for the intended purposes of semiconductor devices, they are not completely satisfactory in every respect. Utility Model Content

[0005] Some embodiments of the present disclosure provide a semiconductor device, comprising: a first region and a second region. The first region comprises: a first section of an active region and a metal-containing gate structure. The metal-containing gate structure is disposed vertically above the first section of the active region in a cross-sectional side view. The second region comprises: a second section of the active region and a dielectric structure. The dielectric structure is disposed vertically above the second section of the active region in a cross-sectional side view, wherein in a plan view, the second section of the active region is thicker than the first section of the active region.

[0006] Other embodiments of the present disclosure provide a semiconductor device comprising: an active region and a gate structure. The active region protrudes upward in a vertical direction in a cross-sectional side view. The gate structure at least partially surrounds the active region in a cross-sectional side view. Wherein: in a top view, the gate structure extends in a first horizontal direction. In a top view, the active region extends in a second horizontal direction, and the second horizontal direction is different from the first horizontal direction. A first portion of the active region located outside the gate structure is thicker in the first horizontal direction than a second portion of the surrounded active region below the gate structure.

[0007] Still other embodiments of the present disclosure provide a semiconductor device comprising: an active region and a gate structure. In a cross-sectional side view, the active region protrudes upward in a vertical direction. In a cross-sectional side view, the gate structure at least partially surrounds the active region. Wherein: in a top view, the gate structure extends in a first horizontal direction. In a top view, the active region extends in a second horizontal direction, and the second horizontal direction is different from the first horizontal direction. A first portion of the active region located outside the gate structure is thicker in the first horizontal direction than a second portion of the active region surrounded by the gate structure below. Wherein, in the first horizontal direction, the first portion of the active region is at least 1.3 times thicker than the second portion of the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be best understood by the following detailed description and by reading it in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered limiting in scope, as the present disclosure may be equally applicable to other embodiments.

[0009] Figure 1A A three-dimensional perspective view of a FinFET device is depicted;

[0010] Figure 1B A top view of a FinFET device is depicted;

[0011] Figure 1C A three-dimensional perspective view of a multi-channel gate-all-around (GAA) device is depicted;

[0012] FIG. 2A to FIG. 7A depicts a series of multiple planar top views of a semiconductor device at various stages of manufacture according to various embodiments of the present disclosure;

[0013] Figures 2B to 7B A series of cross-sectional views of a semiconductor device at various stages of manufacture according to various embodiments of the present disclosure are depicted;

[0014] Figures 2C to 7C A series of cross-sectional views of a semiconductor device at various stages of manufacture according to various embodiments of the present disclosure are depicted;

[0015] Figures 2D to 7D A series of cross-sectional views of a semiconductor device at various stages of manufacture according to various embodiments of the present disclosure are depicted;

[0016] Figure 8 A Static Random Access Memory (SRAM) cell according to an embodiment of the present disclosure is illustrated;

[0017] Fig. 9 An integrated circuit manufacturing system according to an embodiment of the present disclosure is depicted;

[0018] Fig.10 A flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0019]

Explanation of symbols

[0020] 90: Integrated Circuit Device

[0021] 110:Substrate

[0022] 120: Active area (fin structure, fin)

[0023] 120A: Active area (segment)

[0024] 120B: Active area (segment)

[0025] 120C: Active area (segment)

[0026] 120D: Active area (segment)

[0027] 122: Source / drain components

[0028] 130: Isolation Structure

[0029] 140: Gate structure

[0030] 150: Gate full ring device

[0031] 155:Mask

[0032] 160: Gate spacer (spacer, spacer structure)

[0033] 165: Covering layer

[0034] 170:Nanostructure

[0035] 175: Dielectric internal spacer

[0036] 180: Source / drain contact

[0037] 185: Dielectric structure (interlayer dielectric)

[0038] 200: Integrated circuit device

[0039] 200A: Area

[0040] 200B: Area

[0041] 250: Opening

[0042] 300: Width

[0043] 310: Distance

[0044] 350: Width

[0045] 360:Distance

[0046] 400: Gate structure

[0047] 800:SRAM cell

[0048] 900: Manufacturing System

[0049] 902:Entity

[0050] 904:Entity

[0051] 906:Entity

[0052] 908:Entity

[0053] 910:Entity (Craft Tool)

[0054] 912:Entity

[0055] 914:Entity

[0056] 916:Entity

[0057] 918: Network

[0058] 1000:Method

[0059] 1010: Steps

[0060] 1020: Steps

[0061] 1030: Steps

[0062] 1040: Steps

[0063] 1050: Steps

[0064] A-A': cutting line

[0065] B-B': cutting line

[0066] BL: Bit Line

[0067] BLB: Complementary Bit Line

[0068] C-C': cutting line

[0069] N:Entity

[0070] PD1: Pull-down transistor (transistor)

[0071] PD2: Pull-down transistor (transistor)

[0072] PG1: Pass-gate transistor (transistor)

[0073] PG2: Transmission Gate Transistor (Transistor)

[0074] PU1: Pull-up transistor (transistor)

[0075] PU2: Pull-up transistor (transistor)

[0076] SNB1: complementary first storage node

[0077] SN1: First storage node

[0078] Vcc: power supply voltage

[0079] Vss: voltage

[0080] WL: Character Line

[0081] X: Direction

[0082] Y: direction

[0083] Z: Direction DETAILED DESCRIPTION

[0084] The disclosure that follows provides many different implementations or embodiments for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the disclosure. Of course, these are merely embodiments and are not restrictive. For example, in the subsequent description, a first feature is formed above or on a second feature, and an implementation in which the first feature and the second feature are formed in direct contact may be included, and an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not mean the relationship between the various embodiments and / or configurations discussed.

[0085] Additionally, to facilitate description of the relationship of one element or feature to another element or feature as depicted in the figures, spatially relative terms may be used herein, such as "below," "below," "lower," "above," "upper," and the like. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0086] Still further, when "about," "approximately," and the like are used to describe a number or a range of numbers, such terms are intended to encompass numbers within a reasonable range, including the described number, such as within + / -10% of the described number, or other values ​​understood by those skilled in the art. For example, the term "about 5 nanometers" encompasses a size range from 4.5 nanometers to 5.5 nanometers.

[0087] The present disclosure generally relates to semiconductor devices that can be fabricated using field-effect transistors (FETs), such as three-dimensional fin-line FETs (FinFETs), or multi-channel gate-all-around (GAA) devices. FinFET devices have multiple semiconductor fin structures that protrude vertically from a substrate. The fin structures are active regions from which source / drain components and / or channel regions are formed. A gate structure partially surrounds the fin structures. The gate-all-around (GAA) device has multiple elongated nanostructure channels that can be implemented as nanotubes, nanosheets, or nanowires.

[0088] In recent years, FinFET devices and gate-all-around devices have become popular due to their enhanced performance compared to conventional planar transistors. However, as semiconductor device sizes continue to shrink, the formation of active regions of FinFET devices and / or gate-all-around devices may encounter potential problems. In more detail, today's FinFET device and / or gate-all-around device manufacturing may involve the formation of multiple active regions (e.g., multiple semiconductor fin structures protruding upward). It may be desirable to trim the active region before forming source / drain components on the active region. In this regard, trimming the active region may refer to reducing the thickness of each of the multiple active regions in a horizontal direction, such as through one or more etching processes. Trimming the active region is desirable because it may result in certain performance enhancements. For example, a thinner active region (after being trimmed) can achieve an off-state current (I off ) is substantially reduced, and at the same time, the on-state current (I on ) without much sacrifice.

[0089] However, if the active region is trimmed before the source / drain components are epitaxially grown on the active region, certain problems may arise. For example, when the source / drain components are epitaxially grown on the trimmed active region, the small size (e.g., thinness) of the trimmed active region may adversely affect the epitaxial growth of the source / drain components. In some cases, the epitaxially grown source / drain components may also not be able to achieve a sufficiently large size due to the small size of the active region as a substrate for the epitaxial growth of the source / drain. As a result, the smaller than optimal size of the source / drain components may cause the performance of the integrated circuit (in which the source / drain components are implemented) to be less than optimal.

[0090] Another problem associated with trimming the active region before the formation of the source / drain assembly is the increased risk of electrical shorts. In more detail, due to the thinness of the trimmed active region, the resulting source / drain assembly may present a nonlinear (e.g., curved) profile in a plan view. For example, instead of being formed as a long and thin rectangle (with substantially straight or linear walls), the trimmed active region may present various twists and turns, or have a curvature in a plan view that exceeds the desired degree. When forming a gate spacer, such a nonlinear top view profile may cause a narrow space, which may cause the gate spacer to be formed substantially thinner than expected. One of the multiple functionalities provided by the gate spacer is to prevent electrical bridging between adjacent multiple gate electrodes. In other words, at least in part due to the gate spacer located between the adjacent multiple gate structures, the multiple gate electrodes located in the adjacent multiple gate structures are prevented from physically contacting each other. However, if the thickness of the gate spacer is reduced, which may be the case when the active region presents a nonlinear top view profile, the gate spacer may be more susceptible to breaking before the gate electrode is formed. The breakage of the gate spacer may result in an open circuit between adjacent gate structures, and a subsequent gate electrode deposition process may also deposit gate electrode materials (e.g., one or more metal-containing materials) in such an open circuit. As a result, adjacent gate electrodes may physically contact each other, thereby causing an undesirable electrical short circuit between adjacent gate structures, which may degrade device performance or reduce device yield.

[0091] To address the various issues discussed above, the present disclosure performs a trimming process on a first portion of an active region after a source / drain component has been grown on a second portion of the active region. In some embodiments, the active region trimming process is not performed until a dielectric isolation structure (e.g., an interlayer dielectric or ILD) has been formed to cover the second portion of the active region. The first portion of the active region will be exposed during a dummy gate electrode removal process (e.g., as part of a gate replacement process). The fin trimming process is performed on this exposed first portion of the active region prior to the formation of a metal-containing gate (e.g., a high-k metal gate or HKMG) structure thereon.

[0092] It can be seen that according to the process flow of the present disclosure, when the source / drain components are epitaxially grown on the active region, the active region has not yet been trimmed. Due to this, the relatively thick width of the active region (as a base for the epitaxial growth of the source / drain components thereon) allows the source / drain components to reach a larger size, which is beneficial to device performance. In addition, the active region trimming process is performed only on a portion of the exposed active region, which is substantially smaller in length than the entire active region. Due to this, even if the trimmed active region is still thin, it is less likely to present a curved top view profile due to its relatively short length. In other words, the trimmed active region formed according to the present disclosure can still achieve a substantially straight or linear profile in a top view. The substantially linear profile of the trimmed active region can also improve device performance. Further, since the gate spacers have been formed before the trimming of the active region, the gate spacers can still achieve their intended thickness, which in turn allows them to be better used for the purpose of preventing electrical shorts between adjacent multiple gate electrodes. Therefore, the present disclosure may also achieve better device performance and increased yield due to reduced risk of electrical shorts.

[0093] Now refer to the following Figures 1A to 1C , FIG. 2A to FIG. 7A , Figures 2B to 7B , Figures 2C to 7C , Figures 2D to 7D ,and Figures 8 to 10 To discuss various aspects of this disclosure. In more detail, Figure 1A to Figure 1B An embodiment FinFET device is depicted, and Figure 1C An example gate-all-around device is depicted. FIG. 2A to FIG. 7A Various plan views of an integrated circuit device at various stages of fabrication are shown according to various embodiments of the present disclosure. Figures 2B to 7B , Figures 2C to 7C ,and Figures 2D to 7DVarious cross-sectional side views of an integrated circuit device are depicted at various stages of fabrication according to various embodiments of the present disclosure. Figure 8 A memory circuit is shown as an example integrated circuit application implemented using a plurality of integrated circuit devices fabricated according to various aspects of the present disclosure. Fig. 9 An embodiment semiconductor manufacturing system is depicted. Fig.10 A flow chart of a method for manufacturing a semiconductor device is shown.

[0094] Reference now Figure 1A and Figure 1B , respectively, depicts a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90. The integrated circuit device 90 is implemented using a plurality of fin field effect transistors. Figure 1A As shown in , the integrated circuit device 90 includes a substrate 110, such as a silicon substrate. A three-dimensional active region 120 is formed on the substrate 110. The active region 120 may include an elongated fin-like structure protruding upward from the substrate 110. As such, the active region 120 may be interchangeably referred to as a fin structure 120 or fin 120 hereinafter. The integrated circuit device 90 also includes a source / drain component 122 formed above the fin structure 120. The source / drain component 122 may include an epitaxial layer that is epitaxially grown on the fin structure 120.

[0095] The integrated circuit device 90 also includes a plurality of isolation structures 130 formed above the substrate 110. The plurality of isolation structures 130 electrically isolate the various components of the integrated circuit device 90. The isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric material, and / or other suitable materials. In some embodiments, the isolation structures 130 may include shallow trench isolation (STI) features. In one embodiment, the plurality of isolation structures 130 are formed by etching a plurality of trenches in the substrate 110 during the formation of the fin structure 120. The trenches may then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structures 130. Alternatively, the isolation structures 130 may include a multilayer structure, for example, with one or more thermal oxide liner layers.

[0096] The integrated circuit device 90 also includes a gate structure 140, which is formed on three sides in the channel region of each fin 120 and bonded to the fin structure 120. In other words, the plurality of gate structures 140 each surround the plurality of fin structures 120. The gate structures 140 may be dummy gate structures (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or they may be high-k metal gate (HKMG) structures (including a high-k gate dielectric and a metal gate electrode), wherein the HKMG structure is formed by replacing the dummy gate structure. Although not depicted herein, the gate structure 140 may include additional material layers, such as an interface layer, a capping layer, other suitable layers, or a combination thereof, above the fin structure 120.

[0097] refer to Figure 1A to Figure 1B , the plurality of fin structures 120 are each oriented longitudinally along the X direction, and the plurality of gate structures 140 are each oriented longitudinally along the Y direction (i.e., generally perpendicular to the fin structures 120). In many embodiments, the integrated circuit device 90 includes additional features, such as gate spacers disposed along sidewalls of the gate structures 140, a hard mask layer disposed over the gate structures 140, and many other features.

[0098] Figure 1C A three-dimensional perspective view of an embodiment gate full ring device 150 is depicted. For reasons of consistency and clarity, Figure 1C as well as Figure 1A to Figure 1B 1 and 2. In the embodiment of the present invention, similar components are labeled as the same. For example, multiple active regions such as fin structures 120 protrude vertically upward from the substrate 110 in the Z direction. Multiple isolation structures 130 provide electrical isolation between the multiple fin structures 120. A gate structure 140 is located above the fin structures 120 and above the isolation structures 130. A mask 155 is located above the gate structure 140, and a gate spacer 160 is located on the sidewalls of the gate structure 140. A capping layer 165 is formed above the fin structure 120 to protect the fin structure 120 from oxidation during the formation of the isolation structure 130.

[0099] A plurality of nanostructures 170 are disposed above each of the plurality of fin structures 120. The nanostructures 170 may include nanosheets, nanotubes, or nanowires extending horizontally in the X direction, or some other type of nanostructure. Portions of the nanostructures 170 below the gate structure 140 may be used as multiple channels of the gate full ring device 150. A plurality of dielectric internal spacers 175 may be disposed between the plurality of nanostructures 170. In addition, although not illustrated for simplicity, each stack of the nanostructures 170 is surrounded by a gate dielectric and a gate electrode. In the illustrated embodiment, portions of the nanostructures 170 outside the gate structure 140 may be used as source / drain features of the gate full ring device 150. However, in some embodiments, continuous source / drain features may be epitaxially grown above portions of the fin structure 120 outside the gate structure 140. Regardless, conductive source / drain contacts 180 may be formed over the source / drain features to provide electrical connection to the source / drain features. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 and around the gate structure 140 and the source / drain contacts 180 .

[0100] According to various embodiments of the present disclosure, FIG. 2A to FIG. 7A is a schematic partial top plan view of a portion of an integrated circuit device 200 at various stages of fabrication, and Figures 2B to 7B , Figures 2C to 7C ,and Figures 2D to 7D is a schematic partial cross-sectional side view of a portion of an integrated circuit device 200 at various stages of manufacture. Specifically, FIG. 2A to FIG. 7A It is a top view of a horizontal plane defined by the X-direction and the Y-direction. Figures 2B to 7B is a cross-sectional side view of a vertical plane defined by the X-direction and the Z-direction, Figures 2C to 7C is a cross-sectional side view of another vertical plane defined by the Y direction and the Z direction, and Figures 2D to 7D is a cross-sectional side view of yet another vertical plane defined by the Y direction and the Z direction. Respectively, Figures 2B to 7B The cross section is along FIG. 2A to FIG. 7A The plane view is taken by the cutting line AA' shown in the top view. Figures 2C to 7C The cross section is along FIG. 2A to FIG. 7A The plan view is taken along the cutting line BB' shown in FIG. Figures 2D to 7D The cross section is along FIG. 2A to FIG. 7A The plan view is taken along the cutting line CC' shown in FIG.

[0101] refer to FIG. 2A to FIG. 2D , the integrated circuit device 200 includes the above reference Figures 1A to 1CThe substrate 110 discussed. The substrate 110 may include an elemental (single element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. In some embodiments, the substrate 110 may be a single layer of material having a uniform composition. In alternative embodiments, the substrate 110 may include multiple material layers having similar or different compositions suitable for integrated circuit device manufacturing. In one embodiment, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another embodiment, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions may be formed in or on the substrate 110. Depending on the design requirements, the doped regions may be doped with n-type dopants (e.g., phosphorus or arsenic) and / or p-type dopants (e.g., boron). The doped regions may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. The doped regions may be formed via implantation of dopant atoms, epitaxial growth with in-situ doping, and / or other suitable techniques.

[0102] Still reference FIG. 2A to FIG. 2D , an active region 120 is formed on the substrate 110. The active region 120 may be a three-dimensional structure. For example, the active region 120 may include an elongated fin-like structure that protrudes vertically upward (e.g., in the Z direction) from the substrate 110. It is understood that although the active region is illustrated herein as a fin structure 120 for simplicity, the concepts of the present disclosure are also applicable to a gate-all-around device having a nanostructured active region.

[0103] The active region 120 may be fabricated using a suitable process including photolithography and etching processes. The photolithography process may include forming a photoresist layer covering the substrate 110, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element (not shown) including the resist. The mask element is then used to etch a plurality of recesses in the substrate 110, leaving a plurality of active regions 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the active region 120 may be formed via a double patterning or multiple patterning process. Generally speaking, the double patterning or multiple patterning process combines photolithography and self-aligned processes, allowing the pattern to be created to have a pitch smaller than that obtained using a single direct photolithography process, for example. As an example, a layer may be formed above the substrate and patterned using a photolithography process. A plurality of spacers may be formed next to the patterned layer using a self-aligned process. This layer is then removed and the remaining spacers or mandrels may then be used to pattern the active region 120 .

[0104] For simplicity, two example active regions 120A and 120B are depicted herein, although it is understood that any number of active regions may be implemented in various embodiments. Figure 2A As shown in the top view of FIG. 1 , active regions 120A and 120B each extend horizontally in the X direction, and active regions 120A and 120B are horizontally spaced apart from each other in the Y direction. In other words, in the top view, active regions 120A and 120B may each be formed into a shape similar to a rectangle, wherein the rectangles are elongated in the X direction and are substantially parallel to each other. Note that at this stage of fabrication, the active regions 120A and 120B correspond to Figure 2C The cross-sectional side view can be compared with the corresponding Figure 2D It is understood that due to manufacturing process limitations, the edges of the active regions 120A and 120B in an actually manufactured integrated circuit device may not be completely straight, but may have various small protrusions, depressions, and / or bends.

[0105] Reference now FIG. 3A to FIG. 3D , a dummy gate structure may be formed over the active regions 120A-120B and over the substrate 110. For simplicity, one embodiment dummy gate structure 140 is depicted herein, although it is understood that any number of dummy gate structures may be implemented in various embodiments. The dummy gate structure 140 may include a dummy gate dielectric and a dummy gate electrode formed over the dummy gate dielectric. In some embodiments, the dummy gate dielectric may include a silicon oxide material, and the dummy gate electrode may include a polysilicon material.

[0106] As in Figure 3A As shown in the top view in FIG. 1 , the dummy gate structure 140 is formed in the region 200A of the integrated circuit device 200 , but not in the region 200B of the integrated circuit device 200 . Figure 3A In the top view of FIG. 1 , the dummy gate structure 140 extends horizontally in the Y direction and spans (or overlaps) both the active regions 120A and 120B. Figure 3D As shown in the cross-sectional side view of FIG. 1 , the dummy gate structure 140 is also formed to at least partially surround each of the plurality of active regions 120A and 120B. For example, the dummy gate structure 140 surrounds the top surface and the side surface of each of the plurality of active regions 120A and 120B. Note that Figure 3C The gate structure 140 is not shown. This is because Figure 3C The cross section is taken along the cutting line BB′, which is located in the region 200B but not in the region 200A where the dummy gate structure 140 is formed.

[0107] A gate spacer structure may also be formed on the sidewalls of the dummy gate structure 140. Figure 3A and Figure 3B As shown in , the gate spacer structure may include a gate spacer 160. The gate spacer 160 may be formed via various dielectric material deposition processes and subsequent etching processes. For example, the gate spacer 160 may include one or more dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), etc. In some embodiments, each of the plurality of gate spacers 160 may actually include a plurality of different gate spacer layers, wherein at least some of the gate spacer layers have a different material composition than the remaining gate spacer layers. For example, in some embodiments, one of the plurality of gate spacer layers may have a silicon nitride material composition, and another of the plurality of gate spacer layers may have a silicon oxide material composition. However, for the sake of simplicity, in this article, Figure 3A and Figure 3B In FIG. 1 , a plurality of different gate spacer layers may be collectively depicted as a single spacer structure 160 .

[0108] Reference now 4A to 4D, forming a source / drain component 122 above the fin structure 120. As used herein, a source / drain component, or "S / D component", or "S / D region" may refer to a source or drain of a device (e.g., a transistor). It may also refer to a component or region that provides a source and / or drain for multiple devices. Herein, the source / drain component 122 may include an epitaxial layer that is epitaxially grown on the active region 120. In some embodiments, portions of the active regions 120A and 120B may be recessed downward in the Z direction (e.g., via one or more etching processes), and then the source / drain component 122 is epitaxially grown above the recessed surface of the active regions 120A and 120B.

[0109] Note that the active regions 120A and 120B may not be directly visible in a plan view because the source / drain elements 122 are formed above (in the vertical Z direction) the active regions 120A and 120B at this stage of fabrication. However, the active regions 120A and 120B are still visible in the plan view. Figure 4A 1 and 2 to provide an illustration of their locations to aid in understanding various aspects of the present disclosure. It is also noted that due to the presence of the dummy gate structure 140, the source / drain element 122 is formed in the region 200B but may not be formed in the region 200A of the integrated circuit device 200.

[0110] One of the advantages of the present disclosure is that the source / drain components 122 formed herein can be relatively large in size. Figure 4A and Figure 4CAs shown in , the plurality of source / drain components 122 formed on the adjacent plurality of active regions 120A and 120B are large enough so that they merge with each other laterally in the Y direction. One of the reasons that the source / drain components 122 can reach a relatively large size is the sufficiently wide width of the plurality of active regions 120A and 120B, on which the plurality of source / drain components 122 are formed. As discussed above, if the source / drain components have been formed on the active regions that have been trimmed, the reduced thickness of the active regions may result in poor epitaxial growth of the source / drain components. Poorly grown source / drain components may not be able to reach a sufficiently large size, which may result in poor electrical performance. In contrast, one of the aspects of the present disclosure relates to the formation of the source / drain components 122 prior to the trimming of the active regions 120A and 120B. Because the active regions 120A and 120B have not yet been trimmed, at this stage of fabrication, the active regions 120A and 120B are still relatively wide (e.g., in the Y direction). As a result, the source / drain components 122 may be formed to be relatively large (e.g., wider in the Y direction), which may result in enhanced electrical performance for the integrated circuit device 200.

[0111] Reference now FIG. 5A to FIG. 5D , a dielectric structure 185 is formed in region 200B of integrated circuit device 200. In some embodiments, dielectric structure 185 can be an interlayer dielectric (ILD) structure discussed above and can include silicon dioxide or a low dielectric constant (low-k) dielectric (e.g., having a dielectric constant less than that of silicon dioxide) material. Dielectric structure 185 is formed over active regions 120A and 120B and over source / drain components 122. The formation of dielectric structure 185 can include one or more deposition processes followed by one or more grinding processes, such as chemical mechanical planarization. To facilitate the subsequent discussion, still in Figure 5A The active regions 120A and 120B are shown in the top plan view (even though the active regions 120A / 120B are actually covered by the dielectric structure 185), but the source / drain element 122 is not shown in the top plan view. Figure 5A Omitted in .

[0112] Still reference FIG. 5A to FIG. 5D, after the formation of the dielectric structure 185, the dummy gate structure 140 is removed. In some embodiments, the dummy gate structure 140 is removed via one or more etching processes. For example, the etching process may include a dry etching or a wet etching process that has sufficient etching selectivity between the material of the dummy gate structure 140 (e.g., the polysilicon dummy gate electrode and / or the silicon oxide dummy gate dielectric) and other components of the integrated circuit device 200 (e.g., the gate spacer 160 and the dielectric structure 185) so that the material of the dummy gate structure 140 can be etched away without substantially affecting the remaining components of the integrated circuit device 200. For example, after the removal of the dummy gate structure 140, the gate spacer 160 and the dielectric structure 185 may still remain.

[0113] Note that the removal of the dummy gate structure 140 forms an opening 250 (see Figure 5A , Figure 5B ,and Figure 5D ), wherein the opening 250 exposes a first segment of each of the plurality of active regions 120A and 120B in the region 200A of the integrated circuit device 200. The opening 250 is at least partially defined by a pair of adjacent active regions (e.g., the active regions 120A and 120B) and by the plurality of gate spacers 160.

[0114] At this stage of manufacturing, the plurality of active regions 120A and 120B each have a width 300 (e.g., a horizontal dimension) measured in the Y direction. The value of the width 300 is substantially the same for the segments of the active regions 120A and 120B located in region 200A and the segments of the active regions 120A and 120B located in region 200B. In other words, although manufacturing limitations may result in small width variations across the length of the active regions 120A and 120B, at this point there is no significant difference between the portions of the active regions 120A / 120B exposed by the opening 250 and the portions of the active regions 120A / 120B covered by the dielectric structure 185. In addition, adjacent plurality of active regions 120A and 120B are horizontally separated by a distance 310 in the Y direction. Similar to the width 300, in FIG. 5A to FIG. 5D At the stage of manufacturing shown in , the value of the distance 310 remains substantially the same in the region 200A and the region 200B of the integrated circuit device 200 .

[0115] Reference now FIG. 6A to FIG. 6D, an active region trimming process is performed on the integrated circuit device 200 to reduce the width of the segments of the active regions 120A and 120B exposed by the opening 250. In some embodiments, the active region trimming process includes one or more etching processes that have etching selectivity between the material of the active regions 120A / 120B and the material of other components of the integrated circuit device 200 (e.g., the spacer 160 and / or the dielectric structure 185). During the active region trimming process, the dielectric structure 185 is used as a protective etching mask for the segments of the active regions 120A and 120B located thereunder, so that these segments are substantially unaffected by the active region trimming process. At the same time, the portions of the active regions 120A and 120B exposed by the opening 250 are partially etched away, so that the remaining segments 120C and 120D have substantially reduced dimensions in the Y direction.

[0116] For example, as in Fig. 6A Top view and Fig.6D As shown in the cross-sectional side view of , after the trimming process, the remaining segments 120C and 120D of the active region each have a width 350 measured in the Y direction. The width 350 is substantially smaller in value compared to the width 300 of the segments 120A / 120B of the active region overlying the dielectric structure 185. In some embodiments, the width 300 is at least 2 times greater than the width 350 in value. For example, the ratio between the width 300 and the width 350 may be in a range between about 4:1 and about 6:1. Further, due to the reduction in the width of the segments 120C and 120D, the multiple segments 120C and 120D of the active region are separated by a now larger distance 360 ​​than before the active region trimming process was performed. In other words, although the multiple segments 120A and 120B of the active region are still separated by the distance 310, the multiple segments 120C and 120D of the active region are now separated by a substantially larger distance 360. In some embodiments, in terms of value, distance 360 ​​is at least 1.3 times greater than distance 310. For example, the ratio between distance 360 ​​and distance 310 may be in a range between about 1.3:1 and about 2:1.

[0117] It is understood that the above ranges are not randomly selected, but are specifically configured to optimize the performance of the integrated circuit device 200. For example, if the width 350 is too small or the distance 360 ​​is too large, this may mean that the active region trimming process has been over-performed. When this occurs, the multiple sections 120C and 120D of the active region may still be vulnerable or present a non-linear (e.g., curved) top-view profile, which may cause device performance degradation or even device failure. On the other hand, if the width 350 is too large or the distance 360 ​​is too small, this may mean that the active region trimming process has not been fully performed. When this occurs, these sections 120C and 120D of the active region may not fully achieve the performance improvement associated with trimming the active region. For example, multiple transistors associated with the multiple sections 120C and 120D of the active region may not achieve the off-state current (I off The above numerical ranges for width 350 and distance 360 ​​(and their associated ratios) are carefully configured in such a manner that the resulting segments 120C and 120D of the active region are less likely to break or exhibit a non-linear top-view profile, while achieving the benefits associated with active region trimming, e.g., a sufficient reduction in off-state current.

[0118] It is also understood that the fact that the width 350 of the plurality of segments 120C and 120D is smaller than the width 300 of the plurality of segments 120A and 120B of the active region is an inherent result of performing the unique process flow of the present disclosure, and it can be used as evidence to detect a process flow that violates the present disclosure. In more detail, the size disparity between the segments 120C / 120D and the segments 120A / 120B of the active region can be attributed to the fact that the active region trimming process is performed after (rather than before) the formation of the source / drain components 122. Due to this unique process flow, at the time the active region trimming process is performed, the segments 120A and 120B of the active region are already covered by the dielectric structure 185. Therefore, the plurality of segments 120A and 120B will retain their original (and larger) width 300.

[0119] In contrast, the plurality of segments 120C and 120D are trimmed after the source / drain elements 122 are formed and the dummy gate structure 140 has been removed. The removal of the dummy gate structure 140 leaves an opening 250 that exposes the plurality of segments 120C and 120D of the active region, which allows the plurality of segments 120C and 120D to be trimmed to a reduced width 350 (compared to the original width 300). Similarly, the fact that the distance 360 ​​(separating the plurality of segments 120C and 120D) is greater than the distance 310 (separating the plurality of segments 120A and 120B) is also an inherent result of performing the unique process flow of the present disclosure. If the integrated circuit device is not manufactured based on the unique process flow of the present disclosure, the distance separating the plurality of segments of the active region in the plurality of regions 200A and 200B of the integrated circuit device 200 may be substantially the same.

[0120] Note that the segments 120A and 120C are portions of a continuous active region, although based on Fig. 6A 120C. In other words, segment 120A and segment 120C are in direct physical contact with each other. For example, the end of segment 120A that is directly below spacer 160 (vertically in the Z direction) may be in physical contact with segment 120C. In this way, segments 120A and 120C together form a continuous active region in regions 200B and 200A of integrated circuit device 200, and the continuous active region has a variable size. Segment 120A with a larger width 300 is located in region 200B of integrated circuit device 200, while segment 120C with a smaller width 350 is located in region 200A of integrated circuit device 200, wherein region 200A and region 200B share an interface that is substantially consistent with the sidewall of gate spacer 160 (extending horizontally in the Y direction) in the top view. Similarly, in the top view, the segments 120B and 120D are also portions of a continuous active region that spans the regions 200B and 200A of the integrated circuit device 200 .

[0121] Reference now FIG. 7A to FIG. 7D, forming a metal-containing gate structure 400 to replace the dummy gate structure 140. For example, one or more deposition processes may be performed to partially fill the opening with a high-k gate dielectric. The high-k gate dielectric includes a high-k dielectric material, which refers to a dielectric material having a dielectric constant that is greater than the dielectric constant of silicon oxide (e.g., about 3.9). Example materials of the high-k gate dielectric include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or a combination thereof.

[0122] Thereafter, a metal-containing gate electrode is formed over the high-k gate dielectric. The metal-containing gate electrode may be formed by performing one or more deposition processes to fill the opening 250 with various metal-containing materials, followed by a planarization process (e.g., a chemical mechanical planarization process) to planarize the upper surface of the deposited metal-containing material. As a result, the metal-containing gate electrode may include one or more work function (WF) metal layers and a fill metal layer. The work function metal layer may be configured to adjust the work function of the corresponding transistor. Example materials for the work function metal layer may include titanium nitride (TiN), titanium aluminide (TiAl), tantalum nitride (TaN), titanium carbide (Tic), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum nitride (TiAlN), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or a combination thereof. The fill metal layer may be used as the main conductive portion of the metal-containing gate electrode. In some embodiments, the fill metal layer may include cobalt, tungsten, copper, aluminum, or alloys thereof, or combinations thereof. It is understood that the metal-containing gate structure 400 may include additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer, or other applicable layers. For the sake of simplicity, these additional layers are not specifically illustrated herein.

[0123] Another advantage of the present disclosure is that the risk of electrical short circuits during the formation of the metal-containing gate structure 400 is reduced. In more detail, if the active region has been trimmed before the formation of the source-drain component, the resulting trimmed active region may present a non-linear (e.g., curved) top-view profile. Such a non-linear profile may result in space crowding between a pair of adjacent active regions. Such a process flow also typically forms gate spacers after trimming the active region, and space crowding between multiple active regions may result in poor formation of gate spacers. For example, the gate spacer may not reach a target thickness in the X direction, which may make the gate spacer more susceptible to breaking. When the gate spacer breaks, an open path may be formed between multiple adjacent gate structures. Therefore, when depositing a metal-containing material to form a metal-containing gate electrode, the metal-containing gate electrodes from the adjacent multiple gate structures may be electrically shorted to each other via the open path (which is also filled with the metal-containing material during the deposition of the metal-containing material). Such electrical short circuits between multiple adjacent gate structures may reduce device performance or cause device failure.

[0124] The unique manufacturing process flow of the present disclosure avoids the electrical shorting problem discussed above because the gate spacer thickness is not excessively reduced. This is due to the fact that greater linearity can be achieved for the multiple active regions 120A-120D because only a small portion (relative to the entirety) of the active region needs to be trimmed. The greater linearity of the multiple active regions 120A-120D also means that crowding problems between adjacent multiple active regions are less likely to occur. And even if there is some degree of crowding between adjacent multiple active regions, it is not possible to reduce the thickness of the gate spacer 160 because before trimming multiple portions of the active regions 120C / 120D (see Fig. 6A and Fig.6D ), a gate spacer 160 has been formed (see FIG. 3A to FIG. 3B ). For these reasons, the gate spacers 160 can reach and / or maintain their desired thickness in the X direction, which means that they are less likely to break. As a result, no open circuit (not specifically shown herein) will be formed between the metal-containing gate structure 400 and an adjacent metal-containing gate structure. Therefore, the formation of the metal-containing gate structure 400 (e.g., the deposition of a metal-containing material) will not cause the metal-containing gate structure to be electrically shorted to any adjacent metal-containing gate structure. Such a reduction in the risk of electrical shorts can translate into improved device performance and / or yield.

[0125] It is understood that the integrated circuit device 200 discussed above may be implemented in various integrated circuit applications, including memory devices, such as static random access memory (SRAM) devices. In this regard, Figure 8 An embodiment circuit diagram for a single-port SRAM cell (e.g., a 1-bit SRAM cell) 800 is depicted. The single-port SRAM cell 800 includes a plurality of pull-up transistors PU1, PU2; a plurality of pull-down transistors PD1, PD2; and a plurality of pass-gate transistors PG1, PG2. As shown in the circuit diagram, the plurality of transistors PU1 and PU2 are p-type transistors, and the plurality of transistors PG1, PG2, PD1, and PD2 are n-type transistors. Because the SRAM cell 800 includes six transistors in the depicted embodiment, it may also be referred to as a 6T SRAM cell.

[0126] The drain of the pull-up transistor PU1 and the drain of the pull-down transistor PD1 are coupled together, and the drain of the pull-up transistor PU2 and the drain of the pull-down transistor PD2 are coupled together. Multiple transistors PU1 and PD1 are cross-coupled with multiple transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and coupled to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and coupled to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to a power supply voltage Vcc (also called Vdd), and the sources of the pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be electrically grounded.

[0127] The first storage node SN1 of the first data latch is coupled to the bit line BL through the pass gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through the pass gate transistor PG2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes, which are usually at opposite logic potentials (logic high or logic low). The gates of the pass gate transistors PG1 and PG2 are coupled to the word line WL. The static random access memory device (e.g., SRAM cell 800) can be implemented using the integrated circuit device 200 discussed above, which can be implemented as a FinFET device and / or a gate-all-around device.

[0128] Fig. 9 An integrated circuit manufacturing system 900 is depicted according to various embodiments of the present disclosure. Manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916 ... N connected by a communication network 918. Network 918 can be a single network, or can be a variety of different networks, such as an intranet and the Internet, and can include both wired and wireless communication channels.

[0129] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer to control a process and related recipes, or an equipment engineer to monitor or adjust the conditions and settings of a process tool; entity 908 represents a metrology tool for integrated circuit testing and measurement; entity 910 represents a semiconductor process tool, such as a process tool that performs the selective growth process discussed above; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and additional other process tools; and entity 916 represents a sampling module associated with process tool 910.

[0130] Each entity may interact with other entities and may provide integrated circuit manufacturing, process control, and / or computing capabilities to other entities and / or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and implementing automation. For example, the advanced process control module of entity 914 may include a plurality of computer hardware having a plurality of software instructions encoded therein. The computer hardware may include a hard drive, a flash drive, a compact disk read-only memory (CD-ROM), a random access memory (RAM), a display device (e.g., a monitor), and an input / output device (e.g., a mouse and a keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

[0131] The integrated circuit manufacturing system 900 can implement interactions between multiple entities for the purpose of integrated circuit (IC) manufacturing, as well as advanced process control for integrated circuit manufacturing. In one embodiment, the advanced process control includes adjusting process conditions, settings, and / or recipes of a process tool applicable to an associated wafer based on metrology results.

[0132] In another embodiment, metrology results are measured from a subset of the processed plurality of wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of the processed plurality of wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0133] One of the capabilities provided by the integrated circuit manufacturing system 900 may enable collaboration and information access in such multiple areas (design, engineering, and process, metrology, and advanced process control). Another capability provided by the integrated circuit manufacturing system 900 may integrate systems between multiple facilities, such as between metrology tools and process tools. Such integration enables multiple facilities to coordinate their activities. For example, integrating metrology tools and process tools may enable manufacturing information to be more efficiently incorporated into manufacturing processes or advanced process control (APC) modules, and wafer data may be obtained from online or on-site measurements using metrology tools integrated into associated process tools.

[0134] Fig.10 1 is a flow chart illustrating a method 1000 for manufacturing a semiconductor device. The method 1000 includes step 1010 of forming a dummy gate structure above a plurality of active regions. In a plan view, the dummy gate structure extends in a first horizontal direction. In a plan view, each of the plurality of active regions extends in a second horizontal direction. The second horizontal direction is different from the first horizontal direction (e.g., perpendicular to the first horizontal direction).

[0135] The method 1000 includes step 1020 of forming a plurality of source / drain elements above the active region.

[0136] The method 1000 includes step 1030 of forming a dielectric structure over the source / drain components.

[0137] The method 1000 includes step 1040 of removing the dummy gate structure. The removal of the dummy gate structure exposes a first section of each of the plurality of active regions.

[0138] The method 1000 includes step 1050 of reducing a thickness of a first section of each of the plurality of active regions in a first horizontal direction. In some embodiments, the thickness is reduced by performing one or more etching processes. In some embodiments, the dummy gate structure includes a dummy gate electrode and a gate spacer structure, removal of the dummy gate structure removes the dummy gate electrode but does not remove the gate spacer structure or the dielectric structure, and the dielectric structure and the gate spacer structure protect portions of the active regions disposed thereunder from being etched during the one or more etching processes.

[0139] In some embodiments, each of the plurality of active regions includes a second segment covered by the dielectric structure, and a thickness of the second segment of each of the plurality of active regions is not affected by a reduction in thickness of the first segment of each of the plurality of active regions in the first horizontal direction.

[0140] In some embodiments, for each of the plurality of active regions, after the thickness of the first segment has been reduced, the first segment is continuous with the second segment.

[0141] In some embodiments, the first segment has a first thickness in a first horizontal direction, the second segment has a second thickness in the first horizontal direction, and a ratio between the second thickness and the first thickness is in a range from about 4:1 to about 6:1.

[0142] In some embodiments, forming the plurality of source / drain components is performed via an epitaxial growth process such that the plurality of source / drain components grown on adjacent active regions merge with each other in a first horizontal direction.

[0143] It is understood that additional multiple steps may be performed before, during, or after steps 1010 to 1050. For example, after reducing the thickness of the first segment, a metal-containing gate structure is formed above the first segment of each of the multiple active regions. As another embodiment, multiple vertically protruding fin structures are formed as multiple active regions, wherein a dummy gate structure is formed so that it partially surrounds each of the multiple vertically protruding fin structures. As yet another embodiment, method 1000 may include the formation of metallization features, such as conductive contacts and / or vias for gate structures and source / drain components. As a further embodiment, method 1000 may include packaging processes and testing procedures. For the sake of simplicity, these additional steps are not discussed in detail herein.

[0144] In summary, the present disclosure involves performing a unique process flow to trim the active region of a transistor. For example, rather than trimming the entire active region prior to epitaxial growth of source / drain components, the present disclosure trims only the first section of the active region after epitaxial growth has been performed to form source / drain components over the second section of the active region. According to the process flow of the present disclosure, while trimming the first section of the active region, the second section of the active region is protected by a dielectric structure.

[0145] The unique manufacturing process flow and the resulting integrated circuit device structure of the present disclosure provide multiple advantages compared to conventional devices. However, it is understood that no specific advantages are required, other embodiments may provide different advantages, and not all advantages must be disclosed herein. One advantage is to improve the performance of the integrated circuit device. In more detail, as device sizes decrease in newer technology generations, individual integrated circuit components are more susceptible to damage or fail to achieve the expected geometric profile. For example, when a trimming process is performed to reduce the lateral dimensions of a relatively long active region (e.g., a fin structure), the resulting active region may present a nonlinear top-view profile (e.g., a curved profile), or it may even collapse or otherwise be damaged. In addition, source and drain components epitaxially grown on an active region that is too thin (due to being trimmed) may also fail to reach a sufficiently large size, which may also reduce device performance.

[0146] Herein, a unique manufacturing process flow means that a relatively short segment of the active region (rather than an entire active region) needs to be trimmed, which allows the trimmed active region to still maintain a relatively linear (e.g., straight) profile. At least in part due to the smaller length, the trimmed active region herein is also less likely to collapse or become damaged, thereby improving device performance and / or yield. Further, because the source / drain components are formed before the active region is trimmed, the thicker active region serves as a better base structure on which the source / drain components can be epitaxially grown. Therefore, the source / drain components formed herein can reach sufficiently large sizes, thereby also improving device performance.

[0147] Another advantage is the reduction of the risk of electrical short circuits. In this regard, the nonlinear profile of the trimmed active region may mean that adjacent pairs of multiple active regions may be too close to each other in certain regions. This crowding of multiple active regions in certain regions may cause the gate spacer formed subsequently to fail to reach a sufficiently large thickness. When this happens, the gate spacer may not be able to fully serve as an electrical isolation structure between adjacent multiple gate electrodes. In turn, unintentional electrical short circuits between adjacent multiple gate electrodes may occur in subsequent processes. In this article, since the trimmed active region can always maintain a relatively linear profile, it is unlikely that unintentional and undesirable crowding will occur between multiple active regions of a pair of adjacent regions. Further, since the gate spacer has been formed before the trimming of the active region, the gate spacer can still reach the desired thickness even if there is some degree of crowding between adjacent multiple active regions. Due to this, the gate spacer of the present disclosure can still be appropriately used as a blocking structure between adjacent multiple gate electrodes to prevent undesirable electrical short circuits between these gate electrodes. Other advantages may include ease of manufacture and compatibility with existing manufacturing processes.

[0148] The advanced photolithography processes, methods, and materials described above can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between multiple features, and the above disclosure is well suited to this aspect. In addition, spacers, also known as mandrels, used to form the fins of the FinFET can be processed according to the above disclosure. It is also understood that various aspects of the present disclosure discussed above can be applied to multi-channel devices, such as gate-all-around (GAA) devices. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussion can be equally applicable to gate-all-around devices.

[0149] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a first region, the first region includes: a first segment of an active region and a metal-containing gate structure, the metal-containing gate structure is disposed vertically above the first segment of the active region in a cross-sectional side view. The semiconductor device also includes a second region, the second region includes: a second segment of the active region and a dielectric structure, the dielectric structure is disposed vertically above the second segment of the active region in a cross-sectional side view. In a plan view, the second segment of the active region is thicker than the first segment of the active region.

[0150] In some embodiments, in a semiconductor device, an active region includes a fin structure that vertically protrudes from a substrate in a cross-sectional side view.

[0151] In some embodiments, in a semiconductor device, a plan view is defined by a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction; the first region and the second region form an interface in the plan view; and in the plan view, the interface extends in the first horizontal direction.

[0152] In some embodiments, in a semiconductor device, a first segment has a first horizontal dimension in a first horizontal direction; a second segment has a second horizontal dimension in the first horizontal direction; and a ratio between the second horizontal dimension and the first horizontal dimension is in a range between about 4:1 and about 6:1.

[0153] In some embodiments, the first section of the active region is contiguous with the second section of the active region.

[0154] In some embodiments, in a semiconductor device, the active region is a first active region; the device also includes a second active region; a metal-containing gate structure is disposed above a third segment of the second active region; a dielectric structure is disposed above a fourth segment of the second active region; in a planar top view, the third segment of the second active region is separated from the first segment of the first active region by a first distance; in a planar top view, the fourth segment of the second active region is separated from the second segment of the first active region by a second distance; and the first distance is greater than the second distance.

[0155] In some embodiments, in the semiconductor device, a ratio between the first distance and the second distance is in a range from about 1.3:1 to about 2:1.

[0156] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device. A dummy gate structure is formed above a plurality of active regions. In a plan view, the dummy gate structure extends in a first horizontal direction. In a plan view, each of the plurality of active regions extends in a second horizontal direction. The second horizontal direction is different from the first horizontal direction. A plurality of source / drain components are formed above the active regions. A dielectric structure is formed above the source / drain components. The dummy gate structure is removed. The removal of the dummy gate structure exposes a first section of each of the plurality of active regions. The thickness of the first section of each of the plurality of active regions in the first horizontal direction is reduced.

[0157] In some embodiments, reducing the thickness is performed via one or more etching processes.

[0158] In some embodiments, in a method for manufacturing a semiconductor device, the dummy gate structure includes a dummy gate electrode and a gate spacer structure; the removal of the dummy gate structure removes the dummy gate electrode but does not remove the gate spacer structure or the dielectric structure; and the dielectric structure and the gate spacer structure protect portions of the active regions disposed therebelow from being etched during the one or more etching processes.

[0159] In some embodiments, in a method of manufacturing a semiconductor device, each of the active regions includes a second segment covered by a dielectric structure; and the thickness of the second segment of each of the active regions is not affected by the reduction in thickness of the first segment of each of the active regions in the first horizontal direction.

[0160] In some embodiments, in a method of manufacturing a semiconductor device, for each of the active regions, after the thickness of the first section has been reduced, the first section and the second section are continuous.

[0161] In some embodiments, in a method of manufacturing a semiconductor device, a first segment has a first thickness in a first horizontal direction; a second segment has a second thickness in the first horizontal direction; and a ratio between the second thickness and the first thickness is in a range between about 4:1 and about 6:1.

[0162] In some embodiments, in a method of manufacturing a semiconductor device, the forming of the plurality of source / drain components is performed via an epitaxial growth process, such that the source / drain components grown on adjacent active regions are merged with each other in a first horizontal direction.

[0163] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a metal-containing gate structure over the first segment of each of the active regions after reducing the thickness of the first segment.

[0164] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a plurality of vertically protruding fin structures as the plurality of active regions, wherein a dummy gate structure is formed such that the dummy gate structure partially surrounds each of the vertically protruding fin structures.

[0165] Yet another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes an active region protruding upward in a vertical direction in a cross-sectional side view. The semiconductor device includes a gate structure, and the gate structure at least partially surrounds the active region in the cross-sectional side view. In the top view, the gate structure extends in a first horizontal direction. In the top view, the active region extends in a second horizontal direction. The second horizontal direction is different from the first horizontal direction. A first portion of the active region located outside the gate structure is thicker in the first direction than a second portion of the active region surrounded below the gate structure.

[0166] In some embodiments, in a semiconductor device, a first portion of an active region is in direct physical contact with a second portion of an active region.

[0167] In some embodiments, in a semiconductor device, in a first horizontal direction, a first portion of the active region is at least 1.3 times thicker than a second portion of the active region.

[0168] In some embodiments, in a semiconductor device, the active region is a first fin structure; the device also includes a second fin structure, which is substantially parallel to the first fin structure; in a top view, the dielectric structure overlaps with a first portion of the first fin structure and a third portion of the second fin structure; in a top view, the gate structure overlaps with a second portion of the first fin structure and a fourth portion of the second fin structure; a first distance separates the first portion of the first fin structure and the third portion of the second fin structure; a second distance separates the second portion of the first fin structure and the fourth portion of the second fin structure; and a first portion of the active region located outside the gate structure is thicker in a first direction than a second portion of the surrounded active region below the gate structure.

[0169] Yet another aspect of the present disclosure relates to a semiconductor device. In a cross-sectional side view, the semiconductor device includes an active region that protrudes upward in a vertical direction. The semiconductor device includes a gate structure, and in the cross-sectional side view, the gate structure at least partially surrounds the active region. In a top view, the gate structure extends in a first horizontal direction. In a top view, the active region extends in a second horizontal direction. The second horizontal direction is different from the first horizontal direction. A first portion of the active region located outside the gate structure is thicker in the first direction than a second portion of the active region surrounded below the gate structure. Wherein, in the first horizontal direction, the first portion of the active region is at least 1.3 times thicker than the second portion of the active region.

[0170] The above outlines several features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purposes as the embodiments described herein, and / or to achieve the same advantages. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure. For example, by implementing different thicknesses for bit line conductors and word line conductors, different resistances for multiple conductors may be achieved. However, other techniques may also be utilized to change the resistance of metal conductors.

Claims

1. A semiconductor device, characterized in that: Include: A first region comprising: a first section of an active region; and a metal-containing gate structure disposed in a vertical direction over the first section of the active region in a cross-sectional side view; and A second area, comprising: a second section of the active region; and A dielectric structure is disposed above the second section of the active region in the vertical direction in the cross-sectional side view, wherein in a planar top view, the second section of the active region is thicker than the first section of the active region.

2. The semiconductor device according to claim 1, wherein The active region includes a fin structure that vertically protrudes from a substrate in the cross-sectional side view.

3. The semiconductor device according to claim 1, wherein: The plan view is defined by a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction; The first region and the second region form an interface in the plan view; and In the plan view, the interface extends in the first horizontal direction.

4. The semiconductor device according to claim 3, wherein: The first section has a first horizontal dimension in the first horizontal direction; The second section has a second horizontal dimension in the first horizontal direction; and A ratio between the second horizontal dimension and the first horizontal dimension is in a range between 4:1 and 6:

1.

5. The semiconductor device according to claim 1, wherein: The first section of the active region is continuous with the second section of the active region.

6. The semiconductor device according to claim 1, wherein: The active region is a first active region; The device also includes a second active region; The metal-containing gate structure is disposed above a third section of the second active region; The dielectric structure is disposed above a fourth section of the second active region; In the plan view, the third section of the second active region is separated from the first section of the first active region by a first distance; In the plan view, the fourth section of the second active region is separated from the second section of the first active region by a second distance; and The first distance is greater than the second distance.

7. The semiconductor device according to claim 6, wherein: A ratio between the first distance and the second distance is in a range between 1.3:1 and 2:

1.

8. A semiconductor device, characterized in that: Include: an active region protruding upward in a vertical direction in a cross-sectional side view; a gate structure at least partially surrounding the active region in the cross-sectional side view; in: In a top view, the gate structure extends in a first horizontal direction; In the top view, the active region extends in a second horizontal direction, the second horizontal direction being different from the first horizontal direction; and A first portion of the active region outside the gate structure is thicker in the first horizontal direction than a second portion of the active region surrounded by the gate structure below the gate structure.

9. The semiconductor device according to claim 8, wherein: The active region is a first fin structure; The device also includes a second fin structure, the second fin structure being substantially parallel to the first fin structure; In the top view, a dielectric structure overlaps the first portion of the first fin structure and a third portion of the second fin structure; In the top view, the gate structure overlaps the second portion of the first fin structure and a fourth portion of the second fin structure; A first distance separates the first portion of the first fin structure and the third portion of the second fin structure; A second distance separates the second portion of the first fin structure and the fourth portion of the second fin structure; and The second distance is at least 1.3 times greater than the first distance.

10. A semiconductor device, characterized in that: Include: an active region protruding upward in a vertical direction in a cross-sectional side view; a gate structure at least partially surrounding the active region in the cross-sectional side view; in: In a top view, the gate structure extends in a first horizontal direction; In the top view, the active region extends in a second horizontal direction, the second horizontal direction being different from the first horizontal direction; and A first portion of the active region outside the gate structure is thicker in the first horizontal direction than a second portion of the active region surrounded by the gate structure below the gate structure; Wherein, in the first horizontal direction, the first portion of the active region is at least 1.3 times thicker than the second portion of the active region.

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