Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a plurality of rows and columns of pixel circuits. The pixel circuit comprises a data write-in circuit; the data write-in circuit is connected with a data voltage under the control of a scanning signal; a transistor included in the data write-in circuit comprises a first grid electrode and a second grid electrode, and a scanning end comprises a first scanning end and a second scanning end. A first grid electrode of a transistor included in the data write-in circuit is electrically connected with the first scanning end, and a second grid electrode of the transistor included in the data write-in circuit is electrically connected with the second scanning end; the first grid electrode is a top grid electrode, and the second grid electrode is a bottom grid electrode; or, the first grid electrode is a bottom grid electrode, and the second grid electrode is a top grid electrode. The display panel can improve the flicker phenomenon during low-frequency display.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related technologies, as the demand for low-frequency display products increases, flicker (flicker) as one of the important benchmarks for low-frequency evaluation has attracted more and more attention. How to reduce flicker has become the main topic of current R&D personnel. The main reasons for flicker failing to meet customer benchmarks are: ① large △Vp (△Vp is the change value of pixel voltage), resulting in large flicker value; ② poor uniformity of in-plane common electrode voltage Vcom, resulting in poor in-plane flicker uniformity. Utility Model Content

[0003] The main purpose of the utility model is to provide a display panel and a display device to solve the flickering phenomenon of related display products during low-frequency display.

[0004] In one aspect, the display panel described in the embodiment of the utility model comprises a plurality of rows and columns of pixel circuits; the pixel circuits comprise a data writing circuit;

[0005] The data writing circuit is electrically connected to the scanning end and the data line respectively, and is used to access the data voltage provided by the data line under the control of the scanning signal provided by the scanning end;

[0006] The transistor included in the data writing circuit includes a first gate and a second gate, and the scanning end includes a first scanning end and a second scanning end;

[0007] The first gate of the transistor included in the data writing circuit is electrically connected to the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected to the second scanning end;

[0008] The first gate is a top gate, and the second gate is a bottom gate; or, the first gate is a bottom gate, and the second gate is a top gate.

[0009] Optionally, when the potential of the first scanning signal provided by the first scanning end decreases, the potential of the second scanning signal provided by the second scanning end increases;

[0010] When the potential of the first scanning signal provided by the first scanning end increases, the potential of the second scanning signal provided by the second scanning end decreases.

[0011] Optionally, the display panel described in at least one embodiment of the present utility model further includes a driving module; the driving module includes a multi-stage driving circuit;

[0012] The driving circuit includes a first scanning signal output terminal and a second scanning signal output terminal;

[0013] The first scanning signal output terminal of the n-th level driving circuit included in the driving module is electrically connected to the first scanning terminal electrically connected to the data writing circuit in the n-th row pixel circuit;

[0014] The second scanning signal output terminal of the n-th stage driving circuit included in the driving module is electrically connected to the second scanning terminal electrically connected to the data writing circuit in the n-th row pixel circuit.

[0015] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a first scan signal output circuit, and a second scan signal output circuit;

[0016] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0017] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0018] The first scanning signal output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the first voltage terminal and the first scanning signal output terminal respectively, and is used to control the first scanning signal output terminal to be connected to the output clock signal terminal under the control of the potential of the first node, and to control the first scanning signal output terminal to be connected to the first voltage terminal under the control of the potential of the second node;

[0019] The second scanning signal output circuit is electrically connected to the first node, the first scanning signal output terminal, the second scanning signal output terminal, the first voltage terminal and the second voltage terminal respectively, and is used to control the second scanning signal output terminal to be connected to the second voltage terminal under the control of the potential of the first node, and to control the second scanning signal output terminal to be connected to the first voltage terminal under the control of the first scanning signal provided by the first scanning signal output terminal;

[0020] A voltage value of a first voltage signal provided by the first voltage terminal is smaller than a voltage value of a second voltage signal provided by the second voltage terminal.

[0021] Optionally, the first scan signal output circuit includes a first output transistor and a second output transistor;

[0022] The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output clock signal terminal, and the second electrode of the first output transistor is electrically connected to the first scan signal output terminal;

[0023] A gate of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the first scan signal output terminal, and a second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0024] Optionally, the second scanning signal output circuit includes a third output transistor and a fourth output transistor;

[0025] The gate of the third output transistor is electrically connected to the first node, the first electrode of the third output transistor is electrically connected to the second scanning signal output terminal, and the second electrode of the third output transistor is electrically connected to the second voltage terminal;

[0026] A gate of the fourth output transistor is electrically connected to the first scan signal output terminal, a first electrode of the fourth output transistor is electrically connected to the second scan signal output terminal, and a second electrode of the fourth output transistor is electrically connected to the first voltage terminal.

[0027] Optionally, the display panel described in at least one embodiment of the present utility model further includes a substrate; the pixel circuit is arranged on the substrate;

[0028] The orthographic projection of the top gate of the transistor included in the data writing circuit on the substrate does not overlap with the orthographic projection of the connection electrode of the transistor included in the data writing circuit on the substrate;

[0029] The connection electrode of the transistor included in the data write circuit includes a source of the transistor included in the data write circuit and a drain of the transistor included in the data write circuit.

[0030] Optionally, the display panel described in at least one embodiment of the present utility model further includes a substrate; the pixel circuit is arranged on the substrate;

[0031] An overlapping area between an orthographic projection of a top gate of a transistor included in the data writing circuit on the substrate and an orthographic projection of a connection electrode of the transistor included in the data writing circuit on the substrate is a first area;

[0032] An overlapping area between an orthographic projection of a bottom gate of a transistor included in the data writing circuit on the substrate and an orthographic projection of a connection electrode of the transistor included in the data writing circuit on the substrate is a second area;

[0033] The first area is smaller than the second area;

[0034] The connection electrode of the transistor included in the data write circuit includes a source of the transistor included in the data write circuit and a drain of the transistor included in the data write circuit.

[0035] Optionally, the display panel described in at least one embodiment of the utility model further includes a substrate, a light-shielding metal layer, a semiconductor layer and a gate metal layer;

[0036] The light-shielding metal layer, the semiconductor layer and the gate metal layer are arranged in sequence along a direction away from the substrate;

[0037] The semiconductor layer includes a channel of a transistor included in the data writing circuit; the orthographic projection of the light-shielding metal layer on the substrate covers the orthographic projection of the channel on the substrate;

[0038] The light-shielding metal layer includes the bottom gate, and the gate metal layer includes the top gate.

[0039] Optionally, the display panel described in at least one embodiment of the present invention further includes a plurality of rows and columns of touch electrode blocks, a plurality of columns of signal transmission lines, and a voltage supply circuit; the plurality of rows and columns of touch electrode blocks are independent of each other;

[0040] The voltage supply circuit is electrically connected to the first end of the signal transmission line, the signal transmission line includes a connection point, and the connection point is electrically connected to the touch electrode block;

[0041] The voltage supply circuit is used to provide a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line in the display stage.

[0042] Optionally, the display panel described in at least one embodiment of the utility model further includes a common electrode layer and a detection integrated circuit;

[0043] The common electrode layer includes a plurality of common electrode portions, and the plurality of common electrode portions are interconnected;

[0044] The common electrode portion includes at least one detection point;

[0045] The detection integrated circuit is electrically connected to the common electrode portion through the detection point, and is used to detect the potential of the detection point during the detection phase; the detection integrated circuit is also used to obtain a corresponding compensation voltage signal based on the potential of the detection point and the target common electrode voltage signal.

[0046] Optionally, the detection point is directly electrically connected to the detection integrated circuit.

[0047] Optionally, the common electrode layer includes multiple rows and columns of common electrode parts; the display panel includes a display area and a peripheral area, and the pixel circuit is arranged in the display area;

[0048] The detection point extends to a peripheral area through a first connection line extending along a row direction, and the first connection line is electrically connected to the detection integrated circuit through a second connection line arranged in the peripheral area.

[0049] Optionally, the display panel described in at least one embodiment of the present utility model further includes a switch control module, and the switch control module includes a plurality of switch control circuits;

[0050] The control end of the switch control circuit is electrically connected to the corresponding switch control end, the first end of the switch control circuit is electrically connected to the detection integrated circuit, the second end of the switch control circuit is electrically connected to the detection point, and the switch control circuit is used to control the connection between the detection integrated circuit and the detection point in the corresponding detection phase included in the detection cycle;

[0051] The detection integrated circuit is used to detect the potential of the detection point in the corresponding detection stage.

[0052] Optionally, the switch control circuit is used to control the connection between the detection integrated circuit and the detection point during a corresponding compensation phase included in the compensation cycle;

[0053] The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode portion through the switch control circuit during the corresponding compensation stage.

[0054] Optionally, the common electrode layer includes N rows and 2M columns of common electrode parts; N and M are positive integers; the display panel further includes a first switch control module and a second switch control module; the first switch control module includes N first switch control units, and the second switch control module includes N second switch control units;

[0055] The first switch control unit includes M first switch control circuits, and the second switch control unit includes M second switch control circuits;

[0056] The display panel includes a display area and a peripheral area, the pixel circuit is arranged in the display area, and the first switch control module and the second switch control module are arranged in the peripheral area; the first switch control module is arranged on a first side of the display area, and the second switch control module is arranged on a second side of the display area, and the first side and the second side are opposite sides;

[0057] The mth first switch control circuit in the nth first switch control unit is electrically connected to the nth first switch control terminal, the detection integrated circuit and the common electrode portion in the nth row and the mth column, respectively, and is used to control the detection integrated circuit to be connected to the detection point included in the common electrode portion in the nth row and the mth column under the control of the switch control signal provided by the nth first switch control terminal;

[0058] The mth second switch control circuit in the nth second switch control unit is electrically connected to the nth second switch control terminal, the detection integrated circuit and the common electrode portion of the nth row and the M+mth column, respectively, and is used to control the detection integrated circuit to be connected to the detection point included in the common electrode portion of the nth row and the M+mth column under the control of the switch control signal provided by the nth second switch control terminal;

[0059] n is a positive integer less than or equal to N; m is a positive integer less than or equal to M.

[0060] Optionally, the common electrode portion includes a plurality of portions sequentially arranged along the first direction;

[0061] The detection point of the common electrode portion at the nth row and the mth column is included in the ath portion included in the common electrode portion at the nth row and the mth column;

[0062] The detection point of the common electrode portion of the nth row and the M+mth column is included in the bth part of the common electrode portion of the nth row and the M+mth column;

[0063] Both a and b are positive integers, and a is not equal to b.

[0064] Optionally, the display panel described in at least one embodiment of the present invention further includes a first switch control signal generating module and a second switch control signal generating module arranged in the peripheral area; the first switch control signal generating module is arranged on a first side of the display area, and the second switch control signal generating module is arranged on a second side of the display area;

[0065] The first switch control signal generating module is electrically connected to the N first switch control terminals respectively, and is used to provide a valid switch control signal to the nth first switch control terminal in the nth detection phase included in the detection cycle;

[0066] The second switch control signal generating module is electrically connected to the N second switch control terminals respectively, and is used to provide a valid switch control signal to the nth second switch control terminal in the nth detection phase included in the detection cycle;

[0067] The detection integrated circuit is used to detect the potential of the detection points included in each common electrode part located in the nth row in the nth detection stage.

[0068] Optionally, the first switch control signal generating module is electrically connected to the N first switch control terminals respectively, and is used to provide a valid switch control signal to the nth first switch control terminal in the nth compensation stage included in the compensation cycle;

[0069] The second switch control signal generating module is electrically connected to the N second switch control terminals respectively, and is used to provide a valid switch control signal to the nth second switch control terminal in the nth compensation phase included in the compensation cycle;

[0070] The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode part in the nth compensation stage.

[0071] Optionally, the display panel described in at least one embodiment of the utility model further includes a voltage providing circuit and a plurality of columns of signal transmission lines;

[0072] The voltage supply circuit is electrically connected to the common electrode portion through the signal transmission line, and is used to provide the compensation voltage signal to the signal transmission line during a compensation phase.

[0073] In a second aspect, the display device described in the embodiment of the present invention includes the above-mentioned display panel.

[0074] In the display panel and display device described in the embodiments of the utility model, the first gate of the transistor included in the data writing circuit is electrically connected to the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected to the second scanning end. By reducing the coupling of the scanning signal to the data voltage on the data line to reduce △Vp, the Flicker phenomenon is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1A is a circuit diagram of at least one embodiment of a data writing circuit;

[0076] Figure 1B yes Figure 1A An operation timing diagram of at least one embodiment of the data writing circuit shown;

[0077] Figure 2 is a circuit diagram of at least one embodiment of a data writing circuit;

[0078] Figure 3 is a structural diagram of at least one embodiment of a driving circuit in a display panel according to the utility model;

[0079] Figure 4A is a structural diagram of at least one embodiment of a driving circuit in a display panel according to the utility model;

[0080] Figure 4BIt is a schematic diagram of the correspondence between the ratio of the channel width-to-length ratio of the fourth output transistor to the channel width-to-length ratio of the third output transistor (width-to-length ratio) and the Flicer (flicker) value when at least one embodiment of the driving circuit in the display panel of the utility model is working;

[0081] Figure 5 is a circuit diagram of at least one embodiment of a driving circuit in a display panel according to the utility model;

[0082] Figure 6 and Figure 7 is a cross-sectional view of at least one embodiment of a display panel;

[0083] Figure 8 and Fig. 9 is a cross-sectional view of at least one embodiment of a display panel;

[0084] Fig.10 and Fig.11 is a cross-sectional view of at least one embodiment of a display panel;

[0085] Fig. 12A is a schematic diagram of a touch electrode block included in a display panel according to at least one embodiment of the present utility model;

[0086] Fig. 12B is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0087] Fig.13 is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0088] Fig.14 is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0089] Fig.15 is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0090] Fig.16 is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0091] Fig.17 is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0092] Fig.18 is a structural diagram of the common electrode portion;

[0093] Fig.19 is a structural diagram of a display panel according to at least one embodiment of the present utility model;

[0094] Fig. 20 It is a structural diagram of a display panel described in at least one embodiment of the utility model. DETAILED DESCRIPTION

[0095] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0096] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.

[0097] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0098] The display panel described in the embodiment of the utility model comprises a plurality of rows and columns of pixel circuits; the pixel circuits comprise a data writing circuit;

[0099] The data writing circuit is electrically connected to the scanning end and the data line respectively, and is used to access the data voltage provided by the data line under the control of the scanning signal provided by the scanning end;

[0100] The transistor included in the data writing circuit includes a first gate and a second gate, and the scanning end includes a first scanning end and a second scanning end;

[0101] The first gate of the transistor included in the data writing circuit is electrically connected to the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected to the second scanning end;

[0102] The first gate is a top gate, and the second gate is a bottom gate; the first gate is a bottom gate, and the second gate is a top gate.

[0103] In the display panel described in the embodiment of the utility model, the first gate of the transistor included in the data writing circuit is electrically connected to the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected to the second scanning end. By reducing the coupling of the scanning signal to the data voltage on the data line to reduce △Vp, the Flicker phenomenon is improved; wherein △Vp is the change value of the pixel voltage, and the pixel voltage is the data voltage connected to the pixel circuit.

[0104] In at least one embodiment of the present invention, when the potential of the first scanning signal provided by the first scanning end decreases, the potential of the second scanning signal provided by the second scanning end increases;

[0105] When the potential of the first scanning signal provided by the first scanning end increases, the potential of the second scanning signal provided by the second scanning end decreases.

[0106] In a specific implementation, when the potential of the first scanning signal decreases, the potential of the second scanning signal increases; when the potential of the first scanning signal increases, the potential of the second scanning signal decreases; the change in the potential of the second gate of the transistor included in the data writing circuit can offset the change in the first gate of the transistor included in the data writing circuit to offset △Vp.

[0107] like Figure 1A As shown, at least one embodiment of the data writing circuit may include a data writing transistor T0;

[0108] The top gate of T0 is electrically connected to the first scanning terminal G1, and the bottom gate of T0 is electrically connected to the second scanning terminal G2;

[0109] The source of T0 is labeled S, and the drain of T0 is labeled D.

[0110] like Figure 1B As shown, Figure 1A When at least one embodiment of the data writing circuit shown is in operation, when G1 provides a high voltage signal, G2 provides a first low voltage signal LVGL;

[0111] When G1 provides the first low voltage signal LVGL, G2 provides the second low voltage signal VGL.

[0112] The voltage value of the first low voltage signal LVGL is lower than the voltage value of the second low voltage signal VGL.

[0113] like Figure 2 As shown, the data writing circuit may include a data writing transistor T0;

[0114] The bottom gate of T0 is electrically connected to the first scanning terminal G1, and the top gate of T0 is electrically connected to the second scanning terminal G2;

[0115] The source of T0 is marked as S, and the drain of T0 is marked as D;

[0116] The source of T0 may be electrically connected to the data line and receive the data voltage.

[0117] The display panel described in at least one embodiment of the present utility model further includes a driving module; the driving module includes a multi-stage driving circuit;

[0118] The driving circuit includes a first scanning signal output terminal and a second scanning signal output terminal;

[0119] The first scanning signal output terminal of the n-th level driving circuit included in the driving module is electrically connected to the first scanning terminal electrically connected to the data writing circuit in the n-th row pixel circuit;

[0120] The second scanning signal output terminal of the n-th stage driving circuit included in the driving module is electrically connected to the second scanning terminal electrically connected to the data writing circuit in the n-th row pixel circuit.

[0121] In a specific implementation, the display panel may further include a driving module, which may include a first scanning signal output terminal and a second scanning signal output terminal, the first scanning signal output terminal included in the nth driving circuit is electrically connected to the first scanning terminal electrically connected to the data writing circuit in the nth row of pixel circuits, and the second scanning signal output terminal included in the nth driving circuit is electrically connected to the second scanning terminal electrically connected to the data writing circuit in the nth row of pixel circuits.

[0122] In at least one embodiment of the present utility model, the driving circuit includes a first node control circuit, a second node control circuit, a first scan signal output circuit, and a second scan signal output circuit;

[0123] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0124] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0125] The first scanning signal output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the first voltage terminal and the first scanning signal output terminal respectively, and is used to control the first scanning signal output terminal to be connected to the output clock signal terminal under the control of the potential of the first node, and to control the first scanning signal output terminal to be connected to the first voltage terminal under the control of the potential of the second node;

[0126] The second scanning signal output circuit is electrically connected to the first node, the first scanning signal output terminal, the second scanning signal output terminal, the first voltage terminal and the second voltage terminal respectively, and is used to control the second scanning signal output terminal to be connected to the second voltage terminal under the control of the potential of the first node, and to control the second scanning signal output terminal to be connected to the first voltage terminal under the control of the first scanning signal provided by the first scanning signal output terminal;

[0127] A voltage value of a first voltage signal provided by the first voltage terminal is smaller than a voltage value of a second voltage signal provided by the second voltage terminal.

[0128] In a specific implementation, the driving circuit includes a first node control circuit, a second node control circuit, a first scan signal output circuit and a second scan signal output circuit; the first node control circuit controls the potential of the first node; the second node control circuit controls the potential of the second node; the first scan signal output circuit controls the connection between the first scan signal output terminal and the output clock signal terminal under the control of the potential of the first node, and controls the connection between the first scan signal output terminal and the first voltage terminal under the control of the potential of the second node; the second scan signal output circuit controls the connection between the second scan signal output terminal and the second voltage terminal under the control of the potential of the first node, and controls the connection between the second scan signal output terminal and the first voltage terminal under the control of the first scan signal provided by the first scan signal output terminal.

[0129] Optionally, the first voltage terminal may be a first low voltage terminal, and the second voltage terminal may be a second low voltage terminal.

[0130] like Figure 3 As shown, at least one embodiment of the driving circuit includes a first node control circuit 31, a second node control circuit 32, a first scan signal output circuit 33 and a second scan signal output circuit 34;

[0131] The first node control circuit 31 is electrically connected to the first node PU, and is used to control the potential of the first node PU;

[0132] The second node control circuit 32 is electrically connected to the second node PD, and is used to control the potential of the second node PD;

[0133] The first scan signal output circuit 33 is electrically connected to the first node PU, the second node PD, the output clock signal terminal CLK, the first scan signal output terminal OT1 and the first low voltage terminal respectively, and is used to control the first scan signal output terminal OT1 to be connected to the output clock signal terminal CLK under the control of the potential of the first node PU, and to control the first scan signal output terminal OT1 to be connected to the first low voltage terminal under the control of the potential of the second node PD;

[0134] The second scan signal output circuit 34 is electrically connected to the first node PU, the first scan signal output terminal OT1, the second scan signal output terminal OT2, the first low voltage terminal and the second low voltage terminal respectively, and is used to control the second scan signal output terminal OT2 to be connected to the second low voltage terminal under the control of the potential of the first node PU, and to control the second scan signal output terminal OT2 to be connected to the first low voltage terminal under the control of the first scan signal provided by the first scan signal output terminal OT1;

[0135] The first low voltage terminal is used to provide a first low voltage signal LVGL; the second low voltage terminal is used to provide a second low voltage signal VGL;

[0136] A voltage value of the first low voltage signal LVGL is smaller than a voltage value of the second low voltage signal VGL.

[0137] Optionally, the first scan signal output circuit includes a first output transistor and a second output transistor;

[0138] The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output clock signal terminal, and the second electrode of the first output transistor is electrically connected to the first scan signal output terminal;

[0139] A gate of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the first scan signal output terminal, and a second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0140] Optionally, the second scanning signal output circuit includes a third output transistor and a fourth output transistor;

[0141] The gate of the third output transistor is electrically connected to the first node, the first electrode of the third output transistor is electrically connected to the second scanning signal output terminal, and the second electrode of the third output transistor is electrically connected to the second voltage terminal;

[0142] A gate of the fourth output transistor is electrically connected to the first scan signal output terminal, a first electrode of the fourth output transistor is electrically connected to the second scan signal output terminal, and a second electrode of the fourth output transistor is electrically connected to the first voltage terminal.

[0143] like Figure 4A As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the first scanning signal output circuit includes a first output transistor MO1 and a second output transistor MO2;

[0144] The gate of the first output transistor MO1 is electrically connected to the first node PU, the drain of the first output transistor MO1 is electrically connected to the output clock signal terminal CLK, and the source of the first output transistor MO1 is electrically connected to the first scan signal output terminal OT1;

[0145] The gate of the second output transistor MO2 is electrically connected to the second node PD, the drain of the second output transistor MO2 is electrically connected to the first scan signal output terminal OT1, and the source of the second output transistor MO2 is electrically connected to the first low voltage terminal; the first low voltage terminal is used to provide a first low voltage signal LVGL;

[0146] The second scanning signal output circuit includes a third output transistor MO3 and a fourth output transistor MO4;

[0147] The gate of the third output transistor MO3 is electrically connected to the first node PU, the drain of the third output transistor MO3 is electrically connected to the second scan signal output terminal OT2, and the source of the third output transistor MO3 is electrically connected to the second low voltage terminal; the second low voltage terminal is used to provide a second low voltage signal VGL;

[0148] The gate of the fourth output transistor MO4 is electrically connected to the first scan signal output terminal OT1, the source of the fourth output transistor MO4 is electrically connected to the second scan signal output terminal OT2, and the drain of the fourth output transistor MO4 is electrically connected to the first low voltage terminal.

[0149] exist Figure 4A In at least one embodiment of the driving circuit shown, all transistors are n-type transistors.

[0150] exist Figure 4A In at least one embodiment of the driving circuit shown, the channel width-to-length ratio of MO4 is greater than the channel width-to-length ratio of MO3.

[0151] In at least one embodiment of the present invention, the ratio of the channel width-to-length ratio of MO4 to the channel width-to-length ratio of MO3 may be greater than or equal to 10 and less than or equal to 30; for example, the ratio of the channel width-to-length ratio of MO4 to the channel width-to-length ratio of MO3 may be equal to 10, 20, 30, 15 or 25, more specifically, the ratio of the channel width-to-length ratio of MO4 to the channel width-to-length ratio of MO3 may be greater than or equal to 15 and less than or equal to 25; but not limited to this.

[0152] In a specific implementation, the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is set to be larger, so that when MO4 and MO3 are both turned on, OT2 can output the first low voltage signal LVGL;

[0153] Furthermore, the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 may not be set too large, so as to prevent the channel width-to-length ratio of MO4 from being too large, thereby preventing the space occupied by MO4 from being too large, thereby facilitating the realization of a narrow frame.

[0154] like Figure 4B As shown, when the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 (width-to-length ratio) is 1, the Flicer value is -52.2 dB;

[0155] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 2, the Flicer value is -52.2dB;

[0156] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 8, the Flicer value is -52.3dB;

[0157] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 10, the Flicer value is -56.6dB;

[0158] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 15, the Flicer value is -57.1dB;

[0159] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 20, the Flicer value is -57.7dB;

[0160] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 25, the Flicer value is -57.9 dB;

[0161] When the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is 30, the Flicer value is -58.1 dB.

[0162] Depend on Figure 4B It can be seen that when the ratio between the channel width-to-length ratio of MO4 and the channel width-to-length ratio of MO3 is greater than or equal to 10, the Flicker value decreases, which can improve the flicker phenomenon.

[0163] Figure 4A At least one embodiment of the driving circuit shown in the figure is in operation.

[0164] When the potential of PU is a high voltage signal and OT1 provides a high voltage signal, MO3 and MO4 are both turned on. Since the channel width-to-length ratio of MO4 is greater than that of MO3, OT2 outputs a first low voltage signal LVGL.

[0165] When the potential of PU is a high voltage signal and CLK provides a low voltage signal, MO3 is turned on, MO1 is turned on, OT2 outputs the second low voltage signal VGL, and OT1 outputs a low voltage signal; when CLK provides the first low voltage signal LVGL, OT1 outputs the first low voltage signal LVGL; when CLK provides the second low voltage signal VGL, OT1 outputs the second low voltage signal VGL.

[0166] like Figure 5 As shown, in Figure 4A Based on at least one embodiment of the driving circuit shown, the first node control circuit includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0167] The gate of M1 is electrically connected to the input terminal I1, the drain of M1 is electrically connected to the first scan voltage terminal VDS, and the source of M1 is electrically connected to the first node PU;

[0168] The gate of M2 is electrically connected to the second node PD, the drain of M2 is electrically connected to the first node PU, and the source of M2 is electrically connected to the second low voltage terminal;

[0169] The gate of M3 is electrically connected to the reset terminal RST, the drain of M3 is electrically connected to the first node PU, and the source of M3 is electrically connected to the second scan voltage terminal VSD;

[0170] The gate of M4 is electrically connected to the frame reset terminal STV0, the drain of M4 is electrically connected to the first node PU, and the source of M4 is electrically connected to the second low voltage terminal;

[0171] The second node control circuit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a first capacitor C1;

[0172] The gate of M7 and the drain of M7 are both electrically connected to the high level terminal GCH, and the source of M7 is electrically connected to the pull-down control node;

[0173] The gate of M8 is electrically connected to the first node PU, the drain of M8 is electrically connected to the pull-down control node, and the source of M8 is electrically connected to the second low voltage terminal;

[0174] The gate of M5 is electrically connected to the pull-down control node, the drain of M5 is electrically connected to the high level terminal GCH, and the source of M5 is electrically connected to the second node PD;

[0175] The gate of M6 is electrically connected to the first node PU, the drain of M6 is electrically connected to the second node PD, and the source of M6 is electrically connected to the second low voltage terminal;

[0176] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the first scan signal output terminal OT1;

[0177] At least one embodiment of the driving circuit further includes a seventh transistor M7;

[0178] The gate of M7 is electrically connected to the frame start terminal STV0, the drain of M7 is electrically connected to the first scan signal output terminal OT1, and the source of M7 is electrically connected to the first low voltage terminal;

[0179] The first low voltage terminal is used to provide a first low voltage signal LVGL, and the second low voltage terminal is used to provide a second low voltage signal VGL.

[0180] exist Figure 5 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors.

[0181] The utility model Figure 5 When at least one embodiment of the driving circuit shown is in operation, after the TFT (thin film transistor) is fully charged, the first scanning signal output by OT1 changes from the high voltage signal VGH to the second low voltage signal VGL, and the potential of the second scanning signal provided by OT2 changes from the first low voltage signal LVGL to the second low voltage signal VGL; since there is a parasitic capacitance between the top gate of the data writing transistor and the source of the data writing transistor, and there is a parasitic capacitance between the bottom gate of the data writing transistor and the source of the data writing transistor, the source voltage of the data writing transistor will rise, which can reduce or even offset △Vp;

[0182] When the first scan signal output by OT1 rises from the first low voltage signal LVGL to the high voltage signal VGH, the second scan signal output by OT2 changes from the second low voltage signal VGL to LVGL. When the potential of the first scan signal rises, the potential of the second scan signal decreases to reduce or even offset △Vp.

[0183] In the related art, when the first scanning signal output by OT1 changes from the high voltage signal VGH to the second low voltage signal VGL, △Vp1 is equal to (Cgs / (Cgs+Cst))×(VGH-VGL); wherein Cst is the storage capacitor in the pixel circuit;

[0184] In at least one embodiment of the present invention, when the first scan signal output by OT1 changes from the high voltage signal VGH to the second low voltage signal VGL, and the potential of the second scan signal provided by OT2 changes from the first low voltage signal LVGL to the second low voltage signal VGL, △Vp2 is equal to (Cgs / (Cgs+Cst))×(VGH+LVGL-2VGL);

[0185] △Vp1 is greater than △Vp2;

[0186] When VGH is equal to 30V, VGL is equal to -8V, and LVGL is equal to -12V, △Vp1-△Vp2 is equal to 4×(Cgs / (Cgs+Cst)). △Vp1-△Vp2 increases as Cgs increases, and a decrease in △Vp helps improve Flicker.

[0187] △Vp1 is a change value of the pixel voltage in the related art, and △Vp2 is a change value of the pixel voltage in at least one embodiment of the present invention.

[0188] The display panel described in at least one embodiment of the present invention further includes a substrate; the pixel circuit is disposed on the substrate;

[0189] The orthographic projection of the top gate of the transistor included in the data writing circuit on the substrate does not overlap with the orthographic projection of the connection electrode of the transistor included in the data writing circuit on the substrate;

[0190] The connection electrode of the transistor included in the data write circuit includes a source of the transistor included in the data write circuit and a drain of the transistor included in the data write circuit.

[0191] In a specific implementation, the orthographic projection of the top gate of the transistor included in the data writing circuit on the substrate may not overlap with the orthographic projection of the connecting electrode of the transistor included in the data writing circuit on the substrate, so as to reduce the gate-source parasitic capacitance Cgs of the transistor included in the data writing circuit. Therefore, even if the voltage jump amplitude of the bottom gate is much smaller than the voltage jump amplitude of the top gate, it can also play a good role in regulating △Vp.

[0192] Moreover, in addition to reducing the effect of △Vp, the existence of the top gate can shield the pull of the bottom gate on the common electrode voltage Vcom. At this time, the voltage jump of the top gate is much smaller than the voltage jump of the bottom gate. For example, when the top gate voltage changes by 4V, the voltage jump of the bottom gate can be 38V. Reducing the pull of the gate on Vcom can alleviate the LH horizontal stripes and sensor horizontal stripes of TDDI (touch and display driver integration) display products.

[0193] The display panel described in at least one embodiment of the present invention further includes a substrate; the pixel circuit is disposed on the substrate;

[0194] An overlapping area between an orthographic projection of a top gate of a transistor included in the data writing circuit on the substrate and an orthographic projection of a connection electrode of the transistor included in the data writing circuit on the substrate is a first area;

[0195] An overlapping area between an orthographic projection of a bottom gate of a transistor included in the data writing circuit on the substrate and an orthographic projection of a connection electrode of the transistor included in the data writing circuit on the substrate is a second area;

[0196] The first area is smaller than the second area;

[0197] The connection electrode of the transistor included in the data write circuit includes a source of the transistor included in the data write circuit and a drain of the transistor included in the data write circuit.

[0198] In a specific implementation, the overlapping area between the orthographic projection of the top gate of the transistor of the data writing circuit on the substrate and the orthographic projection of the connecting electrode of the transistor included in the data writing circuit on the substrate can be smaller than the overlapping area between the orthographic projection of the bottom gate of the transistor of the data writing circuit on the substrate and the orthographic projection of the connecting electrode of the transistor included in the data writing circuit on the substrate, that is, the orthographic projection of the bottom gate of the transistor of the data writing circuit on the substrate can be reduced, and the gate-source parasitic capacitance Cgs of the transistor included in the data writing circuit can be reduced. Therefore, even if the voltage jump amplitude of the bottom gate is much smaller than the voltage jump amplitude of the top gate, it can also play a good role in regulating △Vp.

[0199] The display panel described in at least one embodiment of the present utility model further includes a substrate, a light-shielding metal layer, a semiconductor layer and a gate metal layer;

[0200] The light-shielding metal layer, the semiconductor layer and the gate metal layer are arranged in sequence along a direction away from the substrate;

[0201] The semiconductor layer includes a channel of a transistor included in the data writing circuit; the orthographic projection of the light-shielding metal layer on the substrate covers the orthographic projection of the channel on the substrate;

[0202] The light-shielding metal layer includes the bottom gate, and the gate metal layer includes the top gate.

[0203] In a specific implementation, when the display panel includes a shading metal layer arranged between the semiconductor layer and the substrate, the shading metal layer can be reused as a gate metal layer, and the shading metal layer can include a bottom gate. In this way, the data writing transistor can be set as a dual-gate transistor without adding a mask.

[0204] like Figure 6 As shown, P1 is a substrate, 61 is a first gate metal layer, 71 is a first gate insulating layer, 62 is a semiconductor layer, 72 is a second gate insulating layer, 63 is a source-drain metal layer, and 64 is a second gate metal layer;

[0205] like Figure 7 As shown, the semiconductor layer 62 includes a channel CH of the data writing transistor T0, a first conductive portion D1 of the data writing transistor T0, and a second conductive portion D2 of the data writing transistor T0;

[0206] The one labeled S0 is the source of T0, and the one labeled D0 is the drain of T0;

[0207] The one labeled GD is the bottom gate of T0, and the one labeled GT is the top gate of T0;

[0208] D1 is connected to S0, and D2 is connected to D0.

[0209] In at least one embodiment of the present invention, Figure 8 , Fig. 9 As shown, the orthographic projection of the top gate GT of T0 on the substrate P1 can be set to be smaller to reduce the overlapping area between GT and S0 and the overlapping area between GT and D0.

[0210] like Figure 8 As shown, P1 is a substrate, 61 is a first gate metal layer, 71 is a first gate insulating layer, 62 is a semiconductor layer, 72 is a second gate insulating layer, 63 is a source-drain metal layer, and 64 is a second gate metal layer;

[0211] like Fig. 9 As shown, the semiconductor layer 62 includes a channel CH of the data writing transistor T0, a first conductive portion D1 of the data writing transistor T0, and a second conductive portion D2 of the data writing transistor T0;

[0212] The one labeled S0 is the source of T0, and the one labeled D0 is the drain of T0;

[0213] The one labeled GD is the bottom gate of T0, and the one labeled GT is the top gate of T0;

[0214] D1 is connected to S0, and D2 is connected to D0.

[0215] like Fig. 9 As shown, the overlapping area between the orthographic projection of the bottom gate GD of T0 on the substrate P1 and the orthographic projection of the connecting electrode of T0 on the substrate P1 is greater than the overlapping area between the orthographic projection of the top gate GT of T0 on the substrate P1 and the orthographic projection of the connecting electrode of T0 on the substrate P1.

[0216] like Fig.10As shown, P1 is the substrate, 101 is the shading metal layer, 102 is the buffer layer, 62 is the semiconductor layer, 103 is the gate insulating layer, 63 is the source and drain metal layer, 104 is the gate metal layer, and 105 is the interlayer dielectric layer.

[0217] exist Fig.10 In at least one embodiment shown, the shading metal layer 101 is reused as the first gate metal layer, the gate metal layer 104 is the second gate metal layer, the bottom gate of the transistor is made by the shading metal layer 101, and the top gate of the transistor is made by the gate metal layer 104.

[0218] like Fig.11 As shown, the bottom gate of T0 is labeled GD, and the top gate of T0 is labeled GT;

[0219] The semiconductor layer 62 includes a channel CH of the data writing transistor T0, a first conductive portion D1 of the data writing transistor T0, and a second conductive portion D2 of the data writing transistor T0;

[0220] The one labeled S0 is the source of T0, and the one labeled D0 is the drain of T0;

[0221] D1 is connected to S0, and D2 is connected to D0.

[0222] like Fig.11 As shown, the orthographic projection of the top gate GT of the data writing transistor T0 on the substrate P1 does not overlap with the orthographic projection of the source S0 of T0 on the substrate P1;

[0223] The orthographic projection of the bottom gate GD of T0 on the substrate P1 does not overlap with the orthographic projection of the drain D0 of T0 on the substrate P1;

[0224] like Fig.10 , Fig.11 As shown, the orthographic projection of the light-shielding metal layer 10 on the substrate P1 covers the orthographic projection of the channel CH on the substrate P1.

[0225] In a specific implementation, in a TDDI display product, Flicker can be improved by improving the uniformity of the common electrode voltage Vcom within the plane.

[0226] The display panel of at least one embodiment of the present invention further comprises a plurality of rows and columns of touch electrode blocks, a plurality of columns of signal transmission lines and a voltage supply circuit; the plurality of rows and columns of touch electrode blocks are independent of each other;

[0227] The voltage supply circuit is electrically connected to the first end of the signal transmission line, the signal transmission line includes a connection point, and the connection point is electrically connected to the touch electrode block;

[0228] The voltage supply circuit is used to provide a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line in the display stage.

[0229] In a specific implementation, when the display panel is a TDDI display panel, the display panel may include multiple rows and columns of touch electrode blocks that are independent of each other. In the display stage, the touch electrode blocks may be reused as common electrode blocks and connected to a common electrode voltage Vcom. The display panel may also include multiple columns of signal transmission lines and a voltage providing circuit. The signal output line is electrically connected to the touch electrode block through a connection point. In the display stage, the voltage providing circuit provides a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line, so that the common electrode blocks received by each touch electrode block are roughly the same, thereby improving the Vcom uniformity in the TDDI display panel and further improving Flicker.

[0230] like Fig. 12AAs shown, the display panel described in at least one embodiment of the utility model includes a first row and first column touch electrode block TB11, a first row and second column touch electrode block TB12, a first row and third column touch electrode block TB13, a first row and fourth column touch electrode block TB14, a first row and fifth column touch electrode block TB15, a first row and sixth column touch electrode block TB16, a second row and first column touch electrode block TB21, a second row and second column touch electrode block TB22, a second row and third column touch electrode block TB23, a second row and fourth column touch electrode block TB24, a second row and fifth column touch electrode block TB25, a second row and sixth column touch electrode block TB16, a third row and first column touch electrode block TB31, a third row and second column touch electrode block TB32, a third row and third column touch electrode block TB33, a third row and fourth column touch electrode block TB34, a third row and fifth column touch electrode block TB35, a third row and The sixth column of touch electrode block TB36, the fourth row and the first column of touch electrode block TB41, the fourth row and the second column of touch electrode block TB42, the fourth row and the third column of touch electrode block TB43, the fourth row and the fourth column of touch electrode block TB44, the fourth row and the fifth column of touch electrode block TB45, the fourth row and the sixth column of touch electrode block TB46, the fifth row and the first column of touch electrode block TB51, the fifth row and the second column of touch electrode block TB52, the fifth row and the third column of touch electrode block TB53, the fifth row and the fourth column of touch electrode block TB54, the fifth row and the fifth column of touch electrode block TB55, the fifth row and the sixth column of touch electrode block TB56, the sixth row and the first column of touch electrode block TB61, the sixth row and the second column of touch electrode block TB62, the sixth row and the third column of touch electrode block TB63, the sixth row and the fourth column of touch electrode block TB64, the sixth row and the fifth column of touch electrode block TB65 and the sixth row and the sixth column of touch electrode block TB66;

[0231] like Fig. 12B As shown, the display panel described in at least one embodiment of the present utility model further includes a voltage providing circuit 10 and a plurality of columns of signal transmission lines;

[0232] exist Fig. 12B Among them, the line labeled L0 is a signal transmission line, and the signal transmission line L0 includes a connection point NJ;

[0233] The voltage supply circuit 10 is electrically connected to the first end of each signal transmission line, and each signal transmission line is electrically connected to the corresponding touch electrode block through a corresponding connection point;

[0234] The voltage providing circuit 10 is used for providing a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line during the display stage.

[0235] In specific implementation, the resistance between the first end of the signal transmission line and the connection of the signal transmission line can be calculated, and the voltage drop on the signal transmission line can be calculated according to the principle of resistance voltage division; in the display stage, the signal transmission line transmits the common electrode voltage Vcom, and the voltage drop caused by the resistance of the signal transmission line itself causes the Vcom of the corresponding touch electrode block to be insufficient, which needs to be compensated. At least one embodiment of the utility model can adjust the common electrode voltage output by the voltage providing circuit 10 through an algorithm, and for the touch electrode blocks located in different rows, the common electrode voltage compensation is performed according to the calculated voltage drop on the signal transmission line to improve the uniformity of the common electrode voltage.

[0236] The display panel described in at least one embodiment of the present utility model further includes a common electrode layer and a detection integrated circuit;

[0237] The common electrode layer includes a plurality of common electrode portions, and the plurality of common electrode portions are interconnected;

[0238] The common electrode portion includes at least one detection point;

[0239] The detection integrated circuit is electrically connected to the common electrode portion through the detection point, and is used to detect the potential of the detection point during the detection phase; the detection integrated circuit is also used to obtain a corresponding compensation voltage signal based on the potential of the detection point and the target common electrode voltage signal.

[0240] In non-TDDI display products, a whole common electrode layer is provided, and the common electrode layer can be provided to include a plurality of common electrode parts interconnected with each other. The detection integrated circuit is electrically connected to the corresponding common electrode part through the corresponding detection point, and the potential of the detection point is detected during the detection stage. According to the potential of the detection point and the target common electrode voltage signal, a corresponding compensation voltage signal can be obtained.

[0241] Optionally, the target common electrode voltage signal may be a maximum value, a minimum value or an average value of common electrode voltages detected by the detection integrated circuit, but is not limited thereto.

[0242] In at least one embodiment of the present invention, the detection point is directly electrically connected to the detection integrated circuit.

[0243] In a specific implementation, the detection point may be directly electrically connected to a detection IC (Integrated Circuit), and the detection IC directly detects the potential of the detection point.

[0244] In at least one embodiment of the present invention, the common electrode layer includes multiple rows and columns of common electrode portions; the display panel includes a display area and a peripheral area, and the pixel circuit is arranged in the display area;

[0245] The detection point extends to a peripheral area through a first connection line extending along a row direction, and the first connection line is electrically connected to the detection integrated circuit through a second connection line arranged in the peripheral area.

[0246] In a specific implementation, the common electrode layer may include multiple rows and columns of common electrode portions interconnected with each other, the detection point may extend to the peripheral area through a first connection line extending along the row direction, and the first connection line is electrically connected to the detection integrated circuit through a second connection line arranged in the peripheral area.

[0247] The display panel described in at least one embodiment of the present utility model further includes a switch control module, and the switch control module includes a plurality of switch control circuits;

[0248] The control end of the switch control circuit is electrically connected to the corresponding switch control end, the first end of the switch control circuit is electrically connected to the detection integrated circuit, the second end of the switch control circuit is electrically connected to the detection point, and the switch control circuit is used to control the connection between the detection integrated circuit and the detection point in the corresponding detection phase included in the detection cycle;

[0249] The detection integrated circuit is used to detect the potential of the detection point in the corresponding detection stage.

[0250] In a specific implementation, the display panel may further include a switch control module. When the common electrode layer includes N rows and 2M columns of common electrode portions, the switch control module may include N switch control circuits; the nth switch control circuit may include M switch control transistors;

[0251] The gate of the mth switch control transistor included in the nth switch control circuit is electrically connected to the nth switch control terminal, the first electrode of the mth switch control transistor included in the nth switch control circuit is electrically connected to the mth terminal of the detection integrated circuit, and the second electrode of the mth switch control transistor included in the nth switch control circuit is electrically connected to the detection point included in the common electrode portion of the nth row and the mth column;

[0252] When the nth switch control terminal provides a valid nth switch control signal, the mth switch control transistor included in the nth switch control circuit is turned on, and the mth terminal of the detection integrated circuit is connected to the detection point included in the common electrode portion of the nth row and mth column.

[0253] When the display panel described in at least one embodiment of the utility model is working, the detection cycle may include N detection stages arranged in succession. In the nth detection stage, when the nth switch control terminal provides a valid nth switch control signal, the mth switch control transistor included in the nth switch control circuit is turned on, and the mth terminal of the detection integrated circuit is connected to the detection point included in the common electrode part of the nth row and mth column.

[0254] Wherein, N and M are positive integers; n is a positive integer less than or equal to N; and m is a positive integer less than or equal to M.

[0255] In at least one embodiment of the present utility model, the switch control circuit is used to control the connection between the detection integrated circuit and the detection point during the corresponding compensation phase included in the compensation cycle;

[0256] The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode portion through the switch control circuit during the corresponding compensation stage.

[0257] In a specific implementation, the compensation cycle may include N compensation stages that are arranged successively. In the nth compensation stage, when the nth switch control terminal provides a valid nth switch control signal, the mth switch control transistor included in the nth switch control circuit is turned on, and the detection integrated circuit transmits the corresponding compensation voltage signal to the common electrode portion of the nth row and mth column.

[0258] Optionally, the common electrode layer includes N rows and 2M columns of common electrode parts; N and M are positive integers; the display panel further includes a first switch control module and a second switch control module; the first switch control module includes N first switch control units, and the second switch control module includes N second switch control units;

[0259] The first switch control unit includes M first switch control circuits, and the second switch control unit includes M second switch control circuits;

[0260] The display panel includes a display area and a peripheral area, the pixel circuit is arranged in the display area, and the first switch control module and the second switch control module are arranged in the peripheral area; the first switch control module is arranged on a first side of the display area, and the second switch control module is arranged on a second side of the display area, and the first side and the second side are opposite sides;

[0261] The mth first switch control circuit in the nth first switch control unit is electrically connected to the nth first switch control terminal, the detection integrated circuit and the common electrode portion in the nth row and the mth column, respectively, and is used to control the detection integrated circuit to be connected to the detection point included in the common electrode portion in the nth row and the mth column under the control of the switch control signal provided by the nth first switch control terminal;

[0262] The mth second switch control circuit in the nth second switch control unit is electrically connected to the nth second switch control terminal, the detection integrated circuit and the common electrode portion of the nth row and the M+mth column, respectively, and is used to control the detection integrated circuit to be connected to the detection point included in the common electrode portion of the nth row and the M+mth column under the control of the switch control signal provided by the nth second switch control terminal;

[0263] n is a positive integer less than or equal to N; m is a positive integer less than or equal to M.

[0264] In a specific implementation, the common electrode layer may include N rows and 2M columns of common electrode portions, and the display panel may include a first switch control module and a second switch control module disposed in the peripheral area, the first switch control module being disposed on a first side of the display area, and the second switch control module being disposed on a second side of the display area, for example, the first side may be a left side, and the second side may be a right side;

[0265] The first switch control module may include N first switch control units, and the second switch control module may include N second switch control units; the first switch control unit may include M first switch control circuits, and the second switch control unit may include M second switch control circuits;

[0266] The mth first switch control circuit in the nth first switch control unit controls the connection between the detection integrated circuit and the detection point included in the common electrode portion of the nth row and mth column under the control of the switch control signal provided by the nth first switch control terminal; the mth second switch control circuit in the nth second switch control unit controls the connection between the detection integrated circuit and the detection point included in the common electrode portion of the nth row and M+mth column under the control of the switch control signal provided by the nth second switch control terminal.

[0267] Optionally, the common electrode portion includes a plurality of portions sequentially arranged along the first direction;

[0268] The detection point of the common electrode portion of the nth row and the mth column is included in the ath portion of the common electrode portion of the nth row and the mth column;

[0269] The detection point of the common electrode portion of the nth row and the M+mth column is included in the bth part of the common electrode portion of the nth row and the M+mth column;

[0270] Both a and b are positive integers, and a is not equal to b.

[0271] In at least one embodiment of the present invention, the first direction may be a longitudinal direction, and the first direction may be substantially the same as an extending direction of the data line;

[0272] In medium and large-sized display products, since the size of the common electrode layer is large, the common electrode voltages connected to different positions of the common electrode layer are not uniform. Therefore, the detection points of the longitudinally symmetrical common electrode parts in the same row are located in different parts to enable uniform compensation.

[0273] The display panel described in at least one embodiment of the present invention further includes a first switch control signal generating module and a second switch control signal generating module disposed in the peripheral area; the first switch control signal generating module is disposed on a first side of the display area, and the second switch control signal generating module is disposed on a second side of the display area;

[0274] The first switch control signal generating module is electrically connected to the N first switch control terminals respectively, and is used to provide a valid switch control signal to the nth first switch control terminal in the nth detection phase included in the detection cycle;

[0275] The second switch control signal generating module is electrically connected to the N second switch control terminals respectively, and is used to provide a valid switch control signal to the nth second switch control terminal in the nth detection phase included in the detection cycle;

[0276] The detection integrated circuit is used to detect the potential of the detection points included in each common electrode part located in the nth row in the nth detection stage.

[0277] In a specific implementation, the display panel may further include a first switch control signal generating module and a second switch control signal generating module. The first switch control signal generating module provides a valid switch control signal to the nth first switch control terminal during the nth detection phase included in the detection cycle. The second switch control signal generating module provides a valid switch control signal to the nth second switch control terminal during the nth detection phase included in the detection cycle. The detection integrated circuit detects the potential of the detection points included in each common electrode portion located in the nth row during the nth detection phase included in the detection cycle.

[0278] In at least one embodiment of the present invention, the first switch control signal generating module is electrically connected to the N first switch control terminals respectively, and is used to provide a valid switch control signal to the nth first switch control terminal in the nth compensation phase included in the compensation cycle;

[0279] The second switch control signal generating module is electrically connected to the N second switch control terminals respectively, and is used to provide a valid switch control signal to the nth second switch control terminal in the nth compensation phase included in the compensation cycle;

[0280] The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode part in the nth compensation stage.

[0281] In a specific implementation, in the nth compensation stage included in the compensation cycle, the first switch control signal generating module provides a valid switch control signal to the nth first switch control terminal; the second switch control signal generating module provides a valid switch control signal to the nth second switch control terminal; and the detection integrated circuit transmits the corresponding compensation voltage signal to the corresponding common electrode part.

[0282] The display panel described in at least one embodiment of the present utility model further includes a voltage providing circuit and a plurality of columns of signal transmission lines;

[0283] The voltage supply circuit is electrically connected to the common electrode portion through the signal transmission line, and is used to provide the compensation voltage signal to the signal transmission line during a compensation phase.

[0284] In a specific implementation, a voltage providing circuit may provide a compensation voltage signal to the corresponding common electrode portion through a signal transmission line.

[0285] like Fig.13 As shown, at least one embodiment of the display panel described in the present utility model may include a common electrode layer;

[0286] The common electrode layer may include four rows and four columns of common electrode portions connected to each other: a first row and first column common electrode portion S11, a first row and second column common electrode portion S12, a first row and third column common electrode portion S13, a first row and fourth column common electrode portion S14, a second row and first column common electrode portion S21, a second row and second column common electrode portion S22, a second row and third column common electrode portion S23, a second row and fourth column common electrode portion S24, a third row and first column common electrode portion S31, a third row and second column common electrode portion S32, a third row and third column common electrode portion S33, a third row and fourth column common electrode portion S34, a fourth row and first column common electrode portion S41, a fourth row and second column common electrode portion S42, a fourth row and third column common electrode portion S43 and a fourth row and fourth column common electrode portion S44;

[0287] Each of the common electrode portions is arranged in the display area;

[0288] At least one embodiment of the display panel described in the present invention further includes a first switch control module KC1, a second switch control module KC2 and a detection integrated circuit 130 disposed in the peripheral area;

[0289] The first switch control module KC1 is disposed on the left side of the display area, and the second switch control module KC2 is disposed on the right side of the display area;

[0290] The detection cycle and the compensation cycle are set successively; the detection cycle includes the first detection stage, the second detection stage, the third detection stage and the fourth detection stage which are set successively; the compensation cycle includes the first compensation stage, the second compensation stage, the third compensation stage and the fourth compensation stage which are set successively;

[0291] The first switch control module KC1 is electrically connected to the first first switch control terminal K11, the second first switch control terminal K21, the third first switch control terminal K31, the fourth first switch control terminal K41, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the first row and first column common electrode portion S11, the first row and second column common electrode portion S12, the second row and first column common electrode portion S21, the second row and second column common electrode portion S22, the third row and first column common electrode portion S31, the third row and second column common electrode portion S32, the fourth row and first column common electrode portion S41, and the fourth row and second column common electrode portion S42 respectively;

[0292] The second switch control module KC2 is electrically connected to the first second switch control terminal K12, the second second switch control terminal K22, the third second switch control terminal K32, the fourth second switch control terminal K42, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the first row and third column common electrode portion S13, the first row and fourth column common electrode portion S14, the second row and third column common electrode portion S23, the second row and fourth column common electrode portion S24, the third row and third column common electrode portion S33, the third row and fourth column common electrode portion S34, the fourth row and third column common electrode portion S43 and the fourth row and fourth column common electrode portion S44 respectively;

[0293] In the first detection stage, under the control of the first first switch control signal provided by K11, the first switch control module KC1 controls the connection between TD1 and S11, and controls the connection between TD2 and S12; under the control of the first second switch control signal provided by K12, the second switch control module KC2 controls the connection between TD3 and S13, and controls the connection between TD4 and S14; the detection integrated circuit 130 detects the potential of S11, the potential of S12, the potential of S13 and the potential of S14; the detection integrated circuit 130 obtains the first row and first column compensation voltage signal according to the potential of S11 and the target common electrode voltage signal, obtains the first row and second column compensation voltage signal according to the potential of S12 and the target common electrode voltage signal, obtains the first row and third column compensation voltage signal according to the potential of S13 and the target common electrode voltage signal, and obtains the first row and fourth column compensation voltage signal according to the potential of S14 and the target common electrode voltage signal;

[0294] In the second detection stage, under the control of the second first switch control signal provided by K21, the first switch control module KC1 controls the connection between TD1 and S21, and controls the connection between TD2 and S22; under the control of the second second switch control signal provided by K22, the second switch control module KC2 controls the connection between TD3 and S23, and controls the connection between TD4 and S24; the detection integrated circuit 130 obtains the second row and first column compensation voltage signal according to the potential of S21 and the target common electrode voltage signal, obtains the second row and second column compensation voltage signal according to the potential of S22 and the target common electrode voltage signal, obtains the second row and third column compensation voltage signal according to the potential of S23 and the target common electrode voltage signal, and obtains the second row and fourth column compensation voltage signal according to the potential of S24 and the target common electrode voltage signal;

[0295] In the third detection stage, under the control of the third first switch control signal provided by K31, the first switch control module KC1 controls the connection between TD1 and S31, and controls the connection between TD2 and S32; under the control of the third second switch control signal provided by K32, the second switch control module KC2 controls the connection between TD3 and S33, and controls the connection between TD4 and S34; the detection integrated circuit 130 obtains the third row and first column compensation voltage signal according to the potential of S31 and the target common electrode voltage signal, obtains the third row and second column compensation voltage signal according to the potential of S32 and the target common electrode voltage signal, obtains the third row and third column compensation voltage signal according to the potential of S33 and the target common electrode voltage signal, and obtains the third row and fourth column compensation voltage signal according to the potential of S34 and the target common electrode voltage signal;

[0296] In the fourth detection stage, under the control of the fourth first switch control signal provided by K41, the first switch control module KC1 controls the connection between TD1 and S41, and controls the connection between TD2 and S42; under the control of the fourth second switch control signal provided by K42, the second switch control module KC2 controls the connection between TD3 and S43, and controls the connection between TD4 and S44; the detection integrated circuit 130 obtains the fourth row and first column compensation voltage signal according to the potential of S41 and the target common electrode voltage signal, obtains the fourth row and second column compensation voltage signal according to the potential of S42 and the target common electrode voltage signal, obtains the fourth row and third column compensation voltage signal according to the potential of S43 and the target common electrode voltage signal, and obtains the fourth row and fourth column compensation voltage signal according to the potential of S44 and the target common electrode voltage signal;

[0297] In the first compensation stage, under the control of the first first switch control signal provided by K11, the first switch control module KC1 controls the connection between TD1 and S11, and controls the connection between TD2 and S12; under the control of the second switch control signal provided by K12, the second switch control module KC2 controls the connection between TD3 and S13, and controls the connection between TD4 and S14; the detection integrated circuit 130 transmits the compensation voltage signal of the first row and the first column to S11, transmits the compensation voltage signal of the first row and the second column to S12, transmits the compensation voltage signal of the first row and the third column to S13, and transmits the compensation voltage signal of the first row and the fourth column to S14;

[0298] In the second compensation stage, under the control of the second first switch control signal provided by K21, the first switch control module KC1 controls the connection between TD1 and S21, and controls the connection between TD2 and S22; under the control of the second second switch control signal provided by K22, the second switch control module KC2 controls the connection between TD3 and S23, and controls the connection between TD4 and S24; the detection integrated circuit 130 transmits the compensation voltage signal of the first column of the second row to S21, transmits the compensation voltage signal of the second column of the second row to S22, transmits the compensation voltage signal of the third column of the second row to S23, and transmits the compensation voltage signal of the fourth column of the second row to S24;

[0299] In the third compensation stage, under the control of the third first switch control signal provided by K31, the first switch control module KC1 controls the connection between TD1 and S31, and controls the connection between TD2 and S32; under the control of the third second switch control signal provided by K32, the second switch control module KC2 controls the connection between TD3 and S33, and controls the connection between TD4 and S34; the detection integrated circuit 130 transmits the compensation voltage signal of the first column of the third row to S31, transmits the compensation voltage signal of the second column of the third row to S32, transmits the compensation voltage signal of the third column of the third row to S33, and transmits the compensation voltage signal of the fourth column of the third row to S34;

[0300] In the fourth compensation stage, under the control of the fourth first switch control signal provided by K41, the first switch control module KC1 controls the connection between TD1 and S41, and controls the connection between TD2 and S42; under the control of the fourth second switch control signal provided by K42, the second switch control module KC2 controls the connection between TD3 and S43, and controls the connection between TD4 and S44; the detection integrated circuit 130 transmits the compensation voltage signal of the first column of the fourth row to S41, transmits the compensation voltage signal of the second column of the fourth row to S42, transmits the compensation voltage signal of the third column of the fourth row to S43, and transmits the compensation voltage signal of the fourth column of the fourth row to S44.

[0301] like Fig.14 As shown, in Fig.13 Based on at least one embodiment of the display panel shown,

[0302] The first switch control module includes a first first switch control unit KD11, a second first switch control unit KD21, a third first switch control unit KD31 and a fourth first switch control unit KD41;

[0303] The second switch control module includes a first second switch control unit KD12, a second second switch control unit KD22, a third second switch control unit KD32 and a fourth second switch control unit KD42;

[0304] KD11 is electrically connected to the first first switch control terminal K11, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the first row and first column common electrode portion S11, and the first row and second column common electrode portion S12, respectively, and is used to control the connection between TD1 and S11, and the connection between TD2 and S12 under the control of the first first switch control signal provided by K11 in the first detection stage and the first compensation stage;

[0305] KD21 is electrically connected to the second first switch control terminal K21, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the second row and first column common electrode portion S21, and the second row and second column common electrode portion S22, respectively, and is used to control the connection between TD1 and S21, and the connection between TD2 and S22 under the control of the second first switch control signal provided by K21 in the second detection stage and the second compensation stage;

[0306] KD31 is electrically connected to the third first switch control terminal K31, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the third row and first column common electrode portion S31, and the third row and second column common electrode portion S32, respectively, and is used to control the connection between TD1 and S31, and the connection between TD2 and S32 under the control of the third first switch control signal provided by K31 in the third detection stage and the third compensation stage;

[0307] KD41 is electrically connected to the fourth first switch control terminal K41, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the fourth row and first column common electrode portion S41, and the fourth row and second column common electrode portion S42, respectively, and is used to control the connection between TD1 and S41, and control the connection between TD2 and S42 under the control of the fourth first switch control signal provided by K41 in the fourth detection stage and the fourth compensation stage;

[0308] KD12 is electrically connected to the first second switch control terminal K12, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the first row and third column common electrode portion S13 and the first row and fourth column common electrode portion S14 respectively, and is used to control the connection between TD3 and S13 and the connection between TD4 and S14 under the control of the first second switch control signal provided by K12 in the first detection stage and the first compensation stage;

[0309] KD22 is electrically connected to the second second switch control terminal K22, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the second row and third column common electrode portion S23, and the second row and fourth column common electrode portion S24, respectively, and is used to control the connection between TD3 and S23, and the connection between TD4 and S24 under the control of the second second switch control signal provided by K22 in the second detection stage and the second compensation stage;

[0310] KD32 is electrically connected to the third second switch control terminal K32, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the third row and third column common electrode portion S33 and the third row and fourth column common electrode portion S34 respectively, and is used to control the connection between TD3 and S33, and control the connection between TD4 and S34 under the control of the third second switch control signal provided by K32 in the third detection stage and the third compensation stage;

[0311] KD42 is electrically connected to the fourth second switch control terminal K42, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the fourth row and third column common electrode portion S43 and the fourth row and fourth column common electrode portion S44, respectively, and is used to control the connection between TD3 and S43, and the connection between TD4 and S44 under the control of the fourth second switch control signal provided by K42 in the fourth detection stage and the fourth compensation stage.

[0312] like Fig.15 As shown, in Fig.14 Based on at least one embodiment of the display panel shown, the first first switch control unit includes a first row and first column switch control circuit C11 and a first row and second column switch control circuit C12;

[0313] The second first switch control unit includes a second row and first column switch control circuit C21 and a second row and second column switch control circuit C22;

[0314] The third first switch control unit includes a third row and first column switch control circuit C31 and a third row and second column switch control circuit C32;

[0315] The fourth first switch control unit includes a switch control circuit C41 in the fourth row and the first column and a switch control circuit C42 in the fourth row and the second column;

[0316] C11 is electrically connected to the first first switch control terminal K11, the first terminal TD1 of the detection integrated circuit 130 and the first row and first column common electrode portion S11 respectively, and is used to control the connection between TD1 and S11 under the control of the first first switch control signal provided by K11 in the first detection stage and the first compensation stage;

[0317] C12 is electrically connected to the first first switch control terminal K11, the second terminal TD2 of the detection integrated circuit 130 and the first row and second column common electrode portion S12 respectively, and is used to control the connection between TD2 and S12 under the control of the first first switch control signal provided by K11 in the first detection stage and the first compensation stage;

[0318] C21 is electrically connected to the second first switch control terminal K21, the first terminal TD1 of the detection integrated circuit 130, and the second row and first column common electrode portion S21, respectively, and is used to control the connection between TD1 and S21 under the control of the second first switch control signal provided by K21 in the second detection stage and the second compensation stage;

[0319] C22 is electrically connected to the second first switch control terminal K21, the second terminal TD2 of the detection integrated circuit 130, and the second row and second column common electrode portion S22, respectively, and is used to control the connection between TD2 and S22 under the control of the second first switch control signal provided by K21 in the second detection stage and the second compensation stage;

[0320] C31 is electrically connected to the third first switch control terminal K31, the first terminal TD1 of the detection integrated circuit 130 and the third row and first column common electrode portion S31 respectively, and is used to control the connection between TD1 and S31 under the control of the third first switch control signal provided by K31 in the third detection stage and the third compensation stage;

[0321] C32 is electrically connected to the third first switch control terminal K31, the second terminal TD2 of the detection integrated circuit 130, and the third row and second column common electrode portion S32, respectively, and is used to control the connection between TD2 and S32 under the control of the third first switch control signal provided by K31 in the third detection stage and the third compensation stage;

[0322] C41 is electrically connected to the fourth first switch control terminal K41, the first terminal TD1 of the detection integrated circuit 130 and the fourth row and first column common electrode portion S41 respectively, and is used to control the connection between TD1 and S41 under the control of the fourth first switch control signal provided by K41 in the fourth detection stage and the fourth compensation stage;

[0323] C42 is electrically connected to the fourth first switch control terminal K41, the second terminal TD2 of the detection integrated circuit 130, and the fourth row and second column common electrode portion S42, respectively, and is used to control the connection between TD2 and S42 under the control of the fourth first switch control signal provided by K41 in the fourth detection stage and the fourth compensation stage;

[0324] The first second switch control unit includes a switch control circuit C13 in the first row and third column and a switch control circuit C14 in the first row and fourth column;

[0325] The second second switch control unit includes a second row and third column switch control circuit C23 and a second row and fourth column switch control circuit C24;

[0326] The third second switch control unit includes a switch control circuit C33 in the third row and the third column and a switch control circuit C34 in the third row and the fourth column;

[0327] The fourth second switch control unit includes a switch control circuit C43 in the fourth row and third column and a switch control circuit C44 in the fourth row and fourth column;

[0328] C13 is electrically connected to the first second switch control terminal K12, the third terminal TD3 of the detection integrated circuit 130 and the first row and third column common electrode portion S13 respectively, and is used to control the connection between TD3 and S13 under the control of the first second switch control signal provided by K12 in the first detection stage and the first compensation stage;

[0329] C14 is electrically connected to the first second switch control terminal K12, the fourth terminal TD4 of the detection integrated circuit 130 and the first row and fourth column common electrode portion S14 respectively, and is used to control the connection between TD4 and S14 under the control of the first second switch control signal provided by K12 in the first detection stage and the first compensation stage;

[0330] C23 is electrically connected to the second second switch control terminal K22, the third terminal TD3 of the detection integrated circuit 130 and the second row and third column common electrode portion S23 respectively, and is used to control the connection between TD3 and S23 under the control of the second second switch control signal provided by K22 in the second detection stage and the second compensation stage;

[0331] C24 is electrically connected to the second second switch control terminal K22, the fourth terminal TD4 of the detection integrated circuit 130 and the second row and fourth column common electrode portion S24 respectively, and is used to control the connection between TD4 and S24 under the control of the second second switch control signal provided by K22 in the second detection stage and the second compensation stage;

[0332] C33 is electrically connected to the third second switch control terminal K32, the third terminal TD3 of the detection integrated circuit 130 and the third row and third column common electrode portion S33 respectively, and is used to control the connection between TD3 and S33 under the control of the third second switch control signal provided by K32 in the third detection stage and the third compensation stage;

[0333] C34 is electrically connected to the third second switch control terminal K32, the fourth terminal TD4 of the detection integrated circuit 130 and the third row and fourth column common electrode portion S34 respectively, and is used to control the connection between TD4 and S34 under the control of the third second switch control signal provided by K32 in the third detection stage and the third compensation stage;

[0334] C43 is electrically connected to the fourth second switch control terminal K42, the third terminal TD3 of the detection integrated circuit 130 and the fourth row and third column common electrode portion S43 respectively, and is used to control the connection between TD3 and S43 under the control of the fourth second switch control signal provided by K42 in the fourth detection stage and the fourth compensation stage;

[0335] C44 is electrically connected to the fourth second switch control terminal K42, the fourth terminal TD4 of the detection integrated circuit 130 and the fourth row and fourth column common electrode portion S44 respectively, and is used to control the connection between TD4 and S44 under the control of the fourth second switch control signal provided by K42 in the fourth detection stage and the fourth compensation stage.

[0336] like Fig.16 As shown, in Fig.15 Based on at least one embodiment of the display panel shown,

[0337] C11 includes a first first switch transistor MK11, C12 includes a first second switch transistor MK12, C13 includes a first third switch transistor MK13, and C14 includes a first fourth switch transistor MK14;

[0338] C21 includes a second first switch transistor MK21, C22 includes a second second switch transistor MK22, C23 includes a second third switch transistor MK23, and C14 includes a second fourth switch transistor MK24;

[0339] C31 includes a third first switch transistor MK31, C32 includes a third second switch transistor MK32, C33 includes a third third switch transistor MK33, and C34 includes a third fourth switch transistor MK34;

[0340] C41 includes a fourth first switch transistor MK41, C42 includes a fourth second switch transistor MK42, C43 includes a fourth third switch transistor MK43, and C44 includes a fourth fourth switch transistor MK44;

[0341] The gate of MK11 is electrically connected to the first first switch control terminal K11, the drain of MK11 is electrically connected to the first terminal TD1 of the detection integrated circuit 130, and the source of MK11 is electrically connected to the first row and first column common electrode portion S11;

[0342] The gate of MK12 is electrically connected to the first first switch control terminal K11, the drain of MK12 is electrically connected to the second terminal TD2 of the detection integrated circuit 130, and the source of MK12 is electrically connected to the first row and second column common electrode portion S12;

[0343] The gate of MK13 is electrically connected to the first second switch control terminal K12, the drain of MK13 is electrically connected to the third terminal TD3 of the detection integrated circuit 130, and the source of MK13 is electrically connected to the first row and third column common electrode portion S13;

[0344] The gate of MK14 is electrically connected to the first second switch control terminal K12, the drain of MK14 is electrically connected to the fourth terminal TD4 of the detection integrated circuit 130, and the source of MK12 is electrically connected to the first row and fourth column common electrode portion S14;

[0345] The gate of MK21 is electrically connected to the second first switch control terminal K21, the drain of MK21 is electrically connected to the first terminal TD1 of the detection integrated circuit 130, and the source of MK21 is electrically connected to the second row and first column common electrode portion S21;

[0346] The gate of MK22 is electrically connected to the second first switch control terminal K21, the drain of MK22 is electrically connected to the second terminal TD2 of the detection integrated circuit 130, and the source of MK22 is electrically connected to the second row and second column common electrode portion S22;

[0347] The gate of MK23 is electrically connected to the second second switch control terminal K22, the drain of MK23 is electrically connected to the third terminal TD3 of the detection integrated circuit 130, and the source of MK23 is electrically connected to the second row and third column common electrode portion S23;

[0348] The gate of MK24 is electrically connected to the second second switch control terminal K22, the drain of MK24 is electrically connected to the fourth terminal TD4 of the detection integrated circuit 130, and the source of MK24 is electrically connected to the second row and fourth column common electrode portion S24;

[0349] The gate of MK31 is electrically connected to the third first switch control terminal K31, the drain of MK31 is electrically connected to the first terminal TD1 of the detection integrated circuit 130, and the source of MK31 is electrically connected to the third row and first column common electrode portion S31;

[0350] The gate of MK32 is electrically connected to the third first switch control terminal K31, the drain of MK32 is electrically connected to the second terminal TD2 of the detection integrated circuit 130, and the source of MK32 is electrically connected to the third row and second column common electrode portion S32;

[0351] The gate of MK33 is electrically connected to the third second switch control terminal K32, the drain of MK33 is electrically connected to the third terminal TD3 of the detection integrated circuit 130, and the source of MK33 is electrically connected to the third row and third column common electrode portion S33;

[0352] The gate of MK34 is electrically connected to the third second switch control terminal K32, the drain of MK34 is electrically connected to the fourth terminal TD4 of the detection integrated circuit 130, and the source of MK34 is electrically connected to the third row and fourth column common electrode portion S34;

[0353] The gate of MK41 is electrically connected to the fourth first switch control terminal K41, the drain of MK42 is electrically connected to the second terminal TD2 of the detection integrated circuit 130, and the source of MK42 is electrically connected to the fourth row and second column common electrode portion S42;

[0354] The gate of MK43 is electrically connected to the fourth second switch control terminal K42, the drain of MK43 is electrically connected to the third terminal TD3 of the detection integrated circuit 130, and the source of MK43 is electrically connected to the fourth row and third column common electrode portion S43;

[0355] The gate of MK44 is electrically connected to the fourth second switch control terminal K32, the drain of MK44 is electrically connected to the fourth terminal TD4 of the detection integrated circuit 130, and the source of MK44 is electrically connected to the fourth row and fourth column common electrode portion S44;

[0356] exist Fig.16 In at least one embodiment of the display panel shown, all transistors are n-type transistors.

[0357] The utility model Fig.16In at least one embodiment of the display panel shown, when working, a detection period and a compensation period are successively arranged, the detection period includes a first detection stage, a second detection stage, a third detection stage and a fourth detection stage which are successively arranged; and the compensation period includes a first compensation stage, a second compensation stage, a third compensation stage and a fourth compensation stage which are successively arranged;

[0358] In the first detection stage and the first compensation stage, K11 provides a high voltage signal, MK11 and MK12 are turned on, TD1 is connected to S11, and TD2 is connected to S12; K12 provides a high voltage signal, MK13 and MK14 are turned on, TD3 is connected to S13, and TD4 is connected to S14;

[0359] In the second detection stage and the second compensation stage, K21 provides a high voltage signal, MK21 and MK22 are turned on, TD1 is connected to S21, and TD2 is connected to S22; K22 provides a high voltage signal, MK23 and MK24 are turned on, TD3 is connected to S23, and TD4 is connected to S24;

[0360] In the third detection stage and the third compensation stage, K31 provides a high voltage signal, MK31 and MK32 are turned on, TD1 is connected to S31, and TD2 is connected to S32; K32 provides a high voltage signal, MK33 and MK34 are turned on, TD3 is connected to S33, and TD4 is connected to S34;

[0361] In the fourth detection stage and the fourth compensation stage, K41 provides a high voltage signal, MK41 and MK42 are turned on, TD1 is connected to S41, and TD2 is connected to S42; K42 provides a high voltage signal, MK43 and MK44 are turned on, TD3 is connected to S43, and TD4 is connected to S44.

[0362] like Fig.17 As shown, in Fig.16 Based on at least one embodiment of the display panel shown, S11 includes the first row and first column detection point J11, S12 includes the first row and second column detection point J12, S13 includes the first row and third column detection point J13, and S14 includes the first row and fourth column detection point J14;

[0363] S21 includes the second row and first column detection point J21, S22 includes the second row and second column detection point J22, S23 includes the second row and third column detection point J23, and S24 includes the second row and fourth column detection point J24;

[0364] S31 includes the third row and first column detection point J31, S32 includes the third row and second column detection point J12, S33 includes the third row and third column detection point J33, and S34 includes the third row and fourth column detection point J34;

[0365] S41 includes the fourth row and first column detection point J41, S42 includes the fourth row and second column detection point J42, S43 includes the fourth row and third column detection point J43, and S44 includes the fourth row and fourth column detection point J44;

[0366] Each common electrode portion is electrically connected to a corresponding switch transistor through a corresponding detection point;

[0367] like Fig.18 As shown, each common electrode portion can be evenly divided into three parts along the vertical direction, which are respectively a first part B1, a second part B2, and a third part B3 from top to bottom;

[0368] like Fig.17 As shown, J11 is located in the first part included by S11, J12 is located in the second part included by S12, J13 is located in the third part included by S13, and J14 is located in the second part included by S14;

[0369] J21 is located in the first part included by S21, J22 is located in the second part included by S22, J23 is located in the third part included by S23, and J24 is located in the second part included by S24;

[0370] J31 is located in the first part included by S31, J32 is located in the second part included by S32, J33 is located in the third part included by S33, and J14 is located in the second part included by S34;

[0371] J41 is located at the first part included in S41, J42 is located at the second part included in S42, J43 is located at the third part included in S43, and J44 is located at the second part included in S44.

[0372] In at least one embodiment of the present invention, S11 and S14 are longitudinally symmetrical, S12 and S13 are longitudinally symmetrical, J11 is included in the first part of S11, J14 is included in the second part of S14, and the first part and the second part are different; J12 is included in the second part of S12, J13 is included in the third part of S13, and the second part and the third part are different;

[0373] S21 and S24 are longitudinally symmetrical, S22 and S23 are longitudinally symmetrical, J21 is included in the first part of S21, J24 is included in the second part of S24, and the first part and the second part are different; J22 is included in the second part of S22, J23 is included in the third part of S23, and the second part and the third part are different;

[0374] S31 and S34 are longitudinally symmetrical, S32 and S33 are longitudinally symmetrical, J31 is included in the first part of S31, J34 is included in the second part of S34, and the first part and the second part are different; J32 is included in the second part of S32, J33 is included in the third part of S33, and the second part and the third part are different;

[0375] S41 and S44 are longitudinally symmetrical, S42 and S43 are longitudinally symmetrical, J41 is included in the first part of S41, J44 is included in the second part of S44, and the first part and the second part are different; J42 is included in the second part of S42, J43 is included in the third part of S43, and the second part and the third part are different.

[0376] like Fig.19 As shown, the display panel described in at least one embodiment of the utility model may further include a first common electrode line CL1, a second common electrode line CL2, a third common electrode line CL3, a fourth common electrode line CL4, a fifth common electrode line CL5, a sixth common electrode line CL6, a seventh common electrode line CL7, an eighth common electrode line CL8, a ninth common electrode line CL9, a tenth common electrode line CL10, an eleventh common electrode line CL11, a twelfth common electrode line CL12, a thirteenth common electrode line CL13, a fourteenth common electrode line CL14, a fifteenth common electrode line CL15 and a sixteenth common electrode line CL16;

[0377] The first common electrode line CL1, the second common electrode line CL2, the third common electrode line CL3, the fourth common electrode line CL4, the fifth common electrode line CL5, the sixth common electrode line CL6, the seventh common electrode line CL7, the eighth common electrode line CL8, the ninth common electrode line CL9, the tenth common electrode line CL10, the eleventh common electrode line CL11, the twelfth common electrode line CL12, the thirteenth common electrode line CL13, the fourteenth common electrode line CL14, the fifteenth common electrode line CL15 and the sixteenth common electrode line CL16 extend in the horizontal direction;

[0378] Each common electrode line can be used to provide a common electrode voltage for the common electrode layer;

[0379] Each common electrode line may be provided on the same layer as a connection line between each switch transistor and the common electrode portion.

[0380] exist Fig.16 In at least one embodiment of the display panel shown, a voltage supply circuit disposed below the display area may provide a compensation voltage signal to each common electrode portion through a plurality of vertically extending signal transmission lines.

[0381] In specific implementation, Fig.16In at least one embodiment of the display panel shown, switching transistors may not be provided, and the detection integrated circuit is directly electrically connected to the common electrode parts through the wiring arranged in the peripheral area to perform common electrode voltage detection; and the voltage providing circuit arranged below the display area provides a compensation voltage signal to each common electrode part through a plurality of vertically extending signal transmission lines.

[0382] like Fig. 20 As shown, in Fig.16 Based on at least one embodiment of the display panel shown, the display panel described in at least one embodiment of the present invention further includes a first switch control signal generating module 201 and a second switch control signal generating module 202;

[0383] The first switch control signal generating module 201 and the second switch control signal generating module 202 are disposed in the peripheral area;

[0384] The first switch control signal generating module 201 is disposed on the left side of the display area, and the second switch control signal generating module 202 is disposed on the right side of the display area;

[0385] The first switch control signal generating module 201 is electrically connected to K11, K21, K31 and K41 respectively, and is used to provide a first first switch control signal for K11, a second first switch control signal for K21, a third first switch control signal for K31, and a fourth first switch control signal for K41;

[0386] The second switch control signal generating module 202 is electrically connected to K12, K22, K32 and K42 respectively, and is used to provide a first second switch control signal for K12, a second second switch control signal for K22, a third second switch control signal for K32, and a fourth second switch control signal for K42.

[0387] The display device described in the embodiment of the present invention includes the above-mentioned display panel.

[0388] The above is a preferred embodiment of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A display panel, characterized in that: It includes a plurality of rows and columns of pixel circuits; the pixel circuit includes a data writing circuit; The data writing circuit is electrically connected to the scanning end and the data line respectively, and is used to access the data voltage provided by the data line under the control of the scanning signal provided by the scanning end; The transistor included in the data writing circuit includes a first gate and a second gate, and the scanning end includes a first scanning end and a second scanning end; The first gate of the transistor included in the data writing circuit is electrically connected to the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected to the second scanning end; The first gate is a top gate, and the second gate is a bottom gate; or, the first gate is a bottom gate, and the second gate is a top gate.

2. The display panel according to claim 1, wherein: When the potential of the first scanning signal provided by the first scanning end decreases, the potential of the second scanning signal provided by the second scanning end increases; When the potential of the first scanning signal provided by the first scanning end increases, the potential of the second scanning signal provided by the second scanning end decreases.

3. The display panel according to claim 1, wherein: Also includes a driving module; the driving module includes a multi-stage driving circuit; The driving circuit includes a first scanning signal output terminal and a second scanning signal output terminal; The first scanning signal output terminal of the n-th level driving circuit included in the driving module is electrically connected to the first scanning terminal electrically connected to the data writing circuit in the n-th row pixel circuit; The second scanning signal output terminal of the n-th stage driving circuit included in the driving module is electrically connected to the second scanning terminal electrically connected to the data writing circuit in the n-th row pixel circuit.

4. The display panel according to claim 3, wherein: The driving circuit includes a first node control circuit, a second node control circuit, a first scan signal output circuit and a second scan signal output circuit; The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The first scanning signal output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the first voltage terminal and the first scanning signal output terminal respectively, and is used to control the first scanning signal output terminal to be connected to the output clock signal terminal under the control of the potential of the first node, and to control the first scanning signal output terminal to be connected to the first voltage terminal under the control of the potential of the second node; The second scanning signal output circuit is electrically connected to the first node, the first scanning signal output terminal, the second scanning signal output terminal, the first voltage terminal and the second voltage terminal respectively, and is used to control the second scanning signal output terminal to be connected to the second voltage terminal under the control of the potential of the first node, and to control the second scanning signal output terminal to be connected to the first voltage terminal under the control of the first scanning signal provided by the first scanning signal output terminal; A voltage value of a first voltage signal provided by the first voltage terminal is smaller than a voltage value of a second voltage signal provided by the second voltage terminal.

5. The display panel according to claim 4, wherein: The first scanning signal output circuit includes a first output transistor and a second output transistor; The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output clock signal terminal, and the second electrode of the first output transistor is electrically connected to the first scan signal output terminal; A gate of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the first scan signal output terminal, and a second electrode of the second output transistor is electrically connected to the first voltage terminal.

6. The display panel according to claim 4, wherein: The second scanning signal output circuit includes a third output transistor and a fourth output transistor; The gate of the third output transistor is electrically connected to the first node, the first electrode of the third output transistor is electrically connected to the second scanning signal output terminal, and the second electrode of the third output transistor is electrically connected to the second voltage terminal; A gate of the fourth output transistor is electrically connected to the first scan signal output terminal, a first electrode of the fourth output transistor is electrically connected to the second scan signal output terminal, and a second electrode of the fourth output transistor is electrically connected to the first voltage terminal.

7. The display panel according to any one of claims 1 to 6, characterized in that: It also includes a substrate; the pixel circuit is arranged on the substrate; The orthographic projection of the top gate of the transistor included in the data writing circuit on the substrate does not overlap with the orthographic projection of the connection electrode of the transistor included in the data writing circuit on the substrate; The connection electrode of the transistor included in the data write circuit includes a source of the transistor included in the data write circuit and a drain of the transistor included in the data write circuit.

8. The display panel according to any one of claims 1 to 6, characterized in that: It also includes a substrate; the pixel circuit is arranged on the substrate; An overlapping area between an orthographic projection of a top gate of a transistor included in the data writing circuit on the substrate and an orthographic projection of a connection electrode of the transistor included in the data writing circuit on the substrate is a first area; An overlapping area between an orthographic projection of a bottom gate of a transistor included in the data writing circuit on the substrate and an orthographic projection of a connection electrode of the transistor included in the data writing circuit on the substrate is a second area; The first area is smaller than the second area; The connection electrode of the transistor included in the data write circuit includes a source of the transistor included in the data write circuit and a drain of the transistor included in the data write circuit.

9. The display panel according to any one of claims 1 to 6, characterized in that: It also includes a substrate, a light-shielding metal layer, a semiconductor layer and a gate metal layer; The light-shielding metal layer, the semiconductor layer and the gate metal layer are arranged in sequence along a direction away from the substrate; The semiconductor layer includes a channel of a transistor included in the data writing circuit; the orthographic projection of the light-shielding metal layer on the substrate covers the orthographic projection of the channel on the substrate; The light-shielding metal layer includes the bottom gate, and the gate metal layer includes the top gate.

10. The display panel according to any one of claims 1 to 6, characterized in that: It also includes a plurality of rows and columns of touch electrode blocks, a plurality of columns of signal transmission lines and a voltage supply circuit; the plurality of rows and columns of touch electrode blocks are independent of each other; The voltage supply circuit is electrically connected to the first end of the signal transmission line, the signal transmission line includes a connection point, and the connection point is electrically connected to the touch electrode block; The voltage supply circuit is used to provide a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line in the display stage.

11. The display panel according to claim 2, wherein: Also includes a common electrode layer and a detection integrated circuit; The common electrode layer includes a plurality of common electrode portions, and the plurality of common electrode portions are interconnected; The common electrode portion includes at least one detection point; The detection integrated circuit is electrically connected to the common electrode portion through the detection point, and is used to detect the potential of the detection point during the detection phase; the detection integrated circuit is also used to obtain a corresponding compensation voltage signal based on the potential of the detection point and the target common electrode voltage signal.

12. The display panel according to claim 11, wherein: The detection point is directly electrically connected to the detection integrated circuit.

13. The display panel according to claim 12, wherein: The common electrode layer includes multiple rows and columns of common electrode parts; the display panel includes a display area and a peripheral area, and the pixel circuit is arranged in the display area; The detection point extends to a peripheral area through a first connection line extending along a row direction, and the first connection line is electrically connected to the detection integrated circuit through a second connection line arranged in the peripheral area.

14. The display panel according to claim 11, wherein: Also included is a switch control module, the switch control module includes a plurality of switch control circuits; The control end of the switch control circuit is electrically connected to the corresponding switch control end, the first end of the switch control circuit is electrically connected to the detection integrated circuit, the second end of the switch control circuit is electrically connected to the detection point, and the switch control circuit is used to control the connection between the detection integrated circuit and the detection point in the corresponding detection phase included in the detection cycle; The detection integrated circuit is used to detect the potential of the detection point in the corresponding detection stage.

15. The display panel according to claim 14, wherein: The switch control circuit is used to control the connection between the detection integrated circuit and the detection point during the corresponding compensation phase included in the compensation cycle; The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode portion through the switch control circuit during the corresponding compensation stage.

16. The display panel according to claim 11, wherein: The common electrode layer includes N rows and 2M columns of common electrode parts; N and M are positive integers; the display panel also includes a first switch control module and a second switch control module; the first switch control module includes N first switch control units, and the second switch control module includes N second switch control units; The first switch control unit includes M first switch control circuits, and the second switch control unit includes M second switch control circuits; The display panel includes a display area and a peripheral area, the pixel circuit is arranged in the display area, and the first switch control module and the second switch control module are arranged in the peripheral area; the first switch control module is arranged on a first side of the display area, and the second switch control module is arranged on a second side of the display area, and the first side and the second side are opposite sides; The mth first switch control circuit in the nth first switch control unit is electrically connected to the nth first switch control terminal, the detection integrated circuit and the common electrode portion in the nth row and the mth column, respectively, and is used to control the detection integrated circuit to be connected to the detection point included in the common electrode portion in the nth row and the mth column under the control of the switch control signal provided by the nth first switch control terminal; The mth second switch control circuit in the nth second switch control unit is electrically connected to the nth second switch control terminal, the detection integrated circuit and the common electrode portion of the nth row and the M+mth column, respectively, and is used to control the detection integrated circuit to be connected to the detection point included in the common electrode portion of the nth row and the M+mth column under the control of the switch control signal provided by the nth second switch control terminal; n is a positive integer less than or equal to N; m is a positive integer less than or equal to M.

17. The display panel according to claim 16, wherein: The common electrode portion includes a plurality of portions arranged sequentially along a first direction; The detection point of the common electrode portion of the nth row and the mth column is included in the ath portion of the common electrode portion of the nth row and the mth column; The detection point of the common electrode portion of the nth row and the M+mth column is included in the bth part of the common electrode portion of the nth row and the M+mth column; Both a and b are positive integers, and a is not equal to b.

18. The display panel according to claim 16, wherein: It also includes a first switch control signal generating module and a second switch control signal generating module disposed in the peripheral area; the first switch control signal generating module is disposed on a first side of the display area, and the second switch control signal generating module is disposed on a second side of the display area; The first switch control signal generating module is electrically connected to the N first switch control terminals respectively, and is used to provide a valid switch control signal to the nth first switch control terminal in the nth detection phase included in the detection cycle; The second switch control signal generating module is electrically connected to the N second switch control terminals respectively, and is used to provide a valid switch control signal to the nth second switch control terminal in the nth detection phase included in the detection cycle; The detection integrated circuit is used to detect the potential of the detection points included in each common electrode part located in the nth row in the nth detection stage.

19. The display panel according to claim 18, wherein: The first switch control signal generating module is electrically connected to the N first switch control terminals respectively, and is used to provide a valid switch control signal to the nth first switch control terminal in the nth compensation phase included in the compensation cycle; The second switch control signal generating module is electrically connected to the N second switch control terminals respectively, and is used to provide a valid switch control signal to the nth second switch control terminal in the nth compensation phase included in the compensation cycle; The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode part in the nth compensation stage.

20. The display panel according to claim 12, 13, 14, 16 or 17, characterized in that: Also included is a voltage supply circuit and a plurality of columns of signal transmission lines; The voltage supply circuit is electrically connected to the common electrode portion through the signal transmission line, and is used to provide the compensation voltage signal to the signal transmission line during a compensation phase.

21. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 1 to 20.

Images