Coding and decoding device and equipment

Abstract

The utility model provides a coding and decoding device and equipment, which are applied to communication equipment, and the coding and decoding device comprises a digital logic circuit and a processor, the digital logic circuit is used for carrying out format conversion between a physical layer transmission signal and a processor interface signal; and the processor is used for decoding a data link layer protocol based on the processor interface signal and encoding the data link layer protocol based on the received user data. According to the device, signal conversion is carried out through the digital logic circuit, then coding and decoding are carried out through the processor, full-duplex communication can be achieved, and the hardware cost can be effectively reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of communication, and more specifically to a coding and decoding device and equipment. Background Art

[0002] FT3 is the transmission frame format of the data link layer defined in the IEC60044-8 specification. FT3 data transmission adopts serial transmission, which can be transmitted in asynchronous mode or synchronous mode. FT3 allows the use of both optical and electrical interfaces, and the communication rate can reach up to 2.5Mbit / s.

[0003] In the existing communication equipment for implementing FT3 frame format encoding and decoding, the encoding and decoding device can only perform simplex communication, not duplex communication; and the encoding and decoding device uses a field-programmable gate array (FPGA) to perform encoding and decoding of FT3 frames and conversion of corresponding physical layer transmission signals, so a large-scale FPGA built-in logic unit is required to implement it, resulting in a high cost of the communication equipment. Utility Model Content

[0004] The present invention is proposed in view of the above problems. The present invention provides a coding and decoding device and equipment, which can realize duplex communication and effectively reduce hardware costs.

[0005] The first aspect of the utility model provides a coding and decoding device, which is applied to a communication device, and the coding and decoding device includes a digital logic circuit and a processor;

[0006] The digital logic circuit is used to perform format conversion between physical layer transmission signals and processor interface signals;

[0007] The processor is used to decode the data link layer protocol based on the processor interface signal, and to encode the data link layer protocol based on the received user data.

[0008] In one embodiment of the present utility model, the processor interface signal is an SPI signal, and the digital logic circuit is electrically connected to the processor via a first SPI bus and a second SPI bus;

[0009] The first SPI bus includes a clock output signal line, an SPI data output signal line, a chip select output signal line, a receiving reset control signal line and a first clock input signal line;

[0010] The second SPI bus includes an SPI data input signal line, a chip select input signal line and a second clock input signal line.

[0011] In one embodiment of the present utility model, the physical layer transmission signal is an FT3 signal;

[0012] The digital logic circuit is used to perform signal conversion on the received first FT3 signal to obtain a first SPI signal, and send the first SPI signal to the processor;

[0013] The digital logic circuit is also used to perform signal conversion on the second SPI signal received from the processor to obtain a second FT3 signal.

[0014] In one embodiment of the utility model, the digital logic circuit includes an SPI to FT3 logic circuit and an FT3 to SPI logic circuit;

[0015] The FT3 to SPI logic circuit acts as a host and sends the first SPI signal through a first SPI bus;

[0016] The SPI to FT3 logic circuit acts as a slave and receives the second SPI signal through a second SPI bus.

[0017] In one embodiment of the utility model, the FT3 to SPI logic circuit includes a clock frequency division circuit, an SPI host startup control circuit, and a bit synchronization decoding circuit;

[0018] The SPI host startup control circuit has a first input end and a second input end, the bit synchronization decoding circuit has a first output end and a second output end, the output end of the clock frequency division circuit is electrically connected to the first input end of the SPI host startup control circuit, and the second output end of the bit synchronization decoding circuit is electrically connected to the second input end of the SPI host startup control circuit.

[0019] In one embodiment of the utility model, the FT3 to SPI logic circuit also includes an input signal synchronization circuit, the input signal synchronization circuit has a first output end and a second output end, the bit synchronization decoding circuit has a first input end and a second input end, the first output end of the input signal synchronization circuit is electrically connected to the first input end of the bit synchronization decoding circuit and the input end of the clock frequency division circuit, and the second output end of the input signal synchronization circuit is electrically connected to the second input end of the bit synchronization decoding circuit.

[0020] In one embodiment of the utility model, the input signal synchronization circuit includes a first asynchronous clear D flip-flop and a second asynchronous clear D flip-flop, the input end of the first asynchronous clear D flip-flop is electrically connected to the receive reset control signal line, and the input end of the second asynchronous clear D flip-flop is electrically connected to the clock access port of the first asynchronous clear D flip-flop.

[0021] In one embodiment of the utility model, the SPI host startup control circuit includes a third asynchronous clear D flip-flop and a first OR gate operator, the first OR gate operator has a first input end and a second input end, the first input end of the first OR gate operator is electrically connected to the output end of the clock frequency division circuit, and the second input end of the first OR gate operator is electrically connected to the output end of the third asynchronous clear D flip-flop.

[0022] In one embodiment of the utility model, the bit synchronization decoding circuit includes a fourth asynchronous reset D flip-flop, a first AND gate operator, a first counter, a second OR gate operator and a first XNOR gate operator; the first AND gate operator, the first counter, the second OR gate operator and the first XNOR gate operator all have a first input terminal and a second input terminal; the first counter and the fourth asynchronous reset D flip-flop have a first output terminal and a second output terminal;

[0023] The second input terminal of the first XNOR gate operator is electrically connected to the second output terminal of the fourth asynchronous reset D flip-flop, and the output terminal of the first XNOR gate operator is electrically connected to the first input terminal of the second OR gate operator;

[0024] The second input end of the second OR gate operator is electrically connected to the output end of the first AND gate operator, and the output end of the second OR gate operator is electrically connected to the second input end of the first counter;

[0025] The first output terminal of the first counter is electrically connected to the first input terminal of the first AND gate operator, and the second output terminal of the first counter is electrically connected to the second input terminal of the first AND gate operator;

[0026] The output terminal of the first AND gate operator is also electrically connected to the second input terminal of the fourth asynchronous reset D flip-flop;

[0027] The second output terminal of the fourth asynchronous reset D flip-flop is also electrically connected to the first input terminal of the fourth asynchronous reset D flip-flop.

[0028] In one embodiment of the utility model, the SPI to FT3 logic circuit includes a clock 4-frequency division circuit, a logic operation circuit and a synchronization circuit;

[0029] The logic operation circuit comprises a first input terminal, a second input terminal and a third input terminal, wherein the first input terminal is electrically connected to the output terminal of the clock 4-frequency division circuit, the second input terminal is connected to the SPI data input signal line, and the third input terminal is connected to the chip select input signal line; the output terminal of the logic operation circuit is electrically connected to the input terminal of the synchronization circuit;

[0030] The input end of the clock frequency divider by 4 circuit is connected to the second clock input signal line;

[0031] The synchronization circuit further has a synchronization signal input port, and the synchronization signal input port is connected to the second clock input signal line.

[0032] In one embodiment of the present invention, the clock divide-by-4 circuit includes a first asynchronous reset D flip-flop and a second asynchronous reset D flip-flop connected in cascade.

[0033] In one embodiment of the utility model, the logic operation circuit includes a third OR gate operator, a fourth OR gate operator, a second AND gate operator, a third AND gate operator, a first NOT gate operator and a second NOT gate operator; the third OR gate operator, the fourth OR gate operator, the second AND gate operator and the third AND gate operator all have a first input terminal and a second input terminal;

[0034] The first input end of the third OR gate operator is connected to the SPI data input signal line, and the second input end is connected to the chip select input signal line;

[0035] The output end of the third OR gate operator is electrically connected to the second input end of the second AND gate operator and the input end of the first NOT gate operator respectively;

[0036] The output end of the clock 4-frequency divider circuit is electrically connected to the first input end of the second AND gate operator and the input end of the second NOT gate operator respectively;

[0037] The output end of the first NOT gate operator is electrically connected to the first input end of the third AND gate operator, and the output ends of the second NOT gate operator are electrically connected to the second input ends of the third AND gate operator respectively;

[0038] The output end of the second AND gate operator is electrically connected to the first input end of the fourth OR gate operator, and the output end of the third AND gate operator is electrically connected to the second input end of the fourth OR gate operator;

[0039] The output end of the fourth OR gate operator is electrically connected to the input end of the synchronization circuit.

[0040] In one embodiment of the utility model, the data link layer protocol includes a first preset protocol, and the processor is used to extract a first frame data in a first preset protocol frame format from a received first SPI signal, decode the first frame data to obtain first user data; and encode the second user data to obtain a second frame data in the first preset protocol frame format, and send the second frame data to the digital logic circuit via a second SPI signal.

[0041] In one embodiment of the utility model, the processor is also used to perform protocol encapsulation on the first user data to obtain third frame data in a second preset protocol frame format; and decode the received fourth frame data to obtain the second user data; wherein the frame format of the fourth frame data is the second preset protocol frame format.

[0042] A second aspect of the present invention provides a coding and decoding device, wherein the communication device comprises the above coding and decoding device.

[0043] In one embodiment of the present utility model, the communication device further comprises a transmission interface circuit and a user data transceiver circuit, and the encoding and decoding device is electrically connected to the transmission interface circuit and the user data transceiver circuit respectively;

[0044] The transmission interface circuit is used to transmit the physical layer transmission signal received and sent by the encoding and decoding device through a transmission line;

[0045] The user data transceiver circuit is used to send the data decoded by the encoding and decoding device through a preset communication interface, receive the data to be encoded through the preset communication interface, and send the data to be encoded to the encoding and decoding device.

[0046] In one embodiment of the present invention, the transmission line is an optical fiber line, and the transmission interface circuit includes a photoelectric conversion circuit and an electro-optical conversion circuit.

[0047] In one embodiment of the present utility model, the communication interface includes any one of the following interfaces: a CAN interface, an RS485 interface, an Ethernet interface, a WIFI interface, and a Bluetooth interface.

[0048] A third aspect of the present invention provides an electronic device, wherein the electronic device comprises the above-mentioned encoding and decoding device.

[0049] The encoding and decoding device of the embodiment of the utility model performs signal conversion through a digital logic circuit and then performs encoding and decoding through a processor, thereby realizing full-duplex communication of signals and effectively reducing hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other purposes, features and advantages of the present invention will become more apparent by describing the embodiments of the present invention in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0051] Figure 1is a schematic structural diagram of a coding and decoding device according to an embodiment of the utility model;

[0052] Figure 2 is a schematic structural diagram of a digital logic circuit according to an embodiment of the utility model;

[0053] Figure 3 It is a schematic structural diagram of an FT3 to SPI logic circuit according to an embodiment of the utility model;

[0054] Figure 4 This is a timing simulation example diagram of an FT3 to SPI logic circuit according to an embodiment of the utility model;

[0055] Figure 5 is a schematic structural diagram of an SPI to FT3 logic circuit according to an embodiment of the utility model;

[0056] Figure 6 is a schematic structural diagram of a coding and decoding device according to an embodiment of the utility model;

[0057] Figure 7 It is a schematic structural diagram of a coding and decoding device according to another embodiment of the utility model. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the utility model more obvious, the exemplary embodiments according to the utility model will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments of the utility model, and it should be understood that the utility model is not limited to the exemplary embodiments described here. Based on the embodiments of the utility model described in the utility model, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the utility model.

[0059] First, refer to Figure 1 The coding and decoding device according to the embodiment of the utility model is described. The coding and decoding device of the utility model can be applied to a transmission device for transmitting user data, and can also be applied to an electronic device that needs to perform protocol conversion, such as an electronic transformer, and can certainly be applied to other devices. This application does not limit the application scenario of the coding and decoding device.

[0060] like Figure 1 As shown, the present application proposes a coding and decoding device, which is applied to a communication device. The coding and decoding device 100 includes a digital logic circuit 110 and a processor 120;

[0061] The digital logic circuit 110 is used for format conversion between the physical layer transmission signal and the processor interface signal;

[0062] The processor 120 is used to decode the data link layer protocol based on the processor 120 interface signal, and to encode the data link layer protocol based on the received user data.

[0063] In the utility model, the digital logic circuit is implemented by using a separation logic circuit device. Specifically, the separation logic circuit device includes a logic gate and a trigger, so the circuit is simple.

[0064] It is understood that digital logic circuits operate at the physical layer.

[0065] The processor 120 is used to extract data link layer protocol data from the received processor interface signal, decode the data link layer protocol to obtain user data; and encode the received user data at the data link layer to obtain data link layer protocol data, and send the data link layer protocol data to the digital logic circuit.

[0066] In the present invention, the processor 120 may be a microcontroller unit (MCU), a central processing unit (CPU), a digital signal processor (DSP), a single chip microcomputer and an embedded device or other processing units with data processing capability and / or instruction execution capability. The processor 120 encodes and decodes the FT3 frame byte stream by software, including a cyclic redundancy check (CRC) check.

[0067] It should be noted that the program stored in the processor 120 for encoding and decoding data of the data link layer protocol, and the interaction instructions between the processor 120 and the peripheral devices under the control of the program, are implemented through existing programs and instructions, belong to the prior art, and have nothing to do with the structural improvements made by the present invention.

[0068] The encoding and decoding device of the embodiment of the utility model performs signal conversion through a digital logic circuit and then performs encoding and decoding through a processor, thereby realizing full-duplex communication of signals and effectively reducing hardware costs compared with FPGA.

[0069] In one embodiment of the utility model, the processor interface signal is an SPI signal, and the digital logic circuit is electrically connected to the processor via a first SPI bus and a second SPI bus;

[0070] The first SPI bus includes a clock output signal line, an SPI data output signal line, a chip select output signal line, a receive reset control signal line and a first clock input signal line; in the first SPI bus, the clock output signal line is used to transmit the SPI clock output signal SPI_CLK, the SPI data output signal line is used to transmit the SPI data output signal SPI_MOSI, the chip select output signal line is used to transmit the SPI chip select output signal SPI_nCS, and the receive reset control signal line is used to transmit the circuit reset input signal The first clock input signal line is used to transmit the SPI clock input signal CLK_80M.

[0071] The second SPI bus includes an SPI data input signal line, a chip select input signal line, and a second clock input signal line. In the second SPI bus, the SPI data input signal line is used to transmit the SPI data input signal Master_SPI_MOSI, the chip select input signal line is used to transmit the SPI chip select input signal Master_SPI_nCS, and the second clock input signal line is used to transmit the SPI clock input signal CLK_80M.

[0072] In one embodiment of the present invention, the physical layer transmission signal is an FT3 signal.

[0073] The digital logic circuit 110 is used to perform signal conversion on the received first FT3 signal to obtain a first SPI signal;

[0074] The digital logic circuit 110 is further configured to perform signal conversion on the second SPI signal received from the processor 120 to obtain a second FT3 signal.

[0075] The digital logic circuit 110 mainly realizes the SPI bit stream timing and FT3 bit stream timing conversion function, and can convert the received SPI signal from the SPI bit sequence to the FT3 frame bit sequence, and can also convert the received first FT3 signal from the FT3 bit sequence to the SPI bit sequence.

[0076] The digital logic circuit 110 can be electrically connected to the processor 120, so as to send the first SPI signal to the processor and receive the second SPI signal sent by the processor. Specifically, the processor 120 and the digital logic circuit 110 are connected via a dual-channel SPI bus 130, so that the digital logic circuit 110 can send the first SPI signal to the processor 120 via the dual-channel SPI bus 130, and the processor 120 can send the second SPI signal to the digital logic circuit 110 via the dual-channel SPI bus 130.

[0077] FT3 signal belongs to the data link layer and can be applied to the Distributed Network Protocol (DNP). DNP is a communication protocol developed based on the TC57 protocol of the International Electrotechnical Commission, which specifies the physical layer, data link layer and application layer. The data link layer uses a variable frame length format: FT3.

[0078] FT3 is also used in the IEC60044-8 protocol, which is the standard for electronic current transformers. The link layer in the standard is selected as the FT3 format. The standard transmission speed of the universal frame is 10Mbit / s (data clock) and Manchester encoding is used.

[0079] The application scenario of FT3 frame is not specifically limited in this application.

[0080] The FT3 frame format is defined as: a fixed-length header followed by an optional data block. Each data block is accompanied by a 16-bit CRC checksum. The fixed header contains a 2-byte start word, a 1-byte length, a 1-byte control word, a 16-bit destination address, a 16-bit source address, and a 16-bit CRC checksum.

[0081] The FT3 frame may be Manchester encoded, and the FT3 signal is a transmission signal obtained by performing Manchester encoding on the FT3 frame.

[0082] Next, refer to Figure 2 A digital logic circuit according to an embodiment of the present invention is described.

[0083] like Figure 2 As shown, in one embodiment of the present utility model, the digital logic circuit includes an SPI to FT3 logic circuit and an FT3 to SPI logic circuit, and the dual SPI bus includes a first SPI bus and a second SPI bus;

[0084] The FT3 to SPI logic circuit acts as a host and sends a first SPI signal through a first SPI bus;

[0085] The SPI to FT3 logic circuit acts as a slave and receives the second SPI signal through the second SPI bus.

[0086] The FT3 to SPI logic circuit is used to convert the bit stream data in the FT3 frame format into the SPI bit stream data, and the SPI to FT3 logic circuit is used to convert the SPI bit stream data into the bit stream data in the FT3 frame format.

[0087] The following uses Manchester encoding when transmitting FT3 signals as an example for explanation.

[0088] The output signal of the SPI to FT3 logic circuit includes the FT3 frame coded data output signal FT3_Do, which is the FT3 frame code stream signal after Manchester encoding. The input signals of the SPI to FT3 logic circuit are Master_SPI_MOSI, Master_SPI_nCS and CLK_80M. All input signals come from the processor. The processor acts as the SPI master and the SPI to FT3 logic circuit acts as the SPI slave.

[0089] The input signal of the FT3 to SPI logic circuit includes the FT3 frame coded data input signal FT3_Di, which is an electrical pulse signal of Manchester encoding in accordance with the IEC60044-8 FT3 frame format, and the signal source is the host of the communication partner. The input signal of the FT3 to SPI logic circuit also includes The output signals of the FT3 to SPI logic circuit include SPI_CLK, SPI_MOSI and SPI_nCS. The FT3 to SPI logic circuit acts as the SPI master and the processor acts as the SPI slave.

[0090] In this embodiment, the SPI clock input signal CLK_80M output by the processor is a square wave clock signal with a frequency of 80M. Specifically, when the processor is an MCU, the clock signal can be output by the GPIO of the MCU. The SPI clock input signal CLK_80M is used as a reference clock signal for the FT3 to SPI logic circuit and the SPI to FT3 logic circuit to drive the digital logic circuit to communicate with the processor.

[0091] In one embodiment of the utility model, the FT3 to SPI logic circuit includes a clock frequency division circuit, an SPI host startup control circuit, and a bit synchronization decoding circuit;

[0092] The SPI host startup control circuit has a first input terminal and a second input terminal, the bit synchronization decoding circuit has a first output terminal and a second output terminal, the output terminal of the clock frequency division circuit is electrically connected to the first input terminal of the SPI host startup control circuit, and the second output terminal of the bit synchronization decoding circuit is electrically connected to the second input terminal of the SPI host startup control circuit.

[0093] In this embodiment, the bit synchronization decoding circuit is used to convert the Manchester code stream of FT3 into the FT3 frame data bit stream, and the decoding principle is as follows:

[0094] The IEC60044-8 protocol FT3 frame adopts Manchester encoding transmission. One data bit is represented by two level bits, with level bit "01" representing data bit "1" and level bit "10" representing data bit "0". When the transmitted FT3 data bit does not change, the output of the level bit shows the alternating change of "0" and "1", and the duration of a single level bit is 50ns; when the transmitted FT3 data bit changes, the output of the level bit shows the output of two consecutive 0s or two consecutive 1s. The level bit output is "0110", indicating that the data bit changes from "1" to "0"; the level bit output is "1001", indicating that the data bit changes from "0" to "1". The bit synchronization decoding circuit confirms the change of the FT3 frame data bit and the changed value by monitoring the continuous level bits, thereby capturing the complete FT3 data frame and transmitting the received data bits to the processor through the SPI interface.

[0095] Specifically, the bit synchronization decoding circuit samples the input FT3 frame Manchester code stream once every 50ns, performs a bit decoding operation every time two Manchester codes are received, and performs clock synchronization every time the bit decoding operation is performed to avoid cumulative decoding failures due to clock source errors between the communicating parties. The bit synchronization decoding circuit monitors the continuous low or high level of 100ns generated on the FT3_Di signal line when the FT3 frame data bit changes, and transmits the corresponding data bit to the SPI data output signal line. The bit synchronization decoding circuit is reset by an external reset signal The control plays the role of decoding synchronization. After reset, the bit synchronization decoding circuit will monitor and decode the data bits of the FT3_Di signal line again.

[0096] In this embodiment, the SPI host startup control circuit is used to After reset, the data output by the bit synchronization decoding circuit is monitored. When the data bit jumps from 1 to 0, the SPI host startup control circuit is immediately started, the chip select output signal line of the SPI is pulled down, a 10MHz square wave is output as the SPI clock signal, and the data signal output by the bit synchronization decoding circuit is transmitted to the SPI data output signal line. The signal output by the SPI host startup control circuit is transmitted to the processor.

[0097] In this embodiment, the clock frequency division circuit is used to divide the input clock signal as a reference clock source of the SPI.

[0098] Preferably, the FT3 to SPI logic circuit also includes an input signal synchronization circuit, the input signal synchronization circuit has a first output terminal and a second output terminal, the bit synchronization decoding circuit has a first input terminal and a second input terminal, the first output terminal of the input signal synchronization circuit is electrically connected to the first input terminal of the bit synchronization decoding circuit and the input terminal of the clock frequency division circuit, and the second output terminal of the input signal synchronization circuit is electrically connected to the second input terminal of the bit synchronization decoding circuit.

[0099] Since the FT3 frame coded data input signal FT3_Di and the circuit reset input signal Different reference clock sources of the SPI clock input signal CLK_80M will randomly cause glitch interference signals to be generated inside the digital logic circuit, resulting in circuit instability. Therefore, an input signal synchronization circuit is introduced at the external signal entrance to synchronize the input signal edges, which can effectively solve the glitch interference problem.

[0100] Specifically, the input signal synchronization circuit resets the signal at the rising edge of FT3_Di. The nRst signal latched into the circuit, the internal reset valid event or invalid event occurs at the rising edge of FT3_Di; the FT3_Di signal is synchronized with the rising edge of the local 80M reference clock CLK_80M, that is, the external signal FT3_Di is latched into the FDi signal inside the circuit at the rising edge of CLK_80M.

[0101] The expressions of nRst signal and FDi signal are as follows:

[0102]

[0103] Among them, the upward arrow ↑ indicates the rising edge of the signal.

[0104] Next, refer to Figure 3 The FT3 to SPI logic circuit according to one embodiment of the present invention is described.

[0105] like Figure 3 As shown, the input signal synchronization circuit may include a first asynchronous clear D flip-flop U1 and a second asynchronous clear D flip-flop U2, the input terminal D of the first asynchronous clear D flip-flop U1 is electrically connected to the receiving reset control signal line, and the input terminal D of the second asynchronous clear D flip-flop is electrically connected to the clock access port of the first asynchronous clear D flip-flop.

[0106] U1 resets the external reset signal at the rising edge of FT3_Di Latched to the nRst signal inside the module. U2 latches the external signal FT3_Di to the FDi signal inside the module at the rising edge of CLK_80M. The output signal of U1 is the nRst signal, that is, the internal reset signal; the output signal of U2 is the FDi signal, that is, the internal FT3 frame Manchester code stream data signal.

[0107] The clock frequency division circuit includes a 3-bit counter U3, whose input clock signal is CLK_80M, whose asynchronous reset signal is nRst signal, whose lower two bits D1 and D2 are left floating, and D3 is selected as output. U3 starts the frequency division function, divides the 80MHz reference clock signal input by 8, and outputs a 10MHz square wave signal as the clock reference of SPI.

[0108] The output signal of U3 is U3_D1 signal, which is the internal SPI clock reference source. The expression of U3_D1 signal is as follows:

[0109]

[0110] The SPI host startup control circuit may include a third asynchronous clear D flip-flop U4 and a first OR gate operator U5, the first OR gate operator having a first input end and a second input end, the first input end of the first OR gate operator being electrically connected to the output end of the clock frequency division circuit, and the second input end of the first OR gate operator being electrically connected to the output end of the third asynchronous clear D flip-flop.

[0111] Trigger U4 is used as the nCS chip select signal generator of SPI. Its input clock signal is the Rx_Trig internal signal, its input data is VCC, i.e. logic 1, its asynchronous reset input signal is the nRst signal, and its reverse output is Output the SPI host internal chip select signal nCS_0. The expression of nCS_0 signal is as follows:

[0112]

[0113] Among them, the Rx_Trig signal is the reverse output signal of the bit synchronization decoding circuit, the Value signal is the output signal of the bit synchronization decoding circuit, and ↓ represents the falling edge of the signal.

[0114] The relationship between the Rx_Trig signal and the Value signal is as follows:

[0115] ↑(Value)=↓(Rx_Trig)

[0116] U5 is the SPI CLK clock output gate controller, and its output signal is the CLK_0 signal. The expression of CLK_0 is as follows:

[0117]

[0118] The bit synchronization decoding circuit may include a fourth asynchronous reset D flip-flop U6, a first AND gate operator U7, a first counter U8, a second OR gate operator U9 and a first XNOR gate operator U10; the first AND gate operator, the first counter, the second OR gate operator and the first XNOR gate operator all have a first input terminal and a second input terminal; the first counter and the fourth asynchronous reset D flip-flop have a first output terminal and a second output terminal;

[0119] The second input terminal of the first XNOR gate operator is electrically connected to the second output terminal of the fourth asynchronous reset D flip-flop, and the output terminal of the first XNOR gate operator is electrically connected to the first input terminal of the second OR gate operator;

[0120] The second input end of the second OR gate operator is electrically connected to the output end of the first AND gate operator, and the output end of the second OR gate operator is electrically connected to the second input end of the first counter;

[0121] The first output terminal of the first counter is electrically connected to the first input terminal of the first AND gate operator, and the second output terminal of the first counter is electrically connected to the second input terminal of the first AND gate operator;

[0122] The output terminal of the first AND gate operator is also electrically connected to the second input terminal CK of the fourth asynchronous reset D flip-flop;

[0123] The second output terminal of the fourth asynchronous clear-to-zero D flip-flop is also electrically connected to the first input terminal of the fourth asynchronous clear-to-zero D flip-flop.

[0124] The input signals of the bit synchronization decoding circuit are FDi signal, nRst signal and CLK_80M signal, and the output signals are Rx_Trig signal and Value signal. The expressions of the output signal and the input signal are as follows:

[0125]

[0126] Among them, FDi(0) represents the first level bit captured, and FDi(1) represents the second level bit captured.

[0127] The bit synchronization decoding circuit captures a level bit every 50nS and outputs a data bit every 100nS.

[0128] Figure 3 U6 is a As the input of the D flip-flop, this will cause it to invert its output value when the rising edge of the trigger signal arrives. In the initial situation after reset, the output Q of U6 is 0, which will serve as the trigger signal of the above U4 flip-flop. is 1, that is, the value passed to SPI_MOSI and the value Value as the input of U10 is 1. The U8 counter and the U7 AND gate together form the trigger signal source of U6. When U8 counts to 6 (0'b110), that is, D2 and D3 are 1 at the same time, the U7 output value Cross will change from 0 to 1, which will generate a rising edge to reverse the output Value of the U6 trigger, that is, SPI_MOSI. U10 and U9 will generate a Roll signal, which will determine whether the U8 counter starts working. In the initial situation after reset, Cross is 0 and Value is 1. At this time, Roll is equal to the synchronized FT3 signal FDi. When FDi is 1, the counter works, and when FDi is 0, the counter is cleared to 0. The U8 counter uses CLK_80M as the clock source, and it takes 75ns (6 CLK_80M clock cycles) to count to 6. Since the level bit transmission rate of the FT3 frame after Manchester encoding is 20Mbps, that is, 1 level bit is transmitted in 50ns, under the single 1 level bit of FDi, the U8 counter cannot count to 6. Only when two consecutive 1s appear, that is, the FT3 data bit is detected to have changed from 1 to 0, can the U8 counter count to 6 and trigger U6 to reverse its output value. At this time, RX_Trig generates a rising edge to trigger U4 to start SPI transmission, and SPI_MOSI (Value) also becomes 0, completing the decoding of a data bit. In the two clock cycles when the U8 counter counts to 6 but has not overflowed, since Cross is 1, the influence of FDi is shielded through the U9 OR gate, and Roll will always be 1. The counter will run for another 25ns until it overflows. The overflow moment is also the start of the next FDi level bit. Since SPI_MOSI (Value) is now 0, after the influence of U10 XOR gate, the signal Roll that controls the counter count will be opposite to FDi, which means that the counter counts when the FDi level is 0, and the counter is cleared when the FDi level is 1. Contrary to the previous situation, two consecutive 0s need to be detected at this time, that is, after detecting that the FT3 data bit has changed from 0 to 1, the counter will count to 6 and trigger U6 to reverse, SPI_MOSI changes from 0 to 1, completing the decoding of a data bit, and the logic circuit will return to the state of monitoring two consecutive 1s. This process continues until the processor receives a complete FT3 frame and pulls down Reset the logic circuit, stop SPI transmission, return the logic circuit to the initial state and wait for the FT3 input to change the data bit from 1 to 0 again.

[0129] Figure 4 : is a timing simulation example diagram of the FT3 to SPI logic circuit of this embodiment, wherein nReset is a reset signal. It can be seen from the figure that the FT3 to SPI logic circuit realizes the FT3 to SPI function.

[0130] In one embodiment of the utility model, the SPI to FT3 logic circuit includes a clock 4-frequency division circuit, a logic operation circuit and a synchronization circuit;

[0131] The logic operation circuit includes a first input terminal, a second input terminal and a third input terminal, the first input terminal is electrically connected to the output terminal of the clock 4-frequency division circuit, the second input terminal is connected to the SPI data input signal line, and the third input terminal is connected to the chip selection input signal line; the output terminal of the logic operation circuit is electrically connected to the input terminal of the synchronization circuit;

[0132] The input end of the clock frequency divider by 4 is connected to the second clock input signal line;

[0133] The synchronization circuit also has a synchronization signal input port, which is connected to the second clock input signal line.

[0134] In this embodiment, the clock divider by 4 circuit is used to divide the external clock signal, ie, the square wave clock signal CLK_80M with a frequency of 80MHz, and output a 20MHz square wave signal CLK_20M as the encoding clock signal of the FT3 frame.

[0135] In this embodiment, the logic operation circuit is used to perform logic operation on the encoding clock signal CLK_20M, the chip select input signal Master_SPI_nCS of the SPI (represented by NSS in the following formula), and the data input signal Master_SPI_MOSI of the SPI (represented by MOSI in the following formula). The logic operation formula of the circuit is as follows:

[0136] CLK_OUT=(CLK_20M and NSS)or(((CLK_20M and MOSI)or(not CLK_20M andnot MOSI))and(not NSS))

[0137] Wherein, CLK_OUT is the output signal of the logic operation circuit.

[0138] When NSS is 1, that is, high level, the expression of CLK_OUT signal can be obtained as:

[0139] CLK_OUT=CLK_20M

[0140] When NSS is 0, that is, low level, the expression of CLK_OUT signal can be obtained as:

[0141] CLK_OUT=((CLK_20M and MOSI)or(not CLK_20M and not MOSI))

[0142] When MOSI=1, CLK_OUT=CLK_20M;

[0143] When MOSI=0, CLK_OUT=not CLK_20M.

[0144] If "CLK_20M" represents data 1 and "not CLK_20M" represents data 0, then combined with the above analysis, it can be seen that the CLK_OUT signal complies with the provisions of the IEC60044-8 link layer.

[0145] In this embodiment, the synchronization circuit is used to output the CLK_OUT signal in synchronization with the edge of the CLK_80M input clock signal, thereby obtaining a Manchester encoded data signal of the FT3 frame.

[0146] In one embodiment of the present invention, the clock divide-by-4 circuit includes a first asynchronous reset D flip-flop and a second asynchronous reset D flip-flop connected in cascade.

[0147] In one embodiment of the utility model, the logic operation circuit includes a third OR gate operator, a fourth OR gate operator, a second AND gate operator, a third AND gate operator, a first NOT gate operator and a second NOT gate operator; the third OR gate operator, the fourth OR gate operator, the second AND gate operator and the third AND gate operator all have a first input terminal and a second input terminal;

[0148] The first input end of the third OR gate operator is connected to the SPI data input signal line, and the second input end is connected to the chip selection input signal line;

[0149] The output end of the third OR gate operator is electrically connected to the second input end of the second AND gate operator and the input end of the first NOT gate operator respectively;

[0150] The output end of the clock 4-frequency dividing circuit is electrically connected to the first input end of the second AND gate operator and the input end of the second NOT gate operator respectively;

[0151] The output end of the first NOT gate operator is electrically connected to the first input end of the third AND gate operator, and the output end of the second NOT gate operator is electrically connected to the second input end of the third AND gate operator respectively;

[0152] The output end of the second AND gate operator is electrically connected to the first input end of the fourth OR gate operator, and the output end of the third AND gate operator is electrically connected to the second input end of the fourth OR gate operator;

[0153] The output end of the fourth OR gate operator is electrically connected to the input end of the synchronization circuit.

[0154] Next, refer to Figure 5 The SPI to FT3 logic circuit according to one embodiment of the present invention is described.

[0155] like Figure 5 As shown, the first asynchronous reset D flip-flop U11 and the second asynchronous reset D flip-flop U12 are cascaded to form a clock 4-division circuit, and the third OR gate operator U13, the first NOT gate operator U14, the second NOT gate operator U15, the second AND gate operator U16, the third AND gate operator U17, and the fourth OR gate operator U18, a total of 6 gate structures, together constitute a logic operation module, and the asynchronous reset flip-flop U19 is used as a synchronization circuit for synchronization before the FT3 frame signal is output.

[0156] The external input CLK_80M signal will generate a 20M clock signal after passing through the internal clock 4-division circuit, namely the CLK_20M signal in the figure, providing the required clock reference source for Manchester encoding.

[0157] The external input Master_SPI_MOSI and Master_SPI_nCS signals pass through the internal U13 OR gate and output the S_FDi signal, which is the data bit stream signal inside the FT3 frame. The logical expression is as follows:

[0158] S_FDi=Master_SPI_MOSI and Master_SPI_nCS

[0159] or

[0160]

[0161] The S_FDi signal and the CLK_20M signal enter the Manchester encoding logic circuit composed of U14, U15, U16, U17, and U18. After logical operation, the S_FDo internal signal is output, which is the code stream signal after the FT3 frame data bits are Manchester encoded. The logical expression of S_FDo is as follows:

[0162] S_FDo=(S_FDi and CLK_20M)or((not S_FDi)and(not CLK_20M))

[0163] or

[0164]

[0165] The internal signal S_FDo then passes through the U19 trigger and is output to the external FT3_Do signal line in synchronization with the edge of the CLK_80M input clock signal.

[0166] In one embodiment of the utility model, the data link layer protocol includes a first preset protocol, and a processor is used to extract a first frame data in a first preset protocol frame format from a received first SPI signal, decode the first frame data to obtain first user data; and encode the second user data to obtain a second frame data in the first preset protocol frame format, and send the second frame data to the digital logic circuit via a second SPI signal.

[0167] Preferably, the processor is also used to perform protocol encapsulation on the first user data to obtain third frame data in the second preset protocol frame format; and decode the received fourth frame data to obtain second user data; wherein the frame format of the fourth frame data is the second preset protocol frame format.

[0168] The processor of this embodiment can encapsulate the first user data into frame data of the second preset protocol, so that the conversion function from the first preset protocol to the second preset protocol can be realized at the data link layer.

[0169] An embodiment of the present application further provides a communication device, which includes the above-mentioned encoding and decoding device.

[0170] Next, refer to Figure 6 A communication device according to an embodiment of the present utility model is described.

[0171] like Figure 6 As shown, in one embodiment of the present utility model, a communication device 600 includes a transmission interface circuit 610, a user data transceiver circuit 630, and a codec device 620 in any one of the embodiments of the first aspect above, and the codec device 620 is electrically connected to the transmission interface circuit 610 and the user data transceiver circuit 630 respectively;

[0172] The transmission interface circuit 610 is used to transmit the physical layer transmission signal received and sent by the codec device 620 through the transmission line;

[0173] The user data transceiver circuit 630 is used to send the data decoded by the encoding and decoding device through a preset communication interface, and to receive the data to be encoded through a preset communication interface and send the data to be encoded to the encoding and decoding device.

[0174] Here, the user data transceiver circuit 630 provides a communication interface for accessing the user application, and sends the user data of the second preset protocol frame format generated in the codec device 620 in the form of a signal corresponding to the communication interface, thereby realizing the function of communicating with other devices. Of course, the user data transceiver circuit 630 can also demodulate the interface signal to obtain the user data of the second preset protocol frame format.

[0175] The transmission interface circuit 610 provides a transmission interface, and its main function is to demodulate the received signal to obtain the first signal, and modulate the second signal to be sent into the transmission signal, and transmit it to the opposite end device through the transmission line. Here, the first signal and the second signal can be FT3 signals, and the FT3 signal is a data signal in the FT3 frame coding format.

[0176] In the present invention, the encoding and decoding device 620 includes a processor and a digital logic circuit, wherein the digital logic circuit is electrically connected to the transmission interface circuit 610, and the processor is electrically connected to the user data transceiver circuit 630. The processor and the user data transceiver circuit 630 can communicate with each other through a communication bus, and the communication bus here includes but is not limited to an integrated circuit bus (Inter-Integrated Circuit, IIC), an SPI bus, etc. The present invention provides a data sending and receiving device that complies with the IEC60044-8 protocol FT3 frame format, which can realize the encoding and decoding of FT3 frame data and the mutual forwarding function of FT3 frame and application data frame, thereby realizing full-duplex communication of the FT3 protocol and effectively reducing hardware costs.

[0177] Preferably, the encoding and decoding device 620 can also perform protocol encapsulation on the first user data to obtain third frame data in the second preset protocol frame format; and decode the received fourth frame data to obtain second user data; wherein the frame format of the fourth frame data is the second preset protocol frame format.

[0178] Here, the second preset protocol frame format may be a frame format defined by a data link layer protocol, such as an Ethernet frame. The present invention does not specifically limit the format of the second preset frame.

[0179] Next, refer to Figure 7 A communication device according to another embodiment of the present invention is described below.

[0180] like Figure 7 As shown, in one embodiment of the present utility model, the communication device includes a user data transceiver circuit, a microprocessor, a digital logic circuit and a transmission interface circuit.

[0181] The user data transceiver circuit receives the byte data frame sent by the application and passes it to the microprocessor. The microprocessor samples the software encoding method, uses software to calculate the CRC check value of the FT3 frame, and encapsulates the application data frame into an FT3 format data frame. After the FT3 frame is encapsulated, the microprocessor controls the NSS signal line of the SPI host peripheral on its MCU chip to output a low-level valid signal, sets the SPI clock frequency to 10MHz, and matches the 10M baud rate specified in the IEC60044-8 protocol; then starts the SPI host controller, and sends the FT3 frame data to the SPI data register in sequence in units of the SPI data register size. After receiving the data unit, the SPI data register outputs the bit stream data from the MOSI signal line, outputs one bit of data every 100ns, and passes it to the digital logic circuit.

[0182] In this embodiment, the transmission line is an optical fiber line, and the transmission interface circuit includes an optical-to-electrical converter and an electro-optical converter for realizing the mutual conversion function between electrical pulses and optical pulses. It should be noted that the optical and electrical pulse signal encoding rules fully comply with the encoding convention of the FT3 frame format of the IEC60044-8 protocol.

[0183] The digital logic circuit performs full-speed encoding on the bit stream data output by the MOSI signal line and outputs it to the FT3_Do signal line. The FT3_Do signal line is connected to the electro-optical converter of the transmission interface circuit. The electro-optical converter converts the electrical pulse signal FT3_Do from the digital logic circuit into an optical pulse signal, which is then transmitted to the optical fiber bus.

[0184] The photoelectric converter converts the optical pulse signal from the optical fiber into an electrical pulse signal FT3_Di, outputs it from the FT3_Di signal line, and transmits it to the FT3 to SPI logic circuit inside the digital logic circuit.

[0185] The FT3 to SPI logic circuit performs bit stream timing conversion and outputs it to the microprocessor.

[0186] The on-chip peripheral slave SPI controller of the MCU inside the microprocessor is always in standby mode. When the NSS signal is pulled low and effective, the slave SPI is immediately activated to start receiving the bit stream data from the FT3 to SPI logic circuit. The slave SPI controller combines the bit stream data in sequence and transfers it to the SPI data register. When a complete data unit is received, the MCU software reads the data unit and transfers it to the internal receive buffer. The number of bytes received is used as the frame delimiter. When the MCU receives a complete FT3 data frame, the MCU controller Pull low to reset the FT3 to SPI logic circuit state machine. At the same time, the MCU starts to perform CRC check calculation. If the CRC passes the check, the FT3 frame is further decoded, the application data is read, and it is encapsulated into an application data frame according to the application protocol. Then, the application data frame is forwarded through the user data transceiver circuit and passed to the application layer.

[0187] The FT3 communication device of this embodiment implements the communication in accordance with the IEC60044-8 FT3 frame format encoding and decoding based on the MCU and the digital logic circuit.

[0188] In one embodiment of the utility model, the communication interface includes any one of the following interfaces: CAN interface, RS485 interface, Ethernet interface, WIFI interface, Bluetooth interface, so that the communication device can realize the functions of CAN communication, RS485 communication, Ethernet communication, WIFI wireless communication, and Bluetooth wireless communication.

[0189] An embodiment of the present application further provides an electronic device, which includes the above-mentioned encoding and decoding device.

[0190] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present invention thereto. A person of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as required by the appended claims.

[0191] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0192] Similarly, it should be understood that in order to streamline the present invention and help understand one or more of the various aspects of the present invention, in the description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present invention should not be interpreted as reflecting the following intention: the claimed invention requires more features than the features explicitly stated in each claim. More specifically, as reflected in the corresponding claims, its utility model point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present invention.

[0193] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0194] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0195] It should be noted that the above embodiments illustrate the utility model rather than limit the utility model, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the existence of elements or steps not listed in the claims. The word "one" or "an" before an element does not exclude the existence of multiple such elements. The utility model can be implemented by means of hardware including several different elements and by means of appropriately programmed computers. In a unit claim that lists several devices, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

[0196] The above is only a specific implementation or description of the specific implementation of the utility model, and the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. The protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. A coding and decoding device, characterized in that: Applied in a communication device, the encoding and decoding device comprises a digital logic circuit and a processor; The digital logic circuit is used to perform format conversion between physical layer transmission signals and processor interface signals; The processor is used to decode the data link layer protocol based on the processor interface signal, and to encode the data link layer protocol based on the received user data.

2. The encoding and decoding device according to claim 1, characterized in that The processor interface signal is an SPI signal, and the digital logic circuit is electrically connected to the processor via a first SPI bus and a second SPI bus; The first SPI bus includes a clock output signal line, an SPI data output signal line, a chip select output signal line, a receiving reset control signal line and a first clock input signal line; The second SPI bus includes an SPI data input signal line, a chip select input signal line and a second clock input signal line.

3. The encoding and decoding device according to claim 2, characterized in that: The physical layer transmission signal is an FT3 signal; The digital logic circuit is used to perform signal conversion on the received first FT3 signal to obtain a first SPI signal, and send the first SPI signal to the processor; The digital logic circuit is also used to perform signal conversion on the second SPI signal received from the processor to obtain a second FT3 signal.

4. The encoding and decoding device according to claim 3, characterized in that: The digital logic circuit includes an SPI to FT3 logic circuit and an FT3 to SPI logic circuit; The FT3 to SPI logic circuit acts as a host and sends the first SPI signal through a first SPI bus; The SPI to FT3 logic circuit acts as a slave and receives the second SPI signal through a second SPI bus.

5. The encoding and decoding device according to claim 4, characterized in that: The FT3 to SPI logic circuit includes a clock frequency division circuit, an SPI host startup control circuit, and a bit synchronization decoding circuit; The SPI host startup control circuit has a first input end and a second input end, the bit synchronization decoding circuit has a first output end and a second output end, the output end of the clock frequency division circuit is electrically connected to the first input end of the SPI host startup control circuit, and the second output end of the bit synchronization decoding circuit is electrically connected to the second input end of the SPI host startup control circuit.

6. The encoding and decoding device according to claim 5, characterized in that: The FT3 to SPI logic circuit also includes an input signal synchronization circuit, which has a first output end and a second output end. The bit synchronization decoding circuit has a first input end and a second input end. The first output end of the input signal synchronization circuit is electrically connected to the first input end of the bit synchronization decoding circuit and the input end of the clock frequency division circuit, and the second output end of the input signal synchronization circuit is electrically connected to the second input end of the bit synchronization decoding circuit.

7. The encoding and decoding device according to claim 6, characterized in that: The input signal synchronization circuit includes a first asynchronous clear D flip-flop and a second asynchronous clear D flip-flop, the input end of the first asynchronous clear D flip-flop is electrically connected to the receive reset control signal line, and the input end of the second asynchronous clear D flip-flop is electrically connected to the clock access port of the first asynchronous clear D flip-flop.

8. The encoding and decoding device according to claim 5, characterized in that: The SPI host startup control circuit includes a third asynchronous clear D flip-flop and a first OR gate operator, the first OR gate operator has a first input end and a second input end, the first input end of the first OR gate operator is electrically connected to the output end of the clock frequency division circuit, and the second input end of the first OR gate operator is electrically connected to the output end of the third asynchronous clear D flip-flop.

9. The encoding and decoding device according to claim 5, characterized in that: The bit synchronization decoding circuit comprises a fourth asynchronous reset D flip-flop, a first AND gate operator, a first counter, a second OR gate operator and a first XNOR gate operator; the first AND gate operator, the first counter, the second OR gate operator and the first XNOR gate operator all have a first input terminal and a second input terminal; the first counter and the fourth asynchronous reset D flip-flop have a first output terminal and a second output terminal; The second input terminal of the first XNOR gate operator is electrically connected to the second output terminal of the fourth asynchronous reset D flip-flop, and the output terminal of the first XNOR gate operator is electrically connected to the first input terminal of the second OR gate operator; The second input end of the second OR gate operator is electrically connected to the output end of the first AND gate operator, and the output end of the second OR gate operator is electrically connected to the second input end of the first counter; The first output terminal of the first counter is electrically connected to the first input terminal of the first AND gate operator, and the second output terminal of the first counter is electrically connected to the second input terminal of the first AND gate operator; The output terminal of the first AND gate operator is also electrically connected to the second input terminal of the fourth asynchronous reset D flip-flop; The second output terminal of the fourth asynchronous reset D flip-flop is also electrically connected to the first input terminal of the fourth asynchronous reset D flip-flop.

10. The encoding and decoding device according to claim 4, characterized in that: The SPI to FT3 logic circuit includes a clock frequency division circuit by 4, a logic operation circuit and a synchronization circuit; The logic operation circuit comprises a first input terminal, a second input terminal and a third input terminal, wherein the first input terminal is electrically connected to the output terminal of the clock 4-frequency division circuit, the second input terminal is connected to the SPI data input signal line, and the third input terminal is connected to the chip select input signal line; the output terminal of the logic operation circuit is electrically connected to the input terminal of the synchronization circuit; The input end of the clock frequency divider by 4 circuit is connected to the second clock input signal line; The synchronization circuit further has a synchronization signal input port, and the synchronization signal input port is connected to the second clock input signal line.

11. The encoding and decoding device according to claim 10, characterized in that: The clock frequency division circuit by four includes a first asynchronous reset D flip-flop and a second asynchronous reset D flip-flop connected in cascade.

12. The encoding and decoding device according to claim 10, characterized in that: The logic operation circuit comprises a third OR gate operator, a fourth OR gate operator, a second AND gate operator, a third AND gate operator, a first NOT gate operator and a second NOT gate operator; the third OR gate operator, the fourth OR gate operator, the second AND gate operator and the third AND gate operator all have a first input terminal and a second input terminal; The first input end of the third OR gate operator is connected to the SPI data input signal line, and the second input end is connected to the chip select input signal line; The output end of the third OR gate operator is electrically connected to the second input end of the second AND gate operator and the input end of the first NOT gate operator respectively; The output end of the clock 4-frequency divider circuit is electrically connected to the first input end of the second AND gate operator and the input end of the second NOT gate operator respectively; The output end of the first NOT gate operator is electrically connected to the first input end of the third AND gate operator, and the output ends of the second NOT gate operator are electrically connected to the second input ends of the third AND gate operator respectively; The output end of the second AND gate operator is electrically connected to the first input end of the fourth OR gate operator, and the output end of the third AND gate operator is electrically connected to the second input end of the fourth OR gate operator; The output end of the fourth OR gate operator is electrically connected to the input end of the synchronization circuit.

13. The coding and decoding device according to any one of claims 2 to 12, characterized in that: The data link layer protocol includes a first preset protocol, and the processor is used to extract first frame data of a first preset protocol frame format from the received first SPI signal, and decode the first frame data to obtain first user data; And encode the second user data to obtain the second frame data in the first preset protocol frame format, and send the second frame data to the digital logic circuit through a second SPI signal.

14. The encoding and decoding device according to claim 13, characterized in that: The processor is also used to perform protocol encapsulation on the first user data to obtain third frame data in a second preset protocol frame format; and decode the received fourth frame data to obtain the second user data; wherein the frame format of the fourth frame data is the second preset protocol frame format.

15. A communication device, characterized in that: The communication device comprises the encoding and decoding device according to any one of claims 1-14.

16. The communication device according to claim 15, characterized in that The communication device further comprises a transmission interface circuit and a user data transceiver circuit, and the encoding and decoding device is electrically connected to the transmission interface circuit and the user data transceiver circuit respectively; The transmission interface circuit is used to transmit the physical layer transmission signal received and sent by the encoding and decoding device through a transmission line; The user data transceiver circuit is used to send the data decoded by the encoding and decoding device through a preset communication interface, receive the data to be encoded through the preset communication interface, and send the data to be encoded to the encoding and decoding device.

17. The communication device according to claim 16, characterized in that The transmission line is an optical fiber line, and the transmission interface circuit includes a photoelectric conversion circuit and an electro-optical conversion circuit.

18. The communication device according to claim 16, characterized in that The communication interface includes any one of the following interfaces: CAN interface, RS485 interface, Ethernet interface, WIFI interface, Bluetooth interface.

19. An electronic device, characterized in that: The electronic device comprises the coding and decoding device according to any one of claims 15 to 18.

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