Image sensor and arrangement structure

Abstract

The utility model provides an image sensor and an arrangement structure, wherein the pixel unit of the image sensor includes a first pixel block, wherein: a first photosensitive module converts a light signal into a first and a second charge signal and stores the first charge signal; a first reset module resets the first photosensitive module and the first floating diffusion node; an overflow control module includes an overflow control transistor and an overflow capacitor, and stores the second charge signal; a potential control module includes a variable potential providing node and a second reset module, wherein the variable potential providing node controls the potential of the first floating diffusion node by controlling the variable potential to improve the exposure readout performance, and the second reset module resets the overflow capacitor by cooperating with the first reset module; and the first readout module reads out the first and the second charge signals. The utility model solves the problem in the prior art that the overflow capacitor will bring a large time delay when the timing is established and improves the exposure readout performance.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor and an arrangement structure. Background Art

[0002] In order to solve the problem of LED flicker, a combination of LPD (large photosensitive element) + SPD (small photosensitive element) is usually used. In order to obtain a better SPD coverage scenario, an overflow capacitor is usually introduced into the SPD to cover a larger signal accumulation requirement. However, due to the large capacitance of the overflow capacitor, it often causes a large time delay when the timing is established; therefore, how to achieve a fast reset of the overflow capacitor is a technical problem that those skilled in the art are eager to solve. In addition, in order to increase the dynamic range, there are technical means for processing the overflow signal (LOFIC) in the prior art. For example, an overflow capacitor is added to the circuit of a single type of photosensitive element. Similarly, in this technology, since the capacitance node of the LOFIC is added, due to the large capacitance of the overflow capacitor, there is a time delay problem when the timing is established. In addition, how to reduce the dark current in the exposure stage and improve the readout efficiency and noise performance in the readout stage are also technical problems that those skilled in the art are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an image sensor and an arrangement structure for solving the problems in the prior art that the overflow capacitor may cause a large time delay when establishing the timing, as well as large dark current in the exposure stage, low readout efficiency and poor noise performance in the readout stage.

[0005] In order to achieve the above-mentioned object and other related objects, the utility model provides an image sensor, the image sensor comprising:

[0006] A plurality of pixel units arranged in an array, wherein the pixel unit comprises a first pixel block, wherein:

[0007] The first pixel block includes a first photosensitive module, a first floating diffusion node, an overflow control module, a first reset module, a potential control module and a first readout module;

[0008] The first photosensitive module is coupled to the first floating diffusion node, and is used to convert the light signal into a charge signal, wherein the charge signal includes a first charge signal and a second charge signal, and is also used to store the first charge signal;

[0009] The first reset module is coupled to the first floating diffusion node, and is used to reset at least the first photosensitive module and the first floating diffusion node;

[0010] The overflow control module includes an overflow control transistor and an overflow capacitor, wherein a first plate of the overflow capacitor is coupled to the first floating diffusion node via the overflow control transistor for storing the second charge signal;

[0011] The potential control module includes a variable potential providing node and a second reset module, wherein:

[0012] The second electrode plate of the overflow capacitor is coupled to the variable potential providing node and receives a variable potential; the variable potential providing node adjusts the potential of the first floating diffusion node by controlling the variable potential to improve exposure readout performance;

[0013] The second reset module is coupled to the second plate of the overflow capacitor, and the first reset module is also coupled to the first plate of the overflow capacitor, and is used to reset the overflow capacitor at least by cooperating with the first reset module;

[0014] The first readout module is coupled to the first floating diffusion node and reads out at least the first charge signal and the second charge signal.

[0015] Optionally, the first photosensitive module includes a first transmission transistor and a first photosensitive element, the control end of the first transmission transistor receives a first transmission control signal, the first end is coupled to the first floating diffusion node, and the second end is coupled to a reference potential via the first photosensitive element;

[0016] And / or, the first reset module comprises a first reset transistor, a control end of which receives a first reset control signal, a first end of which is coupled to a first power supply potential, and a second end of which is coupled to a first plate of the overflow capacitor;

[0017] And / or, the second reset module includes at least one second reset transistor, a control end receives a second reset control signal, a first end is coupled to the first power supply potential, a second end is coupled to the second plate of the overflow capacitor, and a node between the second reset transistor and the second plate of the overflow capacitor serves as the variable potential providing node; or, the second reset module includes at least one second reset transistor, a control end receives a second reset control signal, a second end is coupled to the second plate of the overflow capacitor, and a first end serves as the variable potential providing node;

[0018] And / or, the first read-out module includes a first source follower transistor, whose control end is coupled to the first floating diffusion node, whose first end is coupled to the second power supply potential, and whose second end is coupled to the column line; or, the first read-out module also includes a first row selection transistor, whose control end receives a first selection control signal, whose first end is coupled to the second end of the first source follower transistor, and whose second end is coupled to the column line, wherein, when the first end of the second reset transistor serves as the variable potential providing node, the first end of the first reset transistor and the first end of the second reset transistor are connected together to receive the variable potential instead of the first end of the first reset transistor being coupled to the first power supply potential, and the variable potential providing node is directly connected or separately connected to the first end of the first source follower transistor.

[0019] Optionally, in adjacent rows, at least two of the first pixel blocks share the same second resetting module; and / or, in adjacent columns, at least two of the first pixel blocks share the same second resetting module;

[0020] and / or, when sharing the same second reset module, the second reset module comprises at least two second reset transistors connected in parallel;

[0021] And / or, when sharing the same second reset module, different first pixel blocks sharing the second reset module correspond to different column lines.

[0022] Optionally, the pixel unit further includes a second pixel block, and the second pixel block includes a second photosensitive module, a second floating diffusion node, a third reset module and a second readout module;

[0023] The second photosensitive module is coupled to the second floating diffusion node, and is used to convert the light signal into a charge signal and store the charge signal, wherein the light sensitivity of the second photosensitive module is greater than the light sensitivity of the first photosensitive module;

[0024] The third reset module is coupled to the second floating diffusion node, and is used to reset the second photosensitive module and the second floating diffusion node;

[0025] The second readout module is coupled to the second floating diffusion node and at least reads out the charge signal.

[0026] Optionally, the second photosensitive module includes a second transmission transistor and a second photosensitive element, the control end of the second transmission transistor receives a second transmission control signal, the first end is coupled to the second floating diffusion node, and the second end is coupled to a reference potential via the second photosensitive element;

[0027] And / or, the third reset module comprises a third reset transistor, a control end of which receives a third reset control signal, a first end of which is coupled to a first power supply potential, and a second end of which is coupled to the second floating diffusion node;

[0028] And / or, the second read-out module includes a second source follower transistor, a control end coupled to the second floating diffusion node, a first end coupled to the second power supply potential, and a second end coupled to the column line; or, the second read-out module also includes a second row selection transistor, a control end receiving a second selection control signal, a first end coupled to the second end of the second source follower transistor, and a second end coupled to the column line.

[0029] Optionally, the second pixel block further includes a gain module, coupled between the third reset module and the second floating diffusion node, for switching different conversion gains; and / or, the gain module includes a gain transistor, connected in series between the third reset module and the second floating diffusion node, and a control terminal receives a gain control signal;

[0030] And / or, the overflow control module including the overflow capacitor is used to replace the overflow control module including the overflow control transistor and the overflow capacitor. In this case, the first plate of the overflow capacitor is coupled to the first floating diffusion node.

[0031] Optionally, a third floating diffusion node is used to replace the first floating diffusion node and the second floating diffusion node, a fourth reset module is used to replace the first reset module and the third reset module, and a third readout module is used to replace the first readout module and the second readout module; at this time, the first photosensitive module is coupled to the third floating diffusion node via the overflow control transistor, the second photosensitive module is coupled to the third floating diffusion node, the first plate of the overflow capacitor is coupled to the third floating diffusion node via the overflow control transistor and the second plate is coupled to the variable potential providing node, the fourth reset module is coupled to the third floating diffusion node, and the third readout module is coupled to the third floating diffusion node;

[0032] The fourth reset module includes a fourth reset transistor, a control end of which receives a fourth reset control signal, a first end of which is coupled to the first power supply potential, and a second end of which is coupled to the third floating diffusion node;

[0033] The second reset module is coupled between the second plate of the overflow capacitor and the first power supply potential;

[0034] The third read-out module includes a third source follower transistor, a control end coupled to the third floating diffusion node, a first end coupled to the second power supply potential, and a second end coupled to the column line; or, the third read-out module also includes a third row selection transistor, a control end receiving a third selection control signal, a first end coupled to the second end of the third source follower transistor, and a second end coupled to the column line.

[0035] Optionally, when the second pixel block includes a gain module, the first photosensitive module, the first plate of the overflow capacitor and the fourth reset module are further coupled to the third floating diffusion node via the gain module.

[0036] The utility model also provides an arrangement structure of the image sensor as described above, the arrangement structure comprising:

[0037] The first photosensitive module includes a first transmission transistor and a first photosensitive element, the overflow control module includes an overflow control transistor and an overflow capacitor, the first reset module includes a first reset transistor, and the second reset module includes a second reset transistor;

[0038] The first transfer transistor is arranged at a first corner area of ​​the first photosensitive element, the overflow control transistor is arranged at a side of the first transfer transistor away from the first photosensitive element, the first reset transistor is arranged at a side of the overflow control transistor away from the first transfer transistor, the second reset transistor is arranged at a side of the first reset transistor away from the overflow control transistor, the first floating diffusion node is arranged in an area between the first transfer transistor and the overflow control transistor, and the connection node of the first plate of the overflow capacitor is arranged in an area between the overflow control transistor and the first reset transistor.

[0039] Optionally, when the pixel unit further includes a second pixel block, the second photosensitive module includes a second transmission transistor and a second photosensitive element, the third reset module includes a third reset transistor, and the second readout module includes a second source follower transistor, wherein the first photosensitive element is arranged in an extension direction of a second corner area of ​​the second photosensitive element;

[0040] The second transmission transistor is arranged at a first corner area of ​​the second photosensitive element, the third reset transistor is arranged at one side of the second photosensitive element, the second source follower transistor is arranged at a side of the third reset transistor away from the second photosensitive element, and the second floating diffusion node is arranged at an area between the second transmission transistor and the third reset transistor; or, the second readout module further includes a second row selection transistor, and the second row selection transistor is arranged below the second source follower transistor;

[0041] And / or, the first readout module includes a first source follower transistor, which is arranged below the overflow control transistor, or the first readout module also includes a first row selection transistor, which is arranged below the second reset transistor.

[0042] Optionally, when the second pixel block also includes a gain module and the gain module includes a gain transistor, the gain transistor is arranged above the third reset transistor, and at this time, the second floating diffusion node is arranged in the area between the second transfer transistor and the gain transistor; and / or, the area where the first pixel block is located is divided into a first photosensitive element area and a first pixel transistor area arranged along the first direction, and the area where the second pixel block is located is divided into a second photosensitive element area and a second pixel transistor area arranged along the first direction, wherein, in the second direction, the first photosensitive element area corresponds to the second pixel transistor area, and the second photosensitive element area corresponds to the first pixel transistor area.

[0043] Optionally, the pixel unit further includes a substrate contact disposed below the second source follower transistor or the second row selection transistor.

[0044] As described above, the image sensor and arrangement structure of the utility model reduces the time required to establish the reset timing by introducing a second reset module to quickly reset the overflow capacitor, and reduces the dark current in the exposure stage and improves the readout efficiency and noise performance in the readout stage by introducing a variable potential to control the potential of the first floating diffusion node, thereby improving the readout speed and image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Shown is a circuit diagram of a pixel unit.

[0046] Figure 2 Shown is a schematic structural diagram of the image sensor of the utility model.

[0047] Figure 3 Shown is a circuit diagram of a pixel unit of the utility model.

[0048] Figure 4 Shown is another circuit schematic diagram of the pixel unit of the present invention.

[0049] Figure 5 Shown is another circuit schematic diagram of the pixel unit of the utility model.

[0050] Figure 6 It is a circuit diagram showing that the first pixel columns of two adjacent rows of pixel units share the second reset module of the present invention.

[0051] Figure 7 It is a circuit diagram showing that the first pixel columns of two adjacent columns of pixel units share the second reset module according to the present invention.

[0052] Figure 8 Shown is another circuit schematic diagram of the pixel unit of the utility model.

[0053] Fig. 9 Shown is a schematic diagram of the arrangement structure of the image sensor of the utility model.

[0054] Fig.10 It is a schematic diagram showing the timing control of each stage of the first pixel block in the pixel unit of the present invention.

[0055] Fig.11 It is a schematic diagram showing the timing control of each stage of the second pixel block in the pixel unit of the present invention.

[0056] Fig.12 It is a schematic diagram showing the timing control of each stage of the first pixel block and the second pixel block in the pixel unit of the present invention based on one frame readout.

[0057] Fig.13 Display as Figure 8 Schematic diagram of the timing control of each stage of the pixel unit shown.

[0058] Component number description

[0059] 10 Image Sensor

[0060] 100 pixel unit

[0061] 110 First pixel block

[0062] 111 First photosensitive module

[0063] 112 Overflow Control Module

[0064] 113 First reset module

[0065] 114 Potential Control Module

[0066] 114a Second reset module

[0067] 115 First readout module

[0068] 120 Second pixel block

[0069] 121 Second photosensitive module

[0070] 122 Third reset module

[0071] 123 Second readout module

[0072] 124 Gain Block

[0073] 130 Fourth reset module

[0074] 140 Third readout module DETAILED DESCRIPTION

[0075] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0076] See also Figures 1 to 13 . It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the utility model, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated. In addition, the coupling described in this application represents an electrical connection method, which may be a connection between the two through other transistors or a direct connection. For example, the circuit examples in each diagram illustrate a direct connection method.

[0077] Figure 1 A pixel unit circuit is shown, including a photosensitive element PD', a transmission transistor M1', an overflow control transistor M2', an overflow capacitor COF', a reset transistor M3', a source follower transistor M4' and a row selection transistor M5'. The specific circuit is coupled as shown in FIG. Figure 1 As shown; wherein, the first plate of the overflow capacitor COF' is coupled to the coupling node of the overflow control transistor M2' and the reset transistor M3', and the second plate is coupled to the reference ground.

[0078] In the above circuit, since the capacitance of the overflow capacitor COF' is large, a large time delay is often caused when the timing is established. For example, when resetting the overflow capacitor COF', the reset time is long and the reset speed is slow. In addition, since the potential of the second plate of the overflow capacitor COF' is an uncontrollable fixed potential, it is impossible to take into account the dark current in the exposure stage and the readout efficiency and noise performance in the readout stage, which affects the readout speed and image quality.

[0079] In order to solve the above technical problems, the applicant proposed an image sensor and an arrangement structure, which reduces the time required to establish the reset timing by quickly resetting the overflow capacitor, reduces the dark current in the exposure stage by introducing a variable potential, and improves the readout efficiency and noise performance in the readout stage.

[0080] like Figures 2 to 4 As shown, this embodiment provides an image sensor 10 , including a plurality of pixel units 100 arranged in an array; wherein the pixel unit 100 includes a first pixel block 110 , and further includes a second pixel block 120 .

[0081] like Figure 3 As shown, the first pixel block 110 includes a first photosensitive module 111 , a first floating diffusion node FD1 , an overflow control module 112 , a first reset module 113 , a potential control module 114 and a first readout module 115 .

[0082] The first photosensitive module 111 is coupled to the first floating diffusion node FD1 and is used to convert the light signal into a charge signal. The charge signal includes a first charge signal and a second charge signal. The first photosensitive module 111 is also used to store the first charge signal.

[0083] In combination with actual application scenarios, the first charge signal refers to the charge signal corresponding to the potential well portion, and the second charge signal refers to the charge signal corresponding to the overflow portion after exceeding the potential well portion; in some applications, the first charge signal is defined as the potential well charge signal, and the second charge signal is defined as the overflow charge signal. In fact, when the charge amount sensed by the first photosensitive module 111 does not reach the overflow state, the charge signal converted therefrom only includes the first charge signal, and at this time, the second charge signal can be considered to be zero; when the charge amount sensed by the first photosensitive module 111 reaches the overflow state, the charge signal converted therefrom includes the first charge signal and the second charge signal.

[0084] As an example, the first photosensitive module 111 includes a first transfer transistor M1 and a first photosensitive element PD1; wherein, the control end of the first transfer transistor M1 receives a first transmission control signal TX1, the first end of the first transfer transistor M1 is coupled to the first floating diffusion node FD1, and the second end of the first transfer transistor M1 is coupled to the reference potential via the first photosensitive element PD1, such as, the second end of the first transfer transistor M1 is coupled to the first end of the first photosensitive element PD1, and the second end of the first photosensitive element PD1 is coupled to the reference potential.

[0085] In one implementation, the first transfer transistor M1 includes an NMOS tube, and the first photosensitive element PD1 includes a photodiode; the gate of the first transfer transistor M1 receives the first transfer control signal TX1, the drain of the first transfer transistor M1 is coupled to the first floating diffusion node FD1, the source of the first transfer transistor M1 is coupled to the first end of the first photosensitive element PD1 (e.g., N-type ion doping region), and the second end of the first photosensitive element PD1 (e.g., P-type ion doping region) is coupled to a reference potential; wherein the reference potential includes a ground potential or a negative potential. Of course, in other implementations, it is also feasible that the first transfer transistor M1 includes a PMOS tube, and the first photosensitive element PD1 includes a grating or a photoconductor.

[0086] The overflow control module 112 is coupled to the first floating diffusion node FD1 for storing the second charge signal, wherein the overflow control module 112 may be directly coupled to the first floating diffusion node FD1 or may be electrically coupled to the first floating diffusion node FD1 via other transistors.

[0087] As an example, the overflow control module 112 includes an overflow control transistor M2 and an overflow capacitor COF, the first plate of the overflow capacitor COF is coupled to the first floating diffusion node FD1 via the overflow control transistor M2, and the second plate of the overflow capacitor COF is coupled to the variable potential providing node in the potential control module 114 to receive the variable potential VFD; for example, the control end of the overflow control transistor M2 receives the overflow control signal OF_CTL, the first end of the overflow control transistor M2 is coupled to the first plate of the overflow capacitor COF, the second end of the overflow control transistor M2 is coupled to the first floating diffusion node FD1, and the second plate of the overflow capacitor COF is coupled to the variable potential providing node to receive the variable potential VFD. At this time, the second charge signal can overflow into the overflow capacitor COF based on the overflow control transistor M2. In this example, the first charge signal and the second charge signal can be read out based on the overflow control transistor M2 and the overflow capacitor COF. In addition, at least one transistor can be added between the node of the first reset module 113 and the overflow control transistor M2 and the overflow capacitor COF to achieve multiple gain readouts.

[0088] In one implementation, the overflow control transistor M2 includes an NMOS tube, and the overflow capacitor COF includes a device capacitor; the gate of the overflow control transistor M2 receives the overflow control signal OF_CTL, the drain of the overflow control transistor M2 is coupled to the variable potential VFD via the overflow capacitor COF, and the source of the overflow control transistor M2 is coupled to the first floating diffusion node FD1. Of course, in other implementations, it is also feasible for the overflow control transistor M2 to include a PMOS tube; in addition, since the overflow capacitor COF has a large capacitance, it is usually implemented using a device capacitor rather than an equivalent capacitor, wherein the device capacitor can be a MIM capacitor or a MOS capacitor.

[0089] The first reset module 113 is coupled to the first floating diffusion node FD1. In one example, the first reset module 113 is coupled to the first floating diffusion node FD1 via the overflow control transistor M2 in the overflow control module 112. At this time, the first reset module 113 is also coupled to the first plate of the overflow capacitor COF in the overflow control module 112, for resetting at least the first photosensitive module 111 and the first floating diffusion node FD1.

[0090] As an example, the first reset module 113 includes a first reset transistor M3; wherein the control end of the first reset transistor M3 receives the first reset control signal RST1, the first end of the first reset transistor M3 is coupled to the first power supply potential, and the second end of the first reset transistor M3 is coupled to the first end of the overflow control transistor M2 and the first plate of the overflow capacitor COF.

[0091] In one implementation, the first reset transistor M3 includes an NMOS tube, at which time, the gate of the first reset transistor M3 receives the first reset control signal RST1, the drain of the first reset transistor M3 is coupled to the first power supply potential, and the source of the first reset transistor M3 is coupled to the first plate of the overflow capacitor COF. Of course, in other implementations, it is also feasible for the first reset transistor M3 to include a PMOS tube.

[0092] The potential control module 114 includes a variable potential providing node and a second reset module 114a; wherein the variable potential providing node adjusts the potential of the first floating diffusion node FD1 by controlling the variable potential VFD to improve the exposure readout performance, such as reducing the dark current in the exposure stage and improving the readout efficiency and noise performance in the readout stage; the second reset module 114a is coupled to the second plate of the overflow capacitor COF, and is used to reset the overflow capacitor COF at least by cooperating with the first reset module 111 to achieve fast reset.

[0093] As an example, the second reset module 114a includes at least one second reset transistor M4; in one example, the control end of the second reset transistor M4 receives the second reset control signal RST2, the first end of the second reset transistor M4 is coupled to the first power supply potential, and the second end of the second reset transistor M4 is coupled to the second plate of the overflow capacitor COF. At this time, the node between the second reset transistor M4 and the second plate of the overflow capacitor COF is used as a variable potential providing node to receive the variable potential VFD, such as Figure 3 As shown; in another example, the control end of the second reset transistor M4 receives the second reset control signal RST2, the first end of the second reset transistor M4 serves as a variable potential providing node to receive the variable potential VFD, and the second end of the second reset transistor M4 is coupled to the second plate of the overflow capacitor COF, such as Figure 8shown.

[0094] In one implementation, the second reset transistor M4 includes an NMOS tube, at which time, the gate of the second reset transistor M4 receives the second reset control signal RST2, the drain of the second reset transistor M4 is coupled to the first power supply potential or serves as a variable potential providing node to receive the variable potential VFD, and the source of the second reset transistor M4 is coupled to the second plate of the overflow capacitor COF. Of course, in other implementations, it is also feasible for the second reset transistor M4 to include a PMOS tube.

[0095] The first readout module 115 is coupled to the first floating diffusion node FD1 to read out at least the first charge signal and the second charge signal. In applications, the first readout module 115 usually performs correlated double sampling readout on the first charge signal and performs non-true correlated double sampling readout on the second charge signal.

[0096] As an example, the first read-out module 115 includes a first source follower transistor M5, and further includes a first row selection transistor M6; wherein, the control end of the first source follower transistor M5 is coupled to the first floating diffusion node FD1, the first end of the first source follower transistor M5 is coupled to the second power supply potential, and the second end of the first source follower transistor M5 is coupled to the column line; the first row selection transistor M6 is coupled between the second end of the first source follower transistor M5 and the column line, at this time, the control end of the first row selection transistor M6 receives the first selection control signal SEL1, the first end of the first row selection transistor M6 is coupled to the second end of the first source follower transistor M5, and the second end of the first row selection transistor M6 is coupled to the column line.

[0097] In one embodiment, the first readout module 115 includes a first source follower transistor M5 and a first row selection transistor M6, wherein the first source follower transistor M5 and the first row selection transistor M6 include NMOS transistors; the gate of the first source follower transistor M5 is coupled to the first floating diffusion node FD1, the drain of the first source follower transistor M5 is coupled to the second power supply potential, and the source of the first source follower transistor M5 is coupled to the drain of the first row selection transistor M6; the gate of the first row selection transistor M6 receives the first selection control signal SEL1, and the source of the first row selection transistor M6 is coupled to the column line; in one example, the second power supply potential and the first power supply potential are the same power supply potential VDD. Of course, in other implementations, it is also feasible for the first source follower transistor M5 and the first row selection transistor M6 to include PMOS transistors.

[0098] In the above-mentioned first pixel block 110, when the first end of the second reset transistor M4 is used as a variable potential providing node, there can be different connection modes. Figure 8A connection mode is shown, wherein the first end of the first reset transistor M3 and the first end of the second reset transistor M4 are connected together to receive the variable potential VFD. At this time, the first end of the first reset transistor M3 is no longer coupled to the first power supply potential. In addition, the variable potential providing node and the first end of the first source follower transistor M5 can be directly connected or separately connected. Figure 8 A direct connection is shown.

[0099] like Figure 4 As shown, the second pixel block 120 includes a second photosensitive module 121 , a second floating diffusion node FD2 , a third reset module 122 and a second readout module 123 , and further includes a gain module 124 .

[0100] The second photosensitive module 121 is coupled to the second floating diffusion node FD2 and is used to convert the light signal into a charge signal and store it. The light sensitivity of the second photosensitive module 121 is greater than that of the first photosensitive module 111 .

[0101] As an example, the second photosensitive module 121 includes a second transmission transistor M7 and a second photosensitive element PD2; wherein, the control end of the second transmission transistor M7 receives the second transmission control signal TX2, the first end of the second transmission transistor M7 is coupled to the second floating diffusion node FD2, and the second end of the second transmission transistor M7 is coupled to the reference potential via the second photosensitive element PD2, such as, the second end of the second transmission transistor M7 is coupled to the first end of the second photosensitive element PD2, and the second end of the second photosensitive element PD2 is coupled to the reference potential.

[0102] In one implementation, the second transfer transistor M7 includes an NMOS tube, and the second photosensitive element PD2 includes a photodiode; the gate of the second transfer transistor M7 receives the second transfer control signal TX2, the drain of the second transfer transistor M7 is coupled to the second floating diffusion node FD2, the source of the second transfer transistor M7 is coupled to the first end (e.g., N-type ion doping region) of the second photosensitive element PD2, and the second end (e.g., P-type ion doping region) of the second photosensitive element PD2 is coupled to a reference potential, which may be a ground potential or a negative voltage. Of course, in other implementations, it is also feasible that the second transfer transistor M7 includes a PMOS tube, and the second photosensitive element PD2 includes a grating or a photoconductor.

[0103] The third reset module 122 is coupled to the second floating diffusion node FD2 and is used to reset at least the second photosensitive module 121 and the second floating diffusion node FD2 .

[0104] As an example, the third reset module 122 includes a third reset transistor M8; wherein the control end of the third reset transistor M8 receives a third reset control signal RST3, the first end of the third reset transistor M8 is coupled to the first power supply potential, and the second end of the third reset transistor M8 is coupled to the second floating diffusion node FD2.

[0105] In one implementation, the third reset transistor M8 includes an NMOS tube, at which time, the gate of the third reset transistor M8 receives the third reset control signal RST3, the drain of the third reset transistor M8 is coupled to the first power supply potential, and the source of the third reset transistor M8 is coupled to the second floating diffusion node FD2. Of course, in other implementations, it is also feasible for the third reset transistor M8 to include a PMOS tube.

[0106] The second readout module 123 is coupled to the second floating diffusion node FD2, and reads out at least the charge signal (the charge signal converted by the second photosensitive module 121); in applications, the second readout module 123 usually performs correlated double sampling readout on the charge signal.

[0107] As an example, the second read-out module 123 includes a second source follower transistor M9, and further includes a second row selection transistor M10; wherein, the control end of the second source follower transistor M9 is coupled to the second floating diffusion node FD2, the first end of the second source follower transistor M9 is coupled to the second power supply potential, and the second end of the second source follower transistor M9 is coupled to the column line; the second row selection transistor M10 is coupled between the second end of the second source follower transistor M9 and the column line, at this time, the control end of the second row selection transistor M10 receives the second selection control signal SEL2, the first end of the second row selection transistor M10 is coupled to the second end of the second source follower transistor M9, and the second end of the second row selection transistor M10 is coupled to the column line.

[0108] In one embodiment, the second readout module 123 includes a second source follower transistor M9 and a second row selection transistor M10, wherein the second source follower transistor M9 and the second row selection transistor M10 include NMOS transistors; the gate of the second source follower transistor M9 is coupled to the second floating diffusion node FD2, the drain of the second source follower transistor M9 is coupled to the second power supply potential, and the source of the second source follower transistor M9 is coupled to the drain of the second row selection transistor M10; the gate of the second row selection transistor M10 receives the second selection control signal SEL2, and the source of the second row selection transistor M10 is coupled to the column line. Of course, in other implementations, it is also feasible that the second source follower transistor M9 and the second row selection transistor M10 include PMOS transistors.

[0109] The gain module 124 is coupled between the third reset module 122 and the second floating diffusion node FD2, and is used to switch between different conversion gains, such as switching between a first conversion gain and a second conversion gain, wherein the first conversion gain is not equal to the second conversion gain. As an optional solution, the first conversion gain is less than the second conversion gain. In some applications, the first conversion gain is defined as a low conversion gain (LCG), and the second conversion gain is defined as a high conversion gain (HCG).

[0110] As an example, the gain module 124 includes a gain transistor M11; wherein the gain transistor M11 is connected in series between the third reset module 122 and the second floating diffusion node FD2, such as, the first end of the gain transistor M11 is coupled to the second end of the third reset transistor M8, the second end of the gain transistor M11 is coupled to the second floating diffusion node FD2, and the control end of the gain transistor M11 receives the gain control signal DCG.

[0111] In one implementation, the gain transistor M11 includes an NMOS transistor, in which case the gate of the gain transistor M11 receives the gain control signal DCG, the drain of the gain transistor M11 is coupled to the source of the third reset transistor M8, and the source of the gain transistor M11 is coupled to the second floating diffusion node FD2. Of course, in other implementations, it is also feasible for the gain transistor M11 to include a PMOS transistor.

[0112] The pixel unit 100 of the present embodiment may include only the first pixel block 110, or may include both the first pixel block 110 and the second pixel block 120. In the case where both the first pixel block 110 and the second pixel block 120 are included, the first pixel block 110 and the second pixel block 120 may be independent of each other (as described above), or may have a shared part.

[0113] For the case where the first pixel block 110 and the second pixel block 120 are independent of each other, the overflow control module 112 in the first pixel block 110 may include an overflow control transistor M2 and an overflow capacitor COF, or may only include the overflow capacitor COF. In this case, the first plate of the overflow capacitor COF is no longer coupled to the first floating diffusion node FD1 via the overflow control transistor M2, but is directly coupled to the first floating diffusion node FD1. Furthermore, when the first pixel block 110 only includes the overflow capacitor COF, only a non-true correlated double sampling (image signal first and reset signal later) readout process of the second charge signal can be performed.

[0114] In the case where there are shared parts between the first pixel block 110 and the second pixel block 120, the third floating diffusion node FD3 is used to replace the first floating diffusion node FD1 in the first pixel block 110 and the second floating diffusion node FD2 in the second pixel block 120, the fourth reset module 130 is used to replace the first reset module 113 in the first pixel block 110 and the third reset module 122 in the second pixel block 120, and the third readout module 140 is used to replace the first readout module 115 in the first pixel block 110 and the second readout module 123 in the second pixel block 120, that is, the first pixel block 110 and the second pixel block 120 share the third floating diffusion node FD3, the fourth reset module 130 and the third readout module 140.

[0115] like Figure 5 As shown, in the above-mentioned shared structure, the first photosensitive module 111 is coupled to the third floating diffusion node FD3 via the overflow control transistor M2 (e.g., the first end of the first transmission transistor M1 in the first photosensitive module 111 is coupled to the first end of the overflow control transistor M2, and the second end of the overflow control transistor M2 is coupled to the third floating diffusion node FD3), the second photosensitive module 121 is coupled to the third floating diffusion node FD3 (e.g., the first end of the second transmission transistor M7 in the second photosensitive module 121 is coupled to the third floating diffusion node FD3), the first plate of the overflow capacitor COF is coupled to the third floating diffusion node FD3 via the overflow control transistor M2 (e.g., the first plate of the overflow capacitor COF is coupled to the first end of the overflow control transistor M2), and the second plate of the overflow capacitor COF is coupled to the variable potential providing node to receive the variable potential VFD; in addition, the second reset module 114a is coupled between the second plate of the overflow capacitor COF and the first power supply potential.

[0116] In this example, the charge of the first photosensitive module 111 can overflow to the overflow capacitor COF based on the isolation effect of the overflow control transistor M2. Further, in one implementation, only a non-true correlated double sampling (image signal first and reset signal later) readout process of the second charge signal can be performed.

[0117] The fourth reset module 130 is coupled to the third floating diffusion node FD3 and is used to reset at least the first photosensitive module 111 , the second photosensitive module 121 and the third floating diffusion node FD3 .

[0118] As an example, the fourth reset module 130 includes a fourth reset transistor M12; wherein the control end of the fourth reset transistor M12 receives a fourth reset control signal RST4, the first end of the fourth reset transistor M12 is coupled to the first power supply potential, and the second end of the fourth reset transistor M12 is coupled to the third floating diffusion node FD3.

[0119] In one implementation, the fourth reset transistor M12 includes an NMOS tube, at which time, the gate of the fourth reset transistor M12 receives the fourth reset control signal RST4, the drain of the fourth reset transistor M12 is coupled to the first power supply potential, and the source of the fourth reset transistor M12 is coupled to the third floating diffusion node FD3. Of course, in other implementations, it is also feasible for the fourth reset transistor M12 to include a PMOS tube.

[0120] The third readout module 140 is coupled to the third floating diffusion node FD3 , and reads out at least the first charge signal and the second charge signal in the first pixel block 110 , and reads out at least the charge signal in the second pixel block 120 .

[0121] As an example, the third read-out module 140 includes a third source follower transistor M13, and further includes a third row selection transistor M14; wherein, the control end of the third source follower transistor M13 is coupled to the third floating diffusion node FD3, the first end of the third source follower transistor M13 is coupled to the second power supply potential, and the second end of the third source follower transistor M13 is coupled to the column line; the third row selection transistor M14 is coupled between the third source follower transistor M13 and the column line, at this time, the control end of the third row selection transistor M14 receives the third selection control signal SEL3, the first end of the third row selection transistor M14 is coupled to the second end of the third source follower transistor M13, and the second end of the third row selection transistor M14 is coupled to the column line.

[0122] In one embodiment, the third readout module 140 includes a third source follower transistor M13 and a third row selection transistor M14, wherein the third source follower transistor M13 and the third row selection transistor M14 include NMOS transistors; the gate of the third source follower transistor M13 is coupled to the third floating diffusion node FD3, the drain of the third source follower transistor M13 is coupled to the second power supply potential, and the source of the third source follower transistor M13 is coupled to the drain of the third row selection transistor M14; the gate of the third row selection transistor M14 receives the third selection control signal SEL3, and the source of the third row selection transistor M14 is coupled to the column line. Of course, in other implementations, it is also feasible that the third source follower transistor M13 and the third row selection transistor M14 include PMOS transistors.

[0123] When the second pixel block 120 includes a gain module 124, in the above-mentioned sharing structure, the first pixel block 110 and the second pixel block 120 also share the gain module 124; at this time, the first photosensitive module 111, the first plate of the overflow capacitor COF and the fourth reset module 130 are also coupled to the third floating diffusion node FD3 via the gain module 124, such as, the first end of the first transmission transistor M1 in the first photosensitive module 111, the first plate of the overflow capacitor COF and the second end of the fourth reset transistor M12 in the fourth reset module 130 are all coupled to the first end of the gain transistor M11, and the second end of the gain transistor M11 is coupled to the third floating diffusion node FD3.

[0124] For the image sensor 10 of this embodiment: In one example, the first pixel blocks 110 in at least two adjacent rows of pixel units 100 share the same second reset module 114a, that is, in adjacent rows (including two rows or more), at least two first pixel blocks 110 share the same second reset module 114a, such as Figure 6 As shown; in another example, the first pixel blocks 110 in at least two adjacent columns of pixel units 100 share the same second reset module 114a, that is, in adjacent columns (including two columns or more), at least two first pixel blocks 110 share the same second reset module 114a, such as Figure 7 As shown; Of course, in other examples, the above two sharing schemes can exist simultaneously in the image sensor 10. Among them, when sharing the same second reset module 114a, the second reset module 114a includes at least one second reset transistor M4; in one implementation, the second reset module 114a includes at least two second reset transistors M4 connected in parallel to improve the reset efficiency. In addition, when sharing the same second reset module 114a, different first pixel blocks 110 sharing the second reset module 114a correspond to different column lines to achieve simultaneous readout.

[0125] Correspondingly, this embodiment further provides an arrangement structure of an image sensor 10 , wherein the image sensor 10 is implemented using the structure of the pixel unit 100 described above.

[0126] The first pixel block 110 in the pixel unit 100 includes a first photosensitive module 111, a first floating diffusion node FD1, an overflow control module 112, a first reset module 113, a potential control module 114 and a first readout module 115, and the potential control module 114 includes a variable potential providing node and a second reset module 114a; wherein, the first photosensitive module 111 includes a first transfer transistor M1 and a first photosensitive element PD1, the overflow control module 112 includes an overflow control transistor M2 and an overflow capacitor COF, the first reset module 113 includes a first reset transistor M3, the second reset module 114a includes a second reset transistor M4, the first readout module 115 includes a first source follower transistor M5, and further, the first readout module 115 also includes a first row selection transistor M6.

[0127] When arranging the above components, Fig. 9 As shown, the first transfer transistor M1 is arranged at the first corner area of ​​the first photosensitive element PD1, the overflow control transistor M2 is arranged on the side of the first transfer transistor M1 away from the first photosensitive element PD1, the first reset transistor M3 is arranged on the side of the overflow control transistor M2 away from the first transfer transistor M1, the second reset transistor M4 is arranged on the side of the first reset transistor M3 away from the overflow control transistor M2, the first floating diffusion node FD1 is arranged in the area between the first transfer transistor M1 and the overflow control transistor M2, and the connection node of the first plate of the overflow capacitor COF is arranged in the area between the overflow control transistor M2 and the first reset transistor M3. For example, the overflow capacitor COF is a MIM capacitor, which can be arranged in the metal wiring layer above the semiconductor substrate, and its corresponding first plate is connected to the area between the overflow control transistor M2 and the first reset transistor M3.

[0128] Further, the first source follower transistor M5 is disposed below the overflow control transistor M2; when the first readout module 115 further includes a first row selection transistor M6, the first row selection transistor M6 is disposed below the second reset transistor M4. In addition, it should be noted that the upper and lower parts described in this embodiment are described based on the illustrated examples for ease of understanding, and are actually corresponding elements in the semiconductor substrate, which can be understood by those skilled in the art.

[0129] When the pixel unit 100 further includes a second pixel block 120, the second pixel block 120 includes a second photosensitive module 121, a second floating diffusion node FD2, a third reset module 122 and a second readout module 123, wherein the second photosensitive module 121 includes a second transfer transistor M7 and a second photosensitive element PD2, the third reset module 122 includes a third reset transistor M8, the second readout module 123 includes a second source follower transistor M9, and further, the second readout module 123 also includes a second row selection transistor M10. At this time, in the pixel unit 100, the first photosensitive element PD1 is arranged in the extension direction of the second corner area of ​​the second photosensitive element PD2, and other components in the first pixel block 110 are arranged above the second photosensitive element PD2.

[0130] When arranging the above components, Fig. 9 As shown, the second transfer transistor M7 is arranged at the first corner area of ​​the second photosensitive element PD2, the third reset transistor M8 is arranged at one side of the second photosensitive element PD2, such as, arranged at the side of the second photosensitive element PD2 away from the first photosensitive element PD1, the second source follower transistor M9 is arranged at the side of the third reset transistor M8 away from the second photosensitive element PD2, and the second floating diffusion node FD2 is arranged in the area between the second transfer transistor M7 and the third reset transistor M8; when the second readout module 123 also includes a second row selection transistor M10, the second row selection transistor M10 is arranged below the second source follower transistor M9.

[0131] Further, the second pixel block 120 further includes a gain module 124, wherein the gain module 124 includes a gain transistor M11; when the gain transistor M11 is arranged, the gain transistor M11 is arranged above the third reset transistor M8, and at this time, the second floating diffusion node FD2 is arranged in the area between the second transfer transistor M7 and the gain transistor M11. When the pixel unit 100 includes both the first pixel block 110 and the second pixel block 120, the area where the first pixel block 110 is located is divided into a first photosensitive element area and a first pixel transistor area arranged along a first direction (e.g., X-axis direction), and the area where the second pixel block 120 is located is divided into a second photosensitive element area and a second pixel transistor area arranged along the first direction (e.g., X-axis direction), wherein in the second direction (e.g., Y-axis direction), the first photosensitive element area corresponds to the second pixel transistor area, and the second photosensitive element area corresponds to the first pixel transistor area.

[0132] In the arrangement structure of this embodiment, the pixel unit 100 further includes a substrate contact SUB, such as Fig. 9As shown; when the second readout module 123 in the second pixel block 120 only includes the second source follower transistor M9, the substrate contact SUB is arranged below the second source follower transistor M9; when the second readout module 123 in the second pixel block 120 also includes the second row selection transistor M10, the substrate contact SUB is arranged below the second row selection transistor M10.

[0133] Correspondingly, this embodiment also provides a control method for an image sensor 10, including an exposure stage, a first readout stage and a second readout stage, and further, also including a reset stage before the exposure stage; wherein the image sensor 10 is implemented using the structure described above.

[0134] For the case where the pixel unit 100 in the image sensor 10 only includes the first pixel block 110, the timing control of each stage is as follows: Fig.10 As shown:

[0135] In the reset stage, the first photosensitive module 111 , the first floating diffusion node FD1 , and the overflow control module 112 are reset by the first reset module 113 and the second reset module 114 a .

[0136] Specifically, the first transmission transistor M1 and the overflow control transistor M2 are turned on, and the first floating diffusion node FD1 and the first photosensitive element PD1 are cleared to zero by turning on the first reset transistor M3 to reset the signal; the second reset transistor M4 is turned on, and the overflow capacitor COF is cleared to zero by the first reset transistor M3 and the second reset transistor M4 to reset the signal, thus completing the reset operation; thereafter, the first transmission transistor M1, the first reset transistor M3 and the second reset transistor M4 are turned off. In addition, during the reset operation, the variable potential VFD is controlled to be a high potential, and after the reset operation is completed, the variable potential VFD is controlled to be a low potential.

[0137] In the exposure phase, the overflow control module 112 is turned on and the second reset module 114a is turned off to store the first charge signal and the second charge signal, wherein the potential of the first floating diffusion node FD1 is reduced by controlling the variable potential VFD to be low to reduce the dark current.

[0138] In view of the situation where the node between the second reset transistor M4 and the second plate of the overflow capacitor COF is used as a variable potential providing node, the variable potential VFD is controlled to be a low potential, that is, the potential of the second plate of the overflow capacitor COF is a low potential, so the potential of the first plate of the overflow capacitor COF is a low potential (the potential at both ends of the capacitor cannot change suddenly), thereby lowering the potential of the first floating diffusion node FD1 by opening the overflow control transistor M2, thereby achieving the purpose of reducing the dark current.

[0139] The details are as follows: since the overflow control transistor M2 is not turned off and the second reset transistor M4 is turned off after the reset operation is completed, that is, before the exposure stage begins, the overflow control transistor M2 is turned on and the second reset transistor M4 is turned off, so there is no need to perform additional control on the overflow control transistor M2 and the second reset transistor M4 during the exposure stage.

[0140] When the amount of charge sensed by the first photosensitive module 111 has not reached the overflow state, the converted charge signal only includes the first charge signal, and the second charge signal is considered to be zero. At this time, the first charge signal is stored in the first photosensitive element PD1, and no second charge signal is stored in the overflow capacitor COF; when the amount of charge sensed by the first photosensitive module 111 reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. At this time, the first charge signal is stored in the first photosensitive element PD1, and the second charge signal is stored in the overflow capacitor COF via the first floating diffusion node FD1.

[0141] In the case where the first end of the second reset transistor M4 is used as a variable potential providing node, when the variable potential VFD is controlled to be low, although the second reset transistor M4 has been turned off, the second plate potential of the overflow capacitor COF is still low through the body diode of the second reset transistor M4, thereby achieving the purpose of reducing the dark current as mentioned above. The relevant timing control is as follows: Fig.13 As shown, no further description is given here.

[0142] In the first readout stage, the overflow control module 112 is turned off to read out the first charge signal. In one example, the first charge signal is read out by correlated double sampling. The potential of the first floating diffusion node FD1 is increased by controlling the variable potential VFD to a high potential to increase the readout speed and improve the noise performance.

[0143] In view of the situation where the node between the second reset transistor M4 and the second plate of the overflow capacitor COF is used as a variable potential providing node, the variable potential VFD is controlled to be a high potential, that is, the potential of the second plate of the overflow capacitor COF is a high potential, so the potential of the first plate of the overflow capacitor COF is a high potential. Although the overflow control transistor M2 has been turned off, the potential of the first floating diffusion node FD1 will still be pulled up through the body diode of the overflow control transistor M2, thereby achieving the purpose of increasing the readout speed and improving the noise performance.

[0144] Specifically, the first row selection transistor M6 is turned on first to perform quantization reading of the first reset signal (i.e., H_RST); then, the first transfer transistor M1 is turned on to transfer the first charge signal; finally, the first transfer transistor M1 is turned off to perform quantization reading of the first charge signal (i.e., H_SIG). In one example, the first row selection transistor M6 is turned off before the first transfer transistor M1 is turned on, and the first row selection transistor M6 is turned on after the first transfer transistor M1 is turned off; in addition, the closing action of the overflow control transistor M2 is performed after the first opening action of the first row selection transistor M6.

[0145] In the case where the first end of the second reset transistor M4 is used as a variable potential providing node, when the variable potential VFD is controlled to be high, although the second reset transistor M4 has been turned off, the second plate potential of the overflow capacitor COF is still high through the body diode of the second reset transistor M4, thereby achieving the above-mentioned purpose of increasing the readout speed and improving the noise performance. The relevant timing control is as follows: Fig.13 As shown, no further description is given here.

[0146] In the second readout stage, the overflow control module 112 is turned on to read out the second charge signal. In one example, a non-true correlated double sampling readout is performed on the second charge signal, wherein after the second charge signal is read out and before the reset signal corresponding to the second charge signal is read out, the first reset module 113 and the second reset module 114a are turned on to reset the overflow capacitor COF in the overflow control module 112. In this process, the variable potential VFD is controlled to be a low potential.

[0147] Specifically, the overflow control transistor M2 and the first transfer transistor M1 are turned on to transfer the second charge signal, and the second charge signal (i.e., OF_SIG) is quantized and read out through the turned-on first row selection transistor M6; in one example, the overflow control transistor M2 is turned on, the first row selection transistor M6 is turned off, and then the first transfer transistor M1 is turned on, and then the first row selection transistor M6 is turned on after the first transfer transistor M1 is turned off. Next, the first reset transistor M3 and the second reset transistor M4 are turned on, and the two cooperate to quickly reset the overflow capacitor COF, and the second reset signal (i.e., OF_RST) is quantized and read out through the turned-on first row selection transistor M6; in one example, the first row selection transistor M6 is turned off when the first reset transistor M3 and the second reset transistor M4 are in the turned-on state, and the first row selection transistor M6 is turned on after the first reset transistor M3 and the second reset transistor M4 are turned off.

[0148] For the case where the pixel unit 100 in the image sensor 10 also includes a second pixel block 120, the control method further includes a step of reading out the charge signal in the second pixel block 120. In one example, the charge signal in the second pixel block 120 is subjected to correlated double sampling. Further, when the second pixel block 120 includes a gain module 124, the control method further includes a step of performing correlated double sampling on the corresponding charge signal at different conversion gains. The timing control of each stage is as follows: Fig.11 As shown:

[0149] In the reset stage, the second photosensitive module 121 , the second floating diffusion node FD2 and the gain module 124 are reset through the third reset module 122 .

[0150] The details are as follows: turn on the second transfer transistor M7 and the gain transistor M11, and clear the charge of the second photosensitive element PD2, the second floating diffusion node FD2 and the equivalent gain capacitance of the gain module 124 by turning on the third reset transistor M8 to achieve signal reset and complete the reset operation; then, turn off the second transfer transistor M7, the gain transistor M11 and the third reset transistor M8.

[0151] During the exposure phase, the gain module 124 is turned off to store the charge signal, for example, the charge signal is stored in the second photosensitive element PD2. Since the gain transistor M11 has been turned off after the reset operation is completed, there is no need to perform additional control on the gain transistor M11 during the exposure phase.

[0152] In the readout stage, the charge signal is read out by performing correlated double sampling at different conversion gains by turning on and off the gain module 124 .

[0153] Specifically, the second row selection transistor M10 is turned on, the gain transistor M11 is turned on to enter the first conversion gain and the first reset signal (i.e., L_RST) is quantized and read out at the first conversion gain, and then the gain transistor M11 is turned off to enter the second conversion gain and the first reset signal (i.e., H_RST) is quantized and read out at the second conversion gain; the second transfer transistor M7 is turned on and the charge signal is transferred at the second conversion gain, and then the second transfer transistor M7 is turned off and the charge signal (i.e., H_SIG) is quantized and read out at the second conversion gain; the gain transistor M11 is turned on to enter the first conversion gain, the second transfer transistor M7 is turned on and the charge signal is transferred at the first conversion gain, and then the second transfer transistor M7 is turned off and the charge signal (i.e., L_SIG) is quantized and read out at the first conversion gain. In one example, the second row selection transistor M10 is turned off before the second transfer transistor M7 is turned on, and the second row selection transistor M10 is turned on after the second transfer transistor M7 is turned off.

[0154] In actual applications, the first pixel block 110 and the second pixel block 120 are read out based on one frame, and the readout process includes a reset phase, an exposure phase, a signal readout phase corresponding to the second pixel block 120, and a signal readout phase corresponding to the first pixel block 110. Specifically, in one example, the signal readout phase corresponding to the second pixel block 120 (e.g., the readout of L_RST, H_RST, H_SIG, and L_SIG) and the signal readout phase corresponding to the first pixel block 110 (e.g., the readout of H_RST, H_SIG, OF_SIG, and OF_RST) overlap in timing. At this time, the second pixel block 120 and the first pixel block 110 are read out simultaneously based on different column lines, such as Fig.10 and Fig.11 As shown; in another example, the signal readout phase corresponding to the second pixel block 120 (e.g., the readout of L_RST_2, H_RST_2, H_SIG_2, and L_SIG_2) and the signal readout phase corresponding to the first pixel block 110 (e.g., the readout of H_RST_1, H_SIG_1, OF_SIG_1, and OF_RST_1) do not overlap in timing. At this time, the second pixel block 120 and the first pixel block 110 are read out sequentially based on the same column line, as shown in FIG. Fig.12 shown.

[0155] In summary, the image sensor and arrangement structure of the utility model reduces the time required for reset timing establishment by introducing a second reset module to quickly reset the overflow capacitor, and reduces the dark current in the exposure stage and improves the readout efficiency and noise performance in the readout stage by introducing a variable potential to control the potential of the first floating diffusion node, thereby improving the readout speed and image quality. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0156] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that: The image sensor comprises: A plurality of pixel units arranged in an array, wherein the pixel unit comprises a first pixel block, wherein: The first pixel block includes a first photosensitive module, a first floating diffusion node, an overflow control module, a first reset module, a potential control module and a first readout module; The first photosensitive module is coupled to the first floating diffusion node, and is used to convert the light signal into a charge signal, wherein the charge signal includes a first charge signal and a second charge signal, and is also used to store the first charge signal; The first reset module is coupled to the first floating diffusion node, and is used to reset at least the first photosensitive module and the first floating diffusion node; The overflow control module includes an overflow control transistor and an overflow capacitor, wherein a first plate of the overflow capacitor is coupled to the first floating diffusion node via the overflow control transistor for storing the second charge signal; The potential control module includes a variable potential providing node and a second reset module, wherein: The second electrode plate of the overflow capacitor is coupled to the variable potential providing node and receives a variable potential; the variable potential providing node adjusts the potential of the first floating diffusion node by controlling the variable potential to improve exposure readout performance; The second reset module is coupled to the second plate of the overflow capacitor, and the first reset module is also coupled to the first plate of the overflow capacitor, and is used to reset the overflow capacitor at least by cooperating with the first reset module; The first readout module is coupled to the first floating diffusion node and reads out at least the first charge signal and the second charge signal.

2. The image sensor according to claim 1, characterized in that The first photosensitive module includes a first transmission transistor and a first photosensitive element, wherein the control end of the first transmission transistor receives a first transmission control signal, the first end is coupled to the first floating diffusion node, and the second end is coupled to a reference potential via the first photosensitive element; And / or, the first reset module comprises a first reset transistor, a control end of which receives a first reset control signal, a first end of which is coupled to a first power supply potential, and a second end of which is coupled to a first plate of the overflow capacitor; And / or, the second reset module includes at least one second reset transistor, a control end receives a second reset control signal, a first end is coupled to the first power supply potential, a second end is coupled to the second plate of the overflow capacitor, and a node between the second reset transistor and the second plate of the overflow capacitor serves as the variable potential providing node; or, the second reset module includes at least one second reset transistor, a control end receives a second reset control signal, a second end is coupled to the second plate of the overflow capacitor, and a first end serves as the variable potential providing node; And / or, the first read-out module includes a first source follower transistor, whose control end is coupled to the first floating diffusion node, whose first end is coupled to the second power supply potential, and whose second end is coupled to the column line; or, the first read-out module also includes a first row selection transistor, whose control end receives a first selection control signal, whose first end is coupled to the second end of the first source follower transistor, and whose second end is coupled to the column line, wherein, when the first end of the second reset transistor serves as the variable potential providing node, the first end of the first reset transistor and the first end of the second reset transistor are connected together to receive the variable potential instead of the first end of the first reset transistor being coupled to the first power supply potential, and the variable potential providing node is directly connected or separately connected to the first end of the first source follower transistor.

3. The image sensor according to claim 1 or 2, characterized in that: In adjacent rows, at least two of the first pixel blocks share the same second resetting module; and / or, in adjacent columns, at least two of the first pixel blocks share the same second resetting module; and / or, when sharing the same second reset module, the second reset module comprises at least two second reset transistors connected in parallel; And / or, when sharing the same second reset module, different first pixel blocks sharing the second reset module correspond to different column lines.

4. The image sensor according to claim 1, characterized in that The pixel unit further includes a second pixel block, which includes a second photosensitive module, a second floating diffusion node, a third reset module and a second readout module; The second photosensitive module is coupled to the second floating diffusion node, and is used to convert the light signal into a charge signal and store the charge signal, wherein the light sensitivity of the second photosensitive module is greater than the light sensitivity of the first photosensitive module; The third reset module is coupled to the second floating diffusion node, and is used to reset the second photosensitive module and the second floating diffusion node; The second readout module is coupled to the second floating diffusion node and at least reads out the charge signal.

5. The image sensor according to claim 4, characterized in that: The second photosensitive module includes a second transmission transistor and a second photosensitive element, the control end of the second transmission transistor receives a second transmission control signal, the first end is coupled to the second floating diffusion node, and the second end is coupled to a reference potential via the second photosensitive element; And / or, the third reset module comprises a third reset transistor, a control end of which receives a third reset control signal, a first end of which is coupled to a first power supply potential, and a second end of which is coupled to the second floating diffusion node; And / or, the second read-out module includes a second source follower transistor, a control end coupled to the second floating diffusion node, a first end coupled to the second power supply potential, and a second end coupled to the column line; or, the second read-out module also includes a second row selection transistor, a control end receiving a second selection control signal, a first end coupled to the second end of the second source follower transistor, and a second end coupled to the column line.

6. The image sensor according to claim 4, characterized in that: The second pixel block further comprises a gain module, coupled between the third reset module and the second floating diffusion node, for switching different conversion gains; and / or, the gain module comprises a gain transistor, connected in series between the third reset module and the second floating diffusion node, and a control terminal receives a gain control signal; And / or, the overflow control module including the overflow capacitor is used to replace the overflow control module including the overflow control transistor and the overflow capacitor. In this case, the first plate of the overflow capacitor is coupled to the first floating diffusion node.

7. The image sensor according to any one of claims 4 to 6, characterized in that: The first floating diffusion node and the second floating diffusion node are replaced by a third floating diffusion node, the first reset module and the third reset module are replaced by a fourth reset module, and the first readout module and the second readout module are replaced by a third readout module; at this time, the first photosensitive module is coupled to the third floating diffusion node via the overflow control transistor, the second photosensitive module is coupled to the third floating diffusion node, the first plate of the overflow capacitor is coupled to the third floating diffusion node via the overflow control transistor and the second plate is coupled to the variable potential providing node, the fourth reset module is coupled to the third floating diffusion node, and the third readout module is coupled to the third floating diffusion node; The fourth reset module includes a fourth reset transistor, a control end of which receives a fourth reset control signal, a first end of which is coupled to the first power supply potential, and a second end of which is coupled to the third floating diffusion node; The second reset module is coupled between the second plate of the overflow capacitor and the first power supply potential; The third read-out module includes a third source follower transistor, a control end coupled to the third floating diffusion node, a first end coupled to the second power supply potential, and a second end coupled to the column line; or, the third read-out module also includes a third row selection transistor, a control end receiving a third selection control signal, a first end coupled to the second end of the third source follower transistor, and a second end coupled to the column line.

8. The image sensor according to claim 7, characterized in that: When the second pixel block includes a gain module, the first photosensitive module, the first plate of the overflow capacitor and the fourth reset module are further coupled to the third floating diffusion node via the gain module.

9. An arrangement structure of an image sensor according to any one of claims 1 to 8, characterized in that: The arrangement structure comprises: The first photosensitive module includes a first transmission transistor and a first photosensitive element, the overflow control module includes an overflow control transistor and an overflow capacitor, the first reset module includes a first reset transistor, and the second reset module includes a second reset transistor; The first transfer transistor is arranged at a first corner area of ​​the first photosensitive element, the overflow control transistor is arranged at a side of the first transfer transistor away from the first photosensitive element, the first reset transistor is arranged at a side of the overflow control transistor away from the first transfer transistor, the second reset transistor is arranged at a side of the first reset transistor away from the overflow control transistor, the first floating diffusion node is arranged in an area between the first transfer transistor and the overflow control transistor, and the connection node of the first plate of the overflow capacitor is arranged in an area between the overflow control transistor and the first reset transistor.

10. The arrangement structure of the image sensor according to claim 9, characterized in that: When the pixel unit further includes a second pixel block, the second photosensitive module includes a second transmission transistor and a second photosensitive element, the third reset module includes a third reset transistor, and the second readout module includes a second source follower transistor, wherein the first photosensitive element is arranged in an extension direction of a second corner area of ​​the second photosensitive element; The second transmission transistor is arranged at a first corner area of ​​the second photosensitive element, the third reset transistor is arranged at one side of the second photosensitive element, the second source follower transistor is arranged at a side of the third reset transistor away from the second photosensitive element, and the second floating diffusion node is arranged at an area between the second transmission transistor and the third reset transistor; or, the second readout module further includes a second row selection transistor, and the second row selection transistor is arranged below the second source follower transistor; And / or, the first readout module includes a first source follower transistor, which is arranged below the overflow control transistor, or the first readout module also includes a first row selection transistor, which is arranged below the second reset transistor.

11. The arrangement structure of the image sensor according to claim 10, characterized in that: When the second pixel block also includes a gain module and the gain module includes a gain transistor, the gain transistor is arranged above the third reset transistor, and at this time, the second floating diffusion node is arranged in the area between the second transfer transistor and the gain transistor; and / or, the area where the first pixel block is located is divided into a first photosensitive element area and a first pixel transistor area arranged along a first direction, and the area where the second pixel block is located is divided into a second photosensitive element area and a second pixel transistor area arranged along the first direction, wherein, in the second direction, the first photosensitive element area corresponds to the second pixel transistor area, and the second photosensitive element area corresponds to the first pixel transistor area.

12. The arrangement structure of the image sensor according to claim 10 or 11, characterized in that: The pixel unit further includes a substrate contact disposed below the second source follower transistor or the second row selection transistor.

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